Datasheet ADG3243 Datasheet (Analog Devices)

2.5 V/3.3 V, 2-Bit, Individual Control
Level Translator Bus Switch

ADG3243

FEATURES
225 ps Propagation Delay through the Switch

4.5 ⍀ Switch Connection between Ports
Data Rate 1.5 Gbps

2.5 V/3.3 V Supply Operation
Level Translation

3.3 V to 2.5 V

2.5 V to 1.8 V
Small Signal Bandwidth 710 MHz
8-Lead SOT-23 Package

APPLICATIONS

3.3 V to 2.5 V Voltage Translation

2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Switch Applications

GENERAL DESCRIPTION

The ADG3243 is a 2.5 V or 3.3 V, 2-bit, 2-port digital switch
with individual channel control. It is designed on a low voltage
CMOS process, which provides low power dissipation yet gives
high switching speed and very low on resistance. This allows the
inputs to be connected to the outputs without additional propa­gation delay or generating additional ground bounce noise.

The switches are enabled by means of the bus enable (BEx) input
signal. This digital switch allows a bidirectional signal to be
switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.

This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. This makes the device
suited to applications requiring level translation between different
supplies, such as converter to DSP/microcontroller interfacing.

FUNCTIONAL BLOCK DIAGRAM

A0

BE0

A1

BE1

PRODUCT HIGHLIGHTS

1. 3.3 V or 2.5 V supply operation.

2. Extremely low propagation delay through switch.

3. 4.5 Ω switches connect inputs to outputs.

4. Level/voltage translation.

5. Tiny SOT-23 package.

B0

B1

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADG3243–SPECIFICATIONS

(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications T

1

unless otherwise noted.)

MIN

to T

MAX

,

B Version

Parameter Symbol Conditions Min Typ2Max Unit

DC ELECTRICAL CHARACTERISTICS

Input High Voltage V

Input Low Voltage V

Input Leakage Current I
OFF State Leakage Current I

INH

V

INH

INL

V

INL

I

OZ

ON State Leakage Current 0 ≤ A, B ≤ V
Maximum Pass Voltage V

P

VCC = 2.7 V to 3.6 V 2.0 V
VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 0.8 V
VCC = 2.3 V to 2.7 V 0.7 V

± 0.01 ± 1 µA

0 ≤ A, B ≤ V

CC

CC

± 0.01 ± 1 µA
± 0.01 ± 1 µA

VA/VB = VCC = 3.3 V, IO = –5 µA 2.0 2.5 2.9 V
VA/VB = VCC = 2.5 V, IO= –5 µA 1.5 1.8 2.1 V

CAPACITANCE

3

A Port Off Capacitance CA OFF f = 1 MHz 3.5 pF
B Port Off Capacitance C
A, B Port On Capacitance C
Control Input Capacitance C

SWITCHING CHARACTERISTICS

Propagation Delay A to B or B to A, t
Propagation Delay Matching
Bus Enable Time BEx to A or B
Bus Disable Time BEx to A or B
Bus Enable Time BEx to A or B
Bus Disable Time BEx to A or B

3

5

6

6

6

6

Maximum Data Rate V
Channel Jitter V

OFF f = 1 MHz 3.5 pF

B

, CB ON f = 1 MHz 7 pF

PD

A

IN

4

t

, t

PHL

t

, t

PZH

t

, t

PHZ

t

, t

PZH

t

, t

PHZ

f = 1 MHz 4 pF

CL = 50 pF, VCC = 3 V 225 ps

PLH

VCC = 3.0 V to 3.6 V 1 3.2 4.6 ns

PZL

VCC = 3.0 V to 3.6 V 1 3 4 ns

PLZ

VCC = 2.3 V to 2.7 V 1 3 4 ns

PZL

VCC = 2.3 V to 2.7 V 1 2.5 3.4 ns

PLZ

= 3.3 V; VA/VB = 2 V 1.5 Gbps

CC

= 3.3 V; VA/VB = 2 V 45 ps p-p

CC

5ps

DIGITAL SWITCH

On Resistance R

ON

VCC = 3 V, VA = 0 V, IBA = 8 mA 4.5 8 Ω
VCC = 3 V, VA = 1.7 V, IBA = 8 mA 12 28 Ω

= 2.3 V, VA = 0 V, IBA = 8 mA 5 9 Ω

V

CC

= 2.3 V, VA = 1 V, IBA = 8 mA 9 18 Ω

V

On Resistance Matching ⌬R

ON

CC

VCC = 3 V, VA = 0 V, IA = 8 mA 0.1 0.5 Ω

POWER REQUIREMENTS

V

CC

Quiescent Power Supply Current I
Increase in ICC per Input

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Typical values are at 25°C, unless otherwise stated.

3

Guaranteed by design, not subject to production test.

4

The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.

5

Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.

6

See Timing Measurement Information section.

7

This current applies to the control pin BEx only. The A and B ports contribute no significant ac or dc currents as they transition.

Specifications subject to change without notice.

7

⌬I

CC

CC

Digital Inputs = 0 V or V

CC

VCC = 3.6 V, BE0 = 3.0 V, BE1 = VCC or GND 0.15 8 µA

2.3 3.6 V

0.01 1 µA

REV. 0–2–

ADG3243

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

ADG3243

GND

A1

BE0

B0

BE1

V

CC

A0

B1

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/Ω

␪

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C

IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

PIN CONFIGURATION

8-Lead SOT-23

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 BE0 Bus Enable (Active Low)
2A0 Port A0, Input or Output
3A1 Port A1, Input or Output
4GND Ground Reference
5B1 Port B1, Input or Output
6B0 Port B0, Input or Output
7 BE1 Bus Enable (Active Low)
8VCCPositive Power Supply Voltage

Table I. Truth Table

BEx Function

LAx = Bx, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
H Disconnect

ORDERING GUIDE

Model Temperature Range Package Description Package Branding

ADG3243BRJ-R2 –40°C to +85°CSOT-23 (Small Outline Transistor Package) RJ-8 SFA
ADG3243BRJ-REEL –40°C to +85°CSOT-23 (Small Outline Transistor Package) RJ-8 SFA
ADG3243BRJ-REEL7 –40°C to +85°CSOT-23 (Small Outline Transistor Package) RJ-8 SFA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3243 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0

–3–

ADG3243

TERMINOLOGY

V

CC

Positive Power Supply Voltage.

GND Ground (0 V) Reference.

V

INH

V

INL

I

I

I

OZ

I

OL

V

P

Minimum Input Voltage for Logic 1.

Maximum Input Voltage for Logic 0.

Input Leakage Current at the Control Inputs.

OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.

ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.

Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.

R

ON

Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.

⌬R

ON

OFF OFF Switch Capacitance.

C

X

C

ON ON Switch Capacitance.

X

C

IN

I

CC

ON Resistance Match between Any Two Channels, i.e., RON max – R

Control Input Capacitance. This consists of BEx.

Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.

ON

min.

It is measured when all control inputs are at a logic high or low level and the switches are OFF.

⌬I

t

t

PLH

PZH

CC

, t

, t

PHL

PZL

Extra power supply current component for the EN control input when the input is not driven at the supplies.

Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
R

× CL, where CL is the load capacitance.

ON

Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BEx.

t

PHZ

, t

PLZ

Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control
signal. It is measured as the time taken for the output voltage to change by V

from the original quiescent level,

⌬

with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)

Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.

Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.

REV. 0–4–

Typical Performance Characteristics–ADG3243

40

TA = 25ⴗC

35

30

)

25

⍀

(

ON

20

R

15

10

5

0

0 0.5

1.5 2.5 3.5
VA/VB (V

)

TPC 1. On Resistance vs.
Input Voltage

15

= 2.5V

V

CC

10

ⴙ85ⴗC

(⍀)

ON

R

5

ⴙ25ⴗC

VCC = 3V

VCC = 3.3V

VCC = 3.6V

3.02.01.0

ⴚ40ⴗC

40

TA = 25ⴗC

35

30

)

25

⍀

(

ON

20

R

15

10

5

0

0 0.5

1.5 2.5

VA/VB (V

)

TPC 2. On Resistance vs.
Input Voltage

3.0
TA = 25ⴗC

= –5␮A

I

O

2.5

2.0

(V)

1.5

OUT

V

1.0

0.5

VCC = 2.3V

VCC = 2.5V

= 2.7V

V

CC

VCC = 3.6V

V

CC

VCC = 3V

= 3.3V

20

= 3.3V

V

CC

15

(⍀)

10

ON

R

5

0

3.02.01.0

0 0.5

ⴙ85ⴗC

ⴚ40ⴗC

VA/VB (V)

ⴙ25ⴗC

1.5

2.01.0

TPC 3. On Resistance vs. Input
Voltage for Different Temperatures

2.5
TA = 25ⴗC
I

= –5␮A

O

2.0

1.5

(V)

OUT

V

1.0

0.5

VCC = 2.7V

VCC = 2.5V

VCC = 2.3V

0

0 0.5

VA/VB(V)

1.0

TPC 4. On Resistance vs. Input
Voltage for Different Temperatures

500

TA = 25ⴗC

450

400

350

300

250

(␮A)

CC

I

200

150

100

50

0

051015 20 25 30 35 40 45

ENABLE FREQUENCY (MHz)

VCC = 3.3V

VCC = 2.5V

TPC 7. ICC vs. Enable Frequency

1.2

0

0 0.5

TPC 5. Pass Voltage vs. V

3.0

2.5

2.0

(V)

1.5

OUT

V

1.0

0.5

50

0

1.0 2.0 3.0

1.5 2.5 3.5
VA/VB (V)

TA = 25ⴗC
V

= 0V

A

BEx = 0

VCC = 3.3V

0.02 0.04 0.06 0.08 0.100

CC

VCC = 2.5V

IO (A)

TPC 8. Output Low Characteristic

0

0 0.5

TPC 6. Pass Voltage vs. V

3.0
TA = 25ⴗC
V

= V

A

CC

BEx = 0

VCC = 2.5V

–0.08 –0.06 –0.04 –0.02 0

(V)

V

OUT

2.5

2.0

1.5

1.0

0.5

0

–0.10

1.5 2.5

1.0 2.0 3.0
VA/VB (V)

CC

VCC = 3.3V

IO (A)

TPC 9. Output High Characteristic

REV. 0

–5–

ADG3243

0

TA = 25ⴗC

–0.2

ON OFF
C

= InF

L

–0.4

–0.6

VCC = 2.5V

–0.8

(pC)

–1.0

INJ

Q

–1.2

–1.4

–1.6

–1.8

–2.0

0 0.5

VCC = 3.3V

1.5 2.5

1.0 2.0 3.0
VA/VB (V)

TPC 10. Charge Injection vs.
Source Voltage

0

TA = 25ⴗC

–10

= 3.3V/2.5V

V

CC

= 0dBm

V

IN

–20

N/W ANALYZER

= RS = 50⍀

R

L

–30

–40

–50

–60

ATTENUATION (dB)

–70

–80

–90

–100

0.1 1000110

:

FREQUENCY (MHz)

100

TPC 13. Off Isolation vs. Frequency

0

TA = 25ⴗC

–2

= 3.3V/2.5V

V

CC

= 0dBm

V

IN

–4

N/W ANALYZER

= RS = 50⍀

R

L

–6

–8

ATTENUATION (dB)

–10

–12

–14

0.03 0.1 1000

:

110100

FREQUENCY (MHz)

TPC 11. Bandwidth vs. Frequency

4.0

VCC = 3.3V

3.5

3.0

2.5

ENABLE

2.0

TIME (ns)

1.5

1.0

0.5

0

–40 –20 0

TEMPERATURE (ⴗC)

ENABLE

DISABLE

VCC = 2.5V

DISABLE

20 806040

TPC 14. Enable/Disable Time
vs. Temperature

0

TA = 25ⴗC

–10

V

= 3.3V/2.5V

CC

V

= 0dBm

–20

IN

N/W ANALYZER

–30

R

= RS = 50⍀

L

–40

–50

–60

–70

ATTENUATION (dB)

–80

–90

–100

0.03 0.1 1.0

10 1000100

FREQUENCY (MHz)

TPC 12. Crosstalk vs. Frequency

100

VCC = 3.3V

90

= 1.5V p-p

V

IN

20dB ATTENUATION

80

70

60

50

40

JITTER (ps p-p)

30

20

10

0

0.5

0.7 0.9 1.1 1.3 1.5 1.7 1.9
DATA RATE (Gbps)

TPC 15. Jitter vs. Data Rate;
PRBS 31

100

95

VCC = 3.3V

90

V

= 1.5V p-p

IN

20dB ATTENUATION

85

80

75

70

EYE WIDTH (%)

65

60

% EYE WIDTH = ((CLOCK PERIOD –

55

JITTER p-p)/CLOCK PERIOD) ⴛ 100%

50

0.5
DATA RATE (Gbps)

1.51.31.10.90.7 1.7 1.9

TPC 16. Eye Width vs. Data Rate;
PRBS 31

50mV/DIV
200ps/DIV

VCC = 3.3V

= 1.5V p-p

V

IN

20dB
ATTENUATION
T

= 25ⴗC

A

TPC 17. Eye Pattern; 1.5 Gbps,

= 3.3 V, PRBS 31

V

CC

20mV/DIV
200ps/DIV

V

= 2.5V

CC

V

= 1.5V p-p

IN

20dB
ATTENUATION
T

= 25ⴗC

A

TPC 18. Eye Pattern; 1.244 Gbps,

= 2.5 V, PRBS 31

V

CC

REV. 0–6–

ADG3243

TIMING MEASUREMENT INFORMATION

For the following load circuit and waveforms, the notation that
is used is V

VVand V V or V V and V V

GENERATOR

NOTE S
PULSE GENERATOR FOR ALL PULSES:
FREQUENCY ⱕ 10MHz.

INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.

C

L

RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO Z
OF THE PULSE GENERATOR .

and V

IN

====

IN A OUT B IN B OUT A

PULSE

where

OUT

V

CC

R

OUT

L

R

L

DUT

t

ⱕ 2.5ns,

R

V

OUT

C

L

t

ⱕ 2.5ns,

F

V

IN

R

T

SW1

2 ⴛ V

GND

CC

Figure 1. Load Circuit

V

CONTROL
INPUT BEx

V

OUT

t

PLH

t

PLH

IH

V

T

0V

V

H

V

T

V

L

Figure 2. Propagation Delay

Test Conditions

Symbol VCC = 3.3 V ⴞ 0.3 V VCC = 2.5 V ⴞ 0.2 V Unit

R

L

V

⌬

C

L

V

T

500 500 Ω
300 150 mV
50 30 pF

1.5 0.9 V

Table II. Switch Position

Test S1

CONTROL INPUT BEx

V

SW1 @ 2V

CC

SW1 @ GND

OUT

V

OUT

= 0V

V

IN

= V

V

IN

t
t

CC

PLZ

PHZ

, t

PZL

, t

PZH

ENABLE

t

PZL

t

PZH

2 × V

CC

GND

DISABLE

t

PLZ

V

CC

V

T

t

PHZ

V

T

0V

V

INH

V

T

0V

V

CC

VL + V
V

L

V

H

VH –V

0V

⌬

⌬

Figure 3. Enable and Disable Times

REV. 0

–7–

ADG3243

V

IN

1.8V

V

OUT

0V

2.5V

SWITCH

INPU T

SWITCH

OUTPUT

2.5V SUPPLY

BUS SWITCH APPLICATIONS
Mixed Voltage Operation, Level Translation

Bus switches can provide an ideal solution for interfacing between
mixed voltage systems. The ADG3243 is suitable for applica­tions where voltage translation from 3.3 V technology to a lower
voltage technology is needed. This device can translate from

2.5 V to 1.8 V or bidirectionally from 3.3 V directly to 2.5 V.

Figure 4 shows a block diagram of a typical application in which a
user needs to interface between a 3.3 V ADC and a 2.5 V micro­processor. The microprocessor may not have 3.3 V tolerant inputs,
therefore placing the ADG3243 between the two devices allows
the devices to communicate easily. The bus switch directly
connects the two blocks, thus introducing minimal propagation
delay, timing skew, or noise.

3.3V

3.3V ADC

3.3V

ADG3243

2.5V

2.5V

MICROPROCESSOR

Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor

3.3 V to 2.5 V Translation

When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to within a voltage
threshold below the V

3.3V

2.5V

supply.

CC

3.3V

2.5V

ADG3243

2.5V

2.5 V to 1.8 V Translation

When VCC is 2.5 V and the input signal range is 0 V to VCC, the
maximum output signal will, as before, be clamped to within a
voltage threshold below the V

supply. In this case, the output

CC

will be limited to approximately 1.8 V, as shown in Figure 8.

2.5V

2.5V

ADG3243

1.8V

Figure 7. 2.5 V to 1.8 V Voltage Translation

Figure 8. 2.5 V to 1.8 V Voltage Translation

Bus Isolation

A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3243 is designed specifically for
applications that do not need drive yet require simple logic
functions, it solves this requirement. The device isolates access
to the bus, thus minimizing capacitance loading.

Figure 5. 3.3 V to 2.5 V Voltage Translation

In this case, the output will be limited to 2.5 V, as shown in
Figure 6. This device can be used for translation from 2.5 V to

3.3 V devices and also between two 3.3 V devices.

V

OUT

SWITCH

INPU T

3.3V SUPPLY

3.3V

V

IN

2.5V

SWITCH

OUTPUT

0V

Figure 6. 3.3 V to 2.5 V Voltage Translation

BUS SWITCH

LOCATION

LOAD A

LOAD B

LOAD C

LOAD D

BUS/

BACKPLANE

Figure 9. Location of Bus Switched in a Bus
Isolation Application

Hot Plug and Hot Swap Isolation

The ADG3243 is suitable for hot swap and hot plug applications.
The output signal of the ADG3243 is limited to a voltage that is
below the V

supply, as shown in Figures 6 and 8. Therefore

CC

the switch acts like a buffer to take the impact from hot insertion,
protecting vital and expensive chipsets from damage.

In hot plug applications, the system cannot be shut down when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 10 shows a typical example of this type of application.

REV. 0–8–

CPU

RAM

BUS

ADG3243 ADG3243

PLUG-IN
CARD (1)

PLUG-IN
CARD (2)

CARD I/O

CARD I/O

Figure 10. ADG3243 in a Hot Plug Application

There are many systems, such as docking stations, PCI boards
for servers, and line cards for telecommunications switches, that
require the ability to handle hot swapping. If the bus can be
isolated prior to insertion or removal, there is more control over
the hot swap event. This isolation can be achieved using bus

ADG3243

switches. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the backplane before any other signal or power pins.

Analog Switching

Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.

High Impedance during Power-Up/Power-Down

To ensure the high impedance state during power-up or power­down, BEx should be tied to V
minimum value of the resistor is determined by the current­sinking capability of the driver.

through a pull-up resistor; the

CC

REV. 0

–9–

ADG3243

OUTLINE DIMENSIONS

8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

2.90 BSC

1.60 BSC

PIN 1

1.30

1.15

0.90

0.15 MAX

7

2

1.95

BSC

5 6

4

2.80 BSC

0.65 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08

8

1 3

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-178BA

8ⴗ
4ⴗ
0ⴗ

0.60

0.45

0.30

REV. 0–10–

–11–

C04310–0–8/03(0)

–12–