Datasheet ADG3241 Datasheet (Analog Devices)

2.5 V/3.3 V, 1-Bit, 2-Port

Level Translator Bus Switch in SOT-66

ADG3241

FEATURES
225 ps Propagation Delay through the Switch

4.5  Switch Connection between Ports
Data Rate 1.5 Gbps

2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation

3.3 V to 2.5 V

3.3 V to 1.8 V

2.5 V to 1.8 V
Small Signal Bandwidth 770 MHz
Tiny 6-Lead SC70 Package and 6-Lead SOT-66 Package

APPLICATIONS

3.3 V to 1.8 V Voltage Translation

3.3 V to 2.5 V Voltage Translation

2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Switch Applications

GENERAL DESCRIPTION

The ADG3241 is a 2.5 V or 3.3 V, single digital switch. It is
designed on a low voltage CMOS process, which provides low
power dissipation yet gives high switching speed and very low on
resistance. This allows the input to be connected to the output
without additional propagation delay or generating additional
ground bounce noise.

The switch is enabled by means of the bus enable (BE) input
signal. This digital switch allows a bidirectional signal to be
switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.

This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition to this, a
level translating select pin (SEL) is included. When SEL is low,
V

is reduced internally, allowing for level translation between

CC

3.3 V inputs and 1.8 V outputs. This makes the device suited to
applications requiring level translation between different supplies,
such as converter to DSP/microcontroller interfacing.

FUNCTIONAL BLOCK DIAGRAM

A B

BE

PRODUCT HIGHLIGHTS

1. 3.3 V or 2.5 V supply operation.

2. Extremely low propagation delay through switch.

3. 4.5 Ω switches connect inputs to outputs.

4. Level/voltage translation.

5. Tiny SC70 package and SOT-66 package.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADG3241–SPECIFICATIONS

(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications T

1

otherwise noted.)

MIN

to T

, unless

MAX

B Version

Parameter Symbol Conditions Min Typ2Max Unit

DC ELECTRICAL CHARACTERISTICS

Input High Voltage V

Input Low Voltage V

Input Leakage Current I
OFF State Leakage Current I

INH

V

INH

INL

V

INL

I

OZ

ON State Leakage Current 0 ≤ A, B ≤ V
Maximum Pass Voltage V

P

VCC = 2.7 V to 3.6 V 2.0 V
VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 0.8 V
VCC = 2.3 V to 2.7 V 0.7 V

± 0.01 ± 1 µA

0 ≤ A, B ≤ V

CC

CC

± 0.01 ± 1 µA
± 0.01 ±1 µA

VA/VB = VCC = SEL = 3.3 V, IO = –5 µA 2.2 2.5 2.7 V

= VCC = SEL = 2.5 V, IO = –5 µA 1.5 1.8 2.1 V

V

A/VB

VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 µA 1.5 1.8 2.1 V

CAPACITANCE

3

A Port Off Capacitance CA OFF f = 1 MHz 3.5 pF
B Port Off Capacitance C
A, B Port On Capacitance C
Control Input Capacitance C

SWITCHING CHARACTERISTICS

Propagation Delay A to B or B to A, t
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B

3

PD

5

5

5

5

5

5

Maximum Data Rate V
Channel Jitter V

OFF f = 1 MHz 3.5 pF

B

, CB ON f = 1 MHz 7 pF

A

IN

4

t

, t

PHL

t

, t

PZH

t

, t

PHZ

t

, t

PZH

t

, t

PHZ

t

, t

PZH

t

, t

PHZ

f = 1 MHz 4 pF

CL = 50 pF, VCC = SEL = 3 V 0.225 ns

PLH

VCC = 3.0 V to 3.6 V; SEL = V

PZL

VCC = 3.0 V to 3.6 V; SEL = V

PLZ

VCC = 3.0 V to 3.6 V; SEL = 0 V 1 3 4 ns

PZL

VCC = 3.0 V to 3.6 V; SEL = 0 V 1 2.5 3.8 ns

PLZ

VCC = 2.3 V to 2.7 V; SEL = V

PZL

VCC = 2.3 V to 2.7 V; SEL = V

PLZ

= SEL = 3.3 V; VA/VB = 2 V 1.5 Gbps

CC

= SEL = 3.3 V; VA/VB = 2 V 45 ps p-p

CC

CC

CC

CC

CC

1 3.2 4.6 ns
13 4 ns

13 4 ns
1 2.5 3.4 ns

DIGITAL SWITCH

On Resistance R

ON

VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 4.5 8 Ω
V

= 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA 12 28 Ω

CC

= 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 5 9 Ω

V

CC

= 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 9 18 Ω

V

CC

V

= 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA 5 8 Ω

CC

VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA 12 Ω

POWER REQUIREMENTS

V

CC

Quiescent Power Supply Current I

Increase in ICC per Input

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Typical values are at 25°C, unless otherwise stated.

3

Guaranteed by design, not subject to production test.

4

The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.

5

See Timing Measurement Information section.

6

This current applies to the control pin BE only. The A and B ports contribute no significant ac or dc currents as they transition.

Specifications subject to change without notice.

6

⌬I

CC

CC

Digital Inputs = 0 V or VCC; SEL = V
Digital Inputs = 0 V or V
VCC = 3.6 V, BE = 3.0 V; SEL = V

; SEL = 0 V 0.1 0.2 mA

CC

CC

CC

2.3 3.6 V

0.01 1 µA

0.15 8 µA

REV. A–2–

ADG3241

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

SC70 Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 332°C/W

␪

JA

SOT-66 Package

Thermal Impedance . . . . . . . . . 191°C/W (4-Layer Board)

␪

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C

IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

Table I. Truth Table

BE SEL* Function

LL A = B, 3.3 V to 1.8 V Level Shifting
LH

A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting

HX Disconnect

*SEL = 0 V only when VDD = 3.3 V ± 10%.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3241 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A

–3–

ADG3241

PIN CONFIGURATION

6-Lead SC70

BE

GND

1

2

3

A

ADG3241

TOP VIEW

(Not to Scale)

6

SEL

5

V

CC

4

B

Pin No.
SC70 SOT-66 Mnemonic Description

16 BE Bus Enable (Active Low)
24 GND Ground Reference

Table II. Pin Function Descriptions

33 A Port A, Input or Output

6-Lead SOT-66

1

V

CC

ADG3241

2

SEL

TOP VIEW

3

A

(Not to Scale)

6

BE

5

B

4

GND

45 B Port B, Input or Output
51 V

CC

62 SEL

Positive Power Supply Voltage
Level Translation Select

ORDERING GUIDE

Temperature Package

Model Range Description Package Branding

ADG3241BKS-REEL –40°C to +85°CThin Shrink Small Outline Transistor Package (SC70) KS-6 SKA
ADG3241BKS-REEL7 –40°C to +85°CThin Shrink Small Outline Transistor Package (SC70) KS-6 SKA
ADG3241BKS-500RL7 –40°C to +85°CThin Shrink Small Outline Transistor Package (SC70) KS-6 SKA
ADG3241BRY-REEL7 –40°C to +85°CSmall Outline Transistor Package (SOT-66) RY-6-1 00

TERMINOLOGY

V

CC

Positive Power Supply Voltage.
GND Ground (0 V) Reference.
V

INH

V

INL

I

I

I

OZ

I

OL

V

P

Minimum Input Voltage for Logic 1.

Maximum Input Voltage for Logic 0.

Input Leakage Current at the Control Inputs.

OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.

ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.

Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when

the switch input voltage is equal to the supply voltage.
R

ON

Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified

amount of current through the switch.
C

OFF OFF Switch Capacitance.

X

C

ON ON Switch Capacitance.

X

C

IN

I

CC

Control Input Capacitance. This consists of BE and SEL.

Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.

It is measured when all control inputs are at a logic high or low level and the switches are OFF.
⌬I
t

t

PLH

PZH

CC

, t

, t

PHL

PZL

Extra power supply current component for the BE control input when the input is not driven at the supplies.

Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant

R

× CL, where CL is the load capacitance.

ON

Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on

in response to the control signal, BE.
t

PHZ

, t

PLZ

Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control

signal. It is measured as the time taken for the output voltage to change by V

from the original quiescent level,

⌬

with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.
Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.

REV. A–4–

Typical Performance Characteristics–ADG3241

)



(

ON

R

40

35

30

25

20

15

10

5

0

T

= 25C

A

SEL = V

0 0.5

CC

1.5 2.5 3.5
VA/VB (V

)

V

= 3V

CC

VCC = 3.3V

VCC = 3.6V

3.02.01.0

TPC 1. On Resistance vs.
Input Voltage

20

= 3.3V

V

CC

SEL = V

CC

15

()

10

ON

R

5

0

0 0.5

85C

40C

VA/VB (V)

25C

1.5

2.01.0

TPC 4. On Resistance vs. Input
Voltage for Different Temperatures

40

35

30

)

25



(

ON

20

R

15

10

TA = 25C

SEL = V

5

0

0 0.5

CC

VCC = 2.3V

VCC = 2.5V

VCC = 2.7V

1.5 2.5

VA/VB (V

)

TPC 2. On Resistance vs.
Input Voltage

15

= 2.5V

V

CC

SEL = V

CC

10

85C

()

ON

R

5

0

0 0.5

25C

VA/VB(V)

40C

1.0

TPC 5. On Resistance vs. Input
Voltage for Different Temperatures

40

TA = 25C

35

SEL = 0V

30

)

25



(

ON

20

R

15

10

5

0

3.02.01.0

0 0.5

1.0 2.0 3.0

VCC = 3V

= 3.3V

V

CC

VCC = 3.6V

1.5 2.5
VA/VB (V

)

3.5

TPC 3. On Resistance vs.
Input Voltage

1.2

3.0
TA = 25C

SEL = V
I

= –5A

O

0 0.5

CC

1.0 2.0 3.0

2.5

2.0

(V)

1.5

OUT

V

1.0

0.5

0

TPC 6. Pass Voltage vs. V

VCC = 3.6V

VCC = 3.3V

VCC = 3V

1.5 2.5 3.5
V

(V)

A/VB

CC

2.5

T

= 25C

A

SEL = V
I

O

CC

= –5A

1.0 2.0 3.0
VA/VB (V)

2.0

1.5

(V)

OUT

V

1.0

0.5

0

0 0.5

TPC 7. Pass Voltage vs. V

REV. A

VCC = 2.7V

VCC = 2.5V

VCC = 2.3V

1.5 2.5

CC

2.5

TA = 25C
SEL = 0V

2.0

I

= –5A

O

1.5

(V)

OUT

V

1.0

0.5

0

0 0.5

1.0 2.0 3.0

VCC = 3V

1.5 2.5
VA/VB (V)

TPC 8. Pass Voltage vs. V

–5–

VCC = 3.6V

VCC = 3.3V

CC

3.5

500

TA = 25C

450

400

350

300

VCC = 3.3V

250

(A)

SEL = 0V

CC

I

200

150

100

50

0

051015 20 25 30 35 40 45

VCC = SEL = 3.3V

VCC = SEL = 2.5V

ENABLE FREQUENCY (MHz)

TPC 9. ICC vs. Enable Frequency

50

ADG3241

3.0
TA = 25C
V

= 0V

A

2.5
BE = 0

(V)

OUT

V

2.0

1.5

1.0

0.5

0

0.02 0.04 0.06 0.08 0.100

VCC = 3.3V; SEL = 0V

VCC = SEL = 3.3V

VCC = SEL = 2.5V

IO (A)

TPC 10. Output Low Characteristic

2

1

0

–1

–2

–3

TA = 25C

–4

V

= 3.3V/2.5V

CC

–5

ATTENUATION (dB)

SEL = V

CC

VIN = 0dBm

–6

N/W ANALYZER:

–7

R

= RS = 50

L

–8

0.03 0.1 1.0

10 1000100

FREQUENCY (MHz)

TPC 13. Bandwidth vs. Frequency

3.0
T

= 25C

A

V

= V

A

CC

BE = 0

VCC = SEL = 3.3V

VCC = SEL = 2.5V

VCC = 3.3V; SEL = 0V

–0.08 –0.06 –0.04 –0.02 0

IO (A)

(V)

V

OUT

2.5

2.0

1.5

1.0

0.5

–0.10

0

TPC 11. Output High Characteristic

0

T

= 25C

A

–10

= 3.3V/2.5V

V

CC

SEL = V

–20

–30

–40

–50

–60

ATTENUATION (dB)

–70

–80

–90

–100

0.1 1000110

CC

VIN = 0dBm
N/W ANALYZER

= RS = 50

R

L

FREQUENCY (MHz)

:

100

TPC 14. Off Isolation vs.
Frequency

0

TA = 25C

SEL = V

CC

V

= 2.5V

–0.2

–0.4

(pC)

–0.6

INJ

Q

–0.8

–1.0

–1.2

ON OFF

C

= 1nF

L

0 0.5 1.0

CC

1.5 3.02.52.0

V

A/VB

(V)

TPC 12. Charge Injection vs.
Source Voltage

4.0

VCC = SEL = 3.3V

3.5

3.0

2.5

2.0

TIME (ns)

VCC = 3.3V, SEL = 0V

1.5

1.0

0.5

0

–40 –20 0

TEMPERATURE (C)

ENABLE

DISABLE

ENABLE

20 806040

TPC 15. Enable/Disable Time
vs. Temperature

VCC = 3.3V

DISABLE

4.0

3.5

ENABLE

3.0

2.5

DISABLE

2.0

TIME (ns)

1.5

1.0

0.5

0
–40 –20 0

TEMPERATURE (C)

VCC = SEL = 2.5V

20 806040

TPC 16. Enable/Disable Time
vs. Temperature

100

VCC = SEL = 3.3V

90

= 1.5V p-p

V

IN

20dB ATTENUATION

80

70

60

50

40

JITTER (ps p-p)

30

20

10

0

0.5

0.7 0.9 1.1 1.3 1.5 1.7 1.9
DATA RATE (Gbps)

TPC 17. Jitter vs. Data Rate;
PRBS 31

100

95

VCC = SEL = 3.3V

90

VIN = 1.5V p-p

20dB ATTENUATION

85

80

75

70

EYE WIDTH (%)

65

60

% EYE WIDTH = ((CLOCK PERIOD –

55

JITTER p-p)/CLOCK PERIOD)  100%

50

0.5
DATA RATE (Gbps)

1.51.31.10.90.7 1.7 1.9

TPC 18. Eye Width vs. Data
Rate; PRBS 31

REV. A–6–

50mV/DIV
200ps/DIV

VCC = 3.3V
SEL = 3.3V

= 1.5V p-p

V

IN

20dB
ATTENUATION
TA = 25C

20mV/DIV
200ps/DIV

= 2.5V

V

CC

SEL = 2.5V
V

= 1.5V p-p

IN

20dB
ATTENUATION
T

= 25C

A

ADG3241

TPC 19. Eye Pattern; 1.5 Gbps,
V

= 3.3 V, PRBS 31

CC

TPC 20. Eye Pattern; 1.244 Gbps,
V

= 2.5 V, PRBS 31

CC

REV. A

–7–

ADG3241

TIMING MEASUREMENT INFORMATION

For the following load circuit and waveforms, the notation that is used is VIN and V

VVand V V or V V and V V

====

IN A OUT B IN B OUT A

OUT

where

V

CC

DUT

t

ⱕ 2.5ns,

R

V

OUT

C

L

t

ⱕ 2.5ns,

F

V

PULSE

GENERATOR

NOTES
PULSE GENERATOR FOR ALL PULSES:
FREQUENCY ⱕ 10MHz.

INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.

C

L

IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO Z

R

T

OF THE PULSE GENERATOR.

IN

R

T

OUT

R

L

R

L

SW1

2  V

GND

Figure 1. Load Circuit

Test Conditions

Symbol VCC = 3.3 V ± 0.3 V (SEL = VCC)V

R

L

V

⌬

C

L

V

T

500 500 500 Ω
300 150 150 mV
50 30 30 pF

1.5 0.9 0.9 V

= 2.5 V ± 0.2 V (SEL = VCC)VCC = 3.3 V ± 0.3 V (SEL = 0 V) Unit

CC

V

CC

CONTROL
INPUT BE

V

OUT

t

PLH

t

PLH

IH

V

T

0V

V

H

V

T

V

L

Figure 2. Propagation Delay

CONTROL INPUT BE

V

SW1 @ 2V

CC

SW1 @ GND

OUT

V

OUT

= 0V

V

IN

VIN = V

Figure 3. Enable and Disable Times

CC

ENABLE

t

t

PZL

PZH

DISABLE

t

PLZ

V

CC

V

T

t

PHZ

V

T

0V

V

INH

V

T

0V

V

CC

VL + V
V

L

V

H

VH –V

0V

Table III. Switch Position

Test S1

, t

t

PLZ





t

PHZ

, t

PZL

PZH

2 × V
GND

CC

REV. A–8–

ADG3241

BUS SWITCH APPLICATIONS
Mixed Voltage Operation, Level Translation

Bus switches can provide an ideal solution for interfacing
between mixed voltage systems. The ADG3241 is suitable for
applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally
from 3.3 V directly to 2.5 V.

Figure 4 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V
microprocessor. The microprocessor may not have 3.3 V toler­ant inputs, therefore placing the ADG3241 between the two
devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.

3.3V

3.3V ADC

3.3V

ADG3241

2.5V

2.5V

MICROPROCESSOR

Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor

3.3 V to 2.5 V Translation

When VCC is 3.3 V (SEL = 3.3 V) and the input signal range is
0 V to V
within a voltage threshold below the V

, the maximum output signal will be clamped to

CC

3.3V

3.3V

supply.

CC

2.5V

ADG3241

2.5V

2.5V

2.5 V to 1.8 V Translation

When VCC is 2.5 V (SEL = 2.5 V) and the input signal range is
0 V to V
to within a voltage threshold below the V

, the maximum output signal will, as before, be clamped

CC

supply. In this case,

CC

the output will be limited to approximately 1.8 V, as shown
in Figure 8.

2.5V

V

OUT

OUTPUT

0V

ADG3241

2.5V SUPPLY

SWITCH

INPU T

SEL = 2.5V

2.5V

1.8V

SEL

= 2.5 V

V

IN

SEL

= V

CC

CC

2.5V

Figure 7. 2.5 V to 1.8 V Voltage Translation,

1.8V

SWITCH

Figure 8. 2.5 V to 1.8 V Voltage Translation,

3.3 V to 1.8 V Translation

The ADG3241 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
SEL pin. The SEL pin is an active low control pin. SEL acti­vates internal circuitry in the ADG3241 that allows voltage
translation between 3.3 V devices and 1.8 V devices.

3.3V

Figure 5. 3.3 V to 2.5 V Voltage Translation,

SEL

= V

CC

In this case, the output will be limited to 2.5 V, as shown in
Figure 6. This device can be used for translation from 2.5 V to

3.3 V devices and also between two 3.3 V devices.

V

OUT

2.5V

SWITCH

OUTPUT

0V

Figure 6. 3.3 V to 2.5 V Voltage Translation,

REV. A

SWITCH

INPU T

3.3V SUPPLY

SEL = 3.3V

3.3V

V

IN

SEL

= V

CC

–9–

3.3V

Figure 9. 3.3 V to 1.8 V Voltage Translation,

ADG3241

1.8V

SEL

= 0 V

When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
SEL is unused, it should be tied directly to V

V

1.8V

SWITCH

OUT

OUTPUT

0V

SWITCH

INPU T

3.3V SUPPLY

SEL = 0V

3.3V

Figure 10. 3.3 V to 1.8 V Voltage Translation,

.

CC

V

IN

SEL

= 0 V

ADG3241

Bus Isolation

A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3241 is designed specifically for
applications that do not need drive yet require simple logic
functions, it solves this requirement. The device isolates access
to the bus, thus minimizing capacitance loading.

BUS SWITCH

LOCATION

LOAD A

LOAD B

LOAD C

LOAD D

BUS/

BACKPLANE

Figure 11. Location of Bus Switched in a Bus
Isolation Application

Hot Plug and Hot Swap Isolation

The ADG3241 is suitable for hot swap and hot plug applications.
The output signal of the ADG3241 is limited to a voltage that is
below the V

supply, as shown in Figures 6, 8, and 10. Therefore

CC

the switch acts like a buffer to take the impact from hot insertion,
protecting vital and expensive chipsets from damage.

In hot plug applications, the system cannot be shut down when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 12 shows a typical example of this type of application.

There are many systems, such as docking stations, PCI boards
for servers, and line cards for telecommunications switches, that
require the ability to handle hot swapping. If the bus can be
isolated prior to insertion or removal, there is more control over
the hot swap event. This isolation can be achieved using bus
switches. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the backplane before any other signal or power pins.

Analog Switching

Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.

High Impedance During Power-Up/Power-Down

To ensure the high impedance state during power-up or power­down, BE should be tied to V

through a pull-up resistor; the

CC

minimum value of the resistor is determined by the current­sinking capability of the driver.

CPU

RAM

ADG3241 ADG3241

PLUG-IN
CARD (1)

PLUG-IN
CARD (2)

CARD I/O

CARD I/O

Figure 12. ADG3241 in a Hot Plug Application

REV. A–10–

OUTLINE DIMENSIONS

6-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-6)

Dimensions shown in millimeters

2.00 BSC

4

5

1.25 BSC

1.00

0.90

0.70

0.10 MAX

6

1

2

PIN 1

1.30 BSC

0.30

0.15

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203AB

3

0.65 BSC

2.10 BSC

1.10 MAX

SEATING
PLANE

0.22

0.08

0.46

8
4
0

0.36

0.26

6-Lead Small Outline Transistor Package [SOT-66]

(RY-6-1)

Dimensions shown in millimeters

ADG3241

1.30

1.20

1.10

0.18

0.17

0.13

12 MAX

1.70

1.66

1.50

6

5

TOP VIEW

PIN 1

1 3

2

0.34 MAX

0.27 NOM

0.26

0.19

4

SEATING
PLANE

0.11

1.70

1.65

1.50

0.10 NOM

0.05 MIN

0.60

0.57

0.53

0.20
MIN

BOTTOM

VIEW

0.25 MAX

0.17 MIN

0.50
BSC

0.30

0.23

0.10

REV. A

–11–

ADG3241

Revision History

Location Page

10/04—Data Sheet changed from REV. 0 to REV. A.

Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Changes to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

C04221–0–11/04(A)

–12–

REV. A