Page 1
LC2MOS
Data Sheet
FEATURES
44 V supply maximum rating
±15 V analog signal range
Low R
Low leakage: 0.5 nA typical
Break-before-make switching
Single supply operation possible
Extended plastic temperature range: −40°C to +85°C
TTL/CMOS compatible
Available in 16-lead PDIP/SOIC and 20-pead PLCC packages
Pin compatible to DG211/DG212
: 115 Ω maximum
ON
Quad SPST Switches
ADG211A/ADG212A
FUNCTIONAL BLOCK DIAGRAM
ADG211A
IN1
IN2
IN3
IN4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 I NPUT.
Figure 1.
ADG212A
IN1
IN2
IN3
IN4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 I NPUT.
Figure 2.
S1
D1
S2
D2
S3
D3
S4
D4
10950-001
S1
D1
S2
D2
S3
D3
S4
D4
10950-002
GENERAL DESCRIPTION
The ADG211A and ADG212A are monolithic CMOS devices
comprising four independently selectable switches. They are
designed on an enhanced LC
increased signal handling capability of ±15 V. These switches
also feature high switching speeds and low R
The ADG211A and ADG212A consist of four SPST switches.
They differ only in that the digital control logic is inverted. In
multiplexer applications, all switches exhibit break-before-make
switching action when driven simultaneously. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
Rev. C Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2
MOS process, which gives an
.
ON
PRODUCT HIGHLIGHTS
1. Extended Signal Range.
These switches are fabricated on an enhanced LC
process, resulting in high breakdown and an increased
analog signal range of ±15 V.
2. Single Supply Operation.
For applications where the analog signal is unipolar (0 V to
15 V), the switches can be operated from a single 15 V
supply.
3. Low Leakage.
Leakage currents in the range of 500 pA make these
switches suitable for high precision circuits. The added
feature of break-before-make allows for multiple outputs
to be tied together for multiplexer applications while
keeping leakage errors to a minimum.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
2
MOS
Page 2
ADG211A/ADG212A Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
REVISION HISTORY
10/12—Rev. B to Rev. C
Updated Format .................................................................. Universal
Added Pin Descriptions, Table 3 .................................................... 5
Moved Tabl e 4 ................................................................................... 5
Changes to Figure 5, Figure 6, Figure 8, and Figure 9 ................. 6
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
9/02—Rev. A to Re v. B
ESD Caution...................................................................................4
Pin Configurations and Function Descriptions ............................5
Typical Performance Characteristics ..............................................6
Ter m ino l og y .......................................................................................9
Test Circuits ..................................................................................... 10
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 13
Rev. C | Page 2 of 16
Page 3
Data Sheet ADG211A/ADG212A
INL or INH
1 µA
t
30
ns
See Figure 24
Channel-to-Channel Crosstalk
80
dB
See Figure 27
ISS
0.2 mA
SPECIFICATIONS
VDD = +15 V, VSS = −15 V, VL = 5 V, unless otherwise noted.
Table 1.
25°C −40°C to +85°C
Parameter
ANALOG SWITCH
Analog Signal Range ±15 ±15 V
RON 115 175 Ω −10 V ≤ VS ≤ +10 V, IDS = 1 mA, see Figure 21
RON vs. VD (VS) 20 %
RON Drift 0.5 %/°C
RON Match 5 % VS = 0 V, IDS = 1 mA
LEAKAGE CURRENTS
IS (Off ) 0.5 nA
Off Input Leakage 5 100 nA
ID (Off ) 0.5 nA
Off Output Leakage 5 100 nA
ID (On) 0.5 nA VD = VS = ±14 V; see Figure 23
On Channel Leakage 5 200 nA
DIGITAL CONTROL
V
, Input High Voltage 2.4 V TTL compatibility is independent of VL
INH
V
, Input Low Voltage 0.8 V
INL
Unit Test Conditions/Comments Min Typ Max Min Typ Max
VD = ±14 V; VS = 14 V; see Figure 22
VD = ±14 V; VS = 14 V; see Figure 22
CIN, Digital Input Capacitance 5 pF
DYNAMIC CHARACTERISTICS
1
OPEN
1
t
600 ns See Figure 25
ON
1
t
450 ns See Figure 25
OFF
Off Isolation 80 dB
= 10 V (p-p); f = 100 kHz;
V
S
R
= 75 Ω; see Figure 26
L
CS (Off ) 5 pF
CD (Off ) 5 pF
CS, CD (On) 16 pF
Q
, Charge Injection 20 pC RS = 0 Ω; CL = 1000 pF; VS = 0 V; see Figure 28
INJ
POWER SUPPLY
IDD 0.6 mA Digital inputs = V
INL
or V
INH
IDD 1 mA
ISS 0.1 mA
IL 0.9 mA
1
Sample tested at 25°C to ensure compliance.
Rev. C | Page 3 of 16
Page 4
ADG211A/ADG212A Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise stated.
Table 2.
Parameter Rating
VDD to VSS 44 V
VDD to GND 25 V
VSS to GND −25 V
VL to GND −0.3 V, 25 V
Analog Inputs1
Voltage at S, D VSS − 0.3 V to VDD + 0.3 V
Continuous Current, S or D 30 mA
Pulsed Current S or D
1 ms Duration, 10% Duty Cycle 70 mA
Digital Inputs1
Voltage at IN
Power Dissipation (Any Package)
Up to +75°C 470 mW
Derates above +75°C by 6 mW/°C
Operating Temperature −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 10 sec) +300°C
1
Overvoltage at IN, S, or D will be clamped by diodes. Current should be
limited to the Maximum Rating listed in Table 2.
− 2 V to VDD + 2 V or
V
SS
20 mA, Whichever
Occurs First
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 4 of 16
Page 5
Data Sheet ADG211A/ADG212A
8
10
IN4
Logic Control Input.
14
18
S2
Source Terminal. Can be an input or output.
1 0 Off
IN1
1
D1
2
S1
3
V
SS
4
IN2
16
D2
15
S2
14
V
DD
13
GND
5
S4
6
D4
7
V
L
12
S3
11
D3
10
IN4
8
IN3
9
ADG211A/
ADG212A
TOP VIEW
(Not to S cale)
10950-003
NOTES
1. NIC = NO INTERNAL CONNE CTION.
1 20 1923
4
5
6
7
8
18
17
16
15
14
9
10
11 12 13
S1
V
SS
NIC
GND
S4
S2
V
DD
NIC
V
L
S3
D1
IN1
NIC
IN2
D2
D4
IN4
NIC
IM3
D3
PIN 1
INDENTFIER
ADG211A/
ADG212A
TOP VIEW
(Not to S cale)
10950-004
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. PDIP, SOIC Pin Configuration
Figure 4. PLCC Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
PD IP, SOIC PLCC
Mnemonic Description
1 2 IN1 Logic Control Input.
2 3 D1 Drain Terminal. Can be an input or output.
3 4 S1 Source Terminal. Can be an input or output.
4 5 VSS Most Negative Power Supply Potential.
5 7 GND Ground (0 V) Reference.
6 8 S4 Source Terminal. Can be an input or output.
7 9 D4 Drain Terminal. Can be an input or output.
9 12 IN3 Logic Control Input.
10 13 D3 Drain Terminal. Can be an input or output.
11 14 S3 Source Terminal. Can be an input or output.
12 15 VL Logic Supply Voltage.
13 17 VDD Most Positive Power Supply Potential.
15 19 D2 Drain Terminal. Can be an input or output.
16 20 IN2 Logic Control Input.
1, 6, 11, 16 NIC No Internal Connection.
Table 4. Truth Table
ADG211A In
ADG212A In
0 1 On
Switch Condition
Rev. C | Page 5 of 16
Page 6
ADG211A/ADG212A Data Sheet
120
0
30
60
90
–15 –10 –5 0 5 10 15
R
ON
(Ω)
V
D
(V
S
) (V)
V
DD
= +15V
V
SS
= –15V
70°C
25°C
0°C
10950-005
120
0
30
60
90
–10 –5 0 5 10
R
ON
(Ω)
VD (VS) (V)
V
DD
= +10V
V
SS
= –10V
70°C
25°C
0°C
10950-006
100
10
1
0.1
0.01
20 90807060504030
CURRENT (nA)
TEMPERATURE (°C)
V
DD
= +15V
V
SS
= –15V
ID (ON)
I
D
(OFF)
I
S
(OFF)
10950-007
120
0
30
60
90
0 5 10 15
R
ON
(Ω)
V
D
(V
S
) (V)
V
DD
= 15V
V
SS
= 0V
70°C
25°C
0°C
10950-008
150
0
30
60
90
120
0 5 10
R
ON
(Ω)
VD (V
S
) (V)
V
DD
= 10V
V
SS
= 0V
70°C
25°C
0°C
10950-009
2.5
2.0
1.5
1.0
0.5
0
10 11 12 13 14 15
TRIGGER LEVEL (V)
SUPPLY VOLTAGE (V)
TEMP = 0° C TO 70°C
10950-010
TYPICAL PERFORMANCE CHARACTERISTICS
The switches can comfortably operate anywhere in the 10 V to 15 V single or dual supply range, with only a slight degradation in
performance. The following graphs show the relevant performance curves. The test circuits and test conditions are given in a following
section, Test Circuits.
Figure 5. R
as a Function of VD (VS), Dual ±15 V Supplies
ON
Figure 6. RON as a Function of VD (VS), Dual ±10 V Supplies
Figure 8. R
as a Function of VD (VS), Single +15 V Supply
ON
Figure 9. RON as a Function of VD (VS), Single +10 V Supply
(Note That Leakage Current Reduces as the Supply Voltages Reduce)
Figure 7. Leakage Current as a Function of Temperature
Figure 10. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply
Voltage
Rev. C | Page 6 of 16
Page 7
Data Sheet ADG211A/ADG212A
220
80
100
120
140
160
180
200
10 11 12 13 14 15
t
ON
(ns)
SUPPLY VOLTAGE (±V)
70°C
25°C
0°C
10950-011
80
60
40
20
0
10 11 12 13 14 15
t
OFF
(ns)
SUPPLY VOLTAGE (±V)
70°C
25°C
0°C
10950-012
50
60
70
80
90
10 11 12 13 14 15
OFF ISOLATION (dB)
SUPPLY VOLTAGE (V)
SINGLE SUPPLY
DUAL SUPPLY
10950-013
220
80
100
120
140
160
180
200
10 11 12 13 14 15
t
ON
(ns)
SUPPLY VOLTAGE (V)
70°C
25°C
0°C
10950-014
80
60
40
20
0
10 11 12 13 14 15
t
OFF
(ns)
SUPPLY VOLTAGE (V)
70°C
25°C
0°C
10950-015
60
40
20
0
–20
–40
–16 –12 –8 –4 0 4 8 12 16
CHARGE INJECT ION (pC)
VS (V)
VDD = +15V
V
SS
= –15V
V
DD
= +15V
V
SS
= 0V
10950-016
Figure 11. tON vs. Supply Voltage (Dual Supply)
Figure 12. t
vs. Supply Voltage (Dual Supply)
OFF
Figure 14. tON vs. Supply Voltage (Single Supply)
Figure 15. t
vs. Supply Voltage (Single Supply)
OFF
Figure 13. Off Isolation and Channel-to-Channel Crosstalk vs. Supply Voltage
Figure 16. Charge Injection vs. Source Voltage (V
) for Dual and Single 15 V
S
Supplies
Rev. C | Page 7 of 16
Page 8
ADG211A/ADG212A Data Sheet
60
–40
–20
0
20
40
–16 –12 –8 –4 0 4 8 12 16
CHARGE INJECT ION (pC)
VS (V)
VDD = +10V
V
SS
= –10V
V
DD
= +10V
V
SS
= 0V
10950-017
0.4
0
0.1
0.2
0.3
10 1514131211
I
SS
(µA)
SUPPLY VOLTAGE (±V)
0°C
25°C
70°C
10950-018
0.7
0.6
0.5
0.4
0.3
0.2
0.1
10 11 12 13 14 15
I
DD
(mA)
SUPPLY VOLTAGE (±V)
0°C
25°C
70°C
10950-019
0.7
0.6
0.5
0.4
0.3
0.2
0.1
10 11 12 13 14 15
I
DD
(mA)
SUPPLY VOLTAGE (V)
0°C
25°C
70°C
10950-020
Figure 17. Charge Injection vs. Source Voltage for Dual and Single 10 V
Supplies
Figure 18. I
vs. Supply Voltage (Dual Supply)
SS
Figure 19. I
vs. Supply Voltage, (Dual Supply)
DD
Figure 20. I
vs. Supply Voltage (Single Supply)
DD
Rev. C | Page 8 of 16
Page 9
Data Sheet ADG211A/ADG212A
TERMINOLOGY
t
RON
Ohmic resistance between the out and S terminals.
R
Match
ON
Difference between the R
(Off)
I
S
of any two channels.
ON
Source terminal leakage current when the switch is off.
I
(Off)
D
Drain terminal leakage current when the switch is off.
I
(On)
D
Leakage current that flows from the closed switch into the body.
V
(VS)
D
Analog voltage on the D, S terminals.
C
(Off)
S
Switch input capacitance off condition.
C
(Off)
D
Switch output capacitance off condition.
C
IN
Digital input capacitance.
C
, CS (On)
D
Input or output capacitance when the switch is on.
t
ON
Delay time between the 50% and 90% points of the digital input
and switch on condition.
OFF
Delay time between the 50% and 90% points of the digital input
and switch off condition.
t
OPEN
Off time measured between 50% points of both switches, which
are connected as a multiplexer when switching from one
address state to another.
V
INL
Maximum input voltage for a logic low.
V
INH
Minimum input voltage for a logic high.
I
(I
)
INL
INH
Input current of the digital input.
V
DD
Most positive voltage supply.
V
SS
Most negative voltage supply.
V
L
Logic supply voltage.
I
DD
Positive supply current.
I
SS
Negative supply current.
Rev. C | Page 9 of 16
Page 10
ADG211A/ADG212A Data Sheet
V
V
V
*
TEST CIRCUITS
I
DS
V1
Figure 21.
D
DS
10950-021
V
SD
S
Figure 23.
ID (OFF)IS (OFF)
AA
V
D
10950-022
S
S
S
RON = V1/I
SD
ID (ON)
A
V
D
10950-023
Figure 22.
+5V
+15
V
V
L
DD
D1S1
2V
D2S2
14pF
*
V
IN
BOTH THE BUFFER AND I NVERTER SHOULD
HAVE THE SAME PROPAG ATION DELAY.
IN1
*
IN2
V
GND
SS
–15V
330Ω
ADG211A
V
OUT
ADG212A
3V
V
IN
3V
V
IN
V
OUT
t
OPEN
50%
10950-024
Figure 24.
V
+5V
DD
V
V
L
DD
DS
2V
IN
V
IN
V
GND
V
330Ω
SS
SS
V
14pF
ADG211A
OUT
ADG212A
Figure 25.
3V
V
50% 50%
IN
3V
50% 50%
V
IN
V
OUT
t
ON
90% 90%
t
OFF
10950-025
Rev. C | Page 10 of 16
Page 11
Data Sheet ADG211A/ADG212A
V
SS
V
DD
V
DD
V
S
+5V
V
L
GND
V
SS
V
OUT
DS
V
IN
R
L
75Ω
ADG211A: V
IN
= 5V
ADG212A: V
IN
= 0V
OFF ISOLATION =
20 × log |V
S
/V
OUT
|
10950-026
V
DD
V
DD
+5V
V
L
V
SS
GND
V
SS
V
IN
R
L
75Ω
ADG211A: V
IN
= 0V
ADG212A: V
IN
= 5V
CHANNEL-TO-CHANNEL
CROSSTAL K = 20 × log |VS/V
OUT
|
V
S
DS
V
IN
75Ω
SD
NCV
OUT
10950-027
V
IN
V
OUT
5V
0V
ΔV
OUT
Q
INJ
= CL × ΔV
OUT
V
S
V
OUT
DS
C
L
1µF
V
IN
AD711
R
S
V
DD
V
DD
+5V
V
L
V
SS
GND
V
SS
10950-028
Figure 26. Off Isolation
Figure 27. Channel-to-Channel Crosstalk
Figure 28. Charge Injection
Rev. C | Page 11 of 16
Page 12
ADG211A/ADG212A Data Sheet
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
1
0.100 (2.5 4)
BSC
0.210 (5.33)
MAX
0.150 (3.8 1)
0.130 (3.3 0)
0.115 (2.92)
0.022 (0.5 6)
0.018 (0.4 6)
0.014 (0.3 6)
0.070 (1.7 8)
0.060 (1.5 2)
0.045 (1.1 4)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMET ER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE O NLY AND ARE NOT APP RO P RIATE FOR USE I N DE SIGN.
CORNER LEA DS MAY BE CONFIGURED AS W HOLE OR HALF LE ADS.
Figure 29. 16-Lead Plastic Dual In-Line Package [PDIP]
9
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
8
0.060 (1.52)
0.015
(0.38)
0.015 (0.38)
MIN
SEATING
PLANE
0.005 (0.13)
MIN
COMPLIANT TO J EDEC STANDARDS MS-001-AB
GAUGE
PLANE
0.325 (8.2 6)
0.310 (7.8 7)
0.300 (7.6 2)
MAX
0.430 (10.92)
Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
10.00 (0.3937)
9.80 (0.3858)
MAX
0.195 (4.9 5)
0.130 (3.3 0)
0.115 (2.92)
0.014 (0.3 6)
0.010 (0.2 5)
0.008 (0.2 0)
073106-B
4.00 (0.1575)
3.80 (0.1496)
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
CONTRO LLING DIMENSIONS ARE IN MILLIME TERS; I NC H D IMENSIONS
(IN PARENTHE SE S ) ARE ROUNDED-OFF M ILLIM E TER EQUIVALENTS F OR
REFERENCE O NLYAND ARE NOT APPROPRIATE F O R US E I N DE S IGN.
16
1
1.27 (0. 05 00 )
BSC
0.51 (0.0201)
0.31 (0.0122)
COMPLIANT TO J E DEC STANDARDS MS-012-AC
9
6.20 (0. 24 41 )
5.80 (0. 22 83 )
8
1.75 (0. 06 89 )
1.35 (0. 05 31 )
SEATING
PLANE
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0. 0 19 7)
0.25 (0. 0 09 8)
1.27 (0.0500)
0.40 (0.0157)
45°
060606-A
Figure 30.16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
Rev. C | Page 12 of 16
Page 13
Data Sheet ADG211A/ADG212A
0.048 (1.22 )
0.048 (1.22)
0.042 (1.07)
0.020
(0.51)
0.042 (1.07)
3
4
PIN 1
IDENTIFIER
TOP VIEW
(PINS D OWN)
8
9
0.356 (9.04)
R
0.350 (8.89)
0.395 (10.03)
0.385 (9.78)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.056 (1.42)
0.042 (1.07)
19
18
0.050
(1.27)
BSC
14
13
SQ
SQ
COMPLIANT TO JEDEC STANDARDS MO-047-AA
0.180 (4.57)
0.165 (4.19)
0.120 (3.04)
0.090 (2.29)
0.20 (0.51)
MIN
0.021 (0.53)
0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
0.045 (1.14)
0.025 (0.64)
0.330 (8.38)
0.290 (7.37)
R
0.020 (0.50)
R
BOTTOM
VIEW
(PIN S UP)
Figure 31. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG211AKN −40°C to +85°C 16-Lead PDIP N-16
ADG211AKNZ −40°C to +85°C 16-Lead PDIP N-16
ADG211AKPZ −40°C to +85°C 20-Lead PLCC P-20
ADG211AKR −40°C to +85°C 16-Lead SOIC_N R-16
ADG211AKRZ −40°C to +85°C 16-Lead SOIC_N R-16
ADG211AKRZ-REEL −40°C to +85°C 16-Lead SOIC_N R-16
ADG211AKRZ-REEL7 −40°C to +85°C 16-Lead SOIC_N R-16
ADG212AKNZ −40°C to +85°C 16-Lead PDIP N-16
ADG212AKPZ −40°C to +85°C 20-Lead PLCC P-20
ADG212AKPZ-REEL −40°C to +85°C 20-Lead PLCC P-20
ADG212AKR −40°C to +85°C 16-Lead SOIC_N R-16
ADG212AKRZ −40°C to +85°C 16-Lead SOIC_N R-16
ADG212AKRZ-REEL −40°C to +85°C 16-Lead SOIC_N R-16
1
Z = RoHS Compliant Part.
Rev. C | Page 13 of 16
Page 14
ADG211A/ADG212A Data Sheet
NOTES
Rev. C | Page 14 of 16
Page 15
Data Sheet ADG211A/ADG212A
NOTES
Rev. C | Page 15 of 16
Page 16
ADG211A/ADG212A Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10950-0-10/12(C)
Rev. C | Page 16 of 16
Loading...