0.2 Ω on resistance flatness
±3.3 V to ±8 V dual supply operation
3.3 V to 16 V single supply operation
No V
supply required
L
3 V logic-compatible inputs
Rail-to-rail operation
Continuous current per channel
LFCSP package: 385 mA
TSSOP package: 238 mA
16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Communication systems
Medical systems
Audio signal routing
Video signal routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Relay replacements
+5 V, and +3.3 V Dual SPDT Switches
ADG1636
FUNCTIONAL BLOCK DIAGRAMS
S1A
S1B
IN1
IN2
S2A
S2B
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
S1A
D1
S1B
NOTES
1. SWITCHES SHOWN FOR A 1 INPUT LOGIC.
ADG1636
Figure 1. 16-Lead TSSOP
ADG1636
LOGIC
IN1 IN2
EN
Figure 2. 16-Lead LFCSP
D1
D2
S2A
D2
S2B
07983-001
07983-002
GENERAL DESCRIPTION
The ADG1636 is a monolithic CMOS device containing two
independently selectable single-pole/double-throw (SPDT)
switches. An EN input is used to enable or disable the device.
When disabled, all channels are switched off. Each switch
conducts equally well in both directions when on and has
an input signal range that extends to the supplies. In the off
condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use
in multiplexer applications.
The ultralow on resistance of these switches make them ideal
solutions for data acquisition and gain switching applications where
low on resistance and distortion is critical. The on resistance profile
is very flat over the full analog input range, ensuring excellent
linearity and low distortion when switching audio signals.
The CMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and batterypowered instruments.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
−40°C to
Parameter 25°C
+85°C
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 1 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 23
1.2 1.4 1.6 Ω max VDD = ±4.5 V, VSS = ±4.5 V
On Resistance Match Between Channels (∆RON) 0.04 Ω typ VS = ±4.5 V, IS = −10 mA
0.08 0.09 0.1 Ω max
On Resistance Flatness (R
) 0.2 Ω typ VS = ±4.5 V, IS = −10 mA
FLAT(ON)
0.25 0.29 0.34 Ω max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off) ±0.1 nA typ
±0.25 ±1 ±4 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ
±0.25 ±2 ±10 nA max
Channel On Leakage, ID, IS (On) ±0.3 nA typ VS = VD = ±4.5 V; see Figure 25
±0.6 ±2 ±12 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.005 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
130 ns typ RL = 300 Ω, CL = 35 pF
TRANSITION
209 245 273 ns max VS = 2.5 V; see Figure 30
tON (EN) 119 ns typ RL = 300 Ω, CL = 35 pF
148 166 176 ns max VS = 2.5 V; see Figure 30
t
(EN) 182 ns typ RL = 300 Ω, CL = 35 pF
OFF
228 259 281 ns max VS = 2.5 V; see Figure 30
Break-Before-Make Time Delay, tD 30 ns typ RL = 300 Ω, CL = 35 pF
17 ns min VS1 = VS2 = 2.5 V; see Figure 31
Charge Injection 130 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
Channel-to-Channel Crosstalk 90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion + Noise (THD + N) 0.007 % typ
−3 dB Bandwidth 25 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 27
CS (Off) 68 pF typ VS = 0 V, f = 1 MHz
CD (Off) 127 pF typ VS = 0 V, f = 1 MHz
CD, CS (On) 220 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1.0 μA max
VDD/VSS ±3.3/±8 V min/max
1
Guaranteed by design, not subject to production test.
Analog Signal Range 0 V to VDD V
On Resistance (RON) 0.95 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 23
1.1 1.25 1.45 Ω max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between Channels (∆RON) 0.03 Ω typ VS = 10 V, IS = −10 mA
0.06 0.07 0.08 Ω max
On Resistance Flatness (R
) 0.2 Ω typ VS = 0 V to 10 V, IS = −10 mA
FLAT(ON)
0.23 0.27 0.32 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V; see Figure 24
±0.25 ±1 ±4 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V; see Figure 24
±0.25 ±2 ±10 nA max
Channel On Leakage, ID, IS (On) ±0.3 nA typ VS = VD = 1 V or 10 V; see Figure 25
±0.6 ±2 ±12 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.001 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
100 ns typ RL = 300 Ω, CL = 35 pF
TRANSITION
153 183 206 ns max VS = 8 V; see Figure 30
tON (EN) 80 ns typ RL = 300 Ω, CL = 35 pF
95 103 110 ns max VS = 8 V; see Figure 30
t
(EN) 133 ns typ RL = 300 Ω, CL = 35 pF
OFF
161 187 210 ns max VS = 8 V; see Figure 30
Break-Before-Make Time Delay, tD 25 ns typ RL = 300 Ω, CL = 35 pF
17 ns min VS1 = VS2 = 8 V; see Figure 31
Charge Injection 150 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
Channel-to-Channel Crosstalk 90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion + Noise (THD + N) 0.013 % typ
−3 dB Bandwidth 27 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 27
CS (Off) 65 pF typ VS = 6 V, f = 1 MHz
CD (Off) 120 pF typ VS = 6 V, f = 1 MHz
CD, CS (On) 216 pF typ VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 12 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
IDD 230 μA typ Digital inputs = 5 V
360 μA max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.
Analog Signal Range 0 V to VDD V
On Resistance (RON) 1.7 Ω typ VS = 0 V to 4.5 V, IS = −10 mA; see Figure 23
2.15 2.4 2.7 Ω max VDD = 4.5 V, VSS = 0 V
On Resistance Match Between Channels (∆RON) 0.05 Ω typ VS = 0 V to 4.5 V, IS = −10 mA
0.09 0.12 0.15 Ω max
On Resistance Flatness (R
) 0.4 Ω typ VS = 0 V to 4.5 V, IS = −10 mA
FLAT(ON)
0.53 0.55 0.6 Ω max
LEAKAGE CURRENTS VDD = 5.5 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 24
±0.25 ±1 ±4 nA max
Drain Off Leakage, ID (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 24
±0.25 ±2 ±10 nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = 1 V or 4.5 V; see Figure 25
±0.6 ±2 ±12 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.001 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
160 ns typ RL = 300 Ω, CL = 35 pF
TRANSITION
271 319 355 ns max VS = 2.5 V; see Figure 30
tON (EN) 132 ns typ RL = 300 Ω, CL = 35 pF
172 185 201 ns max VS = 2.5 V; see Figure 30
t
(EN) 210 ns typ RL = 300 Ω, CL = 35 pF
OFF
268 313 345 ns max VS = 2.5 V; see Figure 30
Break-Before-Make Time Delay, tD 30 ns typ RL = 300 Ω, CL = 35 pF
17 ns min VS1 = VS2 = 2.5 V; see Figure 31
Charge Injection 70 pC typ VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation 70 dB typ
Channel-to-Channel Crosstalk 90 dB typ
Total Harmonic Distortion + Noise (THD + N) 0.09 % typ
−3 dB Bandwidth 26 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 27
CS (Off) 76 pF typ VS = 2.5 V, f = 1 MHz
CD (Off) 145 pF typ VS = 2.5 V, f = 1 MHz
CD, CS (On) 237 pF typ VS = 2.5 V, f = 1 MHz
POWER REQUIREMENTS VDD = 5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1.0 1.0 μA max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.
Analog Signal Range 0 V to VDD V
On Resistance (RON) 3.2 3.4 3.6 Ω typ VS = 0 V to VDD, IS = −10 mA; see Figure 23
V
On Resistance Match Between Channels (∆RON) 0.06 0.07 0.08 Ω typ VS = 0 V to VDD, IS = −10 mA
On Resistance Flatness (R
) 1.2 1.3 1.4 Ω typ VS = 0 V to VDD, IS = −10 mA
FLAT(ON)
LEAKAGE CURRENTS VDD = 3.6 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 24
±0.25 ±1 ±4 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 24
±0.25 ±2 ±10 nA max
Channel On Leakage, ID, IS (On) ±0.05 nA typ VS = VD = 0.6 V or 3 V; see Figure 25
±0.6 ±2 ±12 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.001 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
275 ns typ RL = 300 Ω, CL = 35 pF
TRANSITION
449 506 550 ns max VS = 1.5 V; see Figure 30
tON (EN) 225 ns typ RL = 300 Ω, CL = 35 pF
306 327 338 ns max VS = 1.5 V; see Figure 30
t
(EN) 340 ns typ RL = 300 Ω, CL = 35 pF
OFF
454 512 553 ns max VS = 1.5 V; see Figure 30
Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF
28 ns min VS1 = VS2 = 1.5 V; see Figure 31
Charge Injection 50 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26
Channel-to-Channel Crosstalk 90 dB typ
Total Harmonic Distortion + Noise (THD + N) 0.19 % typ
−3 dB Bandwidth 26 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 27
CS (Off) 80 pF typ VS = 1.5 V, f = 1 MHz
CD (Off) 153 pF typ VS = 1.5 V, f = 1 MHz
CD, CS (On) 243 pF typ VS = 1.5 V, f = 1 MHz
POWER REQUIREMENTS VDD = 3.6 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1.0 1.0 μA max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.
−40°C to
+125°C Unit Test Conditions/Comments
= 3.3 V, VSS = 0 V
DD
or VDD
GND
= 50 Ω, CL = 5 pF, f = 100 kHz;
R
L
see Figure 28
= 33 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p;
R
L
see Figure 29
Rev. A | Page 6 of 16
Page 7
ADG1636
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 5.
Parameter
CONTINUOUS CURRENT, S OR D
VDD = +5 V, VSS = −5 V
TSSOP (θJA = 150.4°C/W) 238 151 88 mA maximum
LFCSP (θJA = 48.7°C/W) 385 220 105 mA maximum
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 150.4°C/W) 280 175 98 mA maximum
LFCSP (θJA = 48.7°C/W) 469 259 119 mA maximum
VDD = 5 V, VSS = 0 V
TSSOP (θJA = 150.4°C/W) 189 126 77 mA maximum
LFCSP (θJA = 48.7°C/W) 301 182 98 mA maximum
VDD = 3.3 V, VSS = 0 V
TSSOP (θJA = 150.4°C/W) 189 130 84 mA maximum
LFCSP (θJA = 48.7°C/W) 305 189 105 mA maximum
25°C 85°C 125°C
Unit
Rev. A | Page 7 of 16
Page 8
ADG1636
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to VSS 18 V
VDD to GND −0.3 V to +18 V
VSS to GND +0.3 V to −18 V
Analog Inputs1
Digital Inputs1
Peak Current, S or D
Continuous Current, S or D2 Data + 15%
Operating Temperature Range
Industrial (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
16-Lead TSSOP, θJA Thermal
Impedance (2-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb free
1
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
2
See Table 5.
− 0.3 V to VDD + 0.3 V or
V
SS
30 mA, whichever occurs first
GND − 0.3 V to V
30 mA, whichever occurs first
850 mA (pulsed at 1 ms,
10% duty cycle maximum)
150.4°C/W
48.7°C/W
260°C
+ 0.3 V or
DD
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 8 of 16
Page 9
ADG1636
A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC
IN1
S1
NC
14
13
15
1D1
2S1B
3V
4GND
16
PIN 1
INDICATOR
ADG1636
TOP VIEW
(Not to Scale)
7
5
6
2
NC
NC
IN
12 EN
11 V
DD
10 S2B
9D2
8
S2A
.
SS
07983-004
1
IN1
2
S1A
3
D1
ADG1636
4
S1B
V
GND
NC
NC
TOP VIEW
5
(Not to Scale)
SS
6
7
8
NC = NO CONNECT
Figure 3. 16-Lead TSSOP Pin Configuration
16
NC
15
NC
14
EN
13
V
DD
12
S2B
11
D2
10
S2A
9
IN2
7983-003
SS
NOTES
1. NC = NO CONNECT .
2. EXPOSED P AD TIED TO SUBSTRATE, V
Figure 4. 16-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP
Mnemonic Description
1 15 IN1 Logic Control Input.
2 16 S1A Source Terminal. This pin can be an input or output.
3 1 D1 Drain Terminal. This pin can be an input or output.
4 2 S1B Source Terminal. This pin can be an input or output.
5 3 VSS Most Negative Power Supply Potential.
6 4 GND Ground (0 V) Reference.
7, 8, 15, 16 5, 7, 13, 14 NC No Connection.
9 6 IN2 Logic Control Input.
10 8 S2A Source Terminal. This pin can be an input or output.
11 9 D2 Drain Terminal. This pin can be an input or output.
12 10 S2B Source Terminal. This pin can be an input or output.
13 11 VDD Most Positive Power Supply Potential.
14 12 EN
Active High Digital Input. When this pin is low, the device is disabled and all switches are
off. When this pin is high, the Ax logic inputs determine the on switches.
N/A 17 (EPAD) EP (EPAD) Exposed Pad. Tied to substrate, VSS.
Table 8. ADG1636 TSSOP Truth Table
EN INx SxA SxB
0 X Off Off
1 0 Off On
1 1 On Off
Table 9. ADG1636 LFCSP Truth Table
EN INx SxA SxB
0 X Off Off
1 0 Off On
1 1 On Off
Rev. A | Page 9 of 16
Page 10
ADG1636
TYPICAL PERFORMANCE CHARACTERISTICS
1.4
TA = 25°C
= +3.3V
V
DD
V
= –3.3V
1.2
SS
1.0
= +5V
V
DD
V
= –5V
0.8
ON RESISTANCE (Ω)
0.6
SS
VDD = +8V
V
= –8V
SS
1.4
1.2
1.0
TA = +125°C
T
= +85°C
A
T
= +25°C
A
T
= –40°C
A
VDD = 12V
V
= 0V
SS
0.8
ON RESISTANCE (Ω)
0.6
0.4
–8–6–4–202468
VS OR VD VOLTAGE (V)
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
3.5
TA = 25°C
3.0
VDD = 3.3V
V
= 0V
2.5
SS
2.0
VDD = 5V
V
= 0V
1.5
ON RESISTANCE (Ω)
1.0
0.5
0246810121416
SS
V
= 12V
DD
V
= 0V
SS
VDD = 16V
V
= 0V
SS
VS OR VD VOLTAGE (V)
Figure 6. On Resistance as a Function of VD (VS) for Single Supply
1.4
1.2
0.4
024681012
07983-014
VS OR VD VOLTAGE (V)
07983-011
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
12 V Single Supply
2.5
TA = +125°C
= +125°C
T
A
T
T
= +85°C
= +85°C
A
A
T
T
= +25°C
= +25°C
A
A
T
T
= –40°C
= –40°C
A
A
2.0
1.5
ON RESISTANCE (Ω)
1.0
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
07983-015
VS OR VD VOLTAGE (V)
VDD = 5V
V
= 0V
SS
07983-013
Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,
5 V Single Supply
4.0
VDD = 3.3V
V
= 0V
SS
3.5
1.0
0.8
ON RESISTANCE (Ω)
0.6
VDD = +5V
V
= –5V
SS
0.4
–6–4–20246
VS OR VD VOLTAGE (V)
T
TA = +125°C
= +125°C
A
T
T
= +85°C
= +85°C
A
A
T
T
= +25°C
= +25°C
A
A
T
T
= –40°C
= –40°C
A
A
07983-012
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
±5 V Dual Supply
Rev. A | Page 10 of 16
3.0
T
= +125°C
2.5
ON RESISTANCE (Ω)
A
T
= +85°C
A
T
= +25°C
A
TA = –40°C
2.0
1.5
00.51.01.52.02.53. 03.5
VS OR VD VOLTAGE (V)
07983-007
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,
3.3 V Single Supply
Page 11
ADG1636
(
15
10
5
0
–5
LEAKAGE CURRENT (n A)
–10
–15
0 20406080100120
TEMPERATURE (°C)
ID, IS (ON) +, +
ID (OFF) –, +
IS (OFF) +, –
IS (OFF) –, +
ID, IS (ON) –, –
ID (OFF) +, –
07983-033
Figure 11. Leakage Currents as a Function of Temperature, ±5 V Dual Supply
20
15
10
5
ID, IS (ON) +, +
ID (OFF) –, +
IS (OFF) +, –
18
16
14
12
10
8
6
4
2
LEAKAGE CURRENT (n A)
0
–2
–4
020406080100120
TEMPERATURE (°C)
ID, IS (OFF) +, +
ID, IS (OFF) –, –
ID (OFF) –, +
IS (OFF) +, –
IS (OFF) –, +
ID (OFF) +, –
Figure 14. Leakage Currents as a Function of Temperature,
3.3 V Single Supply
600
500
400
300
IDD = +12V
I
= 0V
SS
IDD PER CHANNEL
= 25°C
T
A
07983-031
0
–5
LEAKAGE CURRENT (n A)
–10
–15
0 20406080100120
TEMPERATURE (°C)
ID, IS (ON) –, –
IS (OFF) –, +
ID (OFF) +, –
Figure 12. Leakage Currents as a Function of Temperature,
12 V Single Supply
20
15
ID, IS (OFF) +, +
10
ID, IS (OFF) –, –
5
LEAKAGE CURRENT (n A)
0
–5
0 20406080100120
TEMPERATURE (°C)
ID (OFF) –, +
IS (OFF) +, –
IS (OFF) –, +
ID (OFF) +, –
Figure 13. Leakage Currents as a Function of Temperature,
The ohmic resistance between Terminal D and Terminal S.
R
FLAT(ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range.
I
(Off)
S
The source leakage current with the switch off.
I
(Off)
D
The drain leakage current with the switch off.
I
, IS (On)
D
The channel leakage current with the switch on.
V
INL
The maximum input voltage for Logic 0.
V
INH
The minimum input voltage for Logic 1.
I
(I
)
INL
INH
The input current of the digital input.
C
(Off)
S
The off switch source capacitance, which is measured with
reference to ground.
C
(Off)
D
The off switch drain capacitance, which is measured with
reference to ground.
C
, CS (On)
D
The on switch capacitance, which is measured with reference to
ground.
C
IN
The digital input capacitance.
t
TRANSITION
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one address
state to another.
t
(EN)
ON
The delay between applying the digital control input and the
output switching on. See Figure 30.
t
(EN)
OFF
The delay between applying the digital control input and the
output switching off. See Figure 30.
Charge Injection
A measure of the glitch impulse transferred from the digital input
to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
AC Power Supply Rejection Ratio (ACPSRR)
The ratio of the amplitude of signal on the output to the amplitude
of the modulation. This is a measure of the ability of the part to
avoid coupling noise and spurious signals that appear on the supply
voltage pin to the output of the switch. The dc voltage on the device
is modulated by a sine wave of 0.62 V p-p.
Rev. A | Page 15 of 16
Page 16
ADG1636
C
OUTLINE DIMENSIONS
5.10
5.00
4.90
0.15
0.05
4.50
4.40
4.30
PIN 1
16
0.65
BSC
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AB
0.10
0.30
0.19
9
81
1.20
MAX
SEATING
PLANE
6.40
BSC
0.20
0.09
8°
0°
0.75
0.60
0.45
Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
0.50
0.40
0.30
16
PA D
4
5
FOR PROPER CO NNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRI PTIONS
SECTION O F THIS DATA SHEET.
P
N
I
N
I
D
1
2.65
2.50 SQ
2.35
0.25 MIN
1
R
O
C
I
A
T
031006-A
INDI
SEATING
PIN 1
ATO R
1.00
0.85
0.80
PLANE
12° MAX
4.00
BSC SQ
3.75
BSC SQ
TOP VIEW
0.80 MAX
0.65 TYP
0.05 MAX
0.30
0.23
0.18
COMPLIANTTOJEDEC STANDARDS MO-220-VGGC.
0.02 NOM
0.20 REF
0.60 MAX
12
0.65
9
BSC
1.95 BCS
COPLANARIT Y
0.08
13
EXPOSED
8
BOTTOM VIEW
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad (CP-16-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG1636BRUZ1 −40°C to +125°C 16- Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1636BRUZ-REEL1 −40°C to +125°C 16- Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1636BRUZ-REEL71 −40°C to +125°C 16- Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1636BCPZ- REEL1 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13
ADG1636BCPZ-REEL71 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13