Datasheet ADG1604 Datasheet (ANALOG DEVICES)

1 Ω Typical On Resistance, ±5 V,

FEATURES

1 Ω typical on resistance

0.2 Ω on resistance flatness ±3.3 V to ±8 V dual-supply operation

3.3 V to 16 V single-supply operation No V

supply required

L

3 V logic-compatible inputs Rail-to-rail operation Continuous current per channel

LFCSP package: 504 mA TSSOP package: 315 mA

14-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP

APPLICATIONS

Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements

+12 V, +5 V, and +3.3 V, 4:1 Multiplexer

ADG1604

FUNCTIONAL BLOCK DIAGRAM

S1

S2

S3

S4

ADG1604

1 OF 4

DECODER

Figure 1.

D

ENA1A0

07982-001

GENERAL DESCRIPTION

The ADG1604 is a complementary metal-oxide semiconductor (CMOS) analog multiplexer and switches one of four inputs to a common output, D, as determined by the 3-bit binary address lines, A0, A1, and EN. Logic 0 on the EN pin disables the device. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action. Inherent in the design is low charge injection for minimum transients when switching the digital inputs.

The ultralow on resistance of these switches make them ideal solutions for data acquisition and gain switching applications where low on resistance and distortion is critical. The on resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The CMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments.

PRODUCT HIGHLIGHTS

1. 1.6 Ω maximum on resistance over temperature.

2. Minimum distortion: THD + N = 0.007%.

3. 3 V logic-compatible digital inputs: V

4. No V

logic power supply required.

L

5. Ultralow power dissipation: <16 nW.

6. 14-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP.

= 2.0 V, V

INH

= 0.8 V.

INL

ADG1604

REVISION HISTORY

9/09—Rev. 0 to Rev. A

Changes to On Resistance (R Match Between Channels (ΔR Flatness (R

1/09—Revision 0: Initial Version

) Parameter, Table 4 ............................................. 6

FLATON

) Parameter, On Resistance

ON

) Parameter, and On Resistance

ON

Continuous Current per Channel, S or D ..................................7

Absolute Maximum Ratings ............................................................8

ESD Caution...................................................................................8

Pin Configurations and Function Descriptions ............................9

Typical Performance Characteristics ........................................... 10

Test Circuits ..................................................................................... 13

Terminology .................................................................................... 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. A | Page 2 of 20

ADG1604

SPECIFICATIONS

±5 V DUAL SUPPLY

VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

−40°C to

Parameter 25°C

+85°C

ANALOG SWITCH

Analog Signal Range VDD to VSS V On Resistance (RON) 1 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 22

1.2 1.4 1.6 Ω max VDD = ±4.5 V, VSS = ±4.5 V On Resistance Match Between Channels (∆RON) 0.04 Ω typ VS = ±4.5 V, IS = −10 mA

0.08 0.09 0.1 Ω max

On Resistance Flatness (R

) 0.2 Ω typ VS = ±4.5 V, IS = −10 mA

FLAT(ON)

0.25 0.29 0.34 Ω max LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V

Source Off Leakage, IS (Off) ±0.1 nA typ

±0.2 ±1 ±8 nA max Drain Off Leakage, ID (Off) ±0.1 nA typ

±0.2 ±2 ±16 nA max

Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = ±4.5 V; see Figure 24 ±0.4 ±2 ±16 nA max DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.005 μA typ VIN = V

INH

±0.1 μA max

Digital Input Capacitance, CIN 8 pF typ DYNAMIC CHARACTERISTICS1

Transition Time, t

150 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

278 336 376 ns max VS = 2.5 V; see Figure 29

tON (EN) 116 ns typ RL = 300 Ω, CL = 35 pF

146 166 177 ns max VS = 2.5 V; see Figure 31

t

(EN) 186 ns typ RL = 300 Ω, CL = 35 pF

OFF

234 277 310 ns max VS = 2.5 V; see Figure 31

Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF

28.5 ns min VS1 = VS2 = 2.5 V; see Figure 30 Charge Injection 140 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 Off Isolation 70 dB typ

Channel-to-Channel Crosstalk 70 dB typ

Total Harmonic Distortion + Noise (THD + N) 0.007 % typ

−3 dB Bandwidth 15 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 CS (Off) 63 pF typ VS = 0 V, f = 1 MHz CD (Off) 270 pF typ VS = 0 V, f = 1 MHz CD, CS (On) 360 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max VDD/VSS ±3.3/±8 V min/max

1

Guaranteed by design, not subject to production test.

−40°C to +125°C Unit Test Conditions/Comments

= ±4.5 V, VD = ∓4.5 V; see Figure 23

V

S

= ±4.5V, VD = ∓4.5 V; see Figure 23

V

S

or VDD

GND

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 25

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 27

= 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;

R

L

see Figure 28

Rev. A | Page 3 of 20

ADG1604

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

−40°C to

Parameter 25°C

+85°C

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance (RON) 0.95 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 22

1.1 1.25 1.45 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match Between Channels (∆RON) 0.03 Ω typ VS = 10 V, IS = −10 mA

0.06 0.07 0.08 Ω max

On Resistance Flatness (R

) 0.2 Ω typ VS = 0 V to 10 V, IS = −10 mA

FLAT(ON)

0.23 0.27 0.32 Ω max

LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.1 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23 ±0.2 ±1 ±8 nA max Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23 ±0.2 ±2 ±16 nA max

Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 1 V or 10 V; see Figure 24 ±0.4 ±2 ±16 nA max DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INH

±0.1 μA max

Digital Input Capacitance, CIN 8 pF typ DYNAMIC CHARACTERISTICS1

Transition Time, t

100 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

161 192 220 ns max VS = 8 V; see Figure 29

tON (EN) 80 ns typ RL = 300 Ω, CL = 35 pF

95 104 111 ns max VS = 8 V; see Figure 31

t

(EN) 144 ns typ RL = 300 Ω, CL = 35 pF

OFF

173 205 234 ns max VS = 8 V; see Figure 31

Break-Before-Make Time Delay, tD 25 ns typ RL = 300 Ω, CL = 35 pF

18 ns min VS1 = VS2 = 8 V; see Figure 30 Charge Injection 125 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32 Off Isolation 70 dB typ

Channel-to-Channel Crosstalk 70 dB typ

Total Harmonic Distortion + Noise 0.013 % typ

−3 dB Bandwidth 19 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 CS (Off) 60 pF typ VS = 6 V, f = 1 MHz CD (Off) 270 pF typ VS = 6 V, f = 1 MHz CD, CS (On) 350 pF typ VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 12 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max IDD 230 μA typ Digital inputs = 5 V 360 μA max VDD 3.3/16 V min/max

1

Guaranteed by design, not subject to production test.

Rev. A | Page 4 of 20

−40°C to +125°C Unit Test Conditions/Comments

or VDD

GND

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 25

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 27

= 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;

R

L

see Figure 28

ADG1604

5 V SINGLE SUPPLY

VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

−40°C to

Parameter 25°C

+85°C

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance (RON) 1.7 Ω typ VS = 0 V to 4.5 V, IS = −10 mA; see Figure 22

2.15 2.4 2.7 Ω max VDD = 4.5 V, VSS = 0 V On Resistance Match Between Channels (∆RON) 0.05 Ω typ VS = 0 V to 4.5 V, IS = −10 mA

0.09 0.12 0.15 Ω max

On Resistance Flatness (R

) 0.4 Ω typ VS = 0 V to 4.5 V, IS = −10 mA

FLAT(ON)

0.53 0.55 0.6 Ω max

LEAKAGE CURRENTS VDD = 5.5 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 23 ±0.2 ±1 ±8 nA max Drain Off Leakage, ID (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 23 ±0.2 ±2 ±16 nA max

Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = 1 V or 4.5 V; see Figure 24 ±0.4 ±2 ±16 nA max DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INH

±0.1 μA max

Digital Input Capacitance, CIN 8 pF typ DYNAMIC CHARACTERISTICS1

Transition Time, t

175 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

283 337 380 ns max VS = 2.5 V; see Figure 29

tON (EN) 135 ns typ RL = 300 Ω, CL = 35 pF

174 194 212 ns max VS = 2.5 V; see Figure 31

t

(EN) 228 ns typ RL = 300 Ω, CL = 35 pF

OFF

288 342 385 ns max VS = 2.5 V; see Figure 31

Break-Before-Make Time Delay, tD 30 ns typ RL = 300 Ω, CL = 35 pF

21 ns min VS1 = VS2 = 2.5 V; see Figure 30 Charge Injection 70 pC typ VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32 Off Isolation 70 dB typ

Channel-to-Channel Crosstalk 70 dB typ

Total Harmonic Distortion + Noise 0.09 % typ

−3 dB Bandwidth 16 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 CS (Off) 70 pF typ VS = 2.5 V, f = 1 MHz CD (Off) 300 pF typ VS = 2.5 V, f = 1 MHz CD, CS (On) 400 pF typ VS = 2.5 V, f = 1 MHz

POWER REQUIREMENTS VDD = 5.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max VDD 3.3/16 V min/max

1

Guaranteed by design, not subject to production test.

Rev. A | Page 5 of 20

−40°C to +125°C Unit Test Conditions/Comments

or VDD

GND

= 50 Ω, CL = 5 pF, f = 100 kHz;

R

L

see Figure 25

= 50 Ω, CL = 5 pF, f = 100 kHz;

R

L

see Figure 27

= 110 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p;

R

L

see Figure 28

ADG1604

3.3 V SINGLE SUPPLY

VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 4.

−40°C to

Parameter 25°C

+85°C

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance (RON) 3.2 3.4 3.6 Ω typ

On Resistance Match Between Channels (∆RON) 0.06 0.07 0.08 Ω typ VS = 0 V to VDD, IS = −10 mA On Resistance Flatness (R

) 1.2 1.3 1.4 Ω typ VS = 0 V to VDD, IS = −10 mA

FLAT(ON)

LEAKAGE CURRENTS VDD = 3.6 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 23 ±0.25 ±1 ±8 nA max Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 23 ±0.25 ±2 ±16 nA max

Channel On Leakage, ID, IS (On) ±0.05 nA typ VS = VD = 0.6 V or 3 V; see Figure 24 ±0.6 ±2 ±16 nA max DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INH

±0.1 μA max

Digital Input Capacitance, CIN 8 pF typ DYNAMIC CHARACTERISTICS1

Transition Time, t

280 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

460 526 575 ns max VS = 1.5 V; see Figure 29

tON (EN) 227 ns typ RL = 300 Ω, CL = 35 pF

308 332 346 ns max VS = 1.5 V; see Figure 31

t

(EN) 357 ns typ RL = 300 Ω, CL = 35 pF

OFF

480 549 601 ns max VS = 1.5 V; see Figure 31

Break-Before-Make Time Delay, tD 25 ns typ RL = 300 Ω, CL = 35 pF

20 ns min VS1 = VS2 = 1.5 V; see Figure 30 Charge Injection 60 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32 Off Isolation 70 dB typ

Channel-to-Channel Crosstalk 70 dB typ

Total Harmonic Distortion + Noise 0.15 % typ

−3 dB Bandwidth 15 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 CS (Off) 76 pF typ VS = 1.5 V, f = 1 MHz CD (Off) 316 pF typ VS = 1.5 V, f = 1 MHz CD, CS (On) 420 pF typ VS = 1.5 V, f = 1 MHz

POWER REQUIREMENTS VDD = 3.6 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 1.0 μA max VDD 3.3/16 V min/max

1

Guaranteed by design, not subject to production test.

−40°C to +125°C Unit Test Conditions/Comments

= 0 V to VDD, IS = −10 mA, VDD = 3.3 V,

V

S

= 0 V; see Figure 22

V

SS

or VDD

GND

= 50 Ω, CL = 5 pF, f = 100 kHz;

R

L

see Figure 25

= 50 Ω, CL = 5 pF, f = 100 kHz;

R

L

see Figure 27

= 110 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p;

R

L

see Figure 28

Rev. A | Page 6 of 20

ADG1604

CONTINUOUS CURRENT PER CHANNEL, S OR D

Table 5.

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, S OR D

VDD = +5 V, VSS = −5 V

TSSOP (θJA = 150.4°C/W) 315 189 95 mA maximum LFCSP (θJA = 48.7°C/W) 504 259 112 mA maximum

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 150.4°C/W) 378 221 112 mA maximum LFCSP (θJA = 48.7°C/W) 627 311 126 mA maximum

VDD = 5 V, VSS = 0 V

TSSOP (θJA = 150.4°C/W) 249 158 91 mA maximum LFCSP (θJA = 48.7°C/W) 403 224 105 mA maximum

VDD = 3.3 V, VSS = 0 V

TSSOP (θJA = 150.4°C/W) 256 165 98 mA maximum LFCSP (θJA = 48.7°C/W) 410 235 116 mA maximum

Rev. A | Page 7 of 20

ADG1604

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to VSS 18 V VDD to GND −0.3 V to +18 V VSS to GND +0.3 V to −18 V Analog Inputs1

Digital Inputs1

Peak Current, S or D

Continuous Current, S or D2 Data + 15% Operating Temperature Range

Industrial (Y Version) −40°C to +125°C

Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 16-Lead TSSOP, θJA Thermal

Impedance (2-Layer Board)

16-Lead LFCSP, θJA Thermal

Impedance (4-Layer Board)

Reflow Soldering Peak

Temperature, Pb free

1

Overvoltages at IN, S, or D are clamped by internal diodes. Current should be

limited to the maximum ratings given.

2

See Table 5.

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs first GND − 0.3 V to V

30 mA, whichever occurs first 1150 mA (pulsed at 1 ms,

10% duty-cycle maximum)

150.4°C/W

48.7°C/W

260°C

+ 0.3 V or

DD

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 8 of 20

ADG1604

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

A0

EN

NC

A1

14

13

15

16

PIN 1

1

A0

2

EN

3

SS

ADG1604

4

S1

TOP VIEW

(Not to Scale)

5

S2

6

D

7

NC

NC = NO CONNECT

14

A1

13

GND

12

V

DD

11

S3

10

S4

9

NC

8

NC

07982-002

Figure 2. 14-Lead TSSOP Pin Configuration

SS

2NC

ADG1604

3S1

TOP VIEW

(Not to Scale)

4S2

5

6

D

NC

NOTES

1. NC = NO CONNECT .

2. EXPOSED PAD TIED TO SUBSTRATE, V

Figure 3. 16-Lead LFCSP Pin Configuration

INDICATOR

1V

Table 7. Pin Function Descriptions

Pin No.

Mnemonic Description 14-Lead TSSOP 16-Lead LFCSP

1 15 A0 Logic Control Input.

2 16 EN

Active High Digital Input. When this pin is low, the device is disabled and all switches

are off. When this pin is high, the Ax logic inputs determine the on switch. 3 1 VSS Most Negative Power Supply Potential. 4 3 S1 Source Terminal. This pin can be an input or output. 5 4 S2 Source Terminal. This pin can be an input or output. 6 6 D Drain Terminal. This pin can be an input or output. 7, 8, 9 2, 5, 7, 8, 13 NC No Connection. 10 9 S4 Source Terminal. This pin can be an input or output. 11 10 S3 Source Terminal. This pin can be an input or output. 12 11 VDD Most Positive Power Supply Potential. 13 12 GND Ground (0 V) Reference. 14 14 A1 Logic Control Input. N/A 17 (EPAD) EP (EPAD) Exposed Pad. Tied to substrate, VSS.

12 GND

11 V

DD

10 S3

9S4

8

7

NC

.

SS

07982-003

Table 8. ADG1604 Truth Table

EN A1 A0 S1 S2 S3 S4

0 X X Off Off Off Off 1 0 0 On Off Off Off 1 0 1 Off On Off Off 1 1 0 Off Off On Off 1 1 1 Off Off Off On

Rev. A | Page 9 of 20

ADG1604

TYPICAL PERFORMANCE CHARACTERISTICS

1.4

TA = 25°C

= +3.3V

V

DD

V

= –3.3V

1.2

1.0

0.8

ON RESISTANCE ()

0.6

SS

= +5V

V

DD

V

= –5V

SS

VDD = +8V V

= –8V

SS

1.4

1.2

1.0

0.8

ON RESISTANCE ()

0.6

TA = +125°C T

= +85°C

A

T

= +25°C

A

T

= –40°C

A

VDD = 12V V

= 0V

SS

0.4

–8 –6 –4 –2 0 2 4 6 8

VS OR VD VOLTAGE (V)

Figure 4. On Resistance as a Function of VD (VS) for Dual Supply

3.5

TA = 25°C

3.0

2.5

2.0

1.5

ON RESISTANCE ()

1.0

0.5

0 2 4 6 8 10 12 14 16

VDD = 3.3V V

= 0V

SS

VDD = 5V V

= 0V

SS

VS OR VD VOLTAGE (V)

V

= 12V

DD

V

= 0V

SS

VDD = 16V V

= 0V

SS

Figure 5. On Resistance as a Function of VD (VS) for Single Supply

1.4

1.2

0.4

024681012

07982-014

VS OR VD VOLTAGE (V)

07982-010

Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,

12 V Single Supply

2.5

TA = +125°C

= +125°C

T

A

T

= +85°C

A

T

= +25°C

A

T

= –40°C

A

2.0

1.5

ON RESISTANCE ()

1.0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

07982-015

VS OR VD VOLTAGE (V)

VDD = 5V V

= 0V

SS

07982-013

Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,

5 V Single Supply

4.0 VDD = 3.3V V

= 0V

SS

3.5

1.0

0.8

ON RESISTANCE ()

0.6

=+5V

V

DD

V

= –5V

SS

0.4

–6–4–20246

VS OR VD VOLTAGE (V)

TA = +125°C T

= +85°C

A

T

= +25°C

A

T

= –40°C

A

07982-012

Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures,

±5 V Dual Supply

Rev. A | Page 10 of 20

3.0

T

= +125°C

2.5

ON RESISTANCE ()

2.0

1.5

0 0.5 1.0 1.5 2.0 2.5 3. 0 3. 5

A

T

= +85°C

A

T

= +25°C

A

TA = –40°C

VS OR VD VOLTAGE (V)

07982-006

Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,

3.3 V Single Supply

ADG1604

(

15

10

5

0

–5

LEAKAGE CURRENT (n A)

–10

–15

0 20 40 60 80 100 120

TEMPERATURE (°C)

ID, IS (ON) +, +

ID (OFF) –, +

IS (OFF) +, –

IS (OFF) –, +

ID, IS (ON) –, –

ID (OFF) +, –

07982-033

Figure 10. Leakage Currents as a Function of Temperature, ±5 V Dual Supply

20

15

10

5

ID, IS (ON) +, +

ID (OFF) –, +

IS (OFF) +, –

Figure 13. Leakage Currents as a Function of Temperature, 3.3 V Single Supply

18

16

14

12

10

8

6

4

2

LEAKAGE CURRENT (n A)

0

–2

–4

0 20406080100120

TEMPERATURE (°C)

ID, IS (OFF) +, +

ID, IS (OFF) –, –

ID (OFF) –, +

IS (OFF) +, –

IS (OFF) –, +

ID (OFF) +, –

600

500

400

300

IDD = +12V I

= 0V

SS

IDD PER CHANNEL

= 25°C

T

A

7982-031

0

–5

LEAKAGE CURRENT (n A)

–10

–15

0 20406080100120

TEMPERATURE (°C)

ID, IS (ON) –, – IS (OFF) –, +

ID (OFF) +, –

07982-032

Figure 11. Leakage Currents as a Function of Temperature, 12 V Single Supply

20

15

ID, IS (OFF) +, +

10

ID, IS (OFF) –, –

5

LEAKAGE CURRENT (n A)

0

–5

0 20406080100120

TEMPERATURE (°C)

ID (OFF) –, +

IS (OFF) +, – IS (OFF) –, + ID (OFF) +, –

07982-030

Figure 12. Leakage Currents as a Function of Temperature, 5 V Single Supply

µA)

200

DD

I

100

0

–100

024681012

= +5V

I

DD

I

= –5V

SS

IDD = +3.3V I

= 0V

SS

Figure 14. I

I

= +5V

DD

I

= 0V

SS

LOGIC (V)

vs. Logic Level

DD

350

300

250

200

150

100

CHARGE INJECTI ON (pC)

50

0

–6 –4 –2 0 2 4 6 8 10 12 14

VDD = +3.3V V

= 0V

SS

VS (V)

VDD = +5V V

= –5V

SS

VDD = +5V V

= 0V

SS

VDD = +12V V

= 0V

SS

Figure 15. Charge Injection vs. Source Voltage

07982-005

07982-009

Rev. A | Page 11 of 20

ADG1604

–

A

450

400

350

300

250

TIME (ns)

200

150

100

50

–40 –20 0 20 40 60 80 100 12 0

VDD = +3.3V, VSS = 0V

V

DD

TEMPERATURE (°C)

Figure 16. tON/t

V

= +5V, VSS = 0V

DD

V

= +5V, VSS = –5V

DD

= +12V, VSS = 0V

Times vs. Temperature

OFF

15

= 25°C

T

A

–20

V

= +5V

DD

–25

V

= –5V

SS

–30 –35 –40 –45 –50 –55 –60

TION (dB)

–65 –70 –75 –80

OFF ISOL

–85 –90

–95 –100 –105

–110

100k 1M 10M 100M 1G10k1k

FREQUENCY ( Hz)

Figure 17. Off Isolation vs. Frequency

7982-019

07982-007

INSERTION LOSS (dB)

ACPSRR (dB)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–1

–2

–3

–4

–5

–6

0

100k 1M 10M 100M10k1k

FREQUENCY (Hz)

Figure 19. On Response vs. Frequency

TA = 25°C V

= +5V

DD

V

= –5V

SS

NO DECOUPLI NG CAPACITORS

DECOUPLING CAPACITORS

100k 1M 10M10k1k

FREQUENCY (Hz)

Figure 20. ACPSRR vs. Frequency

TA = 25°C V

= +5V

DD

V

= –5V

SS

07982-004

07982-008

0.20

RL = 110 T

= 25°C

A

0.18

0.16

0.14

0.12

0.10

0.08

THD + N (%)

0.06

0.04

0.02

VDD = +12V V

= 5V p-p

S

0

FREQUENCY ( Hz)

VDD = +3.3V

V

= 2V p-p

S

VDD = +5V

V

= 3.5V p-p

S

VDD = +5V V

= –5V

SS

V

= 5V p-p

S

15k10k5k 20k

07982-017

Figure 21. THD + N vs. Frequency

CROSSTALK (dB)

–20

–40

–60

–80

–100

–120

0

TA = 25°C V V

= +5V

DD

= –5V

SS

100k 1M 10M 100M 1G10k1k

FREQUENCY ( Hz)

Figure 18. Crosstalk vs. Frequency

07982-018

Rev. A | Page 12 of 20

ADG1604

V

TEST CIRCUITS

DD

SS

0.1µF

50

D

OFF ISOLATION = 20 log

Figure 25. Off Isolation

SS

0.1µF

D

NETWORK

ANALYZER

50

V

S

V

OUT

R

L

50

V

OUT

V

S

NETWORK

ANALYZER

50

V

OUT

R

L

50

V

S

7982-027

V

Sx D

S

Figure 22. On Resistance

IS (OFF) ID (OFF)

Sx D

A A

0.1µF

V

DDVSS

Sx

GND

I

DS

07982-020

DD

0.1µF

V

DDVSS

Sx

GND

ID (ON)

A

V

D

V

D

07982-021

INSERTION LOSS = 20 log

WITH SWITCH

V

OUT

V

WITHOUT SWITCH

OUT

07982-028

Figure 26. Bandwidth

DD

0.1µF

NETWO RK ANALYZER

V

OUT

R

L

50

V

S

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

07982-022

V

DD

S1

S2

GND

V

OUT

V

SS

0.1µF

V

SS

D

R

L

50

S

07982-029

Figure 27. Channel-to-Channel Crosstalk

S

Figure 23. Off Leakage

Sx D

NC

NC = NO CONNECT

Figure 24. On Leakage

Rev. A | Page 13 of 20

ADG1604

V

0.1µF

IN

V

IN

V

DD

SS

0.1µF

V

DD

SS

AUDIO PRECISIO N

R

S

Sx

V

S

V p-p

V

OUT

07982-034

GND

D

R

L

110

Figure 28. THD + Noise

SS

DD

0.1µF

A1

V

IN

2.0V

A0

EN

0.1µF

V

SS

DD

S1

S2

V

S1

ADDRESS

DRIVE (V

S3

GND

S4

D

R

L

300

V

S4

V

OUT

C

L

35pF

3V

)

IN

0V

V

OUT

50% 50%

90%

t

TRANSITI ON

t

TRANSITION

90%

07982-023

Figure 29. Address to Output Switching Times

DD

SS

0.1µF

V

SS

DD

A1

V

IN

300

A0

S1

S2

S3

V

S1

ADDRESS

DRIVE (V

3V

)

IN

0V

S4

2.0V

EN

GND

80%

D

R

L

300

C

L

35pF

V

OUT

V

OUT

t

BBM

80%

07982-024

Figure 30. Break-Before-Make Time Delay

Rev. A | Page 14 of 20

ADG1604

V

DD

SS

0.1µF

A1

A0

EN

V

IN

300

0.1µF

3V

V

OUT

ENABLE

DRIVE (V

OUTPUT

)

IN

0V

V

OUT

0V

V

SS

DD

S1

S2

V

S

S3

S4

D

GND

R

L

300

C

L

35pF

50% 50%

0.9V

OUT

t

(EN)

ON

t

OFF

0.9V

(EN)

OUT

07982-025

Figure 31. Enable-to-Output Switching Delay

SS

DD

V

R

S

V

S

DD

Sx D

DECODER

SS

V

OUT

C

L

1nF

V

OUT

V

IN

SW OFF

Q

INJ

= CL × V

OUT

V

OUT

SW OFF

SW ON

GND

SW OFF

V

A2A1

IN

EN

SW OFF

7982-026

Figure 32. Charge Injection

Rev. A | Page 15 of 20

ADG1604

TERMINOLOGY

IDD

The positive supply current.

I

SS

The negative supply current.

V

(VS)

D

The analog voltage on Terminal D and Terminal S.

R

ON

The ohmic resistance between Terminal D and Terminal S.

R

FLAT(ON)

Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range.

I

(Off)

S

The source leakage current with the switch off.

I

(Off)

D

The drain leakage current with the switch off.

I

, IS (On)

D

The channel leakage current with the switch on.

V

INL

The maximum input voltage for Logic 0.

V

INH

The minimum input voltage for Logic 1.

I

(I

)

INL

INH

The input current of the digital input.

C

(Off)

S

The off switch source capacitance, which is measured with reference to ground.

C

(Off)

D

The off switch drain capacitance, which is measured with reference to ground.

C

, CS (On)

D

The on switch capacitance, which is measured with reference to ground.

C

IN

The digital input capacitance.

t

TRANSITION

The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. See Figure 29.

t

(EN)

ON

The delay between applying the digital control input and the output switching on. See Figure 31.

t

(EN)

OFF

The delay between applying the digital control input and the output switching off. See Figure 31.

Charge Injection

A measure of the glitch impulse transferred from the digital input to the analog output during switching. See Figure 32.

Off Isolation

A measure of unwanted signal coupling through an off switch. See Figure 25.

Crosstalk

A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. See Figure 27.

Bandwidth

The frequency at which the output is attenuated by 3 dB. See Figure 26.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

Total Harmonic Distorition + Noise (THD + N)

The ratio of the harmonic amplitude plus noise of the signal to the fundamental. See Figure 28.

AC Power Supply Rejection Ratio (ACPSRR)

The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p.

Rev. A | Page 16 of 20

ADG1604

C

OUTLINE DIMENSIONS

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

0.15

0.05

COPLANARITY

0.10

14

1

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

8

6.40 BSC

7

1.20

0.20

MAX

SEATING PLANE

0.09

8° 0°

0.75

0.60

0.45

061908-A

Figure 33. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

0.50

0.40

0.30

1

16

PA D

4

5

FOR PROPER CO NNECTION O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DESCRI PTIONS SECTION O F THIS DATA SHEET.

N

P

I

D

N

I

2.65

2.50 SQ

2.35

0.25 MIN

1

R

O

C

I

A

T

031006-A

INDI

SEATING

PIN 1

ATO R

1.00

0.85

0.80

PLANE

12° MAX

4.00

BSC SQ

3.75

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.05 MAX

0.30

0.23

0.18

COMPLIANTTOJEDEC STANDARDS MO-220-VGGC.

0.02 NOM

0.20 REF

0.60 MAX

12

0.65

9

BSC

1.95 BCS

COPLANARIT Y

0.08

13

EXPOSED

8

BOTTOM VIEW

Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-13)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG1604BRUZ1 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADG1604BRUZ-REEL1 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADG1604BRUZ-REEL71 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADG1604BCPZ- REEL1 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13 ADG1604BCPZ-REEL71 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13

1

Z = RoHS Compliant Part.

Rev. A | Page 17 of 20

ADG1604

NOTES

Rev. A | Page 18 of 20

ADG1604

NOTES

Rev. A | Page 19 of 20

ADG1604

NOTES

Rev. A | Page 20 of 20

Datasheet ADG1604 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

±5 V DUAL SUPPLY

12 V SINGLE SUPPLY

5 V SINGLE SUPPLY

3.3 V SINGLE SUPPLY

CONTINUOUS CURRENT PER CHANNEL, S OR D

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

TERMINOLOGY

OUTLINE DIMENSIONS

ORDERING GUIDE