Datasheet ADG1436 Datasheet (ANALOG DEVICES)

1.5 Ω On Resistance,

www.BDTIC.com/ADI

±15 V/12 V/±5 V, iCMOS, Dual SPDT Switch

FEATURES

1.5 Ω on resistance

0.3 Ω on-resistance flatness

0.1 Ω on-resistance match between channels
Continuous current per channel

LFCSP package: up to 400 mA

TSSOP package: up to 260 mA
Fully specified at +12 V, ±15 V, and ±5 V
No V

supply required

L

3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 4 mm × 4 mm, 16-lead LFCSP packages

APPLICATIONS

Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
Relay replacement

ADG1436

FUNCTIONAL BLOCK DIAGRAMS

S1A

S1B

IN1

IN2

S2A

S2B

SWITCHES SHOWN FOR A ONE-INPUT LOGIC.

S1A

D1

S1B

ADG1436

Figure 1. TSSOP Package

ADG1436

LOGIC

S2A

D2

S2B

D1

D2

06817-001

GENERAL DESCRIPTION

The ADG1436 is a monolithic CMOS device containing two
independently selectable SPDT switches. An EN input on the
LFCSP package is used to enable or disable the device. When
disabled, all channels are switched off. Each switch conducts
equally well in both directions when on and has an input signal
range that extends to the supplies. In the off condition, signal
levels up to the supplies are blocked. Both switches exhibit
break-before-make switching action for use in multiplexer
applications.

The ADG1436 is designed on an iCMOS® process. iCMOS
(industrial-CMOS) is a modular manufacturing process combining
high voltage CMOS (complementary metal-oxide semiconductor)
and bipolar technologies. It enables the development of a wide
range of high performance analog ICs capable of 33 V operation

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

IN2 ENIN1

SWITCHES SHOWN FOR A O NE-INPUT L OGIC.

Figure 2. LFCSP Package

06817-002

in a footprint that no previous generation of high voltage parts
has been able to achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high supply
voltages while providing increased performance, dramatically
lower power consumption, and reduced package size.

The on-resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching audio signals. iCMOS construction ensures ultralow
power dissipation, making the part ideally suited for portable
and battery-powered instruments.

PRODUCT HIGHLIGHTS

1. 2.6 Ω maximum on resistance over temperature.

2. Minimum distortion.

3. Ultralow power dissipation: <0.03 μW.

4. 16-lead TSSOP and 16-lead 4 mm × 4 mm LFCSP packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ADG1436

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagrams ............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

15 V Dual Supply .......................................................................... 3

12 V Single Supply ........................................................................ 4

5 V Dual Supply ............................................................................ 5

REVISION HISTORY

7/08—Revision 0: Initial Version

Continuous Current per Channel ...............................................6

Absolute Maximum Ratings ............................................................7

ESD Caution...................................................................................7

Pin Configurations and Function Descriptions ............................8

Truth Table For Switches ..............................................................8

Typical Performance Characteristics ..............................................9

Terminology .................................................................................... 12

Test Circuits ..................................................................................... 13

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

Rev. 0 | Page 2 of 16

ADG1436

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SPECIFICATIONS

15 V DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V

On Resistance (RON) 1.5 Ω typ VS = ±10 V, IS = −10 mA; see Figure 23

1.8 2.3 2.6 Ω max VDD = +13.5 V, VSS = −13.5 V

On-Resistance Match

Between Channels (∆R

0.18 0.19 0.21 Ω max

On-Resistance Flatness (R

0.36 0.4 0.45 Ω max

LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) ±0.04 nA typ VS = ±10 V, VS = ±10 V; see Figure 24

±0.55 ±2 ±12.5 nA max

Drain Off Leakage, ID (Off) ±0.04 nA typ VS = ±10 V, VS = ±10 V; see Figure 24

±0.55 ±2 ±12.5 nA max

Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 25

±2 ±4 ±35 nA max

DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

±0.1 μA max

Digital Input Capacitance, CIN 3.5 pF typ

DYNAMIC CHARACTERISTICS

Transition Time, t

170 215 245 ns max VS = +10 V; see Figure 30

tON (EN) 95 ns typ RL = 300 Ω, CL = 35 pF

120 140 155 ns max VS = 10 V; see Figure 30

t

(EN) 105 ns typ RL = 300 Ω, CL = 35 pF

OFF

130 150 170 ns max VS = 10 V; see Figure 30

Break-Before-Make Time Delay, t

10 ns min VS1 = VS2 = +10 V; see Figure 31

Charge Injection −20 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33

Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26

Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27

Total Harmonic Distortion + Noise 0.011 % typ RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz; see

−3 dB Bandwidth 110 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 28

Insertion Loss −0.18 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28

CS (Off) 23 pF typ f = 1 MHz, VS = 0 V

CD (Off) 50 pF typ f = 1 MHz, VS = 0 V

CD, CS (On) 120 pF typ f = 1 MHz, VS = 0 V

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.001 μA typ Digital Inputs = 0 V or VDD

1 μA max

IDD 170 μA typ Digital Input = 5 V

280 μA max

ISS 0.001 μA typ Digital Inputs = 0 V, 5 V, or VDD

1.0 μA max

VDD/VSS ±4.5/±16.5 V min/max GND = 0 V

1

Guaranteed by design, not subject to production test.

or I

INL

TRANSITION

)

ON

) 0.28 Ω typ VS = ±10 V, IS = −10 mA

FLAT(ON)

2.0 V min

INH

0.8 V max

INL

0.005 μA typ VIN = V

INH

1

125 ns typ RL = 300 Ω, CL = 35 pF

BBM

0.1 Ω typ V

20 ns typ RL = 300 Ω, CL = 35 pF

= ±10 V, IS = −10 mA

S

or VDD

GND

Figure 29

Rev. 0 | Page 3 of 16

ADG1436

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12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit

ANALOG SWITCH

Analog Signal Range

0 V to VDD V

On Resistance (RON) 2.8 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 23

On-Resistance Match

Between Channels (∆R

)

ON

3.5 4.3 4.8 Ω max V

0.13 Ω typ V

0.21 0.23 0.25 Ω max

On-Resistance Flatness (R

) 0.6 Ω typ VS = 0 V to 10 V, IS = −10 mA

FLAT(ON)

1.1 1.2 1.3 Ω max

LEAKAGE CURRENTS

Source Off Leakage, IS (Off) ±0.04

±0.55

Drain Off Leakage, ID (Off) ±0.04

±0.55

Channel On Leakage, ID, IS (On) ±0.1

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INH

INL

or I

0.001

INL

INH

±1

Digital Input Capacitance, CIN 3.5

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANSITION

1

200 ns typ RL = 300 Ω, CL = 35 pF

±2 ±12.5

±2 ±12.5

±4 ±35

±0.1 μA max

nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
nA max
nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
nA max
nA typ VS = VD = 1 V or 10 V; see Figure 25
nA max

2.0 V min

0.8 V max
μA typ VIN = V

pF typ

270 320 350 ns max
tON (EN) 175 ns typ RL = 300 Ω, CL = 35 pF
235 280 310 ns max
t

(EN) 105 ns typ RL = 300 Ω, CL = 35 pF

OFF

145 175 195 ns max
Break-Before-Make Time Delay, t

Charge Injection 30
Off Isolation −80

Channel-to-Channel Crosstalk −80

−3 dB Bandwidth 78

70

BBM

ns typ RL = 300 Ω, CL = 35 pF

10 ns min V

pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 33
dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see

dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see

MHz typ RL = 50 Ω, CL = 5 pF; see Figure 28

Insertion Loss −0.3 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
CS (Off) 40 pF typ f = 1 MHz, VS = 6 V
CD (Off) 80 pF typ f = 1 MHz, VS = 6 V
CD, CS (On) 140 pF typ f = 1 MHz, VS = 6 V

POWER REQUIREMENTS

IDD 0.001

IDD 170

μA typ Digital inputs = 0 V or VDD

1.0 μA max
μA typ Digital inputs = 5 V

280 μA max

VDD 5/16.5 V min/max GND = 0 V, VSS = 0 V

1

Guaranteed by design, not subject to production test.

Te st Conditions/Comments

= +10.8 V, VSS = 0 V

DD

= 0 V to 10 V, IS = −10 mA

S

VDD = 13.2 V, VSS = 0 V

or VDD

GND

V

= 8 V; see Figure 30

S

V

= 8 V; see Figure 30

S

V

= 8 V; see Figure 30

S

= VS2 = 8 V; see Figure 31

S1

Figure 26;

Figure 27

VDD = 13.2 V

Rev. 0 | Page 4 of 16

ADG1436

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5 V DUAL SUPPLY

VDD = 5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 3.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

VDD to V

On Resistance (RON) 3.3 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 23
4 4.9 5.4 Ω max VDD = +4.5 V, VSS = −4.5 V
On-Resistance Match

Between Channels (

∆R

)

ON

0.13 Ω typ V

0.22 0.23 0.25 Ω max
On-Resistance Flatness (R

) 0.9 Ω typ VS = ±4.5 V, IS = −10 mA

FLAT(ON)

1.1 1.24 1.31 Ω max

LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V

Source Off Leakage, IS (Off) ±0.03 nA typ

±0.2

±1 ±12.5

Drain Off Leakage, ID (Off) ±0.03 nA typ

±0.2
Channel On Leakage, ID, IS (On) ±0.05
±0.25

±1 ±12.5

±1.5 ±35

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INL

INH

±0.1 μA max
Digital Input Capacitance, CIN 3.5 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

310 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

445 510 565 ns max VS = 3 V; see Figure 30
tON (EN) 255 ns typ RL = 300 Ω, CL = 35 pF
355 415 460 ns max VS = 3 V; see Figure 30
t

(EN) 215 ns typ RL = 300 Ω, CL = 35 pF

OFF

305 355 400 ns max VS = 3 V; see Figure 30
Break-Before-Make Time Delay, t

80 ns typ RL = 300 Ω, CL = 35 pF

BBM

10 ns min VS1 = VS2 = 3 V; see Figure 31
Charge Injection 30 pC typ
Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27
Total Harmonic Distortion + Noise 0.03 % typ RL = 110 Ω, 2.5 V pp, f = 20 Hz to 20 kHz; see

−3 dB Bandwidth

85 MHz typ R
Insertion Loss −0.28 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
CS (Off) 33 pF typ VS = 0 V, f = 1 MHz
CD (Off) 65 pF typ VS = 0 V, f = 1 MHz
CD, CS (On) 145 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max
VDD/VSS ±4.5/±16.5 V min/max GND = 0 V

1

Guaranteed by design, not subject to production test.

SS

V

= ±4.5 V, IS = −10 mA

S

V

= ±4.5 V, VD = ∓4.5 V; see Figure 24

S

nA max

V

= ±4.5 V, VD = ∓4.5 V; see Figure 24

S

nA max
nA typ VS = VD = ±4.5V; see Figure 25
nA max

or VDD

GND

V

= 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33

S

Figure 29

= 50 Ω, CL = 5 pF; see Figure 28

L

Rev. 0 | Page 5 of 16

ADG1436

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CONTINUOUS CURRENT PER CHANNEL

Table 4.

Parameter 25°C 85°C 125°C Unit Test Conditions/Comments

CONTINUOUS CURRENT PER CHANNEL

15 V Dual Supply VDD = +13.5 V, VSS = −13.5 V

ADG1436 TSSOP 260 170 100 mA max
ADG1436 LFCSP 400 250 120 mA max

12 V Single Supply VDD = 10.8 V, VSS = 0 V

ADG1436 TSSOP 240 160 100 mA max
ADG1436 LFCSP 350 240 120 mA max

5 V Dual Supply V

ADG1436 TSSOP 240 160 100 mA max
ADG1436 LFCSP 300 240 120 mA max

1

Guaranteed by design, not subject to production test.

1

= +4.5 V, VSS = −4.5 V

DD

Rev. 0 | Page 6 of 16

ADG1436

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Ratings

VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs

Digital Inputs

Peak Current, S or D

Continuous Current per

Channel, S or D

Operating Temperature Range

Automotive (Y Version) −40°C to +125°C

Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
16-Lead TSSOP, θJA Thermal

Impedance (4-Layer Board)

16-Lead LFCSP, θJA Thermal

Impedance

Reflow Soldering Peak

Temperature, Pb Free

1

Over voltages at IN, S, and D are clamped by internal diodes. Current should

be limited to the maximum ratings given.

2

See data given in Table 4.

1

1

2

VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first

GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first

600 mA (pulsed at 1 ms, 10%
duty cycle maximum)

Data + 15%

112°C/W

30.4°C/W

260(+0/−5)°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 7 of 16

ADG1436

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

A

1

NC

NC

IN

S1

14

13

15

1D1

2S1B

3V

4GND

16

PIN 1
INDICATO R

ADG1436

TOP VIEW

(Not to Scale)

7

5

6

NC

NC

IN2

12 EN

11 V

DD

10 S2B

9D2

8

S2A

.

SS

06817-004

IN1

1

2

S1A

D1

3

ADG1436

S1B

4

5

V

SS

(Not to Scale)

GND

6

NC

7

8

NC

NC = NO CONNECT

TOP VIEW

NC

16

15

NC

NC

14

V

13

DD

12

S2B

D2

11

S2A

10

9

IN2

06817-003

NOTES

1. EXPOSE D PAD TIED TO SUBSTRATE, V

2. NC = NO CONNECT .

Figure 3.TSSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Function

1 15 IN1 Logic Control Input.
2 16 S1A Source Terminal. Can be an input or output.
3 1 D1 Drain Terminal. Can be an input or output.
4 2 S1B Source Terminal. Can be an input or output.
5 3 VSS Most Negative Power Supply Potential.
6 4 GND Ground (0 V) Reference.
7, 8, 14 to 16 5, 7, 13, 14 NC No Connect.
9 6 IN2 Logic Control Input.
10 8 S2A Source Terminal. Can be an input or output.
11 9 D2 Drain Terminal. Can be an input or output.
12 10 S2B Source Terminal. Can be an input or output.
13 11 VDD Most Positive Power Supply Potential.
N/A 12 EN

Active High Digital Input. When this pin is low, the device is disabled and all switches are
off. When this pin is high, INx logic inputs determine the on switches.

SS

Figure 4. LFCSP Pin Configuration

TRUTH TABLE FOR SWITCHES

Table 7. ADG1436 TSSOP Truth Table

INx SxA SxB

0 Off On
1 On Off

Table 8. ADG1436 LFCSP Truth Table

EN INx SxA SxB

0 X Off Off
1 0 Off On
1 1 On Off

Rev. 0 | Page 8 of 16

ADG1436

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TYPICAL PERFORMANCE CHARACTERISTICS

2.5

2.0

1.5

1.0

ON RESISTANCE ()

0.5

T

= 25°C

A

I

= –10mA

S

0

–16.5 –12.5 –8.5 –4.5 –0.5 3.5 7. 5 15. 5

V

DD

V

SS

V

DD

V

= –10V

SS

= +13.5V,
= –13.5V

= +10V,

V

DD

V

SS

VS OR VD (V)

= +12V,

= –12V

= +15V,

V

DD

V

= –15V

SS

VDD = +16.5V,
V

SS

Figure 5. On Resistance vs. VD or VS, Dual Supply

= –16.5V

11.5

06815-104

3.0

2.5

2.0

1.5

1.0

ON RESISTANCE ()

0.5
VDD = +15V

V

= –15V

SS

I

= –10mA

S

0

–15 151050–5–10

TA = +125°C

= +85°C

T

A

TA = +25°C

T

= –40°C

A

VS OR VD (V)

06815-107

Figure 8. On Resistance vs. VD or VS for Different Temperatures, 15 V Dual Supply

4.0

3.5

3.0

2.5

2.0

1.5

ON RESISTANCE ()

1.0

0.5
TA = 25°C

I

= –10mA

S

0

–7 –6 –5 –3 –1–4 –2 0 1 6

V

DD

V

SS

= +4.5V,
= –4.5V

V

= +5V,

DD

V

= –5V

SS

V

DD

V

SS

VS OR VD (V)

= +5.5V,
= –5.5V

Figure 6. On Resistance vs. VD or VS, Dual Supply

7

6

5

4

3

ON RESISTANCE ( )

2

1

TA = 25°C
I

= –10mA

S

0

01412108642

V

= 5V,

DD

V

= 0V

SS

= 10.8V,

V

= 8V,

V

DD

V

= 0V

SS

DD

V

SS

V

DD

V

SS

VS OR VD (V)

= 0V

= 13.2V,

= 0V

Figure 7. On Resistance vs. VD or VS, Single Supply

34 752

VDD = +7V,
V

= –7V

SS

V

= 12V,

DD

V

= 0V

SS

VDD = 15V,
V

= 0V

SS

5.0

4.5

4.0

3.5

3.0

2.5

2.0

ON RESISTANCE ()

1.5

1.0

VDD = +5V

0.5

V

= –5V

SS

I

= –10mA

S

0

–5 –4 –3 –2 –1 0 1 2 3 4 5

06815-105

= +125°C

T

A

T

= +85°C

A

TA = +25°C

= –40°C

T

A

VS OR VD (V)

06815-108

Figure 9. On Resistance vs. VD or VS for Different Temperatures, 5 V Dual Supply

4.5

4.0

= +125°C

3.5

3.0

2.5

2.0

1.5

ON RESISTANCE ( )

1.0

VDD = 12V

0.5
V

= 0V

SS

I

= –10mA

S

0

01108642

06815-106

T

A

T

= +85°C

A

TA = +25°C

= –40°C

T

A

VS OR VD (V)

2

06815-109

Figure 10. On Resistance vs. VD or VS for Different Temperatures, Single Supply

Rev. 0 | Page 9 of 16

ADG1436

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2

1

0

–1

–2

–3

LEAKAGE (nA)

–4

–5

–6

–7

IS (OFF) + –
I

(OFF) + –

D

I

(OFF) – +

S

I

(OFF) – +

D

I

, IS (ON) + +

D

I

, IS (ON) – –

D

VDD = +15V
V

= –15V

SS

V

= +10V/–10V

BIAS

0 20406080100120

TEMPERATURE (°C)

Figure 11. Leakage Currents vs. Temperature, 15 V Dual Supply

06817-111

80

70

60

50

40

(µA)

DD

I

30

20

10

0

0112108642

V

= +12V

DD

V

= 0V

SS

V

= +5V

DD

V

= –5V

SS

LOGIC, Ax (V)

TA = 25°C
I

PER LOGI C INPUT

DD

VDD = +15V
V

= –15V

SS

4

06817-008

Figure 14. IDD vs. Logic Level

1.5

1.0

0.5

0

(OFF) + –

I

–0.5

–1.0

LEAKAGE (nA)

–1.5

–2.0

–2.5

S

I

(OFF) + –

D

I

(OFF) – +

S

I

(OFF) – +

D

I

, IS (ON) + +

D

I

, IS (ON) – –

D

VDD = +5V
V

= –5V

SS

V

= +4.5V/–4. 5V

BIAS

0 20406080100120

TEMPERATURE (°C)

Figure 12. Leakage Currents vs. Temperature, 5 V Dual Supply

8

7

6

5

4

3

2

LEAKAGE (nA)

1

0

–1

–2

(OFF) + –

I

S

I

(OFF) + –

D

I

(OFF) – +

S

I

(OFF) – +

D

I

, IS (ON) + +

D

I

, IS (ON) – –

D

VDD = 12V
V

= 0V

SS

V

= 1V/10V

BIAS

0 20406080100120

TEMPERATURE (°C)

Figu re 13. Leakage Currents vs. Temperature, 12 V Single Supply

600

= 25°C

T

A

400

200

= +5V, VSS = –5V

V

DD

0

–200

CHARGE INJECTI ON (pC)

–400

–600

–15 –10 –5 0 5 10 15

06817-113

VDD = +15V, VSS = –15V

= +12V, VSS = 0V

V

DD

VS (V)

06817-012

Figure 15. Charge Injection vs. Source Voltage

450

400

350

300

250

200

TIME (ns)

150

100

50

0

–40 120100806040200–20

06817-112

VDD = +5V
V

SS

Figure 16. t

= –5V

V

= +12V

DD

V

= 0V

SS

TEMPERATURE (°C)

Time vs. Temperature

TRANSITION

V
V

DD
SS

= +15V

= –15V

06817-217

Rev. 0 | Page 10 of 16

ADG1436

www.BDTIC.com/ADI

0

VDD = +15V
V

= –15V

–10

SS

T

= 25°C

A

–20

–30

–40

–50

–60

OFF ISOLATION (dB)

–70

–80

–90

–100

1k 10k 100k 1M 10M 1G100M

FREQUENCY (Hz)

Figure 17. Off Isolation vs. Frequency

06817-014

0

VDD = +15V
V

= –15V

–10

SS

V p-p = 0.63V
T

= 25°C

–20

A

–30

–40

–50

–60

ACPSRR (dB)

–70

–80

–90

–100

1k 10k 100k 1M 10M

NO DECOUPLI NG

CAPACITORS

FREQUENCY (Hz)

DECOUPLING
CAPACITORS

ON SUPPLIES

Figure 20. ACPSRR vs. Frequency

06817-017

CROSSTALK (dB)

INSERTION LOSS (dB)

0

–20

–40

–60

–80

–100

–120

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

V

= +15V

DD

V

= –15V

SS

T

= 25°C

A

CHANNEL-TO-CHANNEL
(SxA TO SxB)

1k 100M10M1M100k10k

FREQUENCY (Hz)

Figure 18. Crosstalk vs. Frequency

1k 1G100M10M1M100k10k

FREQUENCY (Hz)

Figure 19. On Response vs. Frequency

MUX-TO-MUX
(S1x TO S2x)

VDD = +15V
V

= –15V

SS

T

= 25°C

A

06817-019

06817-020

0.024

0.022

VDD = +15V
V

= –15V

SS

0.020
T

= 25°C

A

0.018

0.016

0.014

0.012

THD + N (%)

0.010

0.008

0.006

0.004

0.002

10 100 1k 10k 100k

VS = 20V p-p

= 15V p-p

V

S

= 10V p-p

V

S

FREQUENCY (Hz)

Figure 21. THD + N vs. Frequency, 15 V Dual Supply

1

VDD = +5V
V

= –5V

SS

T

= 25°C

A

0.1

THD + N (%)

0.01

0.001

10 100 1k 10k 100k

V

= 10V p-p

S

V

= 5V p-p

S

V

= 2.5V p-p

S

FREQUENCY (Hz)

Figure 22. THD + N vs. Frequency, 5 V Dual Supply

06817-117

06817-118

Rev. 0 | Page 11 of 16

ADG1436

www.BDTIC.com/ADI

TERMINOLOGY

IDD

The positive supply current.

I

SS

The negative supply current.

V

, VS

D

The analog voltage on Terminal D and Terminal S.

R

ON

The ohmic resistance between Terminal D and Terminal S.

R

FLAT(ON)

Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the
specified analog signal range.

I

(Off)

S

The source leakage current with the switch off.

I

(Off)

D

The drain leakage current with the switch off.

I

, IS (On)

D

The channel leakage current with the switch on.

V

INL

The maximum input voltage for Logic 0.

V

INH

The minimum input voltage for Logic 1.

I

, I

INL

INH

The input current of the digital input.

C

(Off)

S

The off-switch source capacitance, which is measured with
reference to ground.

C

(Off)

D

The off-switch drain capacitance, which is measured with
reference to ground.

C

, CS (On)

D

The on-switch capacitance, which is measured with reference
to ground.

C

IN

The digital input capacitance.

t

TRANSITION

The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

Off Isolation

A measure of unwanted signal coupling through an off switch.

Crosstalk

A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

THD + N

The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

Rev. 0 | Page 12 of 16

ADG1436

www.BDTIC.com/ADI

TEST CIRCUITS

V

S

V

SxA/SxB Dx

Figure 23. On Resistance

V

0.1µF

INx

V

IN

I

DS

06817-023

V

DD

SS

V

V

DD

SxA

D

GND

OFF ISOLATION = 20 log

0.1µF

SS

x

SxB

NC

50

Figure 26. Off Isolation

NETWORK
ANALYZER

50

V

S

V

OUT

R

L

50

V

OUT

V

S

06817-030

IS (OFF) ID (OFF)

SxA/SxB Dx

A A

V

S

Figure 24. Off Leakage

SxA/SxB Dx

NC

ID (ON)

A

V

0.1µF

INx

V

IN

V

D

06817-024

INSERTION LOSS = 20 log

V

DD

V

SS

0.1µF

NETWORK

V

DD

SxA

GND

SS

D

x

SxB

NC

50

WITH SWITCH

V

OUT

V

WITHOUT SWITCH

OUT

ANALYZER

50

V

OUT

R

L

50

V

S

06817-031

Figure 27. Channel-to-Channel Crosstalk

NETWORK
ANALYZER

V

OUT

V

0.1µF

R

L

50

V

S

SxA

SxB

INx

V

DD

V

SS

0.1µF

V

DD

SS

Dx

R
50

GND

V

NC = NO CONNECT

D

06817-025

Figure 25. On Leakage

Rev. 0 | Page 13 of 16

CHANNEL-TO -CHANNEL CROS STALK = 20 log

Figure 28. Bandwidth

V

OUT

V

S

06817-032

ADG1436

www.BDTIC.com/ADI

V

0.1µF

SxA/SxB

INx

V

IN

V

DD

V

SS

0.1µF

R

L

110

AUDIO PRECISI ON

R

S

V

S

V p-p

V

OUT

06817-033

V

DD

SS

Dx

GND

Figure 29. THD + Noise

V

V

DD

SS

0.1µF0.1µF

V

V

DD

GND

SS

Dx

R

L

300

C

L

35pF

V

OUT

SxB

V

S

SxA

INx

V

IN

V

IN

V

IN

V

OUT

t

50%

50%

90%

ON

50%

50%

90%

t

OFF

06817-026

Figure 30. Switching Times

V

V

DD

SS

0.1µF0.1µF

V

V

V

DD

GND

SS

Dx

R

L

300

C

L

35pF

V

OUT

V

V

IN

SxB

S

SxA

INx

IN

80%

V

OUT

t

BBM

t

BBM

06817-027

Figure 31. Break-Before-Make Time Delay

Rev. 0 | Page 14 of 16

ADG1436

www.BDTIC.com/ADI

3V

ENABLE
DRIVE (V

0V

OUTPUT

)

IN

50% 50%

0.9V

OUT

t

(EN)tON (EN)

OFF

0.9V

OUT

Figure 32. Enable Delay, t

V

IN

(EN), t

ON

50

OFF

(EN)

V

V

INx

EN

DDVSS

DDVSS

GND

SxA

SxB

Dx

OUTPUT

300

V

S

35pF

06817-028

V

V

DD

SS

0.1µF0.1µF

VIN(NORMALLY

NC

V

OUT

CLOSED SWI TCH)

VIN(NORMALLY
OPEN SWITCH)

V

OUT

V

OUT

Q

INJ

ON

= CL × V

OFF

OUT

V

V

DD

SS

GND

SxB

SxA

C
1nF

L

Dx

V

S

INx

V

IN

06817-029

Figure 33. Charge Injection

Rev. 0 | Page 15 of 16

ADG1436

C

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.50

0.40

INDI

SEATING

PLANE

PIN 1

ATO R

1.00

0.85

0.80

12° MAX

4.00

BSC SQ

3.75

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.05 MAX

0.30

0.23

0.18

COMPLIANTTOJEDEC STANDARDS MO-220-VGGC.

0.02 NOM

0.20 REF

0.60 MAX

12

0.65

9

BSC

1.95 BCS

COPLANARITY

0.08

13

EXPOSED

8

BOTTOM VIEW

PAD

0.30

1

16

4

5

P

N

I

N

I

D

2.65

2.50 SQ

2.35

0.25 MIN

1

R

O

C

I

A

T

031006-A

Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-13)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG1436YRUZ
ADG1436YRUZ-REEL7
ADG1436YCPZ-REEL
ADG1436YCPZ-REEL7

1

Z = RoHS Compliant Part.

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06817-0-7/08(0)

1

1

−40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-13

1

−40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-13

−40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16

Rev. 0 | Page 16 of 16