Datasheet ADG1236 Datasheet (ANALOG DEVICES)

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Low Capacitance, Low Charge Injection,

FEATURES

1.3 pF off capacitance

3.5 pF on capacitance
1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at +12 V, ±15 V

supply required

No V

L

3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 12-lead LFCSP packages
Typical power consumption: <0.03 μW

APPLICATIONS

Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio/video signal routing
Communication systems

GENERAL DESCRIPTION

±15 V/12 V iCMOS™, Dual SPDT Switch

ADG1236

FUNCTIONAL BLOCK DIAGRAM

S1A

S1B

IN1

IN2

S2A

S2B

SWITCHES SHOWN FOR A LOGIC 1 INPUT

ADG1236

Figure 1.

D1

D2

04776-001

The ADG1236 is a monolithic CMOS device containing two
independently selectable SPDT switches. It is designed on an
iCMOS process. iCMOS (industrial CMOS) is a modular
manufacturing process combining high voltage complementary
metal-oxide semiconductor (CMOS) and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no
previous generation of high voltage parts has been able to
achieve. Unlike analog ICs using conventional CMOS processes,
iCMOS components can tolerate high supply voltages while
providing increased performance, dramatically lower power
consumption, and reduced package size.

The ultralow capacitance and charge injection of the part make
it an ideal solution for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth makes the
part suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the part ideally
suited for portable and battery-powered instruments.

Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.

PRODUCT HIGHLIGHTS

1. 1.3 pF off capacitance (±15 V supply).

2. 1 pC charge injection.

3. 3 V logic-compatible digital inputs: V

4. No V

logic power supply required.

L

5. Ultralow power dissipation: <0.03 μW.

6. 16-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP packages.

= 2.0 V, VIL = 0.8 V.

IH

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

ADG1236

TABLE OF CONTENTS

Features.............................................................................................. 1

Absolute Maximum Ratings ............................................................6

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Dual Supply................................................................................... 3

Single Supply................................................................................. 5

REVISION HISTORY

9/05—Revision 0: Initial Version

Truth Table for Switches...............................................................6

ESD Caution...................................................................................6

Pin Configurations and Function Descriptions............................7

Terminology.......................................................................................8

Typical Performance Characteristics..............................................9

Test Circuits..................................................................................... 12

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

ADG1236

SPECIFICATIONS

DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Y Version1

−40°C to

Parameters 25°C

+85°C

ANALOG SWITCH

Analog Signal Range VDD to VSS V
On Resistance (RON) 120 Ω typ VS = ±10 V, IS = −1 mA; Figure 20
190 230 260 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between

Channels (∆R

)

ON

3.5 Ω typ VS = ±10 V, IS = −1 mA

6 10 12 Ω max
On Resistance Flatness (R

) 20 Ω typ VS = −5 V, 0 V, +5 V; IS = −1 mA

FLAT(ON)

57 72 79 Ω max

LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) ±0.02 nA typ

±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ

±0.1 ±0.6 ±1 nA max
Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = ±10 V; Figure 22
±0.2 ±0.6 ±1 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.005 μA typ VIN = V

INH

±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ

DYNAMIC CHARACTERISTICS2

Transition Time, t

TRANS AOFF BON

125 ns typ RL = 300 Ω, CL = 35 pF
150 200 ns max VS = 10 V; Figure 23
Transition Time, t

TRANS BOFF AON

70 ns typ RL = 300 Ω, CL = 35 pF
90 115 ns max VS = 10 V; Figure 23
Break-Before-Make Time Delay, tD 25 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 10 V; Figure 24
Charge Injection −1 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 25
Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26
Channel-to-Channel Crosstalk 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz

−3 dB Bandwidth 1000 MHz typ RL = 50 Ω, CL = 5 pF; Figure 28
CS (Off) 1.3 pF typ f = 1 MHz; VS = 0 V

1.6 pF max f = 1 MHz; VS = 0 V
CD, CS (On) 3.5 pF typ f = 1 MHz; VS = 0 V

4.3 pF max f = 1 MHz; VS = 0 V

−40°C to
+125°C

Unit Test Conditions/Comments1

VS = ±10 V, VS = ∓10 V; Figure 21

VS = ±10 V, VS = ∓10 V; Figure 21

or V

INH

INL

Rev. 0 | Page 3 of 16

ADG1236

Y Version1

−40°C to

Parameters 25°C

+85°C

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max
IDD 170 μA typ Digital inputs = 5 V
230 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max
ISS 0.001 μA typ Digital inputs = 5 V

1.0 μA max

1

Temperature range for Y version is −40°C to +125°C.

2

Guaranteed by design; not subject to production test.

−40°C to
+125°C

Unit Test Conditions/Comments1

Rev. 0 | Page 4 of 16

ADG1236

SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

Y Version1

−40°C to

Parameters 25°C

ANALOG SWITCH

+85°C

Analog Signal Range 0 V to VDD V
On Resistance (RON) 300 Ω typ VS = 0 V to 10 V, IS = −1 mA; Figure 20

On Resistance Match Between

Channels (∆R

)

ON

475 567 625 Ω max V

4.5 Ω typ V

16 26 27 Ω max

On Resistance Flatness (R

) 60 Ω typ VS = 3 V, 6 V, 9 V, IS = −1 mA

FLAT(ON)

LEAKAGE CURRENTS

Source Off Leakage, IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 21

±0.1 ±0.6 ±1 nA max

Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 21

±0.1 ±0.6 ±1 nA max

Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = 1 V or 10 V, Figure 22

±0.2 ±0.6 ±1 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

Digital Input Capacitance, CIN 3

DYNAMIC CHARACTERISTICS2

Transition Time, t

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INH

±0.1 μA max

TRANS BOFF AON

105 ns typ RL = 300 Ω, CL = 35 pF
140 175 ns max VS = 8 V; Figure 23
Transition Time, t

TRANS AOFF BON

155 ns typ RL = 300 Ω, CL = 35 pF
190 255 ns max VS = 8 V; Figure 23
Break-Before-Make Time Delay, tD 50

Charge Injection −0.8
Off Isolation 75
Channel-to-Channel Crosstalk 85

−3 dB Bandwidth 800

10 ns min V

CS (Off) 1.6 pF typ f = 1 MHz; VS = 6 V

1.9 pF max f = 1 MHz; VS = 6 V
CD, CS (On) 4 pF typ f = 1 MHz; VS = 6 V

4.9 pF max f = 1 MHz; VS = 6 V

POWER REQUIREMENTS

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max

IDD 170 μA typ Digital inputs = 5 V

1

Temperature range for Y version is −40°C to +125°C.

2

Guaranteed by design; not subject to production test.

230 μA max

−40°C to
+125°C

Unit Test Conditions/Comments

= 10.8 V, VSS = 0 V

DD

= 0 V to 10 V, IS = −1 mA

S

VDD = 13.2 V

or V

INH

INL

pF typ

ns typ RL = 300 Ω, CL = 35 pF

= VS2 = 8 V; Figure 24

S1

pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 25
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26;
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
MHz typ RL = 50 Ω, CL = 5 pF; Figure 28

VDD = 13.2 V

Rev. 0 | Page 5 of 16

ADG1236

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs1

Digital Inputs1

Peak Current, S or D

Continuous Current per

Channel, S or D

Operating Temperature Range

Automotive (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
16-Lead TSSOP, θJA Thermal

Impedance
12-Lead LFCSP, θJA Thermal

Impedance
Reflow Soldering Peak

Temperature, Pb Free

1

Over voltages at IN, S, or D are clamped by internal diodes. Current should

be limited to the maximum ratings given.

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs first
GND − 0.3 V to V

30 mA, whichever occurs first
100 mA (pulsed at 1 ms,

10% duty cycle max)
25 mA

112°C/W

80°C/W

260°C

+ 0.3 V or

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

TRUTH TABLE FOR SWITCHES

Table 4.

IN Switch A Switch B

0 Off On
1 On Off

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 16

ADG1236

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NC

S1A

IN1
11

10

1D1
2S1B
3V

12

PIN 1
INDICATOR

ADG1236

TOP VIEW

(Not to Scale)

4

5
IN2

GND

9V

DD

8 S2B
7D2

6

S2A

.

04776-003

SS

1

IN1

S1A

2

3

D1

ADG1236

4

S1B

TOP VIEW

5

V

SS

(Not to Scale)

6

GND

7

NC

8

NC

NC = NO CONNECT

16

NC
NC

15

14

NC

13

V

DD

12

S2B

11

D2

10

S2A

9

IN2

04776-002

NC = NO CONNECT

NOTES

1. EXPOSED PAD TIED TO SUBSTRATE, V

Figure 2. TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 11 IN1 Logic Control Input.
2 12 S1A Source Terminal. Can be an input or output.
3 1 D1 Drain Terminal. Can be an input or output.
4 2 S1B Source Terminal. Can be an input or output.
5 3 VSS Most Negative Power Supply Potential.
6 4 GND Ground (0 V) Reference.
7, 8, 14 to 16 10 NC No Connect.
9 5 IN2 Logic Control Input.
10 6 S2A Source Terminal. Can be an input or output.
11 7 D2 Drain Terminal. Can be an input or output.
12 8 S2B Source Terminal. Can be an input or output.
13 9 VDD Most Positive Power Supply Potential.

SS

Figure 3. LFCSP Pin Configuration

Rev. 0 | Page 7 of 16

ADG1236

TERMINOLOGY

IDD

The positive supply current.

I

SS

The negative supply current.

(VS)

V

D

The analog voltage on Terminals D and S.

R

ON

The ohmic resistance between D and S.

R

Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.

I

The source leakage current with the switch off.

I

The drain leakage current with the switch off.

I

The channel leakage current with the switch on.

V

The maximum input voltage for Logic 0.

V

The minimum input voltage for Logic 1.

I

The input current of the digital input.

C

The off switch source capacitance, measured with reference to
ground.

FLAT(ON)

(Off)

S

(Off)

D

, IS (On)

D

INL

INH

(I

INL

INH

(Off)

S

)

C

(Off)

D

The off switch drain capacitance, measured with reference to
ground.

, CS (On)

C

D

The on switch capacitance, measured with reference to ground.

C

IN

The digital input capacitance.

t

TRANS

The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

Off Isolation

A measure of unwanted signal coupling through an off switch.

Crosstalk

A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

THD + N

The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

Rev. 0 | Page 8 of 16

ADG1236

TYPICAL PERFORMANCE CHARACTERISTICS

200

TA = 25°C

180

160

140

120

100

80

ON RESISTANCE (Ω)

60

40

20

0
–18 –15 –12 –9 –6 –3 12 15906318

VDD = 13.5V

= –13.5V

V

SS

VDD = 16.5V
V

SS

SOURCE OR DRAIN VOLTAGE (V)

Figure 4. On Resistance as a Function of V

VDD = 15V

= –15V

V

SS

= –16.5V

(VS) for Dual Supply

D

04776-011

250

200

150

100

ON RESISTANCE (Ω)

50

0

–15 –10 –5 1005 15

TA = +125°C

TA = +85°C

TA = +25°C

TA = –40°C

TEMPERATURE (°C)

Figure 7. On Resistance as a Function of V

Dual Supply

VDD = 15V
V

= –15V

SS

(VS) for Different Temperatures,

D

04776-014

600

TA = 25°C

500

400

300

200

ON RESISTANCE (Ω)

100

0

–6 –4 –2 402 6

VDD = 5.5V
V

SOURCE OR DRAIN VOLTAGE (V)

Figure 5. On Resistance as a Function of V

450

TA = 25°C

400

350

300

250

200

150

ON RESISTANCE (Ω)

100

50

0

0246 12810 14

VDD = 13.2V
V

SS

SOURCE OR DRAIN VOLTAGE (V)

Figure 6. On Resistance as a Function of V

= –5.5V

SS

= 0V

VDD = 4.5V
V

SS

VDD = 10.8V
V

= 0V

SS

= –4.5V

VDD = 5V
V

= –5V

SS

(VS) for Dual Supply

D

VDD = 12V
V

= 0V

SS

(VS) for Single Supply

D

04776-012

04776-013

600

500

400

300

200

ON RESISTANCE (Ω)

100

0

024 1068 12

TA = +125°C

TA = –40°C

TEMPERATURE (°C)

Figure 8. On Resistance as a Function of V

(VS) for Different Temperatures,

D

VDD = 12V
V

SS

TA = +85°C

TA = +25°C

= 0V

Single Supply

0.20
VDD = 15V
V

= –15V

SS

0.15

V

= +10V/–10V

BIAS

0.10

0.05

0

–0.05

LEAKAGE (nA)

–0.10

–0.15

–0.20

0 20 40 10060 80 120

TEMPERATURE (°C)

IS(OFF)

ID, IS(ON)

Figure 9. Leakage Currents as a Function of Temperature, Dual Supply

04776-015

04776-016

Rev. 0 | Page 9 of 16

ADG1236

0.35
VDD = 12V
V

= 0V

SS

0.30
V

= 1V/10V

BIAS

0.25

0.20

0.15

0.10

LEAKAGE (nA)

0.05

0

–0.05

–0.10

0 20 40 10060 80 120

TEMPERATURE (°C)

Figure 10. Leakage Currents as a Function of Temperature, Single Supply

ID, IS(ON)

IS(OFF)

04776-017

220

200
180
160

140
120
100

TIME (ns)

80
60
40
20

0

–40 –20 0 4020 60 80 100 120

A

B

OFF AON

Figure 13. t

12V SS

OFF BON

15V DS

TEMPERATURE (°C)

TRANSITION

A

15V DS

OFF BON

B

12V SS

OFF AON

Times vs. Temperature

04776-004

60

50

40

30

(μA)

DD

I

20

10

0

0 2 4 6 8 10 12 14

6

TA = 25°C

4

2

0

–2

CHARGE INJECTIOIN (pC)

–4

–6

–15 –10 –5 1005 15

VDD = 12V

Figure 11. I

VDD = 15V
V

= –15V

SS

= 0V

V

SS

LOGIC, INX (V)

vs. Logic Level

DD

V

BIAS

(V)

VDD = 15V
V

IDD PER CHANNEL

= 25°C

T

A

= –15V

SS

VDD = 12V
V

SS

= 0V

Figure 12. Charge Injection vs. Source Voltage

04776-018

04776-005

0

VDD = 15V
V

= –15V

–10

SS

T

= 25°C

A

–20

–30

–40

–50

–60

OFF ISOLATION (dB)

–70

–80

–90

–100

10k 100k 10M1M 100M 1G

FREQUENCY (Hz)

Figure 14. Off Isolation vs. Frequency

0

VDD = 15V
V

= –15V

–10

SS

T

= 25°C

A

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

–100

10k 100k 10M1M 100M 1G

BETWEEN
SA AND SB

FREQUENCY (Hz)

Figure 15. Crosstalk vs. Frequency

BETWEEN
S1 AND S2

04776-010

04776-008

Rev. 0 | Page 10 of 16

ADG1236

0

–5

VDD = 15V
V

= –15V

SS

T

= 25°C

A

5

VDD = 15V

= –15V

V

SS

T

= 25°C

A

4

SOURCE/DRAIN ON

–10

–15

–20

ON RESPONSE (dB)

–25

–30

10k 100k 10M1M 100M 10G1G

FREQUENCY (Hz)

Figure 16. On Response vs. Frequency

10.00
LOAD = 10kΩ

T

= 25°C

A

1.00
VDD = 5V, VSS = –5V, VS = 3.5Vrms

THD + N (%)

0.10

VDD = 15V, VSS = –15V, VS = 5Vrms

04776-009

3

2

CAPACITANCE (pF)

1

0

–15 –10 –5 1005 15

SOURCE OFF

V

(V)

BIAS

Figure 18. Capacitance vs. Source Voltage for Dual Supply

5

SOURCE/DRAIN ON

4

VDD = 12V

= 0V

V

SS

= 25°C

T

A

3

2

CAPACITANCE (pF)

1

SOURCE OFF

04776-007

0.01

10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 17. THD + N vs. Frequency

04776-019

0

024 1068 12

V

BIAS

(V)

Figure 19. Capacitance vs. Source Voltage for Single Supply

04776-006

Rev. 0 | Page 11 of 16

ADG1236

V

V

V

TEST CIRCUITS

V

SD

I

V

S

DS

04776-020

Figure 20. Test Circuit 1—On Resistance Figure 21. Test Circuit 2—Off Resistance Figure 22. Test Circuit 3—On Leakage

V

V

DD

SS

V

V

DD

SS

SB

V

S

SA

IN

IN

GND

IS (OFF) ID (OFF)

SD

A A

S

0.1μF0.1μF

D

R

L

300Ω

C

L

35pF

V

OUT

V

IN

V

IN

V

OUT

Figure 23. Test Circuit 4—Switching Times

SD

NC

V

D

04776-021

50%

50%

90%

t

ON

NC = NO CONNECT

50%

50%

90%

t

OFF

04776-023

ID (ON)

A

V

D

04776-022

V

V

DD

SS

0.1μF0.1μF

V

V

V

DD

SS

SB

V

S

SA

IN

V

IN

GND

D

R

L

300Ω

C

L

35pF

V

OUT

IN

80%

V

OUT

t

BBM

t

BBM

04776-024

Figure 24. Test Circuit 5—Break-Before-Make Time Delay

V

V

DD

SS

0.1μF0.1μF
VIN(NORMALLY

NC
V

OUT

CLOSED SWITCH)

VIN(NORMALLY
OPEN SWITCH)

V

OUT

ΔV

OUT

Q

INJ

ON

= CL×ΔV

OUT

OFF

04776-025

V

V

DD

SS

GND

SB

SA

C
1nF

L

D

V

S

IN

IN

Figure 25. Test Circuit 6—Charge Injection

Rev. 0 | Page 12 of 16

ADG1236

V

V

0.1μF

IN

IN

V

DD

SS

0.1μF

V

V

DD

SS

NC

SA

SB

50Ω

D

GND

OFF ISOLATION = 20 log

Figure 26. Test Circuit 7—Off Isolation

NETWORK
ANALYZER

50Ω

V

S

V

OUT

R

L

50Ω

V

OUT

V

S

04776-026

NETWORK

ANALYZER

V

OUT

R

L

50Ω

V

S

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

Figure 28. Test Circuit 9—Bandwidth

V

0.1μF

SA

SB

IN

V

DD

V

SS

0.1μF

V

DD

SS

D

R
50Ω

GND

V

OUT

V

S

04776-028

V

0.1μF

IN

V

IN

INSERTION LOSS = 20 log

Figure 27. Test Circuit 8—Channel-to-Channel Crosstalk

V

DD

V

SS

0.1μF

NETWORK

V

DD

SS

NC

SA

SB

50Ω

D

GND

WITH SWITCH

V

OUT

V

WITHOUT SWITCH

OUT

ANALYZER

50Ω

V

OUT

R

L

50Ω

V

S

04776-027

V

0.1μF

IN

V

IN

V

DD

SS

0.1μF

V

V

DD

SS

AUDIO PRECISION

R

S

S

V

S

V p-p

V

OUT

04776-029

GND

D

R

L

10kΩ

Figure 29. Test Circuit 10—THD + Noise

Rev. 0 | Page 13 of 16

ADG1236

R

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40

BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.75

0.55

0.35

11

12

1

2

3

6

5

4

PIN 1
INDICATOR

*

1.45

1.30 SQ

1.15

0.25 MIN

PIN 1

INDICATO

1.00

0.85

0.80

SEATING

PLANE

12 MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

0.80 MAX

0.65 TYP

*

2.75

BSC SQ

EXPOSED PAD

(BOTTOM VIEW)

0.05 MAX

0.02 NOM

0.20 REF

COMPLIANT TOJEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.

0.45

0.60 MAX

10

9

8
7

0.50

BSC

COPLANARITY

0.08

Figure 31. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad

(CP-12-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG1236YRUZ1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1236YRUZ-REEL1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1236YRUZ-REEL71 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1236YCPZ-500RL71 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1
ADG1236YCPZ-REEL71 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1

1

Z = Pb-free part.

Rev. 0 | Page 14 of 16

ADG1236

NOTES

Rev. 0 | Page 15 of 16

ADG1236

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04776–0–9/05(0)

Rev. 0 | Page 16 of 16