Datasheet ADG1219 Datasheet (ANALOG DEVICES)

Low Capacitance, Low Charge Injection,

FEATURES

<0.5 pC charge injection over full signal range

2.5 pF off capacitance
Low leakage; 0.6 nA maximum @ 85°C
120 Ω on resistance
Fully specified at +12 V, ±15 V
No V

supply required

L

3 V logic-compatible inputs
Rail-to-rail operation
8-lead SOT-23 package

APPLICATIONS

Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio/video signal routing
Communication systems

±15 V/12 V iCMOS SPDT in SOT-23

ADG1219

FUNCTIONAL BLOCK DIAGRAM

ADG1219

SA

SB

DECODER

IN EN

SWITCHES S HOWN FOR A LOGIC 0 INPUT

Figure 1.

D

06575-001

GENERAL DESCRIPTION

The ADG1219 is a monolithic iCMOS® device containing an
SPDT switch. An EN input is used to enable or disable the
device. When disabled, all channels are switched off. When on,
each channel conducts equally well in both directions and has
an input signal range that extends to the supplies. Each switch
exhibits break-before-make switching action.

The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage complementary metal-oxide
semiconductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased perfor­mance, dramatically lower power consumption, and reduced
package size.

The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data acquisi­tion and sample-and-hold applications, where low glitch and
fast settling are required. Figure 2 shows that there is minimum

charge injection over the entire signal range of the device.
iCMOS construction also ensures ultralow power dissipation,
making the parts ideally suited for portable and battery­powered instruments.

0.5
TA = 25ºC

0.4

0.3

0.2

0.1

0

–0.1

–0.2

CHARGE INJECTI ON (pC)

–0.3

–0.4

–0.5

–15 15

Figure 2. Charge Injection vs. Input Voltage

VDD = +15V
V

= –15V

SS

VDD = +12V
V

SS

VDD = +5V
V

= –5V

SS

–10 –5 0 5 10

INPUT VOLTAGE (V)

= 0V

06575-033

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008–2009 Analog Devices, Inc. All rights reserved.

ADG1219

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Dual Supply ................................................................................... 3

Single Supply ................................................................................. 4

REVISION HISTORY

3/09—Rev. 0 to Rev. A

Change to Power Requirements, I
Change to Power Requirements, I

Updated Outline Dimensions ........................................................ 15

4/08—Revision 0: Initial Version

Parameter, Table 1 .............. 4

DD

Parameter, Table 2 .............. 5

DD

Absolute Maximum Ratings ............................................................6

ESD Caution...................................................................................6

Pin Configuration and Function Descriptions ..............................7

Typical Performance Characteristics ..............................................8

Test Circuits ..................................................................................... 12

Terminology .................................................................................... 14

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. A | Page 2 of 16

ADG1219

SPECIFICATIONS

DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

1

B Version
Parameters 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V
On Resistance, RON 120 Ω typ
200 240 270 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between

Channels, ∆R

ON

3.5 Ω typ V

6 10 12 Ω max
On Resistance Flatness, R

20 Ω typ VS = −5 V, 0 V, +5 V; IS = −1 mA

FLAT(ON)

64 76 84 Ω max

LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) ±0.004 nA typ
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.009 nA typ
±0.1 ±0.6 ±1 nA max
Channel On Leakage, ID, IS (On) ±0.02 nA typ
±0.2 ±0.6 ±1 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.005 μA typ VIN = V

INH

±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANSITION

2

140 ns typ RL = 300 Ω, CL = 35 pF

170 200 230 ns max

tON (EN) 85 ns typ RL = 300 Ω, CL = 35 pF

105 130 140 ns max

t

(EN) 105 ns typ RL = 300 Ω, CL = 35 pF

OFF

125 150 170 ns max

Break-Before-Make Time Delay, t

40 ns typ RL = 300 Ω, CL = 35 pF

BBM

10 ns min
Charge Injection 0.1 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;

Off Isolation 77 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

Channel-to-Channel Crosstalk 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz

−3 dB Bandwidth 520 MHz typ
CS (Off) 2.5 pF typ f = 1 MHz; VS = 0 V

3.3 pF max f = 1 MHz; VS = 0 V
CD (Off) 4.3 pF typ f = 1 MHz; VS = 0 V

5.1 pF max f = 1 MHz; VS = 0 V
CD, CS (On) 7.5 pF typ f = 1 MHz; VS = 0 V

10 pF max f = 1 MHz; VS = 0 V

V

= ±10 V, IS = −1 mA; see Figure 23

S

= ±10 V, IS = −1 mA

S

V

= ±10 V, VS = ±10 V; see Figure 24

S

V

= ±10 V, VS = ±10 V; see Figure 24

S

V

= VD = ±10 V; see Figure 25

S

or V

INL

V

= 10 V; see Figure 30

S

V

= 10 V; see Figure 30

S

V

= 10 V; see Figure 30

S

V

= VS2 = 10 V; see Figure 31

S1

see

Figure 32

see

Figure 26

see

Figure 27

R

= 50 Ω, CL = 5 pF; see Figure 28

L

INH

Rev. A | Page 3 of 16

ADG1219

B Version

1

Parameters 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max
IDD 140 μA typ Digital inputs = 5 V
190 μA max
ISS 0.001 μA typ Digital inputs = 0 V, 5 V or VDD

1.0 μA max
VDD/VSS ±5/±16.5 V

|V

| = |VSS|

DD

min/max

1

Temperature range for B version is −40°C to +125°C.

2

Guaranteed by design; not subject to production test.

SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

B Version
Parameters 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V
On Resistance, RON 300 Ω typ

On Resistance Match Between

Channels, ∆R

ON

16 26 27 Ω max

On Resistance Flatness, R

60 Ω typ VS = 3 V, 6 V, 9 V, IS = −1 mA

FLAT(ON)

LEAKAGE CURRENTS

Source Off Leakage, IS (Off) ±0.006 nA typ

Drain Off Leakage, ID (Off) ±0.006 nA typ

Channel On Leakage, ID, IS (On) ±0.02 nA typ

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INL

INH

Digital Input Capacitance, CIN 3

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANSITION

2

195 ns typ RL = 300 Ω, CL = 35 pF

250 300 340 ns max

tON (EN) 120 ns typ RL = 300 Ω, CL = 35 pF
150 190 210 ns max
t

(EN) 145 ns typ RL = 300 Ω, CL = 35 pF

OFF

185 220 255 ns max
Break-Before-Make Time Delay, t

Charge Injection −0.8
Off Isolation 80

Channel-to-Channel Crosstalk 80

−3 dB Bandwidth 400

475 567 625 Ω max V

4.5 Ω typ V

±0.1 ±0.6 ±1 nA max

±0.1 ±0.6 ±1 nA max

±0.2 ±0.6 ±1 nA max

±0.1 μA max

70

BBM

10 ns min

1

Rev. A | Page 4 of 16

V

= 0 V to 10 V, IS = −1 mA; see Figure 23

S

= 10.8 V, VSS = 0 V

DD

= 0 V to 10 V, IS = −1 mA

S

VDD = 13.2 V
V

= 1 V/10 V, VD = 10 V/1 V; see Figure 24

S

V

= 1 V/10 V, VD = 10 V/1 V; see Figure 24

S

V

= VD = 1 V or 10 V; see Figure 25

S

or V

INL

INH

pF typ

V

= 8 V; see Figure 30

S

V

= 8 V; see Figure 30

S

V

= 8 V; see Figure 30

S

ns typ RL = 300 Ω, CL = 35 pF

= VS2 = 8 V; see Figure 31

V

S1

pC typ

V

= 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32

S

dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

see

Figure 26

dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

see

Figure 27

MHz typ

R

= 50 Ω, CL = 5 pF; see Figure 28

L

ADG1219

B Version

1

Parameters 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

CS (Off) 2.9 pF typ f = 1 MHz; VS = 6 V

3.7 pF max f = 1 MHz; VS = 6 V
CD (Off) 5 pF typ f = 1 MHz; VS = 6 V

5.8 pF max f = 1 MHz; VS = 6 V
CD, CS (On) 8.5 pF typ f = 1 MHz; VS = 6 V
11 pF max f = 1 MHz; VS = 6 V

POWER REQUIREMENTS

VDD = 13.2 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max

IDD 140 μA typ Digital inputs = 5 V

190 μA max

VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V

1

Temperature range for B version is −40°C to +125°C.

2

Guaranteed by design; not subject to production test.

Rev. A | Page 5 of 16

ADG1219

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs

Digital Inputs

Peak Current, S or D

Continuous Current per

Channel, S or D

Operating Temperature Range

Industrial (B Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
8-Lead SOT-23, θJA Thermal

Impedance
Reflow Soldering Peak

Temperature, Pb Free

1

Overvoltages at IN, S, or D are clamped by internal diodes. Current should be

limited to the maximum ratings given.

1

1

VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first

GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first

100 mA (pulsed at 1 ms,
10% duty cycle maximum)

30 mA

211.5°C/W

260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 6 of 16

ADG1219

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EN

1

ADG1219

2

V

DD

TOP VIEW

3

GND

(Not to Scale)

V

4

SS

NC = NO CONNECT

Figure 3. SOT-23 Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 EN

Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off.

When this pin is high, the IN logic input determines which switch is turned on.
2 VDD Most Positive Power Supply Potential.
3 GND Ground (0 V) Reference.
4 VSS Most Negative Power Supply Potential.
5 SB Source Terminal. Can be an input or output.
6 D Drain Terminal. Can be an input or output.
7 SA Source Terminal. Can be an input or output.
8 IN Logic Control Input.

Table 5. Truth Table

EN IN Switch A Switch B

0 X Off Off
1 0 On Off
1 1 Off On

IN

8

7

SA

6

D

SB

5

3

06575-00

Rev. A | Page 7 of 16

ADG1219

TYPICAL PERFORMANCE CHARACTERISTICS

200

TA = 25°C

180

160

140

120

100

80

ON RESISTANCE (Ω)

60

40

20

0

–18 –15 –12 –9 –6 –3 12 15906318

VDD = 13.5V
V

= –13.5V

SS

VDD = 16.5V
V

SS

SOURCE OR DRAIN VO LTAGE (V)

= –16.5V

VDD = 15V
V

= –15V

SS

06575-004

Figure 4. On Resistance as a Function of VD (VS) for Dual Supply

250

200

150

100

ON RESISTANCE (Ω)

50

0

–15 –10 –5 1005 15

TA = +125°C

TA = +85°C

TA = +25°C

TA = –40°C

TEMPERATURE (°C)

VDD = 15V
V

= –15V

SS

06575-007

Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,

Dual Supply

600

TA = 25°C

500

400

300

200

ON RESISTANCE (Ω)

100

0

–6 –4 –2 402 6

VDD = 5.5V
V

SOURCE OR DRAIN VO LTAGE (V)

= –5.5V

SS

VDD = 4.5V
V

= –4.5V

SS

VDD = 5V
V

SS

= –5V

Figure 5. On Resistance as a Function of VD (VS) for Dual Supply

450

TA = 25°C

400

350

300

250

200

150

ON RESISTANCE (Ω)

100

50

0

02 46 12810 14

SOURCE OR DRAIN VO LTAGE (V)

Figure 6. On Resistance as a Function of V

VDD = 10.8V
V

VDD = 13.2V
V

= 0V

SS

= 0V

SS

VDD = 12V

V

= 0V

SS

(VS) for Single Supply

D

600

500

400

300

200

ON RESISTANCE (Ω)

100

06575-005

0

024 1068 12

TA = +125°C

TA = –40°C

TEMPERATURE (°C)

VDD = 12V
V

SS

TA = +85°C

TA = +25°C

= 0V

06575-008

Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,

Single Supply

0.6
VDD = 15V

= –15V

V

SS

0.4

0.2

–0.2

–0.4

LEAKAGE (nA)

–0.6

–0.8

06575-006

–1.0

= +10V/–10V

V

BIAS

0

IS(OFF)+–

(OFF)+–

I

D

(OFF)–+

I

S

(OFF)–+

I

D

, IS(ON)++

I

D

, IS(ON)– –

I

D

0

20 40 60 80 100 120

TEMPERATURE ( °C)

06575-030

Figure 9. Leakage Currents as a Function of Temperature, 15 V Dual Supply

Rev. A | Page 8 of 16

ADG1219

0.6

0.5

0.4

0.3

VDD = 12V

= 0V

V

SS

V

= 1V/10V

BIAS

IS(OFF)+–

(OFF)+–

I

D

(OFF)–+

I

S

(OFF)–+

I

D

, IS(ON)++

I

D

, IS(ON)– –

I

D

0.2

0.1

LEAKAGE (nA)

0

–0.1

–0.2

–0.3

0

20 40 60 80 100 120

TEMPERATURE (° C)

Figure 10. Leakage Currents as a Function of Temperature, 12 V Single

Supply

06575-031

0.5

TA = 25ºC

0.4

0.3

VDD = +15V
V

= –15V

SS

0.2

0.1

0

–0.1

–0.2

CHARGE INJECTI ON (pC)

VDD = 12V
V

= 0V

SS

–0.3

–0.4

–0.5

–15 15

VDD = +5V
V

= –5V

SS

–10 –5 0 5 10

INPUT VOLTAGE (V)

Figure 13. Charge Injection vs. Input Voltage

06574-041

0.3
VDD = 5V

= –5V

V

SS

0.2
V

BIAS

= +4.5V/–4.5V

0.1

0

–0.1

–0.2

LEAKAGE (nA)

–0.3

–0.4

–0.5

IS(OFF)+–

(OFF)+–

I

D

(OFF)–+

I

S

(OFF)–+

I

D

, IS(ON)++

I

D

, IS(ON)––

I

D

0

20 40 60 80 100 120

06575-032

TEMPERATURE (° C)

Figure 11. Leakage Currents as a Function of Temperature, 5 V Dual Supply

200

180

160

= +15V

V

140

V

DD
SS

= –15V

120

(µA)

100

DD

I

80

60

40

20

0

0 2 4 6 8 10121416

VDD = +12V
V

= 0V

SS

LOGIC, INX (V)

IDD PER CHANNEL
T

= 25°C

A

06575-009

Figure 12. IDD vs. Logic Level

300

250

12V SS

200

150

15V DS

TIME (ns)

100

50

0

–40 –20 0 12010080604020

TEMPERATURE (ºC)

Figure 14. t

Time vs. Temperature

TRANSITION

0

VDD = 15V

–10

V

= –15V

SS

T

= 25ºC

A

–20

–30

–40

–50

–60

–70

ISOLATION (dB)

–80

–90

–100

–110

10k 1G

100k 1M 10M 100M

FREQUENCY (Hz)

Figure 15. Off Isolation vs. Frequency

06575-027

6575-022
0

Rev. A | Page 9 of 16

ADG1219

0

VDD = 15V

–10

V

= –15V

SS

T

= 25ºC

–20

A

–30

–40

–50

–60

–70

CROSSTALK (d B)

–80

–90

–100

–110

10k 1G

100k 1M 10M 100M

FREQUENCY (Hz)

Figure 16. Crosstalk vs. Frequency

0

VDD = 15V
V

= –15V

SS

–2

T

= 25ºC

A

–4

–6

–8

INSERTION LOSS (dB)

–10

–12

–14

10k 1G

100k 1M 10M 100M

FREQUENCY (Hz)

Figure 17. On Response vs. Frequency

06575-026

06575-021

8

7

6

5

4

3

CAPACITANCE (pF )

2

= 15V

V

DD

V

= –15V

1

SS

T

= 25ºC

A

0

–15 15

–10 –5 0 5 10

SOURCE VOLTAGE (V)

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

06575-023

Figure 19. Capacitance vs. Source Voltage for Dual Supply

9

8

7

6

5

4

3

CAPACITANCE (pF )

2

V
V

1

T

0

012

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

= 12V

DD

= 0V

SS

= 25ºC

A

246810

SOURCE VOLTAGE (V)

06575-024

Figure 20. Capacitance vs. Source Voltage for Single Supply

10.00
LOAD = 10kΩ

T

= 25°C

A

1.00

VDD = 5V, VSS = –5V, VS = 3.5V rms

THD + N (%)

0.10

0.01
10 100 1k 10k 100k

VDD = 15V, VSS = –15V, VS = 5V rms

FREQUENCY ( Hz)

Figure 18. THD + N vs. Frequency

06575-010

Rev. A | Page 10 of

10

9

8

7

6

5

4

CAPACITANCE (pF )

3

2

VDD = 5V
V

1

T

0

–5 5

SOURCE/DRAIN ON

DRAIN OFF

= –5V

SS

= 25ºC

A

–3 –1 1 3

SOURCE VOLTAGE (V)

SOURCE OFF

Figure 21. Capacitance vs. Source Voltage for Dual Supply

16

06575-025

ADG1219

0

VDD = +15V

–10

V

= –15V

SS

V p-p = 0.63V

–20

T

= 25°C

A

–30

–40

–50

–60

ACPSRR (dB)

–70

–80

–90

–100

100k 1M 10M

Figure 22. ACPSRR vs. Frequency

NO DECOUPLI NG CAPS ON

DECOUPLING CAPS ON

FREQUENCY (Hz)

100M

4

06575-03

Rev. A | Page 11 of 16

ADG1219

TEST CIRCUITS

V

SD

V

S

Figure 23. On Resistance

IS (OFF) ID (OFF)

SD

A A

V

S

Figure 24. Off Leakage

SD

NC

NC = NO CONNECT

Figure 25. On Leakage

ID(ON)

A

V

V

0.1µF

I

DS

06575-011

IN

V

IN

INSERTION LOSS = 20 log

V

D

06575-012

D

06575-013

NETWO RK

ANALYZER

V

OUT

CHANNEL-TO -CHANNEL CROS STALK = 20 log

V

DD

SS

0.1µF

V

V

DD

SS

NC

SB

SA

50Ω

D

GND

WITH SWITCH

V

OUT

V

WITHOUT SWITCH

OUT

Figure 27. Channel-to-Channel Crosstalk

V

DD

0.1µF

V

DD

SA

R

L

50Ω

SB

V

S

IN

Figure 28. Bandwidth

GND

V

OUT

V

NETWORK
ANALYZER

50Ω

V

R

L

50Ω

V

SS

V

SS

S

OUT

0.1µF

D

V

S

06575-018

R
50Ω

06575-019

V

0.1µF

IN

V

IN

V

DD

SS

V

V

DD

SA

D

GND

OFF ISOLATION = 20 log

0.1µF

SS

NC

SB

50Ω

Figure 26. Off Isolation

V

NETWORK

ANALYZER

0.1µF

50Ω

V

S

V

OUT

R

L

50Ω

V

OUT

V

S

06575-017

IN

V

IN

V

DD

V

SS

0.1µF

V

DD

SS

AUDIO PRECISIO N

R

S

S

V

S

V p-p

V

OUT

06575-020

GND

D

R

L

10kΩ

Figure 29. THD + Noise

Rev. A | Page 12 of 16

ADG1219

V

IN

V

V

DD

SS

0.1µF0.1µF

V

V

DD

SS

SB

V

S

SA

IN

D

R

L

300Ω

C

L

35pF

V

OUT

GND

V

IN

V

IN

V

OUT

t

50%

50%

90%

ON

50%

50%

90%

t

OFF

06575-014

Figure 30. Switching Times

V

V

DD

SS

0.1µF0.1µF

V

V

V

DD

SS

SB

V

S

SA

IN

V

IN

GND

D

R

L

300Ω

C

L

35pF

V

OUT

IN

80%

V

OUT

t

BBM

t

BBM

06575-015

Figure 31. Break-Before-Make Time Delay

V

V

DD

SS

0.1µF0.1µF

VIN(NORMALLY

NC

V

OUT

CLOSED SWITCH)

VIN(NORMALLY
OPEN SWITCH)

V

OUT

ΔV

OUT

Q

INJ

ON

= CL × ΔV

OFF

OUT

V

V

DD

SS

GND

SB

SA

C
1nF

L

D

V

S

IN

V

IN

06575-016

Figure 32. Charge Injection

Rev. A | Page 13 of 16

ADG1219

TERMINOLOGY

IDD

The positive supply current.

I

SS

The negative supply current.

V

(VS)

D

The analog voltage on Terminal D and Terminal S.

R

ON

The ohmic resistance between Terminal D and Terminal S.

R

FLAT(ON)

Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.

I

(Off)

S

The source leakage current with the switch off.

I

(Off)

D

The drain leakage current with the switch off.

I

, IS (On)

D

The channel leakage current with the switch on.

V

INL

The maximum input voltage for Logic 0.

V

INH

The minimum input voltage for Logic 1.

I

(I

)

INL

INH

The input current of the digital input.

C

(Off)

S

The off switch source capacitance, measured with reference
to ground.

C

(Off)

D

The off switch drain capacitance, measured with reference
to ground.

C

, CS (On)

D

The on switch capacitance, measured with reference to ground.

C

IN

The digital input capacitance.

t

ON (EN)

Delay time between the 50% and 90% points of the digital input
and switch on condition.

t

OFF (EN)

Delay time between the 50% and 90% points of the digital input
and switch off condition.

t

TRANSITION

Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.

T

BBM

Off time measured between the 80% point of both switches
when switching from one address state to another.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

Off Isolation

A measure of unwanted signal coupling through an off switch.

Crosstalk

A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

Total Harmonic Distortion (THD + N)

The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

AC Power Supply Rejection Ratio (ACPSRR)

Measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on
the output to the amplitude of the modulation is the ACPSRR.

Rev. A | Page 14 of 16

ADG1219

OUTLINE DIMENSIONS

3.00

2.90

2.80

76

INDICATOR

1.30

1.15

0.90

0.15 MAX

0.05 MIN

1.70

1.60

1.50

8

1234

PIN 1

1.95
BSC

5

0.38 MAX

0.22 MIN

0.65 BSC

1.45 MAX

0.95 MIN

3.00

2.80

2.60

SEATING
PLANE

0.22 MAX

0.08 MIN

8°

0.60

4°

BSC

0°

0.60

0.45

0.30

COMPLIANT TO JEDEC ST ANDARDS MO-178-BA

121608-A

Figure 33. 8-Lead Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADG1219BRJZ-R2
ADG1219BRJZ-REEL7

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 8-Lead Lead Small Outline Transistor Package [SOT-23] RJ-8 S24

1

−40°C to +125°C 8-Lead Lead Small Outline Transistor Package [SOT-23] RJ-8 S24

Rev. A | Page 15 of 16

ADG1219

NOTES

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06575-0-3/09(A)

Rev. A | Page 16 of 16