Page 1
2 pF Off Capacitance, 1 pC Charge Injection,
S
Preliminary Technical Data
FEATURES
2 pF off capacitance
1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at +12 V, ±15 V
supply required
No V
L
3 V logic-compatible inputs
Rail-to-rail operation
14-lead TSSOP and 12-lead LFCSP
Typical power consumption: <0.03 µW
APPLICATIONS
Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
±15 V/12 V 4:1 iCMOS™ Multiplexer
ADG1204
FUNCTIONAL BLOCK DIAGRAM
S1
2
S3
S4
ADG1204
1 OF 4
DECODER
Figure 1.
D
ENA1A0
04779-0-001
GENERAL DESCRIPTION
The ADG1204 is a CMOS analog multiplexer, comprising four
single channels designed on an iCMOS process. iCMOS
(industrial-CMOS) is a modular manufacturing process that
combines high voltage CMOS (complementary metal-oxide
semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 30-V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike
analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages, while providing
increased performance, dramatically lower power consumption,
and reduced package size.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the parts
ideally suited for portable and battery powered instruments.
The ADG1204 switches one of four inputs to a common output,
D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch
conducts equally well in both directions when on, and has an
input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
PRODUCT HIGHLIGHTS
1. 2 pF off capacitance (±15 V supply).
2. 1 pC charge injection.
3. 3 V logic-compatible digital inputs:
= 2.0 V, VIL = 0.8 V
V
IH
4. No V
5. Ultralow power dissipation: <0.03 µW.
6. 14-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP package.
logic power supply required.
L
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
Page 2
ADG1204 Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Pin Configurations and Function Descriptions ............................8
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings............................................................ 7
Truth Tab l e .................................................................................... 7
ESD Caution.................................................................................. 7
REVISION HISTORY
11/04—Revision PrD: Preliminary Version
Te r m in o l o g y .......................................................................................9
Typical Perfor m a n c e Charac t e r ist i c s ........................................... 10
Tes t Ci rc ui ts ..................................................................................... 13
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Rev. PrD | Page 2 of 16
Page 3
Preliminary Technical Data ADG1204
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 120 160 180 Ω typ VS = ±10 V, IS = −10 mA; Figure 21
Ω max
On Resistance Match between
Channels (∆R
)
ON
5
Ω typ
Ω max
On Resistance Flatness (R
) 25 Ω typ VS = −5 V, 0 V, +5 V; IS = −10 mA
FLAT(ON)
50 Ω max
LEAKAGE CURRENTS VDD = +10 V, VSS = −10 V
Source Off Leakage, IS (Off) ±0.01 nA typ VS = 0 V/10 V, VD = 10 V/0 V; Figure 22
±0.5 ±1 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VS = 0 V/10 V, VD = 10 V/0 V; Figure 22
±0.5 ±1 ±5 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = 0 V or 10 V; Figure 23
±1 ±2 ±5 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
NH
0.005 µA typ VIN = V
±0.5 µA max
Digital Input Capacitance, C
DYNAMIC CHARACTERISTICS
Transition Time, t
40 ns typ RL = 50 Ω, CL = 35 pF
TRANS
IN
2
5 pF typ
ns max V
tON (EN) 40 ns typ RL = 50 Ω, CL = 35 pF
90 ns max VS = ±10 V; Figure 24
t
(EN) 20 ns typ RL = 50 Ω, CL = 35 pF
OFF
40 ns max VS = ±10 V; Figure 24
Break-before-Make Time Delay, tD 15 ns typ RL = 50 Ω, CL = 35 pF
1 ns min VS1 = VS2 = 10 V; Figure 25
Charge Injection 1 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
Off Isolation 75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
Channel-to-Channel Crosstalk 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
Total Harmonic Distortion + Noise 0.002 % typ RL = 600 Ω, 5 V rms, f = 20 Hz to 20 kHz
−3 dB Bandwidth 700 MHz typ RL = 50 Ω, CL = 5 pF; Figure 29
CS (Off) 2 pF typ
CD (Off) 7 pF typ
CD, CS (On) 4 pF typ
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 0.001 µA typ Digital Inputs = 0 V or VDD
5.0 µA max
IDD 150 µA typ Digital Inputs = 5 V
300 µA max
ISS 0.001 µA typ Digital Inputs = 0 V or VDD
5.0 µA max
= ±10 V, IS = −10 mA
V
S
or V
INH
INL
= ±10 V; Figure 24
S
Rev. PrD | Page 3 of 16
Page 4
ADG1204 Preliminary Technical Data
Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments
I
0.001 µA typ Digital Inputs = 0 V or VDD
GND
5.0 µA max
I
150 µA typ Digital Inputs = 5 V
GND
300 µA max
1
Y Version temperature range is −40°C to +125°C.
2
Guaranteed by design, not subject to production test.
= +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
V
DD
Table 2.
Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON) 220 Ω typ VS = ±3.3 V, IS = −10 mA; Figure 21
Ω max
On Resistance Match between
Channels (∆R
)
ON
10 Ω typ
Ω max V
On Resistance Flatness (R
) 30 Ω typ VS = ±3.3 V, IS = −10 mA
FLAT(ON)
Ω max
LEAKAGE CURRENTS VDD = 5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off) ±0.01 nA typ VD = ±4.5 V, VS = ±4.5 V; Figure 22
±0.5 ±1 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VD = ±4.5 V, VS = ±4.5 V; Figure 22
±0.5 ±1 ±5 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VD = VS = ±4.5 V; Figure 23
±1 ±2 ±5 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
INH
0.005 µA typ VIN = V
±0.5 µA max
Digital Input Capacitance, C
IN
5 pF typ
DYNAMIC CHARACTERISTICS2
t
ON
160 ns typ RL = 300 Ω, CL = 35 pF
ns max V
t
OFF
60 ns typ RL = 300 Ω, CL = 35 pF
ns max V
Break-before-Make Time Delay, tD50 ns typ RL = 300 Ω, CL = 35 pF
1 ns min VS1 = VS2 = 3 V; Figure 25
Charge Injection 20 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
pC max
Off Isolation 56
Channel-to-Channel Crosstalk 60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
−3 dB Bandwidth 20 MHz typ RL = 50 Ω, CL = 5 pF; Figure 29
CS (Off) 15 pF typ f = 1 MHz
CD (Off) pF typ f = 1 MHz
CD, CS (On) 100 pF typ f = 1 MHz
VSS to VDD V
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
= ±3.3 V, IS = −10 mA
S
or V
INL
INH
= 3 V; Figure 24
S
= 3 V; Figure 24
S
Rev. PrD | Page 4 of 16
Page 5
Preliminary Technical Data ADG1204
Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V
I
DD
5.0 µA max
I
SS
5.0 µA max
1
Y Version temperature range is −40°C to +125°C.
2
Guaranteed by design, not subject to production test.
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON) 220 Ω typ VS = 10 V, IS = −10 mA; Figure 21
Ω max
On Resistance Match between 1 Ω typ VS = 10 V, IS = −10 mA
Channels (∆RON) Ω max
On Resistance Flatness (R
LEAKAGE CURRENTS VDD = 12 V
Source Off Leakage, IS (Off) ±0.01 nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 22
±0.5 ±1 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 22
±0.5 ±1 ±5 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = 1 V or 10 V; Figure 23
±1 ±2 ±5 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
or I
INL
±0.5 µA max
Digital Input Capacitance, C
DYNAMIC CHARACTERISTICS
Transition Time, t
TRANS
ns max VS = ±10 V; Figure 24
tON (EN) 50 ns typ RL = 50 Ω, CL = 35 pF
ns max VS = 8 V; Figure 24
t
(EN) 15 ns typ RL = 50 Ω, CL = 35 pF
OFF
ns max VS = 8 V; Figure 24
Break-before-Make Time Delay, tD 15 ns typ RL = 50 Ω, CL = 35 pF
1 ns min VS1 = VS2 = 8 V; Figure 25
Charge Injection 5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
Off Isolation 75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
Channel-to-Channel Crosstalk 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
−3 dB Bandwidth 700 MHz typ RL = 50 Ω, CL = 5 pF; Figure 29
CS (Off) 2 pF typ
CD (Off) 2 pF typ
CD, CS (On) 4 pF typ
FLAT(ON)
2.0 V min
INH
0.8 V max
INL
0.001 µA typ VIN = V
INH
IN
2
40 ns typ RL = 50 Ω, CL = 35 pF
0.001 µA typ Digital Inputs = 0 V or 5.5 V
0.001 µA typ Digital Inputs = 0 V or 5.5 V
0 V to V
V
DD
) 12 Ω typ VS = 3 V, 6 V, 9 V; IS = −10 mA
or V
INH
INL
5 pF typ
Rev. PrD | Page 5 of 16
Page 6
ADG1204 Preliminary Technical Data
Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.001 µA typ Digital inputs = 0 V or VDD
5.0 µA max
IDD 150 µA typ Digital inputs = 5 V
300 µA max
1
Y Version temperature range is −40°C to +125°C.
2
Guaranteed by design, not subject to production test.
Rev. PrD | Page 6 of 16
Page 7
Preliminary Technical Data ADG1204
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to V
SS
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs
Digital Inputs
Peak Current, S or D
Continuous Current, S or D 30 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Automotive (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
14-Lead TSSOP, θJA Thermal
Impedance
12-Lead LFCSP, θJA Thermal
Impedance
Lead Temperature, Soldering
Vapor Phase (60 s) 215°C
Infrared (15 s) 220°C
1
38 V
VSS − 0.3 V to VDD + 0.3 V
GND − 0.3 V to V
30 mA, whichever occurs first
100 mA (pulsed at 1 ms, 10%
duty cycle max)
150.4°C/W
30.4°C/W
+ 0.3 V or
DD
1
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
TRUTH TABLE
Table 5.
EN A1 A0 S1 S2 S3 S4
0 X X Off Off Off Off
1 0 0 On Off Off Off
1 0 1 Off On Off Off
1 1 0 Off Off On Off
1 1 1 Off Off Off On
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrD | Page 7 of 16
Page 8
ADG1204 Preliminary Technical Data
V
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
0
N
A
A
1V
2S1
3S2
E
1
2
1
1
PIN 1
INDICATOR
ADG1204
TOP VIEW
(Not to Scale)
4
5
D
C
N
0
1
9 GND
8V
DD
7S3
6
4
S
04779-0-003
1
A0
2
EN
3
SS
4
S1
5
S2
6
D
7
NC
NC = NO CONNECT
ADG1204
TOP VIEW
14
A1
13
GND
12
V
DD
11
S3
S4
10
9
NC
8
NC
04779-0-002
Figure 2. TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
TSSOP LFCSP
Mnemonic Function
1 11 A0 Logic Control Input.
2 12 EN
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
3 1 V
SS
Most Negative Power Supply Potential.
4 2 S1 Source Terminal. Can be an input or an output.
5 3 S2 Source Terminal. Can be an input or an output.
6 4 D Drain Terminal. Can be an input or an output.
7–9 5 NC No Connection.
10 6 S4 Source Terminal. Can be an input or an output.
11 7 S3 Source Terminal. Can be an input or an output.
12 8 V
DD
Most Positive Power Supply Potential.
13 9 GND Ground (0 V) Reference.
14 10 A1 Logic Control Input.
SS
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
Rev. PrD | Page 8 of 16
Page 9
Preliminary Technical Data ADG1204
TERMINOLOGY
IDD
The positive supply current.
I
SS
The negative supply current.
(VS)
V
D
The analog voltage on Terminals D and S.
R
ON
The ohmic resistance between D and S.
FLAT(ON)
R
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
(Off)
I
S
The source leakage current with the switch off.
(Off)
I
D
The drain leakage current with the switch off.
, IS (On)
I
D
The channel leakage current with the switch on.
V
INL
The maximum input voltage for Logic 0.
V
INH
The minimum input voltage for Logic 1.
(I
INL
INH
)
I
The input current of the digital input.
(Off)
C
S
The off switch source capacitance, which is measured with
reference to ground.
(Off)
C
D
The off switch drain capacitance, which is measured with
reference to ground.
, CS (On)
C
D
The on switch capacitance, which is measured with reference to
ground.
C
IN
The digital input capacitance.
(EN)
t
ON
The delay between applying the digital control input and the
output switching on. See Figure 24, Test Circuit 4.
(EN)
t
OFF
The delay between applying the digital control input and the
output switching off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
t
TRANS
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.
Rev. PrD | Page 9 of 16
Page 10
ADG1204 Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. On Resistance as a Function of V
Figure 5. On Resistance as a Function of V
(VS) for Single Supply
D
(VS) for Dual Supply
D
Figure 7. On Resistance as a Function of V
(VS) for Different Temperatures,
D
Single Supply
Figure 8. On Resistance as a Function of V
(VS) for Different Temperatures,
D
Dual Supply
Figure 6. On Resistance as a Function of V
Single Supply
(VS) for Different Temperatures,
D
Rev. PrD | Page 10 of 16
Figure 9. Leakage Currents as a Function of V
D
(VS)
Page 11
Preliminary Technical Data ADG1204
Figure 10. Leakage Currents as a Function of V
Figure 11. Leakage Currents as a Function of V
D
D
(VS)
(VS)
Figure 13. Leakage Currents as a Function of Temperature
Figure 14. Supply Currents vs. Input Switching Frequency
Figure 12. Leakage Currents as a Function of Temperature
Rev. PrD | Page 11 of 16
Figure 15. Charge Injection vs. Source Voltage
Page 12
ADG1204 Preliminary Technical Data
Figure 16. t
Figure 17. Off Isolation vs. Frequency
Times vs. Temperature
ON/tOFF
Figure 19. On Response vs. Frequency
Figure 20. THD + N vs. Frequency
Figure 18. Cross talk vs. Frequency
Rev. PrD | Page 12 of 16
Page 13
Preliminary Technical Data ADG1204
V
V
V
V
TEST CIRCUITS
V
90%
ID (ON)
A
V
D
04779-0-023
04779-0-022
SD
V
S
Figure 21. Test Circuit 1—On Resistance
S
+2.4V
I
0.1µF
IS (OFF) ID (OFF)
SD
A A
DS
04779-0-020
S
V
D
04779-0-021
Figure 22. Test Circuit 2—Off Leakage
SD
NC
NC = No Connect
Figure 23. Test Circuit 3—On Leakage
V
V
SS
DD
0.1µF
A1
A0
EN
0.1µF
V
V
SS
DD
GND
S1
S2
S3
S4
D
R
50Ω
V
S1
V
S4
C
L
35pF
ADDRESS
DRIVE (V
V
OUT
L
3V
)
)
IN
0V
V
OUT
50% 50%
90%
t
TRANSITION
t
TRANSITION
Figure 24. Test Circuit 4—Address to Output Switching Times
V
V
SS
DD
0.1µF
V
V
SS
DD
GND
S1
S2
S3
S4
D
R
50Ω
A1
S
+2.4V
50Ω
A0
EN
V
S1
V
OUT
C
L
L
35pF
ADDRESS
DRIVE (V
3V
)
IN
0V
V
OUT
80%
t
BBM
80%
04779-0-024
Figure 25. Test Circuit 5—Break-before-Make Time
V
V
SS
DD
0.1µF
V
OUT
ENABLE
DRIVE (V
OUTPUT
V
V
SS
DD
GND
S1
S2
S3
S4
D
R
50Ω
V
S
C
L
L
35pF
Figure 26. Test Circuit 6—Enable to Output Switching Delay
3V
)
IN
0V
V
0
0V
50% 50%
0.9V
0
(EN)
t
ON
t
OFF
0.9V
(EN)
0
04779-0-025
Delay.
0.1µF
A1
A0
EN
S
50Ω
Rev. PrD | Page 13 of 16
Page 14
ADG1204 Preliminary Technical Data
V
V
SS
DD
V
V
SS
DD
R
S
V
S
SD
DECODER
C
1nF
V
OUT
L
GND
A2A1
EN
V
OUT
V
IN
SW OFF
Q
INJ
= CL×∆V
OUT
∆V
OUT
SW OFF
SW ON
SW ON
SW OFF
V
IN
SW OFF
04779-0-026
Figure 27. Test Circuit 7— Charge Injection
0.1µF
V
V
DD
V
SS
0.1µF
V
DD
SS
S
50Ω
D
GND
NETWORK
ANALYZER
50Ω
V
OUT
R
L
50Ω
V
S
NETWORK
ANALYZER
V
OUT
R
L
50Ω
V
S
V
0.1µF
S1
S2
V
DD
SS
0.1µF
V
V
DD
SS
D
R
50Ω
GND
0.1µF
Figure 28. Test Circuit 8—Off Isolation
V
V
DD
V
SS
0.1µF
V
DD
SS
S
D
GND
INSERTION LOSS = 20 LOG
Figure 29. Test Circuit 9—Bandwidth
OFF ISOLATION = 20 LOG
NETWORK
ANALYZER
50Ω
V
V
OUT
R
L
50Ω
V
WITH SWITCH
OUT
WITHOUT SWITCH
V
OUT
V
OUT
V
04779-0-027
S
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
Figure 30. Test Circuit 10—Channel-to-Channel Crosstalk
V
V
DD
0.1µF
V
S
IN
SS
0.1µF
V
DD
SS
S
D
V
IN
GND
04779-0-028
Figure 31. Test Circuit 11—THD + Noise
R
L
600Ω
V
OUT
V
S
AUDIO PRECISION
R
S
V
S
V p-p
V
OUT
04779-0-029
04779-0-030
Rev. PrD | Page 14 of 16
Page 15
Preliminary Technical Data ADG1204
R
OUTLINE DIMENSIONS
5.10
5.00
4.90
PIN 1
INDICATO
1.00
0.85
0.80
SEATING
PLANE
1.05
1.00
0.80
4.50
4.40
4.30
PIN 1
14
0.65
BSC
0.15
0.05
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
0.30
0.19
8
6.40
BSC
71
1.20
MAX
SEATING
PLANE
0.20
0.09
COPLANARITY
0.10
8°
0°
Figure 32. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimension shown in millimeters
12 MAX
3.00
BSC SQ
TOP
VIEW
0.30
0.23
0.18
0.80 MAX
0.65 TYP
*
2.75
BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
0.05 MAX
0.02 NOM
0.20 REF
COMPLIANT TOJEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
0.45
0.60 MAX
10
9
8
7
6
0.50
BSC
COPLANARITY
0.08
11
5
Figure 33. 12-Lead Lead Frame Chip Scale Package [VQ_LFCSP]
3 mm × 3 mm Body, Very Thin Quad
(CP-12-1)
Dimensions shown in inches and (millimeters)
0.75
0.60
0.45
0.75
0.55
0.35
12
1
2
3
4
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
0.25 MIN
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG1204YRU −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-14
ADG1204YCP −40°C to +125°C Lead Frame Chip Scale Package (LFCSP) CP-12-1
Rev. PrD | Page 15 of 16
Page 16
ADG1204 Preliminary Technical Data
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04779–0–11/04(PrD)
Rev. PrD | Page 16 of 16
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