Datasheet ADF4158 Datasheet (ANALOG DEVICES)

Page 1
Direct Modulation/Waveform Generating,
6.1 GHz Fractional-N Frequency Synthesizer
ADF4158
LOCK
DETECT
N-COUNTER
CP
SW1
REFERENCE
DATA
LE
TX
DATA
CE
32-BIT
DATA
REGISTER
CLK
REF
IN
AV
DD
AGND
V
DD
V
DD
DGND
R
DIV
N
DIV
DGND CPGND
DV
DD
V
P
R
SET
RFINA RF
IN
B
OUTPUT
MUX
+
HIGH-Z
PHASE
FREQUENCY
DETECTOR
ADF4158
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MODULUS
2
25
FRACTION
REG
INTEGER
REG
CSR
×2
DOUBLER
5-BIT
R-COUNTER
÷2
DIVIDER
CHARGE
PUMP
MUXOUT
08728-001
FL
O
SWITCH
SW2
Data Sheet

FEATURES

RF bandwidth to 6.1 GHz 25-bit fixed modulus allows subhertz frequency resolution Frequency and phase modulation capability Sawtooth and triangular waveforms in the frequency domain Parabolic ramp Ramp superimposed with FSK Ramp with 2 different sweep rates Ramp delay Ramp frequency readback Ramp interruption
2.7 V to 3.3 V power supply Separate V Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Cycle slip reduction for faster lock times Switched bandwidth fast-lock mode Qualified for automotive applications

APPLICATIONS

FMCW radar Communications test equipment
allows extended tuning voltage
P

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The ADF4158 is a 6.1 GHz, fractional-N frequency synthesizer with modulation and waveform generation capability. It contains a 25-bit fixed modulus, allowing subhertz resolution at 6.1 GHz. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (Σ-Δ) based fractional interpolator to allow programmable fractional-N division. The INT and FRAC registers define an overall N-divider as N = INT + (FRAC/2
The ADF4158 can be used to implement frequency shift keying (FSK) and phase shift keying (PSK) modulation. There are also a number of frequency sweep modes available, which generate various waveforms in the frequency domain, for example, sawtooth and triangular waveforms. The ADF4158 features cycle slip reduction circuitry, which leads to faster lock times, without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
25
).
Figure 1.
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog De vices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700
www.analog.com
Page 2
ADF4158 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Pin Function Descriptions ...................... 8
Typ i c al Performance Characteristics ............................................. 9
Circuit Description ......................................................................... 11
Reference Input Section ............................................................. 11
RF Input Stage ............................................................................. 11
RF INT Divider ........................................................................... 11
25-Bit Fixed Modulus ................................................................ 11
INT, FRAC, and R Relationship ............................................... 11
R-Counter .................................................................................... 11
Phase Frequency Detector (PFD) and Charge Pump ............ 12
MUXOUT and LOCK Detect ................................................... 12
Input Shift Registers ................................................................... 12
Program Modes .......................................................................... 12
Register Maps .................................................................................. 13
FRAC/INT Register (R0) Map .................................................. 15
LSB FRAC Register (R1) Map ................................................... 16
R-Divider Register (R2) Map .................................................... 17
Function Register (R3) Map ...................................................... 19
Test Register (R4) Map .............................................................. 21
Deviation Register (R5) Map .................................................... 22
Step Register (R6) Map .............................................................. 23
Delay Register (R7) Map ........................................................... 24
Applications Information .............................................................. 25
Initialization Sequence............................................................... 25
RF Synthesizer: A Worked Example ........................................ 25
Reference Doubler and Reference Divider ............................. 25
Cycle Slip Reduction for Faster Lock Times ........................... 25
Modulation .................................................................................. 26
Waveform Generation................................................................ 26
Other Waveforms ....................................................................... 28
Fast-Lock Timer and Register Sequences ............................... 32
Fast Lock: An Example .............................................................. 32
Fast Lock: Loop Filter Topology ............................................... 32
Spur Mechanisms ....................................................................... 33
Low Frequency Applications..................................................... 33
Filter Design—ADIsimPLL ....................................................... 33
PCB Design Guidelines for the Chip Scale Package .............. 33
Application of ADF4158 in FMCW Radar ................................. 34
Outline Dimensions ....................................................................... 35
Ordering Guide ........................................................................... 35
Automotive Products ................................................................. 35
Rev. D | Page 2 of 36
Page 3
Data Sheet ADF4158

REVISION HISTORY

6/12—Rev. C to Rev. D
Changes to Table 3 and Figure 3 ..................................................... 6
Added Figure 4; Renumbered Sequentially ................................... 6
Added Negative Bleed Current Section ........................................ 21
Changes to Figure 27 ...................................................................... 21
12/11—Rev. B to Rev. C
Changes to Features Section ............................................................ 1
Changes to Figure 6 Caption to Figure 9 Caption ........................ 9
Changes to Figure 11 ...................................................................... 10
Changes to Figure 19 ...................................................................... 12
Changes to Figure 20 ...................................................................... 13
Changed 12-Bit MOD Divider Section to 12-Bit CLK
Divider
1
Section .............................................................................................. 17
Changes to 12-Bit CLK
Divider Section ..................................... 17
1
Changes to Figure 24 ...................................................................... 18
Changes to Delay Clock Select Section and Figure 29 ............... 24
Changes to Timeout Interval Section ........................................... 27
Changes to FMCW Radar Ramp Settings Worked Example
Section .............................................................................................. 28
Changes to Delayed Start, Example Section and Delay Between
Ramps, Example Section ................................................................ 29
Changes to Fast-Lock Timer and Register Sequences Section
and Fast Lock: An Example Section ............................................. 32
Changes to Ordering Guide ........................................................... 35
Added Automotive Products Section ........................................... 35
9/11—Rev. A to Rev. B
Changes to Noise Characteristics Parameter ................................. 3
7/11—Rev. 0 to Rev. A
Changes to Figure 21 ...................................................................... 13
Changes to Figure 25 ...................................................................... 19
Changes to 12-Bit Clock Divider Value Section ......................... 20
Changes to Figure 28 ...................................................................... 22
Changes to FMCW Radar Ramp Settings Worked Example
Section .............................................................................................. 26
Added Ramp Programming Sequence Section, and added
Other Waveforms Heading ............................................................ 27
Changes to Figure 36 ...................................................................... 28
Added Ramp Complete Signal to Muxout Section and changes
to Figure 40 ...................................................................................... 29
Added Figure 42; Renumbered Sequentially ............................... 30
Changes to Figure 45 ...................................................................... 31
Changes to Figure 46 ...................................................................... 33
4/10—Revision 0: Initial Version
Rev. D | Page 3 of 36
Page 4
ADF4158 Data Sheet

SPECIFICATIONS

AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = T otherwise noted.
MIN
to T
, dBm referred to 50 Ω, unless
MAX
Table 1.
1
C Version
Parameter Min Typ Max Unit Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFIN) 0.5 6.1 GHz −10 dBm min to 0 dBm max; for lower frequencies, ensure
slew rate (SR) > 400 V/µs
−15 dBm min to 0 dBm max for 2 GHz to 4 GHz RF input frequency
REFERENCE CHARACTERISTICS
REFIN Input Frequency 10 260 MHz For f < 10 MHz, use a dc-coupled CMOS-compatible
square wave, slew rate > 25 V/µs 16 MHz If an internal reference doubler is enabled REFIN Input Sensitivity 0.4 AVDD V p-p Biased at AVDD/22 REFIN Input Capacitance 10 pF REFIN Input Current ±100 µA
PHASE DETECTOR
Phase Detector Frequency3 32 MHz
CHARGE PUMP
ICP Sink/Source Programmable
Hig h Value 5 mA With R
= 5.1 kΩ
SET
Low Value 312.5 µA Absolute Accuracy 2.5 % With R R
Range 2.7 10
SET
= 5.1 kΩ
SET
ICP Three-State Leakage Current 1 nA Sink and source current Matching 2 % 0.5 V < VCP < VP – 0.5 V ICP vs. VCP 2 % 0.5 V < VCP < VP – 0.5 V ICP vs. Temperature 2 % VCP = VP/2
LOGIC INPUTS
V
, Input High Voltage 1.4 V
INH
V
, Input Low Voltage 0.6 V
INL
I
, Input Current ±1 µA
INH/IINL
CIN, Input Capacitance 10 pF
LOGIC OUTPUTS
VOH, Output High Voltage 1.4 V Open-drain output chosen; 1 kΩ pull-up to 1.8 V VOH, Output High Voltage VDD − 0.4 V CMOS output chosen IOH, Output High Current 100 µA VOL, Output Low Voltage 0.4 V IOL = 500 µA
POWER SUPPLIES
AVDD 2.7 3.3 V DVDD AVDD VP AVDD 5.5 V IDD 23 32 mA
Rev. D | Page 4 of 36
Page 5
Data Sheet ADF4158
t5
25
ns min
CLK low duration
CLK
DATA
LE
LE
DB31 (MSB) DB30
DB1
(CONTROL BIT C2)
DB2
(CONTROL BIT C3)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
08728-026
1
C Version
Parameter Min Typ Max Unit Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PN
)4
SYNTH
Normalized 1/f Noise (PN
)5 −110 dBc/Hz 100 kHz offset; normalized to 1 GHz
1_f
−216 dBc/Hz PLL loop bandwidth = 500 kHz; measured at 100 kHz offset
Phase Noise Performance6 At VCO output
5805 MHz Output7 −93 dBc/Hz At 5 kHz offset, 32 MHz PFD frequency
1
Operating temperature for C version: −40°C to +125°C.
2
AC coupling ensures AVDD/2 bias.
3
Guaranteed by design. Sample tested to ensure compliance.
4
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(f
5
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset f is given by PN = PN
6
The phase noise is measured with the EVAL-ADF4158EB1Z and the Agilent E5052A phase noise system.
7
f
= 128 MHz; f
REFIN
). PN
= PN
PFD
SYNTH
= 32 MHz; offset frequency = 5 kHz; RF
PFD
− 10 log(f
TOT
) − 20 log(N).
PFD
+ 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
1_f
= 5805 MHz; INT = 181; FRAC = 13631488; loop bandwidth = 100 kHz.
OUT

TIMING SPECIFICATIONS

AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = SDGND = 0 V; TA = T unless otherwise noted.
Table 2. Write Timing
Parameter Limit at T
MIN
to T
(C Version) Unit Test Conditions/Comments
MAX
t1 20 ns min LE setup time t2 10 ns min DATA t o CLK setup time t3 10 ns min DATA t o CLK hold time t4 25 ns min CLK high duration
MIN
to T
, dBm referred to 50 Ω,
MAX
t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width

Write Timing Diagram

Figure 2. Write Timing Diagram
Rev. D | Page 5 of 36
Page 6
ADF4158 Data Sheet
CLK
MUXOUT
LE
DB36 DB35 DB1DB2 DB0
08728-226
t
1
t
2
TX
DATA
NOTES
1. LE SHO ULD BE KEPT HIGH DURING READBACK.
t
4
t
5
t
3
100µA
1.5V
I
OL
I
OH
TO OUTPUT
PIN
C
L
10pF
100µA
08728-004
Table 3. Read Timing
Parameter Limit at T
t1 20 ns min TX t2 20 ns min CLK setup time to DATA (on MUXOUT) t3 25 ns min CLK high duration t4 25 ns min CLK low duration t5 10 ns min CKJ to LE setup time

Read Timing Diagram

MIN
to T
(C Version ) Unit Test Conditions/Comments
MAX
setup time
DATA
Figure 3. Read Timing Diagram
Figure 4. Load Circuit for MUXOUT Timing, C = 10 pF
Rev. D | Page 6 of 36
Page 7
Data Sheet ADF4158
VDD to GND
−0.3 V to +4 V
Analog I/O Voltage to GND
−0.3 V to VDD + 0.3 V

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, GND = AGND = DGND = SDGND = 0 V, V
= AVDD = DVDD = SDVDD, unless otherwise noted.
DD
Table 4.
Parameter Rating
VDD to VDD −0.3 V to +0.3 V VP to GND −0.3 V to +5.8 V VP to VDD −0.3 V to +5.8 V Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN, RFIN to GND −0.3 V to VDD + 0.3 V Operating Temperature Range
Industrial (C Version) −40°C to +125°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C LFCSP θJA Thermal Impedance
(Paddle Soldered) Reflow Soldering
Peak Temperature 260°C Time at Peak Temperature 40 sec
30.4°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. D | Page 7 of 36
Page 8
ADF4158 Data Sheet
PIN 1 INDICAT
OR
1CPGND
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTE D TO GND.
2AGND 3AGND 4RF
IN
B
5RF
IN
A
6AV
DD
15 DATA
16 LE
17 MUXOUT
18 SDV
DD
14
CLK
13 CE
7AV
DD
8AV
DD
9REF
IN
11SDGND
12TX
DATA
10DGND
21
SW2
22
V
P
23
R
SET
24
CP
20
SW1
19
DV
DD
ADF4158
TOP VIEW
(Not to S cale)
08728-003
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
22
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to
SET
CPmax
R
I
5.25
=

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
2, 3 AGND Analog Ground. This is the ground return path of the prescaler. 4 RFINB Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass capacitor,
5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO. 6, 7, 8 AVDD Positive Power Supply for the RF Section. Place decoupling capacitors to the digital ground plane as close as possible
9 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ.
10 DGND Digital Ground. 11 SDGND Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator. 12 TX
DATA
13 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. 14 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift
15 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a high
16 LE Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the eight latches,
17 MUXOUT Multiplexer Output. This pin allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be
18 SDVDD Power Supply Pin for the Digital Σ-Δ Modulator. This pin should be the same voltage as AVDD. Place decoupling
19 DVDD Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close as
20 , 21 SW1, SW2 Switches for Fast Lock.
typically 100 pF.
to this pin. AV
must have the same voltage as DVDD.
DD
It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Tx Data Pin. Provide data to be transmitted in FSK or PSK mode on this pin.
register on the CLK rising edge. This input is a high impedance CMOS input.
impedance CMOS input.
with the latch being selected using the control bits.
accessed externally.
capacitors to the ground plane as close as possible to this pin.
possible to this pin. DV
must have the same voltage as AVDD.
DD
5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
23 R
24 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the external VCO. 25 EPAD Exposed Paddle. The LFCSP has an exposed paddle that must be connected to GND.
Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship
SET
between I
where:
I
CPmax
R
SET
CP
= 5 mA.
= 5.1 kΩ.
and R
is
SET
Rev. D | Page 8 of 36
Page 9
Data Sheet ADF4158
–160
–140
–120
–100
–80
–60
–40
1k 10k 100k 1M 10M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
08728-035
5.78
5.79
5.80
5.81
5.82
5.83
5.84
5.85
5.86
–0.025 –0.015 –0.005 0.005 0.015 0.025
FREQUENCY (GHz)
TIME (s)
08728-036
5.75
5.77
5.79
5.81
5.83
5.85
5.87
–0.010 –0.005 0 0.005 0.010
FREQUENCY (GHz)
TIME (s)
08728-037
5.76
5.77
5.78
5.79
5.80
5.81
5.82
5.83
5.84
5.85
5.86
5.87
FREQUENCY (GHz)
TIME (s)
–0.010 –0.005 0 0.005 0.010
08728-039
5.76
5.77
5.78
5.79
5.80
5.81
5.82
5.83
5.84
5.85
5.86
0 0.005 0.010
TIME (s)
FREQUENCY (GHz)
0.015 0.020
NO DELAY DELAY
08728-040
5.790
5.792
5.794
5.796
5.798
5.800
5.802
5.804
5.806
5.808
5.810
–0.010 0.010–0.005 0.0050
FREQUENCY (GHz)
TIME (s)
08728-041

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 6. Phase Noise at 5805 MHz, PFD = 32 MHz, Loop Bandwidth = 100 kHz
Figure 7. Triangular Waveform, PFD = 32 MHz, INT = 181, FRAC = 0,
DEV Offset = 4, DEV Word = 20972, Step Word = 200, CLK DIV = 10,
CLK
Divider = 125
1
Figure 9. Delay Between Ramps for Sawtooth Waveform, PFD = 32 MHz,
INT = 181, FRAC = 0, DEV Offset = 4, DEV Word = 20972, Step Word = 200,
CLK DIV = 10, CLK
Divider = 125, DEL Start Word = 1025
1
Figure 10. Delayed Start of Triangular Burst, PFD = 32 MHz, INT = 181,
FRAC = 0, DEV Offset = 4, DEV Word = 20972, Step Word = 200,
CLK DIV = 10, CLK
Divider = 125, DEL Start Word = 1000
1
Figure 8. Sawtooth Waveform, PFD = 32 MHz, INT = 181, FRAC = 0, DEV Offset = 4, DEV Word = 20972, Step Word = 200, CLK DIV = 10,
CLK
Divider = 125
1
Figure 11. Dual Ramp Rate Waveform, PFD = 32 MHz, INT = 181, FRAC = 0,
Ramp 1: DEV Offset = 3, DEV Word = 16777, Step Word = 100,
Ramp 2: DEV Offset = 3, DEV Word = 20792, Step Word = 80
Rev. D | Page 9 of 36
Page 10
ADF4158 Data Sheet
5.7995
5.7996
5.7997
5.7998
5.7999
5.8000
5.8001
5.8002
5.8003
5.8004
FREQUENCY (GHz)
–0.010 0.010–0.005 0.0050
TIME (s)
08728-042
5.79975
5.79980
5.79985
5.79990
5.79995
5.80005
5.80000
5.80010
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
FREQUENCY (GHz)
TIME (ms)
08728-044
–30
–25
–20
–15
–10
–5
0
0.185 1.185 2.185 3.185 4.185 5.185 6.185 7.185
POWER (dBm)
FREQUENCY (GHz)
08728-128
–8
–6
–4
–2
I
CP
(mA)
0
2
4
6
0 1 2 3
V
CP
(V)
4 5 6
08728-046
Figure 12. FSK Superimposed on Rising Edge of Triangular Waveform;
Ramp Settings: PFD = 32 MHz, INT = 181, FRAC = 0, DEV Offset = 4, DEV
Word = 20972, Step Word = 200, CLK DIV = 10, CLK
Divider = 125;
1
FSK Settings: DEV Offset = 3, DEV Word = 4194
Figure 13. FSK; Settings: Frequency Deviation = 100 kHz, Data Rate = 3 kHz
Figure 14. RF
Sensitivity-Average Over Temperature and V
IN
DD
Figure 15. Charge Pump Output Characteristics
Rev. D | Page 10 of 36
Page 11
Data Sheet ADF4158
BUFFER
TO R-COUNTER
REF
IN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
08728-027
BIAS
GENERATOR
1.6V
AGND
AV
DD
2kΩ 2kΩ
RF
IN
B
RF
IN
A
08728-015
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N-DIVI DE R
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N-COUNTER
08728-016

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
Figure 16. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 17. It is followed by a 2-stage limiting amplifier to generate the current-mode logic (CML) clock levels needed for the prescaler.

25-BIT FIXED MODULUS

The ADF4158 has a 25-bit fixed modulus. This allows output frequencies to be spaced with a resolution of
f
= f
RES
where f
/225 (1)
PFD
is the frequency of the phase frequency detector
PFD
(PFD). For example, with a PFD frequency of 10 MHz, frequency steps of 0.298 Hz are possible.

INT, FRAC, AND R RELATIONSHIP

The INT and FRAC values, in conjunction with the R-counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD). The RF VCO frequency (RF
RF
OUT
where:
RF
is the output frequency of external voltage controlled
OUT
oscillator (VCO).
INT is the preset divide ratio of binary 12-bit counter (23 to 4095). FRAC is the numerator of the fractional division (0 to 2
f
= REFIN × [(1 + D)/(R × (1 + T))] (3)
PFD
where: REF
is the reference input frequency.
IN
D is the REF T is the REF R is the preset divide ratio of the binary, 5-bit, programmable
reference counter (1 to 32).
) equation is
OUT
= f
× (INT + (FRAC/225)) (2)
PFD
doubler bit (0 or 1).
IN
divide-by-2 bit (0 or 1).
IN
25
− 1).
Figure 17. RF Input Stage

RF INT DIVIDER

The RF INT CMOS counter allows a division ratio in the PLL feedback counter. Division ratios from 23 to 4095 are allowed.
Figure 18. RF N-Divider

R-COUNTER

The 5-bit R-counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 32 are allowed.
Rev. D | Page 11 of 36
Page 12
ADF4158 Data Sheet
U3
CLR2
Q2D2
U2
DOWN
UP
HIGH
HIGH
CP
–IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1D1
U1
08728-017
MUXOUT
DV
DD
THREE-STATE OUTPUT
N-DIVIDER OUTPUT
DV
DD
DGND
DGND
R-DIVIDER OUTPUT
DIGITAL LOCK DETECT
SERIAL DAT A OUTPUT
CLK DIVIDE R OUTPUT
R-DIVIDER/2 N-DIVIDER/2
FAST-LOCK SWITCH
READBACK TO MUXOUT
CONTROLMUX
08728-009

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP

The PFD takes inputs from the R-counter and N-counter and produces an output proportional to the phase and frequency difference between them. Figure 19 shows a simplified schematic of the PFD. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level.
Figure 19. PFD Simplified Schematic

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4158 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by the M4, M3, M2, and M1 bits (see Figure 23). Figure 20 shows the MUXOUT section in block diagram form.

INPUT SHIFT REGISTERS

The ADF4158 digital section includes a 5-bit RF R-counter, a 12-bit RF N-counter, and a 25-bit FRAC counter. Data is clocked into the 32-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of eight latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C3, C2, and C1) in the shift register. These are the three LSBs—DB2, DB1, and DB0—as shown in Figure 2. The truth table for these bits is shown in Tabl e 6. Figure 21 and Figure 22 show a summary of how the latches are programmed.

PROGRAM MODES

Table 6 and Figure 23 through Figure 30 show how to set up the program modes in the ADF4158.
Several settings in the ADF4158 are double buffered. These include the LSB fractional value, R-counter value, reference doubler, current setting, and RDIV2. This means that two events must occur before the part uses a new value for any of the double­buffered settings. First, the new value is latched into the device by writing to the appropriate register. Second, a new write must be performed on Register R0.
For example, updating the fractional value can involve a write to the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should be written to first, followed by the write to R0. The frequency change begins after the write to R0. Double buffering ensures that the bits written to in R1 do not take effect until after the write to R0.
Figure 20. MUXOUT Schematic
Table 6. C3, C2, and C1 Truth Table
Control Bits
C3 C2 C1 Register
0 0 0 R0 0 0 1 R1 0 1 0 R2 0 1 1 R3 1 0 0 R4 1 0 1 R5 1 1 0 R6 1 1 1 R7
Rev. D | Page 12 of 36
Page 13
Data Sheet ADF4158
DB31
CONTROL
BITS
12-BIT MSB FRACTIONAL V ALUE
(FRAC)
12-BIT INTEGER VALUE ( INT)
MUXOUT
CONTROL
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M4R1 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)
RAMP ON
FRAC/INT REGISTER (R0)
DB31
CONTROL
BITS
RESERVED
13-BIT LS B FRACTIONAL V ALUE
(FRAC) (DBB)
RESERVED
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(1)
LSB FRAC REGISTER (R1)
DB31
RESERVED
NOTES
1. DBB = DOUBLE - BUFFERED BIT ( S ) .
POWER-DOWN
PD
POLARITY
LDP
COUNTER
RESET
CP
THREE-STATE
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NS1 U12 0 0 RM2 RM1 PE1 FE1 U11 U10 U9 U8 U7 C3(0) C2(1) C1(1)
FUNCTION REGISTER (R3)
DB31
12-BIT CLK1 DIVIDER5-BIT R-CO UNTER
RESERVED
CSR EN
RESERVED
PRESCALER
RDIV2 DBB
CP
CURRENT
SETTING
REFERENCE
DOUBLER DBB
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 CR1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(0)
R-DIVIDER REGISTER (R2)
DBB DBB
SD
RESET
N SEL
RESERVED
RAMP MODE
PSK ENABLE
FSK ENABLE
08728-010

REGISTER MAPS

Figure 21. Register Summary 1
Rev. D | Page 13 of 36
Page 14
ADF4158 Data Sheet
DB31
CONTROL
BITS
20-BIT ST E P WORD
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 SSE1 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 C3(0) C2(0) C1(0)
STEP REGISTER (R6)
DB31
CONTROL
BITS
12-BIT DELAY START DIVIDER
RESERVED
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 RDF1 RD1 DC1 DSE1 DS12 DS11 DS10 DS9 DS8 DS7 DS6 DS5 DS4 DS3 DS2 DS1 C3(0) C2(0) C1(1)
DELAY REGISTER (R7)
RESERVED
STEP SEL
DEL START E N
DEL CLK SEL
RAMP DEL
RAMP DEL FL
RESERVED
RESERVED
DB31
12-BIT CLOCK DIVIDER VALUE
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LS1 0 0 0 0 0 0 0 0 R2 R1 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)
TEST REGISTER (R4)
CLK
DIV
MODE
READ-
BACK
TO
MUXOUT
0
0
0 0
DB31
16-BIT DEVIATION W ORD
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 TR1 PR1 I2 I1 FRE1 R2E1 DS1 DO4 DO3 DO2 DO1 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 C3(1) C2(0) C1(0)
DEVIATION REGISTER (R5)
D4
D3
D2 D1
4-BIT DEV OFFSET
WORD
DEV SEL
RAMP 2 EN
FSK RAMP EN
INTERRUPT
PAR RAMP
TX RAMP CLK
RESERVED
LE SEL
08728-110
Figure 22. Register Summary 2
Rev. D | Page 14 of 36
Page 15
Data Sheet ADF4158
DB31
CONTROL
BITS
12-BIT MSB FRACTIONAL V ALUE
(FRAC)

12-BIT INTEGER VALUE ( INT)

MUXOUT
CONTROL
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R1 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)

RAMP ON

M4 M3 M2 M1 OUTPUT
0 0 0 0 THREE-STATE OUTPUT 0 0 0 1 DV
DD
0 0 1 0 DGND 0 0 1 1 R-DIVIDER OUTPUT 0 1 0 0 N-DIVIDER OUTPUT 0 1 0 1 RESERVED 0 1 1 0 DIGITAL LOCK DETECT 0 1 1 1 SERIAL DATA OUTPUT 1 0 0 0 RESERVED 1 0 0 1 RESERVED 1 0 1 0 CLK DIVIDER OUT P UT 1 0 1 1 RESERVED 1 1 0 0 FAST-LOCK SWITCH 1 1 0 1 R-DIVIDER/2 1 1 1 0 N-DIVIDER/2 1 1 1 1 READBACK TO MUXOUT
R1 RAMP ON
0 RAMP DISABLED
RAMP ENABLED
1
F25 F24 .......... F15 F14
MSB FRACTI ONAL VALUE
(FRAC)*
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 .......... 1 1 4095
N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1
INTEGERVALUE
(INT) 0 0 0 0 0 0 0 1 0 1 1 1 23 0 0 0 0 0 0 0 1 1 0 0 0 24 0 0 0 0 0 0 0 1 1 0 0 1 25 0 0 0 0 0 0 0 1 1 0 1 0 26
. . . . . . . . . . . . .
. . . . . . . . . . . . .
. . . . . . . . . . . . .
1 1 1 1 1 1 1 1 1 1 0 1 4093 1 1 1 1 1 1 1 1 1 1 1 0 4094 1 1 1 1 1 1 1 1 1 1 1 1 4095
*THE FRAC VAL UE IS MADE UP OF THE 12-BIT M S B S TORED IN REGIST E R R0, AND THE 13-BIT LSB REGIS TER STORED IN REGIST E R R1. FRAC VALUE = 13- BIT LSB + 12- BIT MSB × 2
13
.
08728-011

FRAC/INT REGISTER (R0) MAP

With Register R0 DB[2:0] set to [0, 0, 0], the on-chip FRAC/ INT register is programmed as shown in Figure 23.
Ramp On
Setting DB31 to 1 enables the ramp, setting DB31 to 0 disables the ramp.

MUXOUT Control

The on-chip multiplexer is controlled by DB[30:27] on the
ADF4158. See Figure 23 for the truth table.
12-Bit Integer Value (INT)
These 12 bits control what is loaded as the INT value. This is used to determine the overall feedback division factor. It is used in Equation 2. See the INT, F RA C , and R Relationship section for more information.

12-Bit MSB Fractional Value (FRAC)

These 12 bits, along with Bits DB[27:15] in the LSB FRAC register
(Register R1), control what is loaded as the FRAC value into the
fractional interpolator. This is part of what determines the overall
feedback division factor. It is also used in Equation 2. These
12 bits are the most significant bits (MSB) of the 25-bit FRAC
value, and Bits DB[27:15] in the LSB FRAC register (Register R1)
are the least significant bits (LSB). See the RF Synthesizer: A
Worked Example section for more information.
Figure 23. FRAC/INT Register (R0) Map
Rev. D | Page 15 of 36
Page 16
ADF4158 Data Sheet
DB31
CONTROL
BITS
RESERVED
13-BIT LS B FRACTIONAL V ALUE
(FRAC) (DBB)
RESERVED
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4
F3 F2 F1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(1)
F13 F12 .......... F2 F1
LSB FRACTIONAL VALUE (FRAC)*
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 8188
1 1 .......... 0 1 8189
1 1 .......... 1 0 8190
1 1 .......... 1 1 8191
*THE FRAC VAL UE IS MADE UP OF THE 12-BIT M S B S TORED IN
REGIST E R R0, AND THE 13-BIT LSB REGIS TER STORED IN REGIST E R R1. FRAC VALUE = 13- BIT LSB + 12- BIT MSB × 213.
08728-012
NOTES
1. DBB = DOUBLE- BUFFERED BITS.

LSB FRAC REGISTER (R1) MAP

With Register R1 DB[2:0] set to [0, 0, 1], the on-chip LSB FRAC register is programmed as shown in Figure 24.

13-Bit LSB FRAC Value

These 13 bits, along with Bits DB[14:3] in the FRAC/INT register (Register R0), control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is also used in Equation 2. These 13 bits
are the least significant bits (LSB) of the 25-bit FRAC value, and Bits DB[14:3] in the INT/FRAC register are the most significant bits (MSB). See the RF Synthesizer: A Worked Example section for more information.

Reserved Bits

All reserved bits should be set to 0 for normal operation.
Figure 24. LSB FRAC Register (R1) Map
Rev. D | Page 16 of 36
Page 17
Data Sheet ADF4158

R-DIVIDER REGISTER (R2) MAP

With Register R2 DB[2:0] set to [0, 1, 0], the on-chip R-divider register is programmed as shown in Figure 25.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

CSR Enable

Setting this bit to 1 enables cycle slip reduction. This is a method for improving lock times. Note that the signal at the PFD must have a 50% duty cycle in order for cycle slip reduction to work. In addition, the charge pump current setting must be set to a minimum. See the Cycle Slip Reduction for Faster Lock Times section for more information.
Also note that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (DB6 in Register R3). It cannot be used if the phase detector polarity is set to negative.

Charge Pump Current Setting

DB[27:24] set the charge pump current setting (see Figure 25). Set these bits to the charge pump current that the loop filter is designed with.

Prescaler (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the RF
Operating at CML levels, it takes the clock from the RF input stage and divides it down for the counters. It is based on a synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 3 GHz. Therefore, when operating the
ADF4158 above 3 GHz, the prescaler must be set to 8/9. The
prescaler limits the INT value.
to the PFD input.
IN
With P = 4/5, N
With P = 8/9, N
MIN
MIN
= 23.
= 75.

RDIV2

Setting DB21 to 1 inserts a divide-by-2 toggle flip-flop between the R-counter and the PFD. This can be used to provide a 50% duty cycle signal at the PFD for use with cycle slip reduction.

Reference Doubler

Setting DB20 to 0 feeds the REFIN signal directly to the 5-bit RF R-counter, disabling the doubler. Setting this bit to 1 multiplies the REF into the 5-bit R-counter. When the doubler is disabled, the REF
frequency by a factor of 2 before feeding the signal
IN
IN
falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising edge and falling edge of REF
The maximum allowed REF
become active edges at the PFD input.
IN
frequency when the doubler is
IN
enabled is 30 MHz.

5-Bit R-Counter

The 5-bit R-counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 32 are allowed.

12-Bit CLK1 Divider

Bits DB[14:3] are used to program the CLK1 divider, which determines the duration of the time step in ramp mode.
Rev. D | Page 17 of 36
Page 18
ADF4158 Data Sheet
DB31
12-BIT CLK1 DIVIDER5-BIT R COUNTER
RESERVED
CSR EN
RESERVED
PRESCALER
CP
CURRENT
SETTING
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 CR1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(0)
CR1
CYCLE SLIP
REDUCTION 0 DISABLED 1 ENABLED
U1
REFERENCE
DOUBLER 0 DISABLED 1 ENABLED
R5 R4 R3 R2 R1 R-COUNTER DIVIDE RATIO
0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 0 0 1 0 0 4
. . . . .
. . . . .
. . . . .
1 1 1 0 1 29 1 1 1 1 . 30 1 1 1 1 1 31 0 0 0 0 0 32
U2 R DIVIDER
0 DISABLED 1 ENABLED
P1 PRESCALER
0 4/5 1 8/9
ICP(mA)
CPI4 CPI3 CPI2 CPI1 5.1k
0 0 0 0 0.31 0 0 0 1 0.63 0 0 1 0 0.94 0 0 1 1 1.25 0 1 0 0 1.57 0 1 0 1 1.88 0 1 1 0 2.19 0 1 1 1 2.5 1 0 0 0 2.81 1 0 0 1 3.13 1 0 1 0 3.44 1 0 1 1 3.75 1 1 0 0 4.06 1 1 0 1 4.38 1 1 1 0 4.69 1 1 1 1 5
DBB DBB
RDIV2 DBB
REFERENCE
DOUBLER DBB
08728-013
D12 D11 .......... D2 D1
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 .......... 1 1 4095
NOTES
1. DBB = DOUBLE - BUFFERED BIT S .
12-BIT CL K1 DIVIDER VALUE
Figure 25. R-Divider Register (R2) Map
Rev. D | Page 18 of 36
Page 19
Data Sheet ADF4158

FUNCTION REGISTER (R3) MAP

With Register R3 DB[2:0] set to [0, 1, 1], the on-chip function register is programmed as shown in Figure 26.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

N SEL

This setting is used to circumvent the issue of pipeline delay between an update of the integer and fractional values in the N-counter. Typically, the INT value is loaded first, followed by the FRAC value. This can cause the N-counter value to be at an incorrect value for a brief period of time equal to the pipeline delay (about four PFD cycles). This has no effect if the INT value has not been updated. However, if the INT value has been changed, this can cause the PLL to overshoot in frequency while it tries to lock to the temporarily incorrect N value. After the correct fractional value is loaded, the PLL quickly locks to the correct frequency. Introducing an additional delay to the loading of the INT value using the N SEL bit causes the INT and FRAC values to be loaded at the same time, preventing frequency overshoot. The delay is turned on by setting Bit DB15 to 1.

SD Reset

For most applications, DB14 should be set to 0. When DB14 is set to 0, the Σ-Δ modulator is reset on each write to Register R0. If it is not required that the Σ-Δ modulator be reset on each Register R0 write, set this bit to 1.

Ramp Mode

DB[11:10] determine the type of generated waveform.

PSK Enable

When DB9 is set to 1, PSK modulation is enabled. When set to 0, PSK modulation is disabled.

FSK Enable

When DB8 is set to 1, FSK modulation is enabled. When set to 0, FSK modulation is disabled.

Lock Detect Precision (LDP)

When DB7 is programmed to 0, 24 consecutive PFD cycles of 15 ns must occur before digital lock detect is set. When this bit is programmed to 1, 40 consecutive reference cycles of 15 ns must occur before digital lock detect is set.

Phase Detector (PD) Polarity

DB6 sets the phase detector polarity. When the VCO characteristics are positive, set this bit to 1. When the VCO characteristics are negative, set this bit to 0.

Power-Down

DB5 provides the programmable power-down mode. Setting this bit to 1 performs a power-down. Setting this bit to 0 returns the synthesizer to normal operation. While in software power­down mode, the part retains all information in its registers. Only when supplies are removed are the register contents lost.
When a power-down is activated, the following events occur:
1. All active dc current paths are removed.
2. The synthesizer counters are forced to their load state
conditions.
3. The charge pump is forced into three-state mode.
4. The digital lock-detect circuitry is reset.
5. The RF
6. The input register remains active and capable of loading
and latching data.
input is debiased.
IN

Charge Pump Three-State

DB4 puts the charge pump into three-state mode when programmed to 1. It should be set to 0 for normal operation.

Counter Reset

DB3 is the RF counter reset bit. When this bit is set to 1, the RF synthesizer counters are held in reset. For normal operation, set this bit to 0.
Rev. D | Page 19 of 36
Page 20
ADF4158 Data Sheet
DB31
RESERVED
POWER-DOWN
PD
POLARITY
LDP
COUNTER
RESET
CP
THREE-STATE
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NS1 U12 0 0 RM2 RM1 PE1 FE1 U11 U10 U9 U8 U7 C3(0) C2(1) C1(1)
U9 POWER-DOWN
0 DISABLED 1 ENABLED
U11 LDP
0 24 PFD CYCLES 1 40 PFD CYCLES
NS1 N SEL
0 N W ORD LOAD ON SDCLK 1 N W ORD LOAD DELAY E D 4 CY CLES
RM2 RAMP MODE
0 CONTINUOUS SAWTOOTH
1
RM1
0
1 SINGL E RAM P BURS T
1 0 SINGLE SAWTOOTH
0 1 CONT INUOUS TRI ANGULAR
U7
COUNTER RESET
0 DISABLED 1 ENABLED
U10 PD POLARITY
0 NEGATIVE 1 POSITIVE
U8CPTHREE-STATE
0 DISABLED 1 ENABLED
SD
RESET
N SEL
RESERVED
FE1 FSK ENABLE
0 DISABLED 1 ENABLED
U12 Σ-Δ RESET
0 ENABLED 1 DISABLED
PE1 PSK ENABLE
0 DISABLED 1 ENABLED
08728-014
RAMP MODE
PSK EN
FSK EN
Figure 26. Function Register (R3) Map
Rev. D | Page 20 of 36
Page 21
Data Sheet ADF4158
DB33
12-BIT CLOCK DIVIDER VALUERESERVED

LE SEL

RESERVED
CONTROL
BITS
DB32 DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LS1 0 0 0 0 0 0 0 0 R2 R1 CK2 CK1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)
LS1 LE SEL
0 LE FROM PIN 1 LE SYNC WITH REF
D12 D11 .......... D2 D1 CLOCK DI V IDER VALUE
0 0 0 0
. .
. 1 1 1 1
0 0 0 0
. .
. 1 1 1 1
0 0 1 1 . . . 0 0 1 1
0 1 0 1
. .
. 0 1 0 1
0 1 2 3 . . . 4092 4093 4094 4095
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
CK2 CK1 CLOCK DIVIDER M ODE
0 0
CLOCK DIVIDER OFF
0 1
FAST-LOCK DIVIDER
1 0
RESERVED
1 1 RAMP DIVI DE R
0 0
0
0
CLK
DIV
MODE
READ-
BACK
TO
MUXOUT
08728-115
DB24 DB23
NB2 NB1
NEG BLEED CURR-
ENT
R2 READBACK TO M UX OUT
0 DISABLED 1
ENABLED
R1
0 0
NB2 NEGATI V E BLEED CURRENT
0 OFF 1
ON
NB1
0 1

TEST REGISTER (R4) MAP

With Register R4 DB[2:0] set to [1, 0, 0], the on-chip test register (R4) is programmed as shown in Figure 27.
LE SEL
In some applications, it is necessary to synchronize LE with the reference signal. To do this, DB31 should be set to 1. Synchronization is done internally on the part.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

Negative Bleed Current

Setting Bits DB[24:23] to 11 turns on the constant negative bleed current. This ensures that the charge pump operates out of the dead zone. Thus, the phase noise is not degraded and the level of spurs is lower. Enabling constant negative bleed current is particularly important on channels close to multiple PFD frequencies. Refer to the AN-1154 Application Note for more information on the negative bleed current.

Readback to MUXOUT

DB[22:21] enable or disable the readback to MUXOUT function. This function allows reading back the synthesizer’s frequency at the moment of interrupt.

CLK DIV Mode

Depending on the settings of DB[20:19], the 12-bit clock divider may be a counter for the switched R fast-lock ramp (CLK2), or it may be turned off.

12-Bit Clock Divider Value

DB[18:7] program the clock divider, which is used as a timer for ramp − CLK
, while operating in ramp mode. See the Wav e for m
2
Deviations and Timing section for more details. The timer also determines how long the loop remains in wideband mode while the switched R fast-lock technique is used. See Fast-Lock Timer and Register Sequences for more details.
Figure 27. Test Register (R4) Map
Rev. D | Page 21 of 36
Page 22
ADF4158 Data Sheet
DB31

16-BIT DEVIATION WORD

CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 TR1 PR1 I2 I1 FRE1 R2E1 DS1 DO4 DO3 DO2 DO1 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 C3(1) C2(0) C1(1)
07828-116
I2
I1

INTERRUPT

0 0 INTERRUPT OFF
1 1
LOAD CHANNEL CONTINUE SW E E P
D16 D14 .......... D2 D1 16-BIT DE V IATION WORD
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
1 1 .......... 1 1
–1
1 1 .......... 1 0 –2
1 1 .......... 0 1 –3
1 0 .......... 0 0 –32,768
D4 D3
D1
D2
4-BIT DEV OFFSET
WORD
DEV SEL
RAMP 2 EN
FSK RAMP EN
INTERRUPT

PAR RAMP

PR1 PAR RAMP
0 DISABLED 1 ENABLED
0
1
0
1
NOT USED LOAD CHANNEL S TOP SWEE P
FRE1 FSK RAMP ENABLE
0 DISABLED 1 ENABLED
R2E1 RAMP 2 ENABLE
0 DISABLED 1 ENABLED
DO4 DO3 DO2 DO1 4- BIT DEV OFFSET WO RD
0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3
. . . .
. . . .
. . . .
1 1 0 1 13 1 1 1 0 14 1 1 1 1 15
DS1 DEV SEL
0 DEV WORD 1 1 DEV WORD 2
RESERVED

TX RAMP CLK

TR1 TX RAMP CLK
0 CLK DIV 1 TX DATA
0 1 .......... 1 1 32,767
. . .......... . . .
. . .......... . . .

DEVIATION REGISTER (R5) MAP

With Register R5 DB[2:0] set to [1, 0, 1], the on-chip deviation register is programmed as shown in Figure 28.

Reserved Bits

All reserved bits should be set to 0 for normal operation.
Tx Ramp CLK
Setting DB29 to 0 uses the clock divider clock for clocking the ramp. Setting DB29 to 1 uses the Tx data clock for clocking the ramp.
PAR Ramp
Setting DB28 to 1 enables the parabolic ramp. Setting DB28 to 0 disables the parabolic ramp.
Interrupt
DB[27:26] determine which type of interrupt is used. This feature is used for reading back the INT and FARC value of a ramp at a given moment in time (rising edge on the TX the interrupt). From these bits, frequency can be obtained. After readback, the sweep might continue or stop at the readback frequency.
pin triggers
DATA

FSK Ramp Enable

Setting DB25 to 1 enables the FSK ramp. Setting DB25 to 0 disables the FSK ramp.

Ramp 2 Enable

Setting DB24 to 1 enables the second ramp. Setting DB24 to 0 disables the second ramp.

Deviation Select

Setting DB23 to 0 chooses the first deviation word. Setting DB23 to 1, chooses the second deviation word.

4-Bit Deviation Offset Word

DB[22:19] determine the deviation offset. The deviation offset affects the deviation resolution.
16-Bit Deviation Word
DB[18:3] determine the signed deviation word. The deviation word defines the deviation step.
Figure 28. Deviation Register (R5) Map
Rev. D | Page 22 of 36
Page 23
Data Sheet ADF4158
DB31
20-BIT ST E P WORDRESERVED
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 SSE1 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 C3(1) C2(1) C1(0)
08728-117
S20 S19 .......... S2 S1 CLOCK DIVIDER VALUE
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 1048572
1 1 .......... 0 1 1048573
1 1 .......... 1 0 1048574
1 1 .......... 1 1 1048575
S4 S3
S1
S2

STEP SEL

SSE1 STEP SEL
0 STEP WORD 1 1 STEP WORD 2

STEP REGISTER (R6) MAP

With Register R6 DB[2:0] set to [1, 1, 0], the on-chip step register is programmed as shown in Figure 29.

Reserved Bits

All reserved bits should be set to 0 for normal operation.
Step SEL
Setting DB23 to 0 chooses Step Word 1. Setting DB23 to 1 chooses Step Word 2.

20-Bit Step Word

DB[22:3] determine the step word. Step word is a number of steps in the ramp.
Figure 29. Step Register (R6) Map
Rev. D | Page 23 of 36
Page 24
ADF4158 Data Sheet
DB31
12-BIT DELAY START WORDRESERVED
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 RDF1 RD1 DC1 DSE1 DS12 DS11 DS10 DS9 DS8 DS7 DS6 DS5 C3(1) C2(1) C1(1)
08728-118
DS12 DS11
..........
DS2 DS1 12-BIT DELAY START WORD
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 .......... 1 1 4095
DS4 DS3
DS1
DS2
DSE1 DEL START ENABLE
0 DISABLE 1 ENABLE
DEL START EN
DEL CLK SEL
RAMP DEL
RAMP DEL FL
RDF1 RAMP DELAY FAST LO CK
0 DISABLED 1 ENABLED
DC1 DEL CLK SEL
0 PFD CLK 1 PFD × CLK
1
RD1 RAMP DELAY
0 DISABLED 1 ENABLED

DELAY REGISTER (R7) MAP

With Register R7 DB[2:0] set to [1, 1, 1], the on-chip delay register is programmed as shown in Figure 30.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

Ramp Delay Fast Lock

Setting DB18 to 1 enables the ramp delay fast-lock function. Setting DB18 to 0 disables this function.

Ramp Delay

Setting DB17 to 1 enables the ramp delay function. Setting DB17 to 0 disables this function.

Delay Clock Select

Setting DB16 to 0 selects the PFD clock as the delay clock. Setting DB16 to 1 selects PFD × CLK
(CLK1 set by DB[14:3] in
1
Register R2) as delay clock.

Delayed Start Enable

Setting DB15 to 1 enables delayed start. Setting DB15 to 0 disables delayed start.

12-Bit Delayed Start Word

DB[14:3] determine the delay start word. The delay start word affects the duration of the ramp start delay.
Figure 30. Delay Register (R7) Map
Rev. D | Page 24 of 36
Page 25
Data Sheet ADF4158

APPLICATIONS INFORMATION

INITIALIZATION SEQUENCE

After powering up the part, administer the following programming sequence:
1. Delay register (R7)
2. Step register (R6)—load the step register (R6) twice, first
with STEP SEL = 0 and then with STEP SEL = 1
3. Deviation register (R5)—load the deviation register (R5)
twice, first with DEV SEL = 0 and then with DEV SEL = 1
4. Te s t register (R4)
5. Function register (R3)
6. R-divider register (R2)
7. LSB FRAC register (R1)
8. FRAC/INT register (R0)

RF SYNTHESIZER: A WORKED EXAMPLE

The following equation governs how the synthesizer should be programmed:
RF
= [N + (FRAC/225)] × [f
OUT
where:
RF
is the RF frequency output.
OUT
N is the integer division factor. FRAC is the fractionality.
f
= REFIN × [(1 + D)/(R × (1 + T))] (5)
PFD
where:
REF
is the reference frequency input.
IN
D is the RF REF
doubler bit.
IN
R is the RF reference division factor. T is the reference divide-by-2 bit (0 or 1).
For example, in a system where a 5.8002 GHz RF frequency output (RF input (REF
f
RES
f
RES
) is required and a 10 MHz reference frequency
OUT
) is available, the frequency resolution is
IN
= REFIN/225 (6)
= 10 MHz/225
= 0.298 Hz
From Equation 5,
f
= [10 MHz × (1 + 0)/1] = 10 MHz
PFD
5.8002 GHz = 10 MHz × (N + FRAC/2
Calculating N and FRAC values,
N = int(RF FRAC = F F
= int(((RF
MSB
F
= int(((((RF
LSB
MSB
OUT/fPFD
× 213 + F
OUT/fPFD
OUT/fPFD
) = 580
LSB
) − N) × 212) = 81
) − N) × 212) − F
where:
F
is the 12-bit MSB FRAC value in Register R0.
MSB
F
is the 13-bit LSB FRAC value in Register R1.
LSB
int() makes an integer of the argument in parentheses.
] (4)
PFD
25
)
) × 213) = 7537
MSB

REFERENCE DOUBLER AND REFERENCE DIVIDER

The reference doubler on chip allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually improves noise performance by 3 dB.
It is important to note that the PFD cannot be operated above 32 MHz due to a limitation in the speed of the Σ-Δ circuit of the N-divider.

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

In fast-locking applications, a wide loop filter bandwidth is required for fast frequency acquisition, resulting in increased integrated phase noise and reduced spur attenuation. Using cycle slip reduction, the loop bandwidth can be kept narrow to reduce integrated phase noise and attenuate spurs while still realizing fast lock times.

Cycle Slips

Cycle slips occur in integer-N/fractional-N synthesizers when the loop bandwidth is narrow compared with the PFD frequency. The phase error at the PFD inputs accumulates too fast for the PLL to correct, and the charge pump temporarily pumps in the wrong direction, slowing down the lock time dramatically. The ADF4158 contains a cycle slip reduction circuit to extend the linear range of the PFD, allowing faster lock times without loop filter changes.
When the ADF4158 detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. This outputs a constant current to the loop filter or removes a constant current from the loop filter (depending on whether the VCO tuning voltage needs to increase or decrease to acquire the new frequency). The effect is that the linear range of the PFD is increased. Stability is main­tained because the current is constant and is not a pulsed current.
If the phase error increases again to a point where another cycle slip is likely, the ADF4158 turns on another charge pump cell. This continues until the ADF4158 detects that the VCO frequency has gone past the desired frequency. It then begins to turn off the extra charge pump cells one by one until they are all turned off and the frequency is settled.
Up to seven extra charge pump cells can be turned on. In most applications, it is enough to eliminate cycle slips altogether, giving much faster lock times.
Rev. D | Page 25 of 36
Page 26
ADF4158 Data Sheet
OFFSETDEV
PFD
DEV
f
f
DEV
_
25
22×
=
52.971,20
2
2
MHz25
kHz250
4
25
=
×
=DEV
FREQUENCY
TIME
08728-022
FREQUENCY
TIME
08728-021
FREQUENCY
TIME
08728-019
FREQUENCY
TIME
08728-020
Setting Bit DB28 in the R-divider register (Register R2) to 1 enables cycle slip reduction. Note that a 45% to 55% duty cycle is needed on the signal at the PFD in order for CSR to operate correctly. The reference divide-by-2 flip-flop can help to provide a 50% duty cycle at the PFD. For example, if a 100 MHz reference frequency is available and the user wants to run the PFD at 10 MHz, setting the R-divide factor to 10 results in a 10 MHz PFD signal that is not 50% duty cycle. By setting the R-divide factor to 5 and enabling the reference divide-by-2 bit, a 50% duty cycle 10 MHz signal can be achieved.
Note that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (DB6 in Register R3). It cannot be used if the phase detector polarity is negative.

MODULATION

The ADF4158 can operate in frequency shift keying (FSK) or phase shift keying (PSK) mode.

Frequency Shift Keying (FSK)

FSK is implemented by setting the ADF4158 N-divider up for the center frequency and then toggling the TX deviation from the center frequency is set by
f
= (f
DEV
/225) × (DEV × 2
PFD
DEV_OFFSET
) (7)
where:
DEV is a 16-bit word. DEV_OFFSET is a 4-bit word. f
is the PFD frequency.
PFD
The ADF4158 implements this by incrementing or decrementing the set N-divide value by DEV × 2
DEV_OFFSET

Phase Shift Keying (PSK)

When the ADF4158 is set up in PSK mode, it is possible to toggle the output phase of the ADF4158 between 0° and 180°. The TX
pin controls the phase.
DATA

FSK Settings Worked Example

For example, take an FSK system operating at 5.8 GHz, with a 25 MHz PFD, 250 kHz deviation and DEV_OFFSET = 4. Rearrange Equation 4 as follows
.
DATA
pin. The

WAVEFORM GENERATION

The ADF4158 is capable of generating four types of waveforms in the frequency domain: single ramp burst, single sawtooth burst, sawtooth ramp, and triangular ramp. Figure 31 through Figure 34 show the types of waveforms available.
Figure 31. Single Ramp Burst
Figure 32. Single Sawtooth Burst
Figure 33. Sawtooth Ramp
(8)
The DEV value is rounded to 20,972. Toggling the TX causes the frequency to hop between ±250 kHz frequencies from the programmed center frequency.
pin
DATA
Rev. D | Page 26 of 36
Figure 34. Triangular Ramp
Page 27
Data Sheet ADF4158
TIMER
f
DEV
FREQUENCY
TIME
08728-023

Waveform Deviations and Timing

Figure 35 shows a version of a burst or ramp. The key parameters that define a burst or ramp are
Frequency deviation
Timeout interval
Number of steps
Figure 35. Waveform Timing
Frequency Deviation
The frequency deviation for each frequency hop is set by
f
DEV
= (f
/225) × (DEV × 2
PFD
DEV_OFFSET
) (9)
where:
DEV is a 16-bit word. DEV_OFFSET is a 4-bit word.
Timeout Interval
The time between each frequency hop is set by
Timer = CLK
× CLK2 × (1/f
1
) (10)
PFD
where:
CLK
and CLK2 are 12-bit clock values (12-bit CLK1 divider in
1
R2, 12-bit clock divider in R4—CLK DIV set as RAMP DIV).
f
is the PFD frequency.
PFD
Number of Steps
A 20-bit step value defines the number of frequency hops that take place. The INT value cannot be incremented by more than
8
2
= 256 from its starting value.

Single Ramp Burst

The most basic waveform is the single ramp burst. All other waveforms are slight variations on this.
In the single ramp burst, the ADF4158 is locked to the fre­quency defined in the FRAC/INT register. When the ramp mode is enabled, the ADF4158 increments the N-divide value by DEV × 2
DEV_OFSET
, causing a frequency shift, f
, on each
DEV
timer interval. This happens until the set number of steps has taken place. The ADF4158 then retains the final N-divide value.

Single Sawtooth Burst

In the single sawtooth burst, the N-divide value is reset to its initial value on the next timeout interval after the number of steps has taken place. The ADF4158 retains this N-divide value.

Sawtooth Ramp

The sawtooth ramp is a repeated version of the single sawtooth burst. The waveform repeats until the ramp is disabled.

Triangular Ramp

The triangular ramp is similar to the single ramp burst. However, when the steps have been completed, the ADF4158 begins to decrement the N-divide value by DEV × 2
DEV_OFFSET
on each timeout interval. When the number of steps has again been completed, it reverts to incrementing the N-divide value. Repeating this creates a triangular waveform. The waveform repeats until the ramp is disabled.

FMCW Radar Ramp Settings Worked Example

Take as an example, an FMCW radar system requiring the RF LO to sawtooth ramp over a 50 MHz range every 2 ms. The PFD frequency is 25 MHz, and the RF output range is 5800 MHz to 5850 MHz.
The frequency deviation for each hop in the ramp is set to ~250 kHz.
The frequency resolution of ADF4158 is calculated as follows:
f
= f
RES
/225 (11)
PFD
Numerically:
f
= 25 MHz/225 = 0.745 Hz
RES
The DEV_OFFSET is calculated after rearranging Equation 9:
DEV_OFFSET = log2(f
Expressed in log
(x), Equation 10 can be transformed into the
10
DEV
/(f
× DEV
RES
)) (12)
MAX
following equation:
DEV_OFFSET = log
10(fDEV
/(f
× DEV
RES
))/log10(2) (13)
MAX
where:
DEV
= 215 − Maximum of the Deviation Word.
MAX
f
= frequency deviation.
DEV
DEV_OFFSET = a 4-bit word.
Using Equation 13, DEV_OFFSET is calculated as follows
DEV_OFFSET = log
(250 kHz/(0.745 Hz × 215))/log10(2) = 3.356
10
After rounding, DEV_OFFSET = 4.
From DEV_OFFSET, the resolution of frequency deviation can be calculated as follows
f
= f
DEV_RES
f
= 0.745 Hz × 24 = 11.92 Hz
DEV_RES
RES
× 2
DEV_OFFSET
(14)
Rev. D | Page 27 of 36
Page 28
ADF4158 Data Sheet
52.971,20
2
2
MHz25
zkH250
4
25
=
×
=DEV
FREQUENCY
TIME
SWEEP RATE SET BY OTHER REGISTER
SWEEP RATE SET BY ONE REGISTER
08728-024
To calculate the DEV word, use Equation 12.
DEV = f
DEV
/(f
RES
× 2
DEV_OFFSET
) (15)
Rounding this to 20,972 and recalculating using Equation 9 to get the actual deviation frequency, f
f
= (25 MHz/225) × (20,972 × 24) = 250.006 kHz
DEV
The number of f
steps required to cover the 50 MHz range is
DEV
, thus produces the following:
DEV
50 MHz/250.006 kHz = 200. To cover the 50 MHz range in 2 ms, the ADF4158 must hop every 2 ms/200 = 10 µs.
Rearrange Equation 10 to set the timer value (and fix CLK
CLK
= Timer × f
1
/CLK2 = 10 µs × 25 MHz /1 = 250
PFD
to 1):
2
To s ummarize the settings: DEV = 20,972, number of steps = 200, CLK
= 250 (12-bit CLK1 divider in R2), CLK2 = 1 (R4-CLK DIV
1
set as RAMP DIV). Using these settings, program the ADF4158 to a center frequency of 5800 MHz, and enable the sawtooth ramp to produce the required waveform. If a triangular ramp was used with the same settings, the ADF4158 would sweep from 5800 MHz to 5850 MHz and back down again. The entire sweep would take 4 ms.

Activating the Ramp

After setting all of the previous parameters, the ramp must be activated. It is achieved by choosing the desired type of ramp (DB[11:10] in Register R3) and starting the ramp (DB31 = 1 in Register R0).

Ramp Programming Sequence

Set parameters as described in the FMCW Radar Ramp Settings Worked Example section and activate the ramp as described in the Activating the Ramp section in the following register write order.
1. Delay register (R7)
2. Step register (R6)
3. Deviation register (R5)
4. Test register (R4)
5. Function register (R3)
6. R-divider register (R2)
7. LSB FRAC register (R1)
8. FRAC/INT register (R0)

OTHER WAVEFORMS

Two Ramp Rates

This feature allows for two ramps with different step and deviation settings. It also allows the ramp rate to be reprogrammed while another ramp is running.
Example
If, for example
PLL is locked to 5790 MHz and f
= 25MHz.
PFD
Ramp 1 jumps 100 steps, each of which lasts 10 µs and has
a frequency deviation of 100 kHz.
Ramp 2 jumps 80 steps, each of which lasts 10 µs and has a
frequency deviation of 125 kHz.
Then,
1. DB24 in Register R5 should be set to 1, which activates
Ramp 2 rates mode.
2. Program Ramp 1 and Ramp 2 as follows to get two ramp rates:
Ramp 1: Register R5 DB[18:3] = 16,777, DB[22:19] = 3 with DB23 = 0; Register R6 DB[22:3] = 100, DB23 = 0. Ramp 2: Register R5 DB[18:3] = 20,972, DB[22:19] = 3 with DB23 = 1; Register R6 DB[22:3] = 80, DB23 = 1.
The resulting ramp with two various rates is shown in Figure 36. Eventually, the ramp must be activated as described in Activating the Ramp section.
Figure 36. Dual Sweep Rate

Ramp Mode with FSK Signal on Ramp

In traditional approaches a FMCW radars used either linear frequency modulation (LFM) or FSK modulation. These modulations used separately introduce ambiguity between measured distance and velocity, especially in multitarget situations. To overcome this issue and enable unambiguous (range − velocity) multitarget detection, use a ramp with FSK on it.
Example
If, for example
PLL is locked to 5790 MHz. f
= 25MHz
PFD
There are 100 steps each of which lasts 10 µs and has a
deviation of 100 kHz.
The FSK signal is 25 kHz.
Then,
1. Program the ramp as described in the FMCW Radar Ramp
Settings Worked Example section. While doing that DB23 in Register R5 and DB23 in Register R6 should be set to 0.
2. Set the bits in Register R5 as follows to program FSK on ramp
to 25 kHz: DB[18:3] = 4194 (deviation word), DB[22:19] = 3 (deviation offset), DB23 = 1 (deviation select for FSK on ramp), and DB25 = 1 (ramp with FSK enabled).
Rev. D | Page 28 of 36
Page 29
Data Sheet ADF4158
08728-025
FREQUENCY
0 RAMP END
FREQUENCY SWEEP
FSK SHIFT
TIME
LFM STEP = FREQUENCY SWEEP/NUMBER OF STEPS
FREQUENCY
TIME
RAMP WIT H

DELAYED ST ART

RAMP WIT HOUT
DELAYED ST ART
08728-126
FREQUENCY
TIME
DELAY
08728-028
An example of ramp with FSK on the top of it is shown in Figure 37. Eventually, the ramp must be activated as described in Activating the Ramp section.

Delay Between Ramps

This feature adds a delay between bursts in ramp. Figure 39 shows a delay between ramps in sawtooth mode.
Figure 37. Combined FSK and LFM Waveform (N Corresponds to the
Number of LFM Steps)
Delayed Start
A delayed start can be used with two different parts to control the start time. The idea of delayed start is shown in Figure 38.
Figure 38. Delayed Start of Sawtooth Ramp
Example
For example, to program a delayed start with two different parts to control the start time,
1. Set DB15 in Register R7 to 1 to enable the delayed start of
ramp option.
2. Set Bit DB16 in Register R7 to 0 and the 12-bit delay start
word (DB[14:3] in Register R7) to 125 to delay the ramp on the first part is delayed by 5 µs, f
= 25 MHz. The delay is
PFD
calculated as follows:
Delay = t
× Delay Start Word
PFD
= 40 ns × 125 = 5 µs
3. Set Bit DB16 in Register R7 to 1 and the 12-bit delay start
word (DB[14:3] in Register R7) to 125 to delay the ramp on the second part is delayed by 125 µs. Use the following formula for calculating the delay:
Figure 39. Delay Between Ramps for Sawtooth Mode
Example
For example, to add a delay between bursts in a ramp,
1. Set DB17 in Register R7 to 1 to enable delay between
ramps option.
2. Set Bit DB16 in Register R7 to 0 and the 12-bit delay start
word (DB[14:3] in Register R7) to 125 to delay the ramp by 5 µs, f
Delay = t
= 25 MHz. The delay is calculated as follows:
PFD
× Delay Start Word
PFD
= 40 ns × 125 = 5 µs
If a longer delay is needed, for example, 125 µs, Bit DB16 in Register R7 should be set to 1 and the 12-bit delay start word (DB[14:3] in Register R7) should be set to 125. The delay is calculated as follows
Delay = t = 40 ns × 25 × 125 = 125 µs
× CLK1 × Delay Start Word
PFD
There is also a possibility to activate fast-lock operation for the first period of delay. This is done by setting Bit DB18 in Register R7 to 1. This feature is useful for sawtooth ramps to mitigate the frequency overshoot on the transition from one sawtooth to the next. Eventually, the ramp must be activated as described in Activating the Ramp section.

Nonlinear Ramp Mode

The ADF4158 is capable of generating a parabolic ramp. The output frequency is generated according to the following equation:
f
(n + 1) = f
OUT
(n) + n × f
OUT
(16)
DEV
where:
f
is output frequency.
OUT
f
is frequency deviation.
DEV
n is step number.
Delay = t
× CLK1 × Delay Start Word
PFD
= 40 ns × 25 × 125 = 125 µs
Eventually, the ramp must be activated as described in Activating the Ramp section.
Rev. D | Page 29 of 36
Page 30
ADF4158 Data Sheet
FREQUENCY
TIME
08728-029
08728-100
TIME
TIME
VOLTAGE FREQUENCY
FREQUENCYLOGIC LEVEL
TIME
TIME
TIME OF INTERRUPT
FREQUENCY AT WHICH INT E RRUP T TOOK P LACE
INTERRUPT S IGNAL
LOGIC HIGH
LOGIC LOW
1. SWEEP CONTINUES MODE
2. SWEEP STOPS MODE
1 2
08728-030
Figure 40. Parabolic Ramp
The following example explains how to set up and use this function.
Example
f
= 5790 MHz
OUT
f
= 100 kHz
DEV
Number of steps = 50
Duration of a single step = 10 µs
Ramp mode must be either triangular (Register R3, DB[11:10] = 01) or single ramp burst (Register R3, DB[11:10] = 11).
In the first case, the generated frequency range is calculated as follows:
Δf = f
× (Number of Steps + 2) × (Number of Steps + 1)/2
DEV
= 132.6 MHz
In the second case, the generated frequency range is calculated as follows:
Δf = f
× (Number of Steps + 1) × Number of Steps/2
DEV
= 127.5 MHz
The timer is set in the same way as for its linear ramps described in the Waveform Generation section.
Activation of the parabolic ramp is achieved by setting Bit DB28 in Register R5 to 1.
Next the counter reset (DB3 in Register R3) should be set first to 1 and then to 0.
Eventually, the ramp must be activated as described in the Activating the Ramp section.

Ramp Complete Signal To Muxout

Ramp complete signal on Muxout is shown in Figure 41.
Figure 41. Ramp Complete Signal on Muxout
To activate this function DB[30:27] = 1111 in Register 0 and DB[25:21] = 00011 in Register 4

Interrupt Modes and Frequency Readback

Interrupt modes are triggered from the rising edge of TX
DATA
. Depending on the settings of DB[27:26] in Register R5, the modes in Table 7 are activated.
Table 7. Interrupt Modes
Mode Action
DB[27:26] = 00 Interrupt is off DB[27:26] = 01 Interrupt on TX DB[27:26] = 11 Interrupt on TX
, sweep continues
DATA
, sweep stops
DATA
When an interrupt takes place, the data consisting of the INT and FRAC values can be read back via MUXOUT. The data is made up of 37 bits, 12 of which represent the INT value and 25 the FRAC value.
The idea of frequency readback is shown in Figure 42.
Figure 42. Interrupt and Frequency Readback
Rev. D | Page 30 of 36
Page 31
Data Sheet ADF4158
08728-101
MUXOUT
CLK
LE
TX
DATA
DATA CLOCKED OUT ON POSITIVE EDGE OF CLKAND READ ON NE GATIVE EDGE OF CLK RE ADBACK WORD (37 BITS) 0 0001 1100 1111 0110 0010 0011 1010 0111 1000 (HEX 01CF623A78)
LSBMSB
12-BIT I NTERGER W ORD
0000 1110 0111
0x0E7
231
25-BIT F RAC WORD
1 0110 0010 0011 1010 0111 1000
0x1623A78
23214712
RF = F
PFD
× (231 + 23214712 ÷ 2
25
) = 5.7922963GHz
CLK
MUXOUT
LE
TX
DATA
DATA
R0 WRITE R4 WRITE R4 WRITE
FREQUENCY
READBACK
FREQUENCY
READBACK
FREQUENCY
READBACK
37 CLK
PULSES
37 CLK
PULSES
37 CLK
PULSES
32 CLK
PULSES
32 CLK
PULSES
32 CLK
PULSES
08728-144
Note that DB[22:21] in Register R4 should be set to 2 and DB[30:27] in Register R0 (MUXOUT control) should be set to 15 (1111).
The mechanism of how single bits are read back is shown in Figure 43.
For continuous frequency readback the following sequence should be used:
Register 0 write
LE high
Pulse on TX
DATA
Frequency readback (as described at the beginning of the
Interrupt Modes and Frequency Readback section and Figure 43)
Pulse on TX
DATA
Register R4 write
Frequency readback (as described at the beginning of the
Interrupt Modes and Frequency Readback section and Figure 43)
Pulse on TX
DATA
The sequence is also shown in Figure 44.
Figure 43. Reading Back Single Bits to Determine the Output Frequency at the Moment of Interrupt
Figure 44. Continuous Frequency Readback
Rev. D | Page 31 of 36
Page 32
ADF4158 Data Sheet
VCOCP
C1 C2 C3
R3 R2
R1
R1A
SW2
SW1
ADF4158
08728-032
VCOCP
C1 C2 C3
R3 R2
R1R1A
SW2
SW1
ADF4158
08728-102

FAST-LOCK TIMER AND REGISTER SEQUENCES

If the fast-lock mode is used, a timer value needs to be loaded into the PLL to determine the time spent in wide bandwidth mode.
When the DB[20:19] bits in Register 4 (R4) are set to 01 (fast­lock divider), the timer value is loaded via the 12-bit clock divider value. To use fast lock, the PLL must be written to in the following sequence:
1. Initialization sequence (see the Initialization Sequence
section). This should only be performed once after powering up the part.
2. Load Register R4 DB[20:19] = 01 and the chosen fast-lock
timer value (DB[18:7]).
3. Load Register R2 with the chosen CLK
(DB[14:3]) if longer time in wide loop bandwidth is required.
Note that the duration that the PLL remains in wide bandwidth is equal to the CLK 12-bit CLK
divider in Register R2.
1
× fast-lock timer/f
1
In addition, note that the fast-lock feature does not work in ramp mode.
divider value
1
, where CLK1 is the
PFD

FAST LOCK: LOOP FILTER TOPOLOGY

To use fast-lock mode, an extra connection from the PLL to the loop filter is needed. The damping resistor in the loop filter must be reduced to ¼ of its value while in wide bandwidth mode. This is required because the charge pump current is increased by 16 while in wide bandwidth mode, and stability must be ensured. To further enhance stability and mitigate frequency overshoot while frequency change (in wide band­width mode), Resistor R3 is connected. During fast lock, the SW1 pin is shorted to ground and SW2 is connected to CP (it is done by setting Bits DB[20:19] in Register R4 to 01—fast lock divider). The following two topologies can be used:
Divide the damping resistor (R1) into two values (R1 and
R1A) that have a ratio of 1:3 (see Figure 45).
Connect an extra resistor (R1A) directly from SW1, as shown
in Figure 46. The extra resistor must be chosen such that the parallel combination of an extra resistor and the damping resistor (R1) is reduced to ¼ of the original value of R1.
For both of the topologies, the ratio R3:R2 should equal 1:4.

FAST LOCK: AN EXAMPLE

If a PLL has a reference frequency of 13 MHz, that is, f 13 MHz, as well as CLK and a required lock time of 50 µs, the PLL is set to wide bandwidth for 40 µs.
If the time period set for the wide bandwidth is 40 µs, then
Fast-Lock Timer Value = Time in Wide Bandwidth × f
Fast-Lock Timer Value = 40 µs × 13 MHz /10 = 52.
Therefore, 52 must be loaded into the clock divider value in Register R4 in Step 2 of the sequence described in the Fast-Lock Timer and Register Sequences section.
= 10 (12-bit CLK1 divider in Register R2)
1
PFD
=
PFD
/MOD
Figure 45. Fast-Lock Loop Filter Topology—Topology 1
Figure 46. Fast-Lock Loop Filter Topology—Topology 2
Rev. D | Page 32 of 36
Page 33
Data Sheet ADF4158

SPUR MECHANISMS

The fractional interpolator in the ADF4158 is a third-order Σ-Δ modulator (SDM) with a 25-bit fixed modulus (MOD). The SDM is clocked at the PFD reference rate (f frequencies to be synthesized at a channel step resolution of f MOD. The various spur mechanisms possible with fractional-N synthesizers and how they affect the ADF4158 are discussed in this section.

Fractional Spurs

In most fractional synthesizers, fractional spurs can appear at the set channel spacing of the synthesizer. In the ADF4158, these spurs do not appear. The high value of the fixed modulus in the ADF4158 makes the SDM quantization error spectrum look like broadband noise, effectively spreading the fractional spurs into noise.

Integer Boundary Spurs

Interactions between the RF VCO frequency and the PFD frequency can lead to spurs known as integer boundary spurs. When these frequencies are not integer related (which is the purpose of the fractional-N synthesizer), spur sidebands appear on the VCO output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the PFD and the VCO frequency.
These spurs are named integer boundary spurs because they are more noticeable on channels close to integer multiples of the PFD where the difference frequency can be inside the loop bandwidth. These spurs are attenuated by the loop filter on channels far from integer multiples of the PFD.

Reference Spurs

Reference spurs are generally not a problem in fractional-N synthesizers because the reference offset is far outside the loop bandwidth. However, any reference feedthrough mechanism that bypasses the loop can cause a problem. One such mechanism is the feedthrough of low levels of on-chip reference switching noise out through the RF spur levels as high as −90 dBc. Tak e care in the PCB layout to ensure that the VCO is well separated from the input reference to avoid a possible feedthrough path on the board.
pins back to the VCO, resulting in reference
IN
) that allows PLL output
PFD
PFD
/

LOW FREQUENCY APPLICATIONS

The specification on the RF input is 0.5 GHz minimum; however, RF frequencies lower than this can be used if the minimum slew rate specification of 400 V/µs is met. An appropriate LVDS driver can be used to square up the RF signal before it is fed back to the
ADF4158 RF input. The FIN1001 from Fairchild Semiconductor
is one such LVDS driver.

FILTER DESIGN—ADIsimPLL

A filter design and analysis program is available to help the user implement PLL design. Visit www.analog.com/pll for a free download of the ADIsimPLL™ software. This software designs, simulates, and analyzes the entire PLL frequency domain and time domain response. Various passive and active filter architectures are allowed.

PCB DESIGN GUIDELINES FOR THE CHIP SCALE PACKAGE

The lands on the chip scale package (CP-24) are rectangular. The printed circuit board (PCB) pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. Center the land on the pad. This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad. The thermal pad on the PCB should be at least as large as this exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve the thermal performance of the package. If vias are used, they should be incorporated into the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ounce of copper to plug the via. Connect the PCB thermal pad to AGND.
Rev. D | Page 33 of 36
Page 34
ADF4158 Data Sheet
08728-034
LINEAR
FREQUENCY
SWEEP
NO DDS REQUI RE D
WITH ADF 4158
REFERENCE
OSCILLATOR
26MHz
VCO
ADF4158
PLL
×5
MULTIPLY
×15
×3
PA
Tx
ANTENNA
Rx
ANTENNAS
76.5GHz TO
77.0GHz
5.1GHz TO
5.1333GHz
MICRO-
CONTROLLER
16B 10B
TO
12B
BUS
CAN/FLEXRAY
RANGE
COMPENSATION
BASEBAND
MIXER
DSP
ADSP-BF531
AD9288 AD9203 AD9235
MUX
AMP
ADC
HPF

APPLICATION OF ADF4158 IN FMCW RADAR

The ADF4158 in FMCW radar is used for generating ramps (sawtooth or triangle) that are necessary for this type of radar to operate. Traditionally, the PLL was driven directly by a direct digital synthesizer (DDS) to generate the required type of waveform.
Due to the implemented waveform generating mechanism on the
ADF4158, a DDS is no longer needed, which reduces cost. In
addition, the PLL solution has advantages over another method
(the DAC driving the VCO directly) for generating FMCW ramps, which suffered from VCO tuning characteristics nonlinearities requiring compensation. The PLL method gives highly linear ramps without the need for calibration.
The application of ADF4158 in FMCW radar is shown in Figure 47.
Figure 47. FMCW Radar with ADF4158
Rev. D | Page 34 of 36
Page 35
Data Sheet ADF4158
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.18
COMPLIANTTOJEDEC STANDARDS MO-220-WGG D.
04-12-2012-A
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN 1 INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.65
2.50 SQ
2.45
1
24
7
12
13
18
19
6
FOR PROP E R CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CO NFIGURATI ON AND FUNCTIO N DE S CRIPTIONS SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM

OUTLINE DIMENSIONS

Figure 48. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-7)
Dimensions shown in millimeters

ORDERING GUIDE

1, 2
Model
Temperature Range Package Description Package Option
ADF4158CCPZ −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-7 ADF4158CCPZ-RL7 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-7 ADF4158WCCPZ −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-7 ADF4158WCCPZ-RL7 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-7 EVAL-ADF4158EB1Z Evaluation Board
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The ADF4158W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. D | Page 35 of 36
Page 36
ADF4158 Data Sheet
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
registered trademarks are the property of their respective owners. D08728-0-6/12(D)
Rev. D | Page 36 of 36
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