Datasheet ADF4154 Datasheet (Analog Devices)

Fractional-N Frequency Synthesizer

FEATURES

RF bandwidth 500 MHz to 4 GHz

2.7 V to 3.3 V power supply
Separate V
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the ADF4110/ADF4111/

ADF4112/ADF4113, ADF4106 and ADF4153
Programmable modulus on fractional-N synthesizer
Trade-off noise versus spurious performance
Fast-lock mode with built-in timer

APPLICATIONS

CATV equipment
Base stations for mobile radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment

allows extended tuning voltage

P

ADF4154

GENERAL DESCRIPTION

The ADF4154 is a fractional-N frequency synthesizer that
implements local oscillators in the up conversion and down
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD),
a precision charge pump, and a programmable reference divider.
There is a Σ-Δ based fractional interpolator to allow program­mable fractional-N division. The INT, FRAC, and MOD regis­ters define an overall N divider (N = (INT + (FRAC/MOD))).
In addition, the 4-bit reference counter (R counter) allows
selectable REF
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and a voltage controlled
oscillator (VCO).

A key feature of the ADF4154 is the fast-lock mode with a built­in timer. The user can program a predetermined count-down
time value so that the PLL will remain in wide bandwidth mode,
instead of having to control this time externally.

Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to

3.3 V, and can be powered down when not in use.

frequencies at the PFD input. A complete

IN

FUNCTIONAL BLOCK DIAGRAM

REF

IN

HIGH Z

MUXOUT

CLOCK

DATA

LE

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

×2

DOUBLER

OUTPUT

MUX

24-BIT

DATA

REGISTER

AGND

V

DD

DGND

V

DD

R

DIV

N

DIV

4-BIT

R COUNTER

LOCK

DETECT

FAST-LOCK

SWITCH

THIRD ORDER

FRACTIONAL

INTERPOLATOR

FRACTION

REG

DGND CPGND

AV

DD

Figure 1.

DV

DDVP

MODULUS

REG

SDV

DD

+

PHASE

FREQUENCY

DETECTOR

–

N COUNTER

INTEGER REG

P = 4/5 OR 8/9

B = 9 BITS; A = 3 BITS

R

SET

REFERENCE

CHARGE

PUMP

CURRENT

SETTING

RFCP3 RFCP2 RFCP1

CP

RFINA
RF

IN

B

ADF4154

04833-0-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADF4154

TABLE OF CONTENTS

Specifications..................................................................................... 3

R-Divider Register, R1 ............................................................... 15

Timing Characteristics..................................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Pin Function Descriptions...................... 6

Typical Performance Characteristics ............................................. 7

Circuit Description........................................................................... 9

Reference Input Section............................................................... 9

RF Input Stage............................................................................... 9

RF INT Divider............................................................................. 9

INT, FRAC, MOD, and R Relationship...................................... 9

RF R Counter ................................................................................ 9

Phase Frequency Detector (PFD) and Charge Pump.............. 9

MUXOUT and Lock Detect...................................................... 10

Input Shift Registers................................................................... 10

Program Modes .......................................................................... 10

Control Register, R2................................................................... 15

Noise and Spur Register, R3 ...................................................... 16

Reserved Bits............................................................................... 16

RF Synthesizer: A Worked Example ........................................ 16

Modulus....................................................................................... 17

Reference Doubler and Reference Divider ............................. 17

12-Bit Programmable Modulus................................................ 17

Spurious Optimization and Fast-lock...................................... 17

Fast-Lock Timer and Register Sequences ............................... 17

Fast-Lock: A Worked Example ................................................. 18

Fast-Lock: Loop Filter Topology .............................................. 18

Spurious Signals.......................................................................... 18

Filter Design—ADIsimPLL....................................................... 18

Interfacing ................................................................................... 18

PCB Design Guidelines for Chip Scale Package .................... 19

Registers........................................................................................... 11

Register Definition ..................................................................... 15

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Rev. 0 | Page 2 of 20

ADF4154

SPECIFICATIONS

Table 1. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T
noted; dBm referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C.

Parameter B Version Unit Test Conditions/Comments

RF CHARACTERISTICS (3 V)

Figure 18 for input circuit.

See

RF Input Frequency (RFIN)1 0.5/4.0 GHz min/max −8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 396 V/µs.

1.0/4.0 GHz min/max −10 dBm/0 dBm min/max.

REFERENCE CHARACTERISTICS See Figure 17 for input circuit.

REFIN Input Frequency1

10/250 MHz min/max

For f < 10 MHz, use a dc-coupled, CMOS compatible square wave, slew rate >
21 V/µs.

REFIN Input Sensitivity 0.7/AVDD V p-p

AC-coupled.

min/max
0 to AVDD V max CMOS compatible.
REFIN Input Capacitance 10 pF max
REFIN Input Current ±100 µA max

PHASE DETECTOR

Phase Detector Frequency2 32 MHz max

CHARGE PUMP

ICP Sink/Source Programmable. See Table 5.

High Value 5 mA typ With R

= 5.1 kΩ.

SET

Low Value 312.5 µA typ
Absolute Accuracy 2.5 % typ With R
R

Range 1.5/10 kΩ min/max

SET

= 5.1 kΩ.

SET

ICP Three-State Leakage Current 1 nA typ Sink and source current.
Matching 2 % typ 0.5 V < VCP < VP – 0.5.
ICP vs. VCP 2 % typ 0.5 V < VCP < VP – 0.5.
ICP vs. Temperature 2 % typ VCP = VP/2.

LOGIC INPUTS

V

, Input High Voltage 1.4 V min

INH

V

, Input Low Voltage 0.6 V max

INL

I

, Input Current ±1 µA max

INH/IINL

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 V min Open-drain 1 kΩ pull-up to 1.8 V.
VOL, Output Low Voltage 0.4 V max IOL = 500 µA.

POWER SUPPLIES

AVDD 2.7/3.3 V min/V max
DVDD, SDVDD AVDD
VP AVDD/5.5 V min/V max

3

I

24 mA max 20 mA typical.

DD

Low Power Sleep Mode 1 µA typ

NOISE CHARACTERISTICS

Phase Noise Figure of Merit4 −213 dBc/Hz typ
ADF4154 Phase Noise Floor5 −143 dBc/Hz typ @ 10 MHz PFD frequency.

−139 dBc/Hz typ @ 26 MHz PFD frequency.
Phase Noise Performance6 @ VCO output.

1750 MHz Output7 −102 dBc/Hz typ @ 1 kHz offset, 26 MHz PFD frequency.

1

Use a square wave for frequencies below f

2

Guaranteed by design. Sample tested to ensure compliance.

3

AC coupling ensures AVDD/2 bias. See for typical circuit. Figure 17

4

This figure can be used to calculate phase noise for any application. Use the formula –213 + 10log(f

at the VCO output. The value given is the lowest noise mode.

5

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N-divider value).

The value given is the lowest noise mode.

6

The phase noise is measured with the EVAL-ADF4154EB1 evaluation board and the HP8562E spectrum analyzer.

7

f

REFIN

= 26 MHz; f

= 26 MHz; offset frequency = 1 kHz; RF

PFD

.

MIN

) + 20logN to calculate in-band phase noise performance, as seen

PFD

= 1750 MHz; loop B/W = 20 kHz; lowest noise mode.

OUT

MIN

to T

, unless otherwise

MAX

Rev. 0 | Page 3 of 20

ADF4154

TIMING CHARACTERISTICS

Table 2. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T
noted; dBm referred to 50 Ω.

Parameter1 Limit at T

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t1 20 ns min LE Setup Time
t2 10 ns min DATA to CLOCK Setup Time
t3 10 ns min DATA to CLOCK Hold Time
t4 25 ns min CLOCK High Duration
t5 25 ns min CLOCK Low Duration
t6 10 ns min CLOCK to LE Setup Time
t7 20 ns min LE Pulse Width

1

Guaranteed by design, but not production tested.

CLOCK

t

4

t

5

MIN

to T

, unless otherwise

MAX

DATA

LE

LE

t

2

DB23 (MSB) DB22 DB2

t

1

t

3

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

7

t

6

04833-0-026

Figure 2. Timing Diagram

Rev. 0 | Page 4 of 20

ADF4154

ABSOLUTE MAXIMUM RATINGS

Table 3. Absolute Maximum Ratings.

1, 2, 3

TA = 25°C, unless

otherwise noted.

Parameter Rating

VDD to GND −0.3 V to +4 V
VDD to VDD −0.3 V to +0.3 V
VP to GND −0.3 V to +5.8 V
VP to VDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN, RFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 150.4°C/W
LFCSP θJA Thermal Impedance

122°C/W

(Paddle Soldered)

LFCSP θJA Thermal Impedance

216°C/W

(Paddle Not Soldered)

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

1

This device is a high performance RF integrated circuit with an ESD rating of

< 2 kV, and it is ESD sensitive. Proper precautions should be taken for
handling and assembly.

2

GND = A

3

VDD = AVDD = DVDD = SDVDD.

GND

= D

GND

= 0 V.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 20

ADF4154

D

D

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

D

D

1

R

SET

CP

CPGND 3

AGND
RFINB 5
RFINA

AV

DD

REF

IN

2

ADF4154

4

TOP VIEW

(Not to Scale)

6
7
8

16
15
14
13
12
11
10

9

V

P

DV

DD

MUXOUT
LE
DATA
CLK
SDV

DD

DGND

04833-0-002

CPGND

AGND
AGND
RF

IN

RFINA

1
2
3
4

B

5

Figure 3. TSSOP Pin Configuration

Figure 4. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

TSSOP LFCSP Mnemonic Description

1 19 R

2 20 CP

SET

Connecting a resistor between this pin and ground sets the maximum charge pump output current.
The relationship between I

525I.

=

CP

max

R

SET

where R

= 5.1 kΩ and I

SET

Charge Pump Output. When enabled, this provides ±I

CPmax

and R

CP

= 5 mA.

SET

is

to the external loop filter, which in turn drives

CP

the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a

small bypass capacitor, typically 100 pF (see Figure 18).
6 5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7 6, 7 AVDD

8 8 REFIN

Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. AV

as DV

.

DD

has a value of 3 V ± 10%. AVDD must have the same voltage

DD

Reference Input. This is a CMOS input with a nominal threshold of V

resistance of 100 kΩ (see Figure 17). This input can be driven from a TTL or CMOS crystal oscillator, or it

can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 SDVDD

11 12 CLK

Σ-∆ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to

this pin. SDV

has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD.

DD

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a

high impedance CMOS input.
13 14 LE

Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of

the four latches, the latch being selected using the control bits.
14 15 MUXOUT

This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.
15 16, 17 DVDD

16 18 VP

Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. DV

voltage as AV

.

DD

has a value of 3 V ± 10%. DVDD must have the same

DD

Charge Pump Power Supply. This should be greater than or equal to V

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

SET

CP

R

VPDV

DV

20

191817

16

15

9

10

DGND

DGND

MUXOUT

14

LE

13

DATA

12

CLK
SDV

11

DD

PIN 1
INDICATOR

ADF4154

TOP VIEW

678

IN

DD

AVDDAV

REF

/2 and an equivalent input

DD

. In systems where VDD is 3 V, it

DD

04833-0-003

Rev. 0 | Page 6 of 20

ADF4154

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5 to Figure 10, and Figure 12: RF
Modulus = 130, Fraction = 30/130, and I

Loop Bandwidth = 20 kHz, Reference = 26 MHz, VCO = Vari-L VCO190-1750T, Evaluation Board = EVAL-ADF4154EB1. Measurements
were taken on the HP8562E spectrum analyzer.

= 1.722 GHz, PFD Frequency = 26 MHz, INT = 66, Channel Spacing = 200 kHz,

OUT

= 5 mA.

CP

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

REFERENCE
LEVEL = –4dBm

–2kHz –1kHz 1kHz 2kHz1.722GHz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST NOISE MODE
N = 66 30/130
RBW = 10Hz

Figure 5. Phase Noise (Lowest Noise Mode)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

REFERENCE
LEVEL = –4.2dBm

–2kHz –1kHz 1kHz 2kHz1.722GHz

VDD = 3V, VP = 5V
I

= 5mA

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOW NOISE AND
SPUR MODE
N = 66 30/130
RBW = 10Hz

–95dBc/Hz

Figure 6. Phase Noise (Low Noise Mode and Spur Mode)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

REFERENCE
LEVEL = –4.2dBm

–2kHz –1kHz 1kHz 2kHz1.722GHz

VDD = 3V, VP = 5V
I

= 5mA

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST SPUR MODE
N = 66 30/130
RBW = 10Hz

–90dBc/Hz

Figure 7. Phase Noise (Lowest Spur Mode)

–102dBc/Hz

04833-0-004

04833-0-005

04833-0-006

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

REFERENCE
LEVEL = –4.2dBm

–71dBc@200kHz

–400kHz –200kHz 200kHz 400kHz1.722GHz

Figure 8. Spurs (Lowest Noise Mode)

0

–10

REFERENCE
LEVEL = –4.2dBm

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–74dBc@200kHz

–400kHz –200kHz 200kHz 400kHz1.722GHz

Figure 9. Spurs (Low Noise and Spur Mode)

0

–10

REFERENCE
LEVEL = –4.2dBm

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–400kHz –200kHz 200kHz 400kHz1.722GHz

Figure 10. Spurs (Lowest Spur Mode)

VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST NOISE MODE
N = 66 30/130
RBW = 10Hz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOW NOISE AND
SPUR MODE
N = 66 30/130
RBW = 10Hz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST SPUR NOISE
N = 66 30/130
RBW = 10Hz

04833-0-007

04833-0-008

04833-0-009

Rev. 0 | Page 7 of 20

ADF4154

–130

–140

–80

–85

–90

–150

PHASE NOISE (dBc/Hz)

–160

–170

100 1000 10000 100000

PHASE DETECTOR FREQUENCY (kHz)

Figure 11. PFD Noise Floor vs. PFD Frequency (Lowest Noise Mode)

5

0

–5

–10

–15

–20

AMPLITUDE (dBm)

–25

–30

–35

0 0.5 1.0 1.5 4.03.53.02.52.0 4.5

FREQUENCY (GHz)

P = 4/5

P = 8/9

Figure 12. RF Input Sensitivity

6
5
4
3

2
1
0

(mA)

–1

CP

I

–2
–3

–4
–5
–6

012345

VCP(V)

Figure 13. Charge Pump Output Characteristics

04833-0-010

04833-0-011

04833-0-012

–95

–100

PHASE NOISE (dBc/Hz)

–105

–110

PHASE NOISE (dBc/Hz)

–90

–92

–94

–96

–98

–100

–102

–104

–60 100–40

0330252015105

R

VALUE (kΩ)

SET

Figure 14. Phase Noise vs. R

–20 0 20 40 60

TEMPERATURE(°C)

SET

5

04833-0-013

80

04833-0-014

Figure 15. Phase Noise vs. Temperature

1.700

1.696

1.692

1.688

1.684
A

1.680

1.676

1.672

1.668

1.664

1.660

FREQUENCY (GHz)

1.656

1.652

1.648

1.644

1.640

B

TIME (µs)

1000 10203040506065758595

04833-0-028

Figure 16. A) Lock Time in Fast-lock Mode. Fast Counter = 150, Low Spur

Mode: a 1649.7 MHz to 1686.8 MHz Frequency Jump.

Final Loop Bandwidth = 60 kHz

B) Lock Time with the PLL in Normal Mode (Non Fast-lock), Low Spur Mode, a

1649.7 MHz to 1686.8 MHz Frequency Jump. Final Loop Bandwidth = 60 kHz

Rev. 0 | Page 8 of 20

ADF4154

()(

)

(

)

+×=

+

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that the REF

pin is not loaded on

IN

power-down.

POWER-DOWN

CONTROL

100kΩ

NC

REF

SW1

NO

SW2

SW3

IN

NC

Figure 17. Reference Input Stage

BUFFER

TO R COUNTER

04833-0-027

RF INPUT STAGE

The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.

BIAS

GENERATOR

1.6V

2kΩ 2kΩ

AV

DD

INPFD

where:

REF

is the reference input frequency.

IN

D is the REF

doubler bit.

IN

R is the preset divide ratio of binary 4-bit programmable

reference counter (1 to 15).

INT is the preset divide ratio of binary 9-bit counter (31 to 511).
MOD is the preset modulus ratio of binary 12-bit program-

mable FRAC counter (2 to 4095).

FRAC is the preset fractional ratio of binary 12-bit

programmable FRAC counter (0 to MOD).

RF R COUNTER

The 4-bit RF R counter allows the input reference frequency

) to be divided down to produce the reference clock to

(REF

IN

the PFD. Division ratios from 1 to 15 are allowed.

RF N-DIVIDER N = INT + FRAC/MOD

FROM RF

INPUT STAGE

N COUNTER

INT

REG

RDREFF

1

(2)

TO PFD

THIRD ORDER

FRACTIONAL

INTERPOLATOR

MOD
REG

FRAC

VALUE

A

RF

IN

B

RF

IN

AGND

04833-0-015

Figure 18. RF Input Stage

RF INT DIVIDER

The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.

INT, FRAC, MOD, AND R RELATIONSHIP

The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more

RF

information. The RF VCO frequency (

+×=

where

PFD

OUT

RF

is the output frequency of the external voltage

OUT

controlled oscillator (VCO).

) equation is

OUT

MODFRACINTFRF

(1)

04833-0-016

Figure 19. A and B Counters

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 20 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and gives a consistent reference spur level.

HI

IN

HI

–IN

UP

Q1D1

U1

CLR1

U3

CLR2

U2

DELAY

DOWN

Q2D2

Figure 20. PFD Simplified Schematic

CHARGE

PUMP

CP

04833-0-017

Rev. 0 | Page 9 of 20

ADF4154

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4154 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (see Table 9).
Figure 21 shows the MUXOUT section in block diagram form.

The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, the lock detect is high with
narrow low-going pulses.

DV

DD

LOGIC LOW

ANALOG LOCK DETECT

R-DIVIDER OUTPUT
N-DIVIDER OUTPUT

FAST-LOCK CONTROL
THREE-STATE OUTPUT
DIGITAL LOCK DETECT

LOGIC HIGH

Figure 21. MUXOUT Schematic

CONTROLMUX

INPUT SHIFT REGISTERS

The ADF4154 digital section includes a 4-bit RF R counter, a
9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 24-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.

MUXOUT

DGND

04833-0-018

Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2 and C1) in the shift register.
These are the 2 LSBs, DB1, and DB0, as shown in Figure 2. The
truth table for these bits is shown in Table 5. Table 6 shows a
summary of how the latches are programmed.

PROGRAM MODES

Table 5 through Table 10 show how to set up the program
modes in the ADF4154.

The ADF4154 programmable modulus is double-buffered. This
means that two events have to occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R-divider register. Second, a new write
must be performed on the N-divider register. Therefore, when­ever the modulus value is updated, the N-divider register must
then be written to so that the modulus value is loaded correctly.

Table 5. C2 and C1 Truth Table

Control Bits
C2 C1 Data Latch

0 0 N-divider register
0 1 R-divider register
1 0 Control register
1 1 Noise and spur register

Rev. 0 | Page 10 of 20

ADF4154

REGISTERS

Table 6. Register Summary

N-DIVIDER REG

9-BIT RF INTEGER VALUE

FAST-LOCK

DB23 DB22 DB21

FL1

LOAD

CONTROL

DB23 DB22 DB21

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

N7N8N9

MUXOUT

RESERVED

PRESCALER

DB20 DB19

M2M3P3

DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P2

P1M1

Table 7. Noise and Spur Register

N2

4-BIT

R COUNTER

R2

DB15

12-BIT RF FRACTIONAL VALUE

12-BIT MODULUS

CP3

T9

CP/2

RESERVED

CP CURRENT

SETTING

NOISE AND SPUR

MODE

PD POLARITY

LDP

POWER-

RESERVED

CP

DOWN

THREE-STATE

RESERVED

DOUBLER

REFERENCE

DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB1 DB0

CONTROL

BITS

C2 (0) C1 (0)F1F2F3F4F5F6F7F8F9F10F11F12N1N3N4N5N6

R-DIVIDER REG

CONTROL

BITS

C2 (0) C1 (1)

M1M2M3M4M5M6M7M8M9M10M11M12R1R3R4

CONTROL REG

CONTROL

BITS

RESET

COUNTER

C2 (1) C1 (0)

U1U2U3U4U5CP0CP1CP2U60000

NOISE AND SPUR REG

CONTROL

BITS

MODE

NOISE

AND SPUR

DB2

C2 (1) C1 (1)

T1T2T3T4T5T6T7T8

04833-0-019

NOISE AND SPUR

RESERVED

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB1

T9

DB9, DB8, DB7, DB6, DB2
00000

11100
11111

MODE

NOISE AND SPUR SETTING
LOWEST SPUR MODE

LOW NOISE AND SPUR MODE
LOWEST NOISE MODE

RESERVED

DB10, DB5, DB4, DB3
0

THESE BITS MUST BE SET TO 0
FOR NORMAL OPERATION.

NOISE

DB2

T1T2T3T4T5T6T7T8

MODE

AND SPUR

RESERVED
RESERVED

CONTROL

C2 (1)

Rev. 0 | Page 11 of 20

BITS

DB0

C1 (1)

04833-0-023

ADF4154

Table 8. N-Divider Register Map

FAST-LOCK

DB23 DB22

N9

FL1

F1F2F3F4F5F6F7

CONTROL

BITS

C2 (0) C1 (0)

9-BIT INTEGER VALUE (INT)

DB21

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

N8

N7

N9

N8

0

0

0

0

0

0

0

0

.

.

.

.

.

.

1

1

1

1

1

1

N7
0

0
0
0
.
.
.
1
1
1

N6
0

1
1
1
.
.
.
1
1
1

F12
0

0
0
0
.
.
.
1
1
1
1

N2

N1N3N4N5N6

F11
0

0
0
0
.
.
.
1
1
1
1

N5
1

0
0
0
.
.
.
1
1
1

F10
0

0
0
0
.
.
.
1
1
1
1

N4
1

0
0
0
.
.
...
1
1
1

N3
1

0
0
0
.
.
.
1
1
1

12-BIT FRACTIONAL VALUE (FRAC)

F8

F9F10F11F12

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

N2
1

0
0
1
.
.
.
0
1
1

F3
0

0
0
0
.
.
.
1
1
1
1

N1
1

0
1
0
.
.
.
1
0
1

F2
0

0
1
1
.
.
.
0
0
1
1

INTEGER VALUE (INT)
31

32
33
34
.
.
.
509
510
511

F1
0

1
0
1
.
.
.
0
1
0
1

FRACTIONAL VALUE (FRAC)
0

1
2
3
.
.
.
4092
4093
4094
4095

FL1

FAST-LOCK

0

NORMAL OPERATION

1

FAST-LOCK ENABLED

Rev. 0 | Page 12 of 20

04833-0-020

ADF4154

Table 9. R-Divider Register Map

LOAD

CONTROL

DB23 DB22 DB21

P3

P3

LOAD CONTROL

0

NORMAL OPERATION

1

LOAD FAST-LOCK TIMER

MUXOUT

M2M3

DB20 DB19

P2

P1
0

1

M1M2M3M4M5M6M7M8M9M10M11M12R1R3R4

CONTROL

C2 (0) C1 (1)

12-BIT INTERPOLATOR MODULUS VALUE (MOD)4-BIT R COUNTER

RESERVED

PRESCALER

DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P1M1

PRESCALER
4/5

8/9

R4
0

0
0
0
.
.
.
1
1
1
1

R2

M12
0

0
0
.
.
.
1
1
1
1

R2

R3

0

0

1

0

1

0

0

1

.

.

.

.

.

.

0

1

0

1

1

1

1

1

M11
0

0
0
.
.
.
1
1
1
1

R1
1

0
1
0
.
.
.
0
1
0
1

M10
0

0
0
.
.
.
1
1
1
1

RF R-COUNTER
DIVIDE RATIO

1
2
3
4
.
.
.
12
13
14
15

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

M3
0

0
1
.
.
.
1
1
1
1

0

1

1

1

0

0

.

.

.

.

.

.

0

0

1

0

0

1

1

1

M1

M2

INTERPOLATOR
MODULUS VALUE (MOD)

2
3
4
.
.
.
4092
4093
4094
4095

BITS

M3
0

0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

THREE-STATE OUTPUT

0

DIGITAL LOCK DETECT

1

ANALOG LOCK DETECT

0

N-DIVIDER OUTPUT

1

LOGIC HIGH

0

LOGIC LOW

1

R-DIVIDER OUTPUT

0

FAST-LOCK SWITCH

1

04833-0-021

MUXOUT

M1

M2

Rev. 0 | Page 13 of 20

ADF4154

Table 10. Control Register Map

CP3

CP/2

CP CURRENT

SETTING

I

(mA)

CP

5.100kΩ

0.630

1.250

1.880

2.500

3.130

3.750

4.380

5.000

0.310

0.630

0.940

1.250

1.570

1.880

2.190

2.500

10.00kΩ

0.290

0.590

0.880

1.150

1.470

1.760

2.060

2.350

0.150

0.300

0.440

0.588

0.740

0.880

1.030

1.180

PD POLARITY

U5
0

1

LDP

POWER-

U3
0

1

LDP

U4

3

0

5

1

PD POLARITY
NEGATIVE

POSITIVE

CP

DOWN

THREE-STATE

U2
0

1

POWER-DOWN
NORMAL OPERATION

POWER-DOWN

RESERVED

DOUBLE

REFERENCE

DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB15

REFERENCE

U6

DOUBLER

0

DISABLED

1

ENABLED

÷3
0

0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

CP0
0

0
0
0
1
1
1
1

0
0
0
0
1
1
1
1

CP1
0

0
1
1
0
0
1
1

0
0
1
1
0
0
1
1

CP0
0

1
0
1
0
1
0
1

0
1
0
1
0
1
0
1

2.700kΩ

1.090

2.180

3.260

4.350

5.440

6.530

7.620

8.700

0.540

1.100

1.640

2.180

2.730

3.270

3.810

4.350

CONTROL

BITS

RESET

COUNTER

C2 (1) C1 (0)

U1U2U3U4U5CP0CP1CP2U60000

U1

COUNTER RESET

0

DISABLED

1

ENABLED

CP THREE-STATE
DISABLED

THREE-STATE

04833-0-022

Rev. 0 | Page 14 of 20

ADF4154

REGISTER DEFINITION

N-Divider Register, R0

The on-chip N-divider register is programmed by setting
R0[1, 0] to [0, 0]. Table 8 shows the input data format for
programming this register.

9-Bit INT Value

These nine bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor (see
Equation 1).

12-Bit FRAC Value

These 12 bits control what is loaded as the FRAC value into the
fractional interpolator. This value helps determine the overall
feedback division factor (see Equation 1). The FRAC value must
be less than the value loaded into the MOD register.

Fast-Lock

Setting the part to logic high enables fast-lock mode. To use
fast-lock, the required time value for wide bandwidth mode
needs to be loaded into the R-divider register.

The charge pump current increases from 16× the minimum
current and reverts back to 1× the minimum current once the
time value loaded has expired.

See the Fast-Lock Timer and Register Sequences section for
more information.

R-DIVIDER REGISTER, R1

The on-chip R-divider register is programmed by setting
R1[1, 0] to [0, 1]. Table 9 shows the input data format for
programming this register.

Load Control

When set to logic high, the value being programmed in the
modulus is not loaded into the modulus. Instead, it sets the fast­lock timer. The value of the fast-lock timer/F
of time the PLL stays in wide bandwidth mode.

MUXOUT

The on-chip multiplexer is controlled by R1[22...20] on the
ADF4154. Table 9 shows the truth table.

Digital Lock Detect

The digital lock detect output goes high if there are 40
successive PFD cycles with an input error of less than 15 ns. It
stays high until a new channel is programmed or until the error
at the PFD input exceeds 30 ns for one or more cycles. If the
loop bandwidth is narrow compared to the PFD frequency, the
error at the PFD inputs may drop below 15 ns for 40 cycles
around a cycle slip. Therefore, the digital lock detect may go
falsely high for a short period until the error again exceeds
30 ns. In this case, the digital lock detect is reliable only as a
loss-of-lock detector.

is the amount

PFD

Prescaler (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division ratio
from the RF

to the PFD input. Operating at CML levels, it

IN

takes the clock from the RF input stage and divides it down for
the counters. It is based on a synchronous 4/5 core. When set to
4/5, the maximum RF frequency allowed is 2 GHz. Therefore,
when operating the ADF4154 above 2 GHz, this must be set to
8/9. The prescaler limits the INT value.

With P = 4/5, N
With P = 8/9, N

MIN

MIN

= 31.
= 91.

The prescaler can also influence the phase noise performance. If
INT < 91, a prescaler of 4/5 should be used. For applications
where INT > 91, P = 8/9 should be used for optimum noise
performance (see Table 9).

4-Bit RF R Counter

The 4-bit RF R counter allows the input reference frequency

) to be divided down to produce the reference clock to

(REF

IN

the phase frequency detector (PFD). Division ratios from 1 to
15 are allowed.

12-Bit Interpolator Modulus/Fast-Lock Timer

Bits DB13–DB2 have two functions depending on the value of
the load control bit: modulus or fast lock timer value.

When the load control bit = 0 (DB23), the required modulus
may be programmed into the R-divider register (DB13–DB2).

When the load control bit = 1 (DB23), the required fast-lock
timer value may be programmed into the R-divider register
(DB13–DB2).

This programmable register sets the fractional modulus, which
is the ratio of the PFD frequency to the channel step resolution
on the RF output. Refer to the RF Synthesizer: A Worked
Example section for more information.

The ADF4154 programmable modulus is double-buffered. This
means that two events must occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R-divider register. Second, a new write
must be performed on the N-divider register. Therefore, when­ever the modulus value is updated, the N-divider register must
be written to so that the modulus value is loaded correctly.

CONTROL REGISTER, R2

The on-chip control register is programmed by setting R2[1, 0]
to [0, 1]. Table 10 shows the input data format for programming
this register.

RF Counter Reset

DB3 is the RF counter reset bit for the ADF4154. When this is 1,
the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.

Rev. 0 | Page 15 of 20

ADF4154

RF Charge Pump Three-State

This bit puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.

RF Power-Down

DB4 on the ADF4154 provides the programmable power-down
mode. Setting Bit DB4 to 1 powers down the device. Setting
Bit DB4 to 0 returns the synthesizer to normal operation. While
in software power-down mode, the part retains all information
in its registers. Only when supplies are removed are the register
contents lost.

When a power-down is activated, the following events occur:

1. All active dc current paths are removed.

2. The synthesizer counters are forced to their load
state conditions.

3. The charge pump is forced into three-state mode.

4. The digital lock detect circuitry is reset.

5. The RF

6. The input register remains active and capable of loading
and latching data.

Lock Detect Precision (LDP)

When the LDP bit is programmed to 0, 24 consecutive reference
cycles of 15 ns must occur before the digital lock detect is set.
When this bit is programmed to 1, 40 consecutive reference
cycles of 15 ns must occur before digital lock detect is set.

Phase Detector Polarity

DB6 in the ADF4154 sets the phase detector polarity. When the
VCO characteristics are positive, this should be set to 1. When
they are negative, it should be set to 0.

Charge Pump Current Setting

DB7, DB8, DB9, and DB10 set the charge pump current, which
should be set according to the loop filter design (see Table 10).

REFIN Doubler

Setting the REFIN bit to 0 feeds the REFIN signal directly to the
4-bit RF R counter, which disables the doubler. Setting the REF
bit to 1 multiplies the REF
feeding into the 4-bit R counter. When the doubler is disabled,
the REF
fractional synthesizer. When the doubler is enabled, both the
rising and falling edges of REF
PFD input.

When the doubler is enabled and the lowest spur mode is
chosen, the in-band phase noise performance is sensitive to the

duty cycle. The phase noise degradation can be as much

REF

IN

as 5 dB for the REF
The phase noise is insensitive to the REF
lowest noise mode and in the lowest noise and spur mode. The
phase noise is insensitive to the REF
doubler is disabled.

input is de-biased.

IN

frequency by a factor of 2 before

IN

falling edge is the active edge at the PFD input to the

IN

become active edges at the

IN

duty cycles outside a 45% to 55% range.

IN

duty cycle in the

IN

duty cycle when the

IN

NOISE AND SPUR REGISTER, R3

The on-chip noise and spur register is programmed by setting
R3[1, 0] to [1, 1]. Table 7 shows the input d ata format for
programming this register.

Noise and Spur Mode

Noise and spur mode allows the user to optimize a design either
for improved spurious performance or for improved phase
noise performance. When the lowest spur setting is chosen,
dither is enabled. This randomizes the fractional quantization
noise so that it looks more like white noise rather than spurious
noise. This means that the part is optimized for improved
spurious performance. This operation would normally be used
when the PLL closed-loop bandwidth is wide for fast-locking
applications. A wide-loop bandwidth is seen as a loop
bandwidth greater than 1/10 of the RF
resolution (f

). A wide-loop filter does not attenuate the spurs

RES

channel step

OUT

to a level that a narrow-loop bandwidth would. When the low
noise and spur setting is enabled, dither is disabled. This
optimizes the synthesizer to operate with improved noise
performance. However, the spurious performance is degraded
in this mode compared to the lowest spurs setting. To further
improve noise performance, the lowest noise setting option can
be used, which reduces the phase noise. As well as disabling the
dither, it ensures that the charge pump operates in an optimum
region for noise performance. This setting is extremely useful
where a narrow-loop filter bandwidth is available. The
synthesizer ensures extremely low noise and the filter attenuates
the spurs. The typical performance characteristics give the user
an idea of the trade-off in a typical WCDMA setup for the
different noise and spur settings.

RESERVED BITS

These bits should be set to 0 for normal operation.

RF SYNTHESIZER: A WORKED EXAMPLE

This equation governs how the synthesizer should be
programmed.

RF

= [INT + (FRAC/MOD)] × [F

IN

OUT

where:

RF

is the RF frequency output.

OUT

INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.

F

= [REFIN × (1 = D)/R] (4)

PFD

where:

REF

is the reference frequency input.

IN

D is the RF REF

doubler bit.

IN

R is the RF reference division factor.

] (3)

PFD

Rev. 0 | Page 16 of 20

ADF4154

(

)

For example, in a GSM 1800 system, where a 1.8 GHz RF
frequency output (RF
frequency input (REF
resolution (f

) is required on the RF output.

RES

=

MOD

) is required, a 13 MHz reference

OUT

) is available and a 200 kHz channel

IN

fREFMOD

IN

RES

65kHz200MHz13 ==

From Equation 4,

= [13 MHz × (1 + 0)/1] = 13 MHz (5)

F

PFD

65MHz138.1

FRACINTG

30;138

=≥=

FRACINT

≥+×=

(6)

MODULUS

The choice of modulus (MOD) depends on the reference signal
(REFIN) available and the channel resolution (f
the RF output. For example, a GSM system with 13 MHz REF

) required at

RES

IN

would set the modulus to 65, resulting in the RF output resolu­tion (f

) of 200 kHz (13 MHz/65) that is necessary for GSM.

RES

REFERENCE DOUBLER AND REFERENCE DIVIDER

The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually results in an improvement in noise performance of 3 dB.
It is important to note that the PFD cannot be operated above
32 MHz due to a limitation in the speed of the Σ-Δ circuit of
the N divider.

12-BIT PROGRAMMABLE MODULUS

Unlike most other fractional-N PLLs, the ADF4154 allows the
user to program the modulus over a 12-bit range. This means
that the user can set up the part in many different configura­tions for the application, when combined with the reference
doubler and the 4-bit R counter.

For example, consider an application that requires a 1.75 GHz
RF and a 200 kHz channel step resolution. The system has a
13 MHz reference signal.

One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65, which would
result in the required 200 kHz resolution.

Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz signal is
then fed into the PFD, which programs the modulus to divide
by 130. This setup also results in 200 kHz resolution and offers
superior phase noise performance over the previous setup.

The programmable modulus is also very useful for multi­standard applications. If a dual-mode phone requires PDC and
GSM 1800 standards, the programmable modulus is a huge
benefit. The PDC requires a 25 kHz channel step resolution,
whereas the GSM 1800 requires a 200 kHz channel step

resolution. A 13 MHz reference signal could be fed directly to
the PFD. The modulus would be programmed to 520 when in
PDC mode (13 MHz/520 = 25 kHz). The modulus would be
reprogrammed to 65 for GSM 1800 operation (13 MHz/65 =
200 kHz). It is important that the PFD frequency remains con­stant (13 MHz). By keeping the PFD constant, the user can
design a one-loop filter that can be used in both setups without
running into stability issues. The ratio of the RF frequency to
the PFD frequency affects the loop design. Keeping this
relationship constant instead of changing the modulus factor
results in a stable filter.

SPURIOUS OPTIMIZATION AND FAST-LOCK

The ADF4154 can be optimized for low spurious signals by
using the noise and spur register. However, in order to achieve
fast-lock time, a wider loop bandwidth is needed. Note that a
wider loop bandwidth can lead to notable spurious signals,
which cannot be reduced significantly by the loop filter.

Using the fast-lock feature can achieve the same fast-lock time
as the noise and spur register, but with the advantage of lower
spurious signals, since the final loop bandwidth is reduced by
a quarter.

FAST-LOCK TIMER AND REGISTER SEQUENCES

If the fast-lock mode is used, a timer value needs to be loaded
into the PLL to determine the time of the wide bandwidth.

When the load control bit = 1, the timer value is loaded via the
12-bit modulus value. To use fast-lock, the PLL must be written
to in the following sequence:

1.

Load the R-divider register with DB23 = 1 and the chosen

fast-lock timer value (DB13–DB2) instead of the modulus.
Note that the duration of time the PLL remains in wide
bandwidth is equal to the fast-lock timer/F

2.

Load the noise and spur register.
Load the control register.

3.

Load R-divider register with DB23 = 0 and MUXOUT =

4.
110 (DB22–DB20). All the other needed parameters,
including the modulus, also need to be loaded.

5.

Load the N-divider register, including fast-lock = 1

(DB23), to activate fast-lock mode.

Once this procedure is completed, future frequency jumps
deploying fast-lock need to repeat only Step 5.

PFD

.

Rev. 0 | Page 17 of 20

ADF4154

If fast-lock is not used, then use the following sequence:

Load the noise and spur register.

1.

Load the control register.

2.

3.

Load the R-divider register with DB23 = 0 and other

necessary parameters.

ADF4154

MUXOUT

CP

R2

C1

C2

R1R1A

VCO

C3

4.

Load the N-divider register, including fast-lock = 0

(DB23) for normal operation.

To change frequency, only Step 4 need be repeated.

FAST-LOCK: A WORKED EXAMPLE

Consider an example in which PLL has reference frequencies of
13 MHz and F

= 13 MHz and a required lock time of 50 µs.

PFD

Therefore, the PLL is set to wide bandwidth for 40 µs.

If the time period chosen for the wide bandwidth is 40 µs, then

Fast-lock timer value = time in wide bandwidth × F

PFD

Fast-lock timer value = 40 µs × 13 MHz = 520

Therefore, 520 has to be loaded into the R-divider register in
Step 1 of the sequence described in the Fast-Lock Timer and
Register Sequences section.

FAST-LOCK: LOOP FILTER TOPOLOGY

To use fast-lock mode, an extra connection from the PLL to the
loop filter is needed. The MUXOUT must reduce the damping
resistor in the loop filter to ¼ while in wide bandwidth mode.
This is required because the charge pump current is increased
by 16 while in wide bandwidth mode and stability must be
ensured. This can be done with the following two topologies:

1.

Divide the damping resistor (R1) into two values (R1 and

R1A) of ratio 1:3 (see Figure 22).

2.

Use an extra resistor (R1A) and connect it directly from the

MUXOUT, as shown in Figure 22. The extra resistor must
be chosen such that the parallel combination of an extra
resistor and the damping resistor (R1) is reduced to ¼ of
the original value of R1 alone (see Figure 23).

ADF4154

CP

C1

MUXOUT

Figure 22 Fast-lock Loop Filter Topology—Topology 1

R2

C2

R1

R1A

VCO

C3

04833-0-029

04833-0-030

Figure 23. Fast-lock Loop Filter Topology—Topology 2

SPURIOUS SIGNALS

Predicting Where They Appear

As in integer-N PLLs, spurs appear at PFD frequency offsets
from the carrier. In a fractional-N PLL, spurs also appear at
frequencies equal to the RF

channel step resolution (f

OUT

RES

).
The third-order fractional interpolator engine of the ADF4154
may also introduce subfractional spurs. If the fractional deno­minator (MOD) is divisible by 2, spurs appear at ½ f

RES.

If the
fractional denominator (MOD) is divisible by 3, spurs appear at
1/3 f

Harmonics of all spurs mentioned also appear. With the

RES.

lowest spur mode enabled, the fractional and subfractional
spurs are attenuated dramatically. The worst-case spurs appear
when the fraction is programmed to 1/MOD. For example, in a
GSM 900 MHz system with a 26 MHz PFD frequency and an
RF

channel step resolution (f

OUT

) of 200 kHz, the MOD = 130.

RES

PFD spurs appear at 26 MHz offset and fractional spurs appear
at 200 kHz offset. Since the MOD is divisible by 2, subfractional
spurs are also present at 100 kHz offset.

FILTER DESIGN—ADISIMPLL

A filter design and analysis program is available to help the user
implement the PLL design. Visit www.analog.com/pll for a free
download of the ADIsimPLL software. The software designs,
simulates, and analyzes the entire PLL frequency and time
domain response. Various passive and active filter architectures
are allowed. Rev. 2 of ADIsimPLL allows analysis of the
ADF4154.

INTERFACING

The ADF4154 has a simple, SPI® compatible serial interface for
writing to the device. SCLK, SDATA, and LE control the data
transfer. When LE (latch enable) is high, the 22 bits that have
been clocked into the input register on each rising edge of
SCLK are transferred to the appropriate latch. See Figure 2 for
the timing diagram and Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
909 kHz or one update every 1.1 µs. This is more than adequate
for systems that have typical lock times in the hundreds of
microseconds.

Rev. 0 | Page 18 of 20

ADF4154

ADuC812 Interface

Figure 24 shows the interface between the ADF4154 and the
ADuC812 MicroConverter®. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, bring the I/O
port driving LE low. Each latch of the ADF4154 needs a 24-bit
word, which is accomplished by writing three 8-bit bytes from
the MicroConverter to the device. After the third byte is written,
the LE input should be brought high to complete the transfer.

ADSP-21xx ADF4154

SCLOCK

DT

TFS

I/O FLAGS

Figure 25. ADSP-21xx to ADF4154 Interface

SCLK

SDATA

LE

MUXOUT
(LOCK DETECT)

04833-0-025

When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that the
maximum rate at which the output frequency can be changed is
180 kHz.

ADuC812 ADF4154

SCLOCK

MOSI

I/O PORTS

Figure 24. ADuC812 to ADF4154 Interface

SCLK

SDATA

LE

MUXOUT
(LOCK DETECT)

04833-0-024

ADSP-2181 Interface

Figure 25 shows the interface between the ADF4154 and the
ADSP-21xx digital signal processor. As discussed previously, the
ADF4154 needs a 24-bit serial word for each latch write. The
easiest way to accomplish this using the ADSP-21xx family is to
use the autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for eight bits and use three memory locations for each
24-bit word. To program each 24-bit latch, store each of the
three 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad.
This ensures that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to avoid shorting.

Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated into the thermal pad at

1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz. of
copper to plug the via.

The user should connect the printed circuit board thermal pad
to AGND.

Rev. 0 | Page 19 of 20

ADF4154

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

Figure 26. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.60

MAX

0.60

MAX

0.75

0.55

0.35

COPLANARITY

0.08

16

15

11

10

BOTTOM

VIEW

0.30

0.23

0.18

12° MAX

BSC SQ

0.50
BSC

4.0

TOP

VIEW

0.80 MAX

0.65 TYP

0.20
REF

3.75

BSC SQ

0.05 MAX

0.02 NOM

0.75

0.60

0.45

20

1

2.25

2.10 SQ

1.95

5

6

0.25MIN

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

Figure 27. 20-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body, (CP-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model Description Temperature Range Package Option

ADF4154BRU Thin Shrink Small Outline Package (TSSOP) −40°C to +85°C RU-16
ADF4154BRU-REEL Thin Shrink Small Outline Package (TSSOP) −40°C to +85°C RU-16
ADF4154BRU-REEL7 Thin Shrink Small Outline Package (TSSOP) −40°C to +85°C RU-16
ADF4154BCP Lead Frame Chip Scale Package (LFCSP) −40°C to +85°C CP-20
ADF4154BCP-REEL Lead Frame Chip Scale Package (LFCSP) −40°C to +85°C CP-20
ADF4154BCP-REEL7 Lead Frame Chip Scale Package (LFCSP) −40°C to +85°C CP-20
EVAL-ADF4154EB1

Purchase of licensed I2C components of Analog Devices, Inc. or one of its sublicensed Associated Companies conveys a license for the purchaser under the

2

Philips I

C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04833–0–4/04(0)

Rev. 0 | Page 20 of 20