Datasheet ADF4108 Datasheet (ANALOG DEVICES)

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PLL Frequency Synthesizer

FEATURES

8.0 GHz bandwidth

3.2 V to 3.6 V power supply
Separate charge pump supply (V

voltage in 3.3 V systems

Programmable, dual-modulus prescaler

8/9, 16/17,

32/33, or 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
Loop filter design possible with ADIsimPLL
4 mm × 4 mm, 20-lead chip scale package

APPLICATIONS

Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio

) allows extended tuning

P

DV

AV

DD

DD

GENERAL DESCRIPTION

The ADF4108 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. It consists of a
low noise digital PFD (phase frequency detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual-modulus prescaler (P/P + 1).
The A (6-bit) and B (13-bit) counters, in conjunction with the
dual-modulus prescaler (P/P + 1), implement an N divider
(N = BP + A). In addition, the 14-bit reference counter (R counter),
allows selectable REF
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and voltage controlled oscillator
(VCO). Its very high bandwidth means that frequency doublers
can be eliminated in many high frequency systems, simplifying
system architecture and reducing cost.

FUNCTIONAL BLOCK DIAGRAM

V

CPGND

P

ADF4108

frequencies at the PFD input. A complete

IN

R

SET

REFERENCE

REF

IN

CLK

DATA

LE

RFINA

B

RF

IN

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

24-BIT INP UT

REGISTER

SD

OUT

FUNCTION

PRESCALER

FROM

LATCH

P/P + 1

CE

22

N = BP + A

AGND

14-BIT

R COUNTER

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

B COUNTER

LOAD

LOAD

A COUNTER

DGND

14

13

13-BIT

6-BIT

6

19

Figure 1.

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

SD

CURRENT

SETTING 1

CPI3 CPI2 CPI1

AV

DD

OUT

CHARGE

MUX

M3 M2 M1

PUMP

CURRENT

SETTING 2

CPI6 CPI5 CPI4

HIGH-Z

CP

MUXOUT

ADF4108

06015-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

ADF4108

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ........................................................................ 9

Reference Input Stage................................................................... 9

RF Input Stage............................................................................... 9

Prescaler (P/P + 1)........................................................................ 9

A and B Counters ......................................................................... 9

R Counter ...................................................................................... 9

Phase Frequency Detector and Charge Pump....................... 10

MUXOUT and Lock Detect...................................................... 10

Input Shift Register .................................................................... 10

Latch Summary........................................................................... 11

Reference Counter Latch Map.................................................. 12

AB Counter Latch Map ............................................................. 13

Function Latch Map................................................................... 14

Initialization Latch Map ............................................................ 15

Function Latch............................................................................ 16

Initialization Latch..................................................................... 17

Power Supply Considerations................................................... 17

Interfacing ....................................................................................... 18

ADuC812 Interface.................................................................... 18

ADSP-21xx Interface ................................................................. 18

PCB Design Guidelines for Chip Scale Package......................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

12/07—Rev. 0 to Rev. A

Removed TSSOP Package..................................................Universal

Changes to Features.......................................................................... 1

Changes to Table 1 Endnote 10 and Endnote 11.......................... 4

Changes to Table 3............................................................................ 6

Deleted Figure 3................................................................................ 7

Changes to Table 4............................................................................ 7

Changes to Figure 10 and Figure 11............................................... 8

Updated Outline Dimensions....................................................... 20

Deleted Figure 24............................................................................ 20

Changes to Ordering Guide.......................................................... 20

4/06—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADF4108

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SPECIFICATIONS

AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
T

, unless otherwise noted.

MAX

Table 1.

B Chips2

Parameter B Version

1

(Typ) Unit Test Conditions/Comments

RF CHARACTERISTICS See Figure 11 for input circuit

RF Input Frequency (RFIN) 1.0/8.0 1.0/8.0 GHz min/max For lower frequencies, ensure slew rate (SR) > 320 V/μs
RF Input Sensitivity −5/+5 −5/+5 dBm min/max
Maximum Allowable Prescaler

Output Frequency

3

300 300 MHz max P = 8

325 325 MHz max P = 16

REFIN CHARACTERISTICS

REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, ensure SR > 50 V/μs
REFIN Input Sensitivity

4

0.8/VDD 0.8/VDD V p-p min/max Biased at AVDD/2
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 μA max

PHASE DETECTOR

Phase Detector Frequency

6

104 104 MHz max

CHARGE PUMP Programmable; see Figure 18

ICP Sink/Source

High Value 5 5 mA typ With R
Low Value 625 625 μA typ
Absolute Accuracy 2.5 2.5 % typ With R
R

Range 3.0/11 3.0/11 kΩ typ See Figure 18

SET

ICP Three-State Leakage 1 1 nA typ 1 nA typical; TA = 25°C
Sink and Source Current Matching 2 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. VCP 1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 1.4 V min
VIL, Input Low Voltage 0.6 0.6 V max
I

, I

, Input Current ±1 ±1 μA max

INH

INL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 1.4 V min Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V
VOH, Output High Voltage VDD − 0.4 VDD − 0.4 V min CMOS output chosen
IOH, Output High Current 100 100 μA max
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 μA

POWER SUPPLIES

AVDD 3.2/3.6 3.2/3.6 V min/max
DVDD AVDD AVDD
VP AVDD/5.5 AVDD/5.5 V min/max AVDD ≤ VP ≤ 5.5 V
IDD (AIDD + DIDD)

7

17 17 mA max 15 mA typ
IP 0.4 0.4 mA max TA = 25°C
Power-Down Mode (AIDD + DIDD)810 10 μA typ

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

5

= 5.1 kΩ

SET

= 5.1 kΩ

SET

MIN

to

Rev. A | Page 3 of 20

ADF4108

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B Chips2

Parameter B Version

NOISE CHARACTERISTICS

Normalized Phase Noise Floor
Phase Noise Performance

7900 MHz Output

11

9

10

−219 −219 dBc/Hz typ
@ VCO output

−81 −81 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency

Spurious Signals

7900 MHz Output

1

Operating temperature range (B version) is −40°C to +85°C.

2

The B chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

4

AVDD = DVDD = 3.3 V.

5

AC coupling ensures AVDD/2 bias.

6

Guaranteed by design. Sample tested to ensure compliance.

7

TA = 25°C; AVDD = DVDD = 3.3 V; P = 32; RFIN = 8 GHz, f

8

TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz.

9

This value can be used to calculate phase noise for any application. Use the formula −219 + 10 log(f

seen at the VCO output. The value given is the lowest noise mode.

10

The phase noise is measured with the EVAL-ADF4108EB1Z evaluation board, with the ZComm CRO8000Z VCO. The spectrum analyzer provides the REFIN for the
synthesizer (f

11

f

REFIN

REFOUT

= 10 MHz; f

PFD

11

= 10 MHz @ 0 dBm).

= 1 MHz; fRF = 7900 MHz; N = 7900; loop B/W = 30 kHz, VCO = ZComm CRO8000Z.

−82 −82 dBc typ @ 1 MHz offset and 1 MHz PFD frequency

1

(Typ) Unit Test Conditions/Comments

= 200 kHz, REFIN = 10 MHz.

PFD

) + 20 logN to calculate in-band phase noise performance as

PFD

Rev. A | Page 4 of 20

ADF4108

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TIMING CHARACTERISTICS

AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
T

, unless otherwise noted.

MAX

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

MIN

to

Table 2.

Parameter

1

Limit2 (B Version) Unit Test Conditions/Comments

t1 10 ns min DATA to CLOCK setup time
t2 10 ns min DATA to CLOCK hold time
t3 25 ns min CLOCK high duration
t4 25 ns min CLOCK low duration
t5 10 ns min CLOCK to LE setup time
t6 20 ns min LE pulse width

1

Guaranteed by design but not production tested.

2

Operating temperature range (B Version) is −40°C to +85°C.

t

t

3

4

CLOCK

DATA

DB23 (MSB)

LE

LE

t

t

1

2

DB22

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

Figure 2. Timing Diagram

06015-002

Rev. A | Page 5 of 20

ADF4108

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.9 V
AVDD to DVDD −0.3 V to +0.3 V
VP to GND −0.3 V to +5.8 V
VP to AVDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
CSP θJA Thermal Impedance

(Paddle Soldered)
Reflow Soldering

Peak Temperature (60 sec) 260°C

Time at Peak Temperature 40 sec
Transistor Count

CMOS 6425

Bipolar 303

1

GND = AGND = DGND = 0 V.

30.4°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an

D rating of <2 kV, and it is ESD sensitive. Proper precautions

ES
should be taken for handling and assembly.

ESD CAUTION

Rev. A | Page 6 of 20

ADF4108

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DD

DD

P

SET

V

DV

R

DV

20 CP

191817

16

CPGND 1

AGND 2
AGND 3
RFINB 4
RF

A 5

IN

PIN 1
INDICATOR

ADF4108

TOP VIEW

(Not to Scale)

6

7

DD

AV

AV

Figure 3. Pin Configuration

DD

8

IN

REF

DGND 9

DGND 10

15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE

6015-003

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
4 RFINB

Complementary Input to the RF Prescaler. This point must be d

ecoupled to the ground plane with a small bypass

capacitor, typically 100 pF. See Figure 11.
5 RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
6, 7 AVDD

8 REFIN

Analog Power Supply. This voltage may range from 3.2 V to 3.6

plane should be placed as close as possible to this pin. AV

Reference Input. This is a CMOS input with a nominal thr

V. Decoupling capacitors to the analog ground

must be the same value as DVDD.

DD

eshold of V

/2 and a dc equivalent input resistance of

DD

100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9, 10 DGND Digital Ground.
11 CE

12 CLK

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state

. Taking the pin high powers up the device, depending on the status of the power-down bit, F2.

mode

Serial Clock Input. This serial clock is used to clock in the serial d

ata to the registers. The data is latched into the

24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
13 DATA

Serial Data Input. The serial da

ta is loaded MSB first with the 2 LSBs being the control bits. This input is a high

impedance CMOS input.
14 LE

Load Enable, CMOS Input. When LE goes high, the data stored i

n the shift registers is loaded into one of the four

latches, the latch being selected using the control bits.
15 MUXOUT

This multiplexer output allows either the lock de

tect, the scaled RF, or the scaled reference frequency to be

accessed externally.
16, 17 DVDD

18 VP

Digital Power Supply. This may range from 3.2 V to 3.6 V. Dec

be placed as close as possible to this pin. DV

must be the same value as AVDD.

DD

Charge Pump Power Supply. This voltage should be greater than or equal to V

oupling capacitors to the digital ground plane should

. In systems where VDD is 3.3 V, it

DD

can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
19 R

20 CP

SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal

oltage potential at the R

v

25.5

=

I

MAXCP

R

SET

with R

= 5.1 kΩ, I

SET

CP MAX

pin is 0.66 V. The relationship between ICP and R

SET

= 5 mA.

Charge Pump Output. When enabled, this pin provides ±I

to the external loop filter, which in turn drives the

CP

SET

is

external VCO.

Rev. A | Page 7 of 20

ADF4108

–

–

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TYPICAL PERFORMANCE CHARACTERISTICS

FREQ UNIT: GHz KEYWORD: R
PARAM TYPE: s
DATA FORMAT: MA

Freq MAGS11 ANGS11

0.89148

0.88133

0.87152

0.85855

0.84911

0.83512

0.82374

0.80871

0.79176

0.77205

0.75696

0.74234

0.72239

0.69419

0.67288

0.66227

0.64758

0.62454

0.59466

0.55932

0.52256

0.48754

0.46411

0.45776

0.44859

0.44588

0.43810

0.43269

0.42777

0.42859

0.43365

0.43849

0.44475

0.44800

0.45223

0.45555

0.45313

0.45622

–17.2820
–20.6919
–24.5386
–27.3228
–31.0698
–34.8623
–38.5574
–41.9093
–45.6990
–49.4185
–52.8898
–56.2923
–60.2584
–63.1446
–65.6464
–68.0742
–71.3530
–75.5658
–79.6404
–82.8246
–85.2795
–85.6298
–86.1854
–86.4997
–88.8080
–91.9737
–95.4087
–99.1282
–102.748
–107.167
–111.883
–117.548
–123.856
–130.399
–136.744
–142.766
–149.269
–154.884

0.50000

0.60000

0.70000

0.80000

0.90000

1.00000

1.10000

1.20000

1.30000

1.40000

1.50000

1.60000

1.70000

1.80000

1.90000

2.00000

2.10000

2.20000

2.30000

2.40000

2.50000

2.60000

2.70000

2.80000

2.90000

3.00000

3.10000

3.20000

3.30000

3.40000

3.50000

3.60000

3.70000

3.80000

3.90000

4.00000

4.10000

4.20000

Freq MAGS11 ANGS11

0.45555

4.30000

0.46108

4.40000

0.45325

4.50000

0.45054

4.60000

0.45200

4.70000

0.45043

4.80000

0.45282

4.90000

0.44287

5.00000

0.44909

5.10000

0.44294

5.20000

0.44558

5.30000

0.45417

5.40000

0.46038

5.50000

0.47128

5.60000

0.47439

5.70000

0.48604

5.80000

0.50637

5.90000

0.52172

6.00000

0.53342

6.10000

0.53716

6.20000

0.55804

6.30000

0.56362

6.40000

0.58268

6.50000

0.59248

6.60000

0.61066

6.70000

0.61830

6.80000

0.61633

6.90000

0.61673

7.00000

0.60597

7.10000

0.58376

7.20000

0.57673

7.30000

0.58157

7.40000

0.60040

7.50000

0.61332

7.60000

0.62927

7.70000

0.63938

7.80000

0.65320

7.90000

0.65804

8.00000

Figure 4. S Parameter Data for the RF Input

–159.680
–164.916
–168.452
–173.462
–176.697

178.824

174.947

170.237

166.617

162.786

158.766

153.195

147.721

139.760

132.657

125.782

121.110

115.400

107.705

101.572

97.5379

93.0936

89.2227

86.3300

83.0956

80.8843

78.0872

75.3727

73.9456

73.5883

74.1975

76.2136

77.1545

76.1122

74.8359

74.0546

72.0061

69.9926

06015-004

0

VDD = 3.3V, VP = 5V
I

= 5mA

CP

PFD FREQUENCY = 1MHz
LOOP BANDWI DTH = 30kHz

–20

RES BANDWIDTH = 3kHz
VIDEO BANDWI DTH = 3kHz
AVERAGES = 1
OUTPUT PO WER = –0. 3dBm

–40

VCO = ZCOM M CRO8000Z

–60

OUTPUT PO WER (dBm)

–80

–100

CENTER 7.9GHz
RES BW 24kHz

Figure 7. Reference Spurs at 7.9 GHz

1R

VBW 24kHz

MARKER 1 1MHz

–82.091dBc

SPAN 2.5MHz

1

06015-011

0

VDD = 3.3V

–5

T

= +85°C

A

–10

–15

T

= +25°C

A

–20

–25

RF INPUT POWER (dBm)

–30

–35

198765432

RF INPUT FREQUENCY (GHz)

Figure 5. RF Input Sensitivity

50

–60

–70

–80

1

–90

–100

–110

CARRIER POWER –5. 23dBm

–120

PHASE NOISE (dBc/Hz)

V

= 3.3V, VP = 5V

DD

I

= 5mA

CP

–130

PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 50kHz

–140

PHASE NOISE = –82dBc/Hz @ 1kHz
VCO = ZCO MM CRO8000Z

–150

100Hz 10MHz

FREQUENCY OFFSET

MARKER 1 1kHz

Figure 6. Phase Noise at 7.9 GHz

T

= –40°C

A

–82.51dBc/Hz

6

5

4

3

VP = 5V
I

SETTLING = 5mA

CP

2

1

0

(mA)

CP

I

–1

–2

–3

–4

–5

–6

V

(V)

06015-005

CP

5.00 0.5 1.0 1.5 2. 0 2.5 3.0 3.5 4.0 4.5

06015-015

Figure 8. Charge Pump Output Characteristics

120

–130

–140

–150

–160

PHASE NOISE (dBc/Hz)

–170

–180

06015-010

PHASE FREQUENCY DETECTOR ( Hz)

VDD = 3V

= 5V

V

P

100M10k 100k 1M 10M

06015-014

Figure 9. Phase Noise (Referred to CP Output) vs. PFD Frequency

Rev. A | Page 8 of 20

ADF4108

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THEORY OF OPERATION

REFERENCE INPUT STAGE

The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF

IN

pin

on power-down.

POWER-DOWN

CONTROL

NC

100kΩ

SW1

NO

SW2

SW3

BUFFER

TO R COUNTER

6015-016

REF

IN

NC

Figure 10. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 11. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.

500Ω

1.6V

500Ω

AV

DD

BIAS

GENERATOR

A AND B COUNTERS

The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is as follows:

f

[]

()

VCO

where:

f

is the output frequency of external voltage controlled

VCO

oscillator (VCO).
P is the preset modulus of dual-modulus prescaler (8/9, 16/17,
and so on.).

B is the preset divide ratio of binary 13-bit counter (3 to 8191).
A is the preset divide ratio of binary 6-bit swallow counter

(0 to 63).

f

is the external reference frequency oscillator.

REFIN

N = BP + A

REFIN

ABPf

×+×=

R

RFINA

B

RF

IN

AGND

Figure 11. RF Input Stage

6015-017

PRESCALER (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized (N =
BP + A). The dual-modulus prescaler, operating at CML levels,
takes the clock from the RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9,
16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.
A minimum divide ratio is possible for contiguous output
frequencies. This minimum is determined by P, the prescaler
value, and is given by (P

2

− P).

TO PFD

FROM RF

INPUT STAG

PRESCALER

P/P + 1

MODULUS
CONTROL

N DIVIDER

Figure 12. A and B Counters

13-BIT B

COUNTER

LOAD

LOAD

6-BIT A

COUNTER

R COUNTER

The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.

06015-018

Rev. A | Page 9 of 20

ADF4108

V

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PHASE FREQUENCY DETECTOR AND CHARGE PUMP

The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 13 is a simplified schematic. The PFD includes a
p

rogrammable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse (see

he minimum antibacklash pulse width is not recommended.

t

UP

HI

R DIVIDER

HID1D2

N DIVIDER

Figure 13. PFD Simplified Schemat

Q1

U1

CLR1

PROGRAMMABLE

ABP2

CLR2

DOWN

Q2

U2

DELAY

U3

ABP1

ic and Timing (in Lock)

Figure 16). Use of

P

CHARGE

PUMP

CP

CPGND

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4108 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch.

Figure 18 shows the full truth table. Figure 14 shows the

OUT section in block diagram form.

MUX

Lock Detect

MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.

Digital lock detect is active high. When the lock detect precision
(

LDP) bit in the R counter latch is set to 0, digital lock detect is
set high when the phase error on three consecutive phase
detector (PD) cycles is less than 15 ns. With LDP set to 1, five

06015-019

consecutive cycles of less than 15 ns are required to set the lock
detect. It stays set high until a phase error of greater than 25 ns
is detected on any subsequent PD cycle.

The N-channel open-drain analog lock detect should be
op

erated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, this output is high with narrow,
low going pulses.

DV

DD

ANALOG LO CK DETECT

DIGITAL LOCK DET ECT

R COUNTER OUT PUT

N COUNTER OUT PUT

SDOUT

MUX

Figure 14. MUXOUT Circuit

CONTROL

MUXOUT

DGND

INPUT SHIFT REGISTER

The ADF4108 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the 2 LSBs, DB1 and DB0, as
shown in the timing diagram of

hese bits is shown in Tabl e 5.

t

Figure 15 shows a summary of how the latches are
pro

grammed.

Table 5. C2 and C1 Truth Table

Control Bits

C2 C1

Data Latch

0 0 R counter
0 1 N counter (A and B)
1 0

Function latch (including prescaler)

1 1 Initialization latch

Figure 2. The truth table for

6015-020

Rev. A | Page 10 of 20

ADF4108

www.BDTIC.com/ADI

LATCH SUMMARY

REFERENCE COUNTER LATCH

RESERVED

00X

RESERVED

PRESCALER

VALUE

DB22DB23

TEST

MODE BITS

LOCK

DETECT

PRECISION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

G1XX

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ANTI-

BACKLASH

WIDTH

CURRENT

SETTING

CPI3CPI4

13-BIT B COUNTE R

1

N COUNTER LATCH

FUNCTION L ATCH

TIMER COUNT ER

CONTROL

TC3 TC2 TC1

14-BIT REFE RENCE COUNTER

R6

R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP

MODE

ENABLE

FASTLOCK

FASTLOCK

F4F5

PD

STATE

POLARITY

CP THREE-

6-BIT A COUNT ER

MUXOUT

CONTROL

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

POWER-

DOWN 1

COUNTER

C2 (0) C1 (0)R1R2R3R4R5

C2 (0)

RESET

C2 (1) C1 (0)F1PD1M1M2M3F3P1P2 CPI1CPI2CPI5CPI6 TC4PD2 F2

CONTROL

BITS

CONTROL

BITS

C1 (1)

CONTROL

BITS

PRESCALER

VALUE

DB21

DB22DB23

P1P2 CPI1CPI2

CURRENT

SETTING

POWER-

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

CPI5

CPI6 T C4PD2

CPI3CPI4

CURRENT

SETTING

1

INITIALIZATION LATCH

TIMER COUNTER

CONTROL

TC3 TC2 TC1

Figure 15. Latch Summary

Rev. A | Page 11 of 20

DOWN 1

RESET

COUNTER

F1PD1M1M2M3

CONTROL

BITS

C2 (1) C1 (1)

06015-021

MODE

ENABLE

FASTLOCK

FASTLOCK

F4F5

PD

STATE

CP THREE-

D

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

B

8

F3

F2

MUXOUT

CONTROL

POLARITY

POWER-

ADF4108

www.BDTIC.com/ADI

REFERENCE COUNTER LATCH MAP

RESERVED

X

X

= DON’T CARE

DB21DB22DB 23

00

TEST

MODE BITS

LOCK

DETECT

PRECISION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ANTI-

BACKLASH

WIDTH

R14 R13 R12 .......... R3 R2 R1

0 0 0 .......... 0 0 1 1

0 0 0 .......... 0 1 0 2

0 0 0 .......... 0 1 1 3

0 0 0 .......... 1 0 0 4

. . . .......... . . . .

. . . .......... . . . .

. . . .......... . . . .

1 1 1 .......... 1 0 0 16380

1 1 1 .......... 1 0 1 16381

1 1 1 .......... 1 1 0 16382

1 1 1 .......... 1 1 1 16383

ABP2 ABP1

0 0 2.9n s
0 1 1.3n s TEST M ODE ONLY . DO NOT USE
1 0 6.0n s
1 1 2.9n s

ANTIBACKLASH PULSE WIDTH

14-BIT REFE RENCE COUNTER

CONTROL

BITS

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP

DIVIDE RATI O

LDP

0

1

BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPE RATION.

TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATIO N.

OPERATIO N

THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST O CCUR BEFORE LOCK DETECT I S SET.
FIVE CONSECUTIVE CYCL ES OF PHASE DELAY LESS T HAN
15ns MUST O CCUR BEFORE LOCK DETECT I S SET.

Figure 16. Reference Counter Latch Map

06015-022

Rev. A | Page 12 of 20

ADF4108

www.BDTIC.com/ADI

AB COUNTER LATCH MAP

RESERVED

DB22DB23

XX

13-BIT B COUNTER

CP GAIN

DB21

G1

DB19

DB20

X = DON’T CARE

B13 B12 B11 B3 B2 B1

0 0 0 .......... 0 0 0

0 0 0 .......... 0 0 1

0 0 0 .......... 0 1 0

0 0 0 .......... 0 1 1

. . . ..... ..... . . .

. . . ..... ..... . . .

. . . ..... ..... . . .

1 1 1 .......... 1 0 0

1 1 1 .......... 1 0 1

1 1 1 .......... 1 1 0

1 1 1 .......... 1 1 1

DB18 DB17

DB16 DB15 DB14

DB13 DB12 DB11

DB10 DB9

B COUNTER DIVIDE RAT IO

NOT ALL OWED

NOT ALLOW ED

NOT ALLOW ED
3
.

.
.
8188
8189
8190

8191

DB8 DB7

A6 A5 .......... A2 A1

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . ..... ..... . . .

. . ..... ..... . . .

. . ..... ..... . . .

1 1 .......... 0 0 60

1 1 .......... 0 1 61

1 1 .......... 1 0 62

1 1 .......... 1 1 63

6-BIT A COUNTER

DB6 DB5

DB4 DB3

CONTROL

DB2 D B1

C2 (0) C1 (1)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

A COUNTER
DIVIDE RATIO

BITS

DB0

F4 (FUNCTION L ATCH)
FASTLOCK ENABLE

00

0

1

11

THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS .

G1
CP GAIN

1

0

OPERATION

CHARGE PUMP CURRENT
SETTING 1 IS PE RMANENTLY USED.

CHARGE PUMP CURRENT
SETTING 2 IS PERMANENTLY USED.

CHARGE PUMP CURRENT
SETTING 1 IS USED.

CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTL OCK
MODE IS USED. SEE F UNCTION
LATCH DESCRIPTIO N.

Figure 17. AB Counter Latch Map

Rev. A | Page 13 of 20

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION
LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR
CONTINUOUSLY ADJACENT VALUES OF (N × F
OUTPUT, N

IS (P2 – P).

MIN

REF

), AT THE

6015-023

ADF4108

www.BDTIC.com/ADI

FUNCTION LATCH MAP

PRESCALER

VALUE

DB22DB23

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 D B12 DB1 1 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB 3 DB2 DB1 DB0

CPI6

CURRENT

SETTING

1

CPI3CPI 4

TC4TC3TC2TC1

00003
00017

001011
001115

010019
010123
011027
011131
100035
100139
101043
101147
110051
110155
111059
111163

TIMER COUNTER

CONTROL

TC3 TC2 TC1

TC4PD2 F2

MODE

FASTLOCK

F5

F4

0
1
1

TIMEOUT
(PFD CYCLES)

STATE

ENABLE

CP THREE-

FASTLOCK

F4

CHARGE PUMP

F3

OUTPUT

0

NORMAL
THREE-STATE

1

F5

FASTLOCK MODE

X

FASTLOCK DISABL ED

0

FASTLOCK MODE 1

1

FASTLOCK MODE 2

MUXOUT

PD

CONTROL

POLARITY

PHASE DETECTOR

F2

POLARITY

NEGATIVE

0

POSITIVE

1

M3 M2 M1

000
001

010
011
100
101

110
111

POWER-

DOWN 1

M1M2M3F3P1P2 CPI1CPI2CPI5

PD1

F1

0
1

COUNTER

F1

CONTRO L

BITS

RESET

C2 (1) C1 (0)

COUNTER
OPERATION

NORMAL
R, A, B CO UNTERS

HELD IN RE SET

OUTPUT

THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)

N DIVIDE R OUTPUT
DV

DD

R DIVIDE R OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUT PUT
DGND

(mA)

CPI6 CPI5 CPI4

CPI3 CPI2 CPI1

0 0 0 1.06 0.625 0. 289
0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0. 870
0 1 1 4.24 2.5 1.160

1 0 0 5.30 3.125 1. 450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2. 020
1 1 1 8.50 5.0 2.320

CE PIN

0
1
101
111

P2 P1

00 8/9
0 1 16/17
1 0 32/33
1 1 64/65

PD2 PD1 MODE

X
X0

PRESCALER VALUE

3kΩ 5. 1kΩ 11kΩ

ASYNCHRONOUS POWER-DOW N

X

NORMAL O PERAT ION
ASYNCHRONOUS POWER-DOW N
SYNCHRONOUS POWER-DO WN

I

CP

Figure 18. Function Latch Map

Rev. A | Page 14 of 20

6015-024

ADF4108

www.BDTIC.com/ADI

INITIALIZATION LATCH MAP

PRESCALER

VALUE

DB22DB23

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB 9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPI6

CURRENT

SETTING

1

CPI3CPI 4

TC4 TC3 TC2 TC1

00003
00017

001011
001115

010019
010123
011027
011131
100035
100139
101043
101147
110051
110155
111059
111163

TIMER COUNTER

CONTROL

TC3 TC2 TC1

TC4PD2 F2

MODE

FASTLOCK

F5

F4

0
1
1

TIMEOUT
(PFD CYCLES)

STATE

ENABLE

CP THREE-

FASTLOCK

F4

CHARGE PUMP

F3

OUTPUT

NORMAL

0

THREE-STATE

1

F5

FASTLOCK MODE

X

FASTLOCK DISABLED

0

FASTLOCK MODE 1

1

FASTLOCK MODE 2

MUXOUT

PD

CONTROL

POLARITY

PHASE DETECTOR

F2

POLARITY

0

NEGATIVE
POSITIVE

1

M3 M2 M1

000
001

010
011
100
101

110
111

POWER-

DOWN 1

M1M2M3F3P1P2 CPI1CPI2CPI5

PD1

F1

0
1

COUNTER

F1

CONTROL

BITS

RESET

C2 (1) C1 (1)

COUNTER
OPERATION

NORMAL
R, A, B COUNTERS

HELD IN RESET

OUTPUT

THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)

N DIVIDE R OUTPUT
DV

DD

R DIVIDE R OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND

(mA)

CPI6 CPI5 CPI4

CPI3 CPI2 CPI1

0 0 0 1.06 0.625 0. 289
0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0. 870
0 1 1 4.24 2.5 1.160

1 0 0 5.30 3.125 1. 450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2. 020
1 1 1 8.50 5.0 2.320

CE PIN

0
1
101
111

P2 P1

00 8/9
01 16/17
10 32/33
11 64/65

PD2 PD1 MODE

X
X0

PRESCALER VALUE

3kΩ 5. 1kΩ 11kΩ

ASYNCHRONOUS POWER-DO WN

X

NORMAL OPERATI ON
ASYNCHRONOUS POWER-DO WN
SYNCHRONOUS POWER-DOWN

I

CP

Figure 19. Initialization Latch Map

Rev. A | Page 15 of 20

6015-025

ADF4108

www.BDTIC.com/ADI

FUNCTION LATCH

The on-chip function latch is programmed with C2 and C1 set
to 1 and 0, respectively. Figure 18 shows the input data format

or programming the function latch.

f

Counter Reset

DB2 (F1) is the counter reset bit. When this bit is 1, the R
counter and the AB counters are reset. For normal operation,
this bit should be 0. Upon powering up, the F1 bit needs to be
disabled (set to 0). Then, the N counter resumes counting in
close alignment with the R counter. (The maximum error is one
prescaler cycle.)

Power-Down

DB3 (PD1) and DB21 (PD2) provide programmable power­down modes. They are enabled by the CE pin.

When the CE pin is low, the device is immediately disabled
re

gardless of the states of PD2 and PD1.

In the programmed asynchronous power-down, the device
p

owers down immediately after latching a 1 into the PD1 bit,

with the condition that PD2 has been loaded with a 0.

In the programmed synchronous power-down, the device

ower-down is gated by the charge pump to prevent unwanted

p
frequency jumps. Once the power-down is enabled by writing a
1 into PD1 (on condition that a 1 has also been loaded to PD2),
the device goes into power-down on the occurrence of the next
charge pump event.

When a power-down is activated (either synchronous or
asy

nchronous mode, including CE pin activated power-down),

the following events occur:

ll active dc current paths are removed.

• A

• The R

• The cha

• The dig

• The RFIN

• T

• The i

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4108. Figure 18 shows the truth table.

Fastlock Enable Bit

DB9 of the function latch is the fastlock enable bit. Fastlock is
enabled only when this bit is 1.

Fastlock Mode Bit

DB10 of the function latch is the fastlock mode bit. When
fastlock is enabled, this bit determines which fastlock mode is

, N, and timeout counters are forced to their load

state conditions.

rge pump is forced into three-state mode.

ital lock detect circuitry is reset.

input is debiased.

he reference input buffer circuitry is disabled.

nput register remains active and capable of loading

and latching data.

used. If the fastlock mode bit is 0, then Fastlock Mode 1 is
selected; and if the fastlock mode bit is 1, then Fastlock Mode 2
is selected.

Fastlock Mode 1

The charge pump current is switched to the contents of Current
Setting 2.

The device enters fastlock by having a 1 written to the CP gain
b

it in the AB counter latch. The device exits fastlock by having a

0 written to the CP gain bit in the AB counter latch.

Fastlock Mode 2

The charge pump current is switched to the contents of Current
Setting 2.

The device enters fastlock by having a 1 written to the CP gain
b

it in the AB counter latch. The device exits fastlock under the
control of the timer counter. After the timeout period
determined by the value in TC4:TC1, the CP gain bit in the AB
counter latch is automatically reset to 0 and the device reverts to
normal mode instead of fastlock. See

riods.

pe

Figure 18 for the timeout

Timer Counter Control

The user has the option of programming two charge pump
currents. The intent is that Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic and in
a state of change (that is, when a new output frequency is
programmed).

The normal sequence of events is as follows:

The user initially decides what the preferred charge pump
c

urrents are going to be. For example, the choice may be 2.5 mA

as Current Setting 1 and 5 mA as Current Setting 2.

At the same time, it must be decided how long the secondary

urrent is to stay active before reverting to the primary current.

c
This is controlled by the timer counter control bits, DB14:DB11
(TC4:TC1) in the function latch. The truth table is given in
Figure 18.

Now, to program a new output frequency, the user simply
p

rograms the AB counter latch with new values for A and B. At
the same time, the CP gain bit can be set to 1, which sets the
charge pump with the value in CPI6:CPI4 for a period of time
determined by TC4:TC1. When this time is up, the charge
pump current reverts to the value set by CPI3:CPI1. At the
same time, the CP gain bit in the AB counter latch is reset to 0
and is now ready for the next time the user wishes to change the
frequency.

Note that there is an enable feature on the timer counter. It is
ena

bled when Fastlock Mode 2 is chosen by setting the fastlock

mode bit (DB10) in the function latch to 1.

Rev. A | Page 16 of 20

ADF4108

www.BDTIC.com/ADI

Charge Pump Currents

CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in

Figure 18.

Prescaler Value

P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 300 MHz. Thus, with
an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but
a value of 8/9 is not valid.

PD Polarity

This bit sets the phase detector polarity bit. See Figure 18.

CP Three-State

This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.

INITIALIZATION LATCH

The initialization latch is programmed when C2 and C1 are set
to 1 and 1. This is essentially the same as the function latch
(programmed when C2, C1 = 1, 0).

However, when the initialization latch is programmed, an

itional internal reset pulse is applied to the R and AB

add
counters. This pulse ensures that the AB counter is at load point
when the AB counter data is latched and the device will begin
counting in close phase alignment.

If the latch is programmed for synchronous power-down (CE

in is high; PD1 bit is high; PD2 bit is low), the internal pulse

p
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse
and so close phase alignment is maintained when counting
resumes.

When the first AB counter data is latched after initialization, the
in

ternal reset pulse is again activated. However, successive AB

counter loads after this do not trigger the internal reset pulse.

Device Programming After Initial Power-Up

After initially powering up the device, there are three ways to
program the device.

Initialization Latch Method

1. Apply V

2. Pr

ogram the initialization latch (11 in 2 LSBs of input

word). Make sure that the F1 bit is programmed to 0.

3. N

ext, do a function latch load (10 in 2 LSBs of the control

word), making sure that the F1 bit is programmed to a 0.

4. Then

5. Then

.

DD

do an R load (00 in 2 LSBs).

do an AB load (01 in 2 LSBs).

When the initialization latch is loaded, the following occurs:

1. The f

2. A

3. L

unction latch contents are loaded.

n internal pulse resets the R, AB, and timeout counters to
load state conditions and also three-states the charge pump.
Note that the prescaler band gap reference and the oscillator
input buffer are unaffected by the internal reset pulse,
allowing close phase alignment when counting resumes.

atching the first AB counter data after the initialization
word activates the same internal reset pulse. Successive AB
loads do not trigger the internal reset pulse unless there is
another initialization.

CE Pin Method

1. Apply VDD.

ing CE low to put the device into power-down. This is an

2. Br

asynchronous power-down in that it happens immediately.

rogram the function latch (10).

3. P

4. P

rogram the R counter latch (00).

5. P

rogram the AB counter latch (01).

ring CE high to take the device out of power-down. The R

6. B

and AB counters will now resume counting in close
alignment.

Note that after CE goes high, a duration of 1 s may be required

r the prescaler band gap voltage and oscillator input buffer

fo
bias to reach steady state.

CE can be used to power the device up and down to check for

nnel activity. The input register does not need to be repro-

cha
grammed each time the device is disabled and enabled as long
as it has been programmed at least once after V
applied.

was initially

DD

Counter Reset Method

1. Apply V

2. Do a f

load 1 to the F1 bit. This enables the counter reset.

3. Do a

4. Do a

5. Do a f

load 0 to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the
i

nitialization method. It offers direct control over the internal
reset. Note that counter reset holds the counters at load point
and three-states the charge pump, but does not trigger
synchronous power-down.

.

DD

unction latch load (10 in 2 LSBs). As part of this,

n R counter load (00 in 2 LSBs).

n AB counter load (01 in 2 LSBs).

unction latch load (10 in 2 LSBs). As part of this,

POWER SUPPLY CONSIDERATIONS

The ADF4108 operates over a power supply range of 3.2 V to

3.6 V. The ADP3300ART-3.3 is a low dropout linear regulator

rom Analog Devices, Inc. It outputs 3.3 V with an accuracy of

f

1.4% and is recommended for use with the ADF4108.

Rev. A | Page 17 of 20

ADF4108

www.BDTIC.com/ADI

INTERFACING

The ADF4108 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE (latch enable) goes high, the 24 bits that have
been clocked into the input register on each rising edge of CLK
are transferred to the appropriate latch. See
t

iming diagram and Tabl e 5 for the latch truth table.

Figure 2 for the

The maximum allowable serial clock rate is 20 MHz. This
m

eans that the maximum update rate possible for the device is
833 kHz or one update every 1.2 µs. This is certainly more than
adequate for systems that have typical lock times in hundreds of
microseconds.

ADuC812 INTERFACE

Figure 20 shows the interface between the ADF4108 and the

ADuC812 MicroConverter®. Because the ADuC812 is based on

n 8051 core, this interface can be used with any 8051-based

a
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4108 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
has been written, the LE input should be brought high to
complete the transfer.

On first applying power to the ADF4108, it needs four writes
(o

ne each to the initialization latch, function latch, R counter
latch, and N counter latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power-

wn (CE input) and to detect lock (MUXOUT configured as

do
lock detect and polled by the port input).

When operating in the mode described, the maximum

OCK rate of the ADuC812 is 4 MHz. This means that

SCL
the maximum rate at which the output frequency can be
changed is 166 kHz.

SCLOCK

MOSI

ADuC812

I/O PORTS

Figure 20. ADuC812 to ADF4108 Interface

ADSP-21xx INTERFACE

Figure 21 shows the interface between the ADF4108 and the
ADSP-21xx digital signal processor. The ADF4108 needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the autobuffered mode, and then write to the transmit
register of the DSP. This last operation initiates the autobuffer
transfer.

SCLOCK

MOSI

ADSP-21x x

TFS

I/O FLAGS

Figure 21. ADSP-21xx to ADF4108 Interface

CLK

DATA

LE

ADF4108

CE

MUXOUT
(LOCK DETECT )

CLK

DATA

LE

ADF4108

CE

MUXOUT
(LOCK DETECT )

6015-026

6015-027

Rev. A | Page 18 of 20

ADF4108

www.BDTIC.com/ADI

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The lands on the chip scale package (CP-20-1) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized. The
bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least
as la

rge as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This ensures that
shorting is avoided.

Thermal vias can be used on the printed circuit board thermal

ad to improve thermal performance of the package. If vias are

p
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and

0.33 mm and the via barrel should be plated with 1 oz. copper
to plug the via.

The user should connect the printed circuit board thermal pad
to

AGND.

Rev. A | Page 19 of 20

ADF4108

C

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.08

0.50

BSC

0.75

0.60

0.50

0.60 MAX

15

11

16

EXPOSED

PAD

(BOTTOM VIEW)

10

1

P

N

I

R

C

A

O

T

N

I

D

2.25

2.10 SQ

1.95

0.25 MIN

I

082207-B

20

1

5

6

4.00

INDI

ATO R

1.00

0.85

0.80

SEATING

PLANE

PIN 1

12° MAX

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT

BCS SQ

TO

0.60 MAX

3.75

0.05 MAX

0.02 NOM
COPLANARITY

0.20 REF

JEDEC STANDARDS MO-220-VGGD-1

Figure 22. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm x 4 mm Body, Very Thin Quad

(CP-20-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADF4108BCPZ
ADF4108BCPZ-RL
ADF4108BCPZ-RL7
EVAL-ADF4108EBZ1

1

Z = RoHS Compliant Part.

1

1

1

1

−40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1

−40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1

−40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1
Evaluation Board

©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06015-0-12/07(A)

Rev. A | Page 20 of 20