Datasheet ADF4107 Datasheet (Analog Devices)

PLL Frequency Synthesizer

FEATURES

7.0 GHz bandwidth

2.7 V to 3.3 V power supply
Separate charge pump supply (V

voltage in 3 V systems

Programmable dual-modulus prescaler

8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulsewidth
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode

APPLICATIONS

Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio

AV

) allows extended tuning

P

DV

DD

DD

GENERAL DESCRIPTION

The ADF4107 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low-noise digital PFD (phase frequency detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual-modulus prescaler (P/P + 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual­modulus prescaler (P/P + 1), implement an N divider
(N = BP + A). In addition, the 14-bit reference counter
(R counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (phase-locked loop) can be implemented
if the synthesizer is used with an external loop filter and VCO
(voltage controlled oscillator). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.

FUNCTIONAL BLOCK DIAGRAM

V

P

CPGND

REFERENCE

ADF4107

R

SET

REF

IN

CLK

DATA

LE

RFINA
RF

B

IN

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

24-BIT INPUT

REGISTER

SD

OUT

FUNCTION

PRESCALER

FROM

LATCH

P/P + 1

CE

22

N = BP + A

AGND

14-BIT

R COUNTER

14

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

13-BIT

B COUNTER

LOAD

LOAD

A COUNTER

DGND

13

6-BIT

6

19

Figure 1.

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

SETTING 1

CPI3 CPI2 CPI1

AV

DD

SD

OUT

CURRENT

CHARGE

MUX

M3 M2 M1

PUMP

CURRENT

SETTING 2

CPI6 CPI5 CPI4

HIGH Z

CP

MUXOUT

ADF4107

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADF4107

TABLE OF CONTENTS

ADF4107—Specifications................................................................ 3

Latch Summary........................................................................... 11

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 5

Pin Configurations and Functional Descriptions........................ 6

Typical Performance Characteristics ............................................. 7

Functional Description.................................................................... 9

Reference Input Stage................................................................... 9

RF Input Stage............................................................................... 9

Prescaler (P/P + 1)........................................................................ 9

A and B Counters ......................................................................... 9

R Counter ...................................................................................... 9

Phase Frequency Detector and Charge Pump........................ 10

MUXOUT and Lock Detect...................................................... 10

Input Shift Register..................................................................... 10

Reference Counter Latch Map.................................................. 12

AB Counter Latch Map ............................................................. 13

Function Latch Map................................................................... 14

Initialization Latch Map ............................................................ 15

Function Latch............................................................................ 16

Initialization Latch..................................................................... 17

Applications..................................................................................... 18

Local Oscillator for LMDS Base Station Transmitter............ 18

Interfacing ................................................................................... 19

PCB Design Guidelines for Chip Scale Package .................... 19

Outline Dimensions....................................................................... 20

ESD Caution.................................................................................... 20

Ordering Guide............................................................................... 20

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADF4107

ADF4107—SPECIFICATIONS

Table 1. (AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R

to T

T

MAX

Parameter B

, unless otherwise noted.)

MIN

Version

1

B Chips
(Typ)

2

Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RFIN)3 1.0/7.0 1.0/7.0 GHz min/max See Figure 18 for input circuit.

RF Input Sensitivity –5/+5 –5/+5 dBm min/max

Maximum Allowable Prescaler

Output Frequency

4

300 300 MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, use dc-coupled square wave (0 to VDD).

REFIN Input Sensitivity5 0.8/VDD 0.8/VDD V p-p min/max

AC-coupled; when dc-coupled, 0 to V

compatible).
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 µA max

PHASE DETECTOR

Phase Detector Frequency6 104 104 MHz max

CHARGE PUMP Programmable; see Figure 25.

ICP Sink/Source

High Value 5 5 mA typ With R
Low Value 625 625 µA typ
Absolute Accuracy 2.5 2.5 % typ With R
R

Range 3.0/11 3.0/11 kΩ typ See Figure 25.

SET

ICP Three-State Leakage 1 1 nA typ
Sink and Source Current

2 2 % typ 0.5 V ≤ V

Matching

ICP vs. VCP 1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP – 0.5 V
ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 1.4 V min
VIL, Input Low Voltage 0.6 0.6 V max
I

, I

, Input Current ±1 ±1 µA max

INH

INL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 1.4 V min Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V.
VOH, Output High Voltage VDD – 0.4 VDD – 0.4 V min CMOS output chosen.
IOH 100 100 µA max
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

POWER SUPPLIES

AVDD 2.7/3.3 2.7/3.3 V min/V max
DVDD AVDD AVDD
VP AVDD/5.5 AVDD/5.5 V min/V max AVDD ≤ VP ≤5.5V

7

I

(AIDD + DIDD) 17 15 mA max 15 mA typ

DD

IP 0.4 0.4 mA max TA = 25°C
Power-Down Mode8 (AIDD + DIDD) 10 10 µA typ

= 5.1 kΩ, dBm referred to 50 Ω, TA =

SET

DD

= 5.1 kΩ

SET

= 5.1 kΩ

SET

≤ VP – 0.5 V

CP

, max (CMOS

Rev. 0 | Page 3 of 20

ADF4107

2

Parameter B

Version

1

B Chips
(Typ)

Unit Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4107 Phase Noise Floor9 –174 –174 dBc/Hz typ @ 25 kHz PFD Frequency
–166 –166 dBc/Hz typ @ 200 kHz PFD Frequency
–159 –159 dBc/Hz typ @ 1 MHz PFD Frequency
Phase Noise Performance10 @ VCO Output

900 MHz Output11 –93 –93 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD Frequency
6400 MHz Output12 –76 –76 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD Frequency
6400 MHz Output13 –83 –83 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD Frequency

Spurious Signals

900 MHz Output11 –90/–92 –90/–92 dBc typ @ 200 kHz/400kHz and 200 kHz PFD Frequency
6400 MHz Output12 –65/–70 –65/–70 dBc typ @ 200 kHz/400kHz and 200 kHz PFD Frequency
6400 MHz Output13 –70/–75 –70/–75 dBc typ @ 1 MHz/2MHz and 1 MHz PFD Frequency

1

Operating temperature range (B Version) is –40°C to +85°C.

2

The B Chip specifications are given as typical values.

3

Use a square wave for lower frequencies, below the minimum stated.

4

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

5

AVDD = DVDD = 3 V.

6

Guaranteed by design. Sample tested to ensure compliance.

7

TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 7.0 GHz.

8

TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz.

9

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

10

The phase noise is measured with the EVAL-ADF4107EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the

synthesizer (f

11

f

= 10 MHz; f

REFIN

12

f

= 10 MHz; f

REFIN

13

f

= 10 MHz; f

REFIN

= 10 MHz @ 0 dBm).

REFOUT

= 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.

PFD

= 200 kHz; Offset Frequency = 1 kHz; fRF = 6400 MHz; N = 32000; Loop B/W = 20 kHz.

PFD

= 1 MHz; Offset Frequency = 1 kHz; fRF = 6400 MHz; N = 6400; Loop B/W = 100 kHz.

PFD

Rev. 0 | Page 4 of 20

ADF4107

TIMING CHARACTERISTICS

Table 2. (AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R

= T

to T

T

A

MAX

, unless otherwise noted.) 1

MIN

Parameter Limit2 (B Version) Unit Test Conditions/Comments

t1 10 ns min DATA to CLOCK Setup Time
t2 10 ns min DATA to CLOCK Hold Time
t3 25 ns min CLOCK High Duration
t4 25 ns min CLOCK Low Duration
t5 10 ns min CLOCK to LE Setup Time
t6 20 ns min LE Pulsewidth

1

Guaranteed by design but not production tested.

2

Operating temperature range (B Version) is –40°C to +85°C.

CLOCK

DATA

LE

DB23 (MSB)

LE

t

t

1

2

DB22

Figure 2. Timing Diagram

DB2

t

3

t

4

DB1 (CONTRO L

BIT C2)

= 5.1 kΩ, dBm referred to 50 Ω,

SET

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

ABSOLUTE MAXIMUM RATINGS

Table 3. (TA = 25°C, unless otherwise noted.)

Parameter Rating

AVDD to GND1 –0.3 V to +3.6 V
AVDD to DVDD –0.3 V to +0.3 V
VP to GND –0.3 V to +5.8 V
VP to AVDD –0.3 V to +5.8 V
Digital I/O Voltage to GND –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND –0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) –40°C to +85°C

Storage Temperature Range –65°C to +125°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 150.4°C/W
CSP θJA Thermal Impedance 122°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

Transistor Count

CMOS 6425
Bipolar 303

1

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

Rev. 0 | Page 5 of 20

ADF4107

T

T

PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS

TSSOP

R

SET

CP

CPGND

AGND

RFINB

RF

IN

AV

REF

A

DD

IN

1

2

3

4

ADF4107

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

V

P

DV

DD

MUXOU

LE

DATA

CLK

CE

DGND

CPGND 1

AGND 2
AGND 3
RFINB

A

RF

IN

4
5

Figure 3. ADF4107 TSSOP (Top View)

Figure 4. ADF4107 Chip Scale Package

Table 4. Pin Functional Descriptions

Mnemonic Function

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage
potential at the R

R

SET

I

MAXCP

so, with R

SET

pin is 0.66 V. The relationship between ICP and R

SET

5.25

=

= 5.1 kΩ, I

R

SE

= 5 mA.

CP MAX

is

SET

CP Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives the external VCO.
CPGND Charge Pump Ground. This is the ground return path for the charge pump.
AGND Analog Ground. This is the ground return path of the prescaler.

RFINB

Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor,
typically 100 pF. See Figure 18.

RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.

AVDD

REFIN

Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should
be placed as close as possible to this pin. AV

Reference Input. This is a CMOS input with a nominal threshold of V

must be the same value as DVDD.

DD

/2 and a dc equivalent input resistance of 100 kΩ. See

DD

Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.

DGND Digital Ground.

CE

CLK

DATA

LE

MUXOUT

DVDD

VP

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking
the pin high will power up the device, depending on the status of the power-down bit, F2.

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift
register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance
CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the
latch being selected using the control bits.

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed
externally.

Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed
as close as possible to this pin. DV

must be the same value as AVDD.

DD

Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5
V and used to drive a VCO with a tuning range of up to 5 V.

CSP

(Chip Scale Package)

DD

DD

SETVP

DV

R
191817

PIN 1
INDICATOR

DV
16

20 CP

ADF4107

TOP VIEW

6

7

8

IN

DD

DD

AV

AV

REF

DGND 9

DGND 10

15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE

Rev. 0 | Page 6 of 20

ADF4107

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Parameter Data for the RF Input

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz 1MHz

FREQUENCY OFFSET FROM 900MHz CARRIER

Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz)

10dB/DIV

= –40dBc/Hz

R

L

RMS NOISE = 0.36

o

0

–5

–10

–15

–20

RF INPUT POWER – dBm

–25

–30

012 4 635

TA = –40oC

RF INPUT FREQUENCY – GHz

TA = +85oC

TA = +25oC

Figure 6. Input Sensitivity

0

REF LEVEL = –14.3dBm

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

–2kHz

FREQUENCY

= 3V, VP = 5V

V

DD

I

= 5mA

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10

–93.0dBc/Hz

Figure 7. Phase Noise (900 MHz, 200 kHz, 20 kHz)

VDD = 3V

= 3V

V

P

+2kHz900MHz–1kHz +1kHz

7

0

REF LEVEL = –14.0dBm

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

–400kHz +400kHz900MHz–200kHz +200kHz

FREQUENCY

= 3V, VP = 5V

V

DD

= 5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30

–91.0dBc/Hz

Figure 9. Reference Spurs (900 MHz, 200 kHz, 20 kHz)

0

REF LEVEL = –10dBm

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

–2kHz +2kHz6400MHz–1kHz +1kHz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10

FREQUENCY

Figure 10. Phase Noise (6.4 GHz, 1 MHz, 100 kHz)

–83.0dBc/Hz

Rev. 0 | Page 7 of 20

ADF4107

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz 1MHz

FREQUENCY OFFSET FROM 6400MHz CARRIER

Figure 11. Integrated Phase Noise (6.4 GHz, 1 MHz, 100 kHz)

10dB/DIV
R

= –40dBc/Hz

L

RMS NOISE = 1.85

–5

o

–15

–25

–35

–45

–55

–65

–75

–85

FIRST REFERENCE SPUR – dBc

–95

–105

012 34

Figure 14. Reference Spurs vs. V

TUNING VOLTAGE – V

(6.4 GHz, 1 MHz, 100 kHz)

TUNE

VDD = 3V

= 5V

V

P

5

0

REF LEVEL = –10dBm

–10

–20

–30

–40

–50

–66.0dBc/Hz

–60

–70

OUTPUT POWER – dB

–80

–90

–100

–2MHz +2MHz6400MHz–1MHz +1MHz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1

FREQUENCY

–65.0dBc/Hz

Figure 12. Reference Spurs (6.4 GHz, 1 MHz, 100 kHz)

–60

–70

–80

PHASE NOISE – dBc/Hz

–90

–100

–40 100–20 0 20 40 60 80

TEMPERATURE –

o

C

VDD = 3V

= 3V

V

P

Figure 13. Phase Noise (6.4 GHz, 1 MHz, 100 kHz) vs. Temperature

–120

–130

–140

–150

–160

PHASE NOISE – dBc/Hz

–170

–180

10k 100M100k 1M 10M

PHASE DETECTOR FREQUENCY – Hz

VDD = 3V

= 5V

V

P

Figure 15. Phase Noise (referred to CP output) vs. PFD Frequency

6

5

4

3

2

1

0

– mA

CP

I

–1

–2

–3

–4

–5

–6

0 2.00.5 1.0 1.5

V

CP

– V

VP = 5V
I

SETTLING = 5mA

CP

4.02.5 3.0 3.5 5.04.5

Figure 16. Charge Pump Output Characteristics

Rev. 0 | Page 8 of 20

ADF4107

R

FUNCTIONAL DESCRIPTION

Reference Input Stage

The Reference Input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF

IN

pin

on power-down.

POWER-DOWN

CONTROL

100kΩ

NC

REF

SW2

IN

NC

SW1

SW3

NO

Figure 17. Reference Input Stage

BUFFER

TO R COUNTER

RF Input Stage

The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.

synchronous 4/5 core. A minimum divide ratio is possible for
fully contiguous output frequencies. This minimum is

2

determined by P, the prescaler value, and is given by: (P

– P).

A and B Counters

The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is as follows:

f

f

VCO

[]

()

VCO

Output frequency of external voltage controlled

oscillator (VCO).

P

Preset modulus of dual-modulus prescaler

(8/9, 16/17, etc.).

REFIN

×+×=

ABPf

RFINA

RF

IN

BIAS

GENERATOR

B

Figure 18. RF Input Stage

500Ω

1.6V

500Ω

AV

DD

AGND

Prescaler (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B
counters. The prescaler is programmable. It can be set in
software to 8/9, 16/17, 32/33, or 64/65. It is based on a

B

Preset divide ratio of binary 13-bit counter

(3 to 8191).

A

Preset divide ratio of binary 6-bit swallow counter

(0 to 63).

f

External reference frequency oscillator.

REFIN

N = BP + A

13-BIT B

COUNTER

FROM RF

INPUT STAGE

PRESCALER

P/P + 1

MODULUS

CONTROL

N DIVIDER

LOAD

LOAD

6-BIT A

COUNTER

TO PFD

Figure 19. A and B Counters

R Counter

The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.

Rev. 0 | Page 9 of 20

ADF4107

Phase Frequency Detector and Charge Pump

The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 20 is a simplified schematic. The PFD includes a
programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse. See Figure 23.

V

P

CHARGE

UP

HI

R DIVIDER

HID1D2

N DIVIDER

Figure 20. PFD Simplified Schematic and Timing (in Lock)

Q1

U1

CLR1

PROGRAMMABLE

ABP2

CLR2

DOWN

Q2

U2

DELAY

U3

ABP1

MUXOUT and Lock Detect

The output multiplexer on the ADF4107 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 25 shows the full truth table. Figure 21 shows the
MUXOUT section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.

Digital lock detect is active high. When the lock detect precision
(LDP) bit in the R counter latch is set to 0, digital lock detect is
set high when the phase error on three consecutive phase
detector (PD) cycles is less than 15 ns. With LDP set to 1, five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than
25 ns is detected on any subsequent PD cycle.

PUMP

CP

CPGND

The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, this output will be high with
narrow, low-going puls es.

DV

DD

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

MUX

Figure 21. MUXOUT Circuit

CONTROL

DGND

MUXOUT

Input Shift Register

The ADF4107 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5. Figure 22 shows a summary of
how the latches are programmed.

Table 5. C2, C1 Truth Table

Control Bits
C2 C1

Data Latch

0 0 R Counter
0 1 N Counter (A and B)
1 0 Function Latch (Including Prescaler)
1 1 Initialization Latch

Rev. 0 | Page 10 of 20

ADF4107

Latch Summary

REFERENCE COUNTER LATCH

RESERVED

00X

RESERVED

PRESCALER

VALUE

DB22DB23

TEST

MODE BITS

LOCK

DETECT

PRECISION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

DB21DB22DB23

G1XX

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ANTI-

BACKLASH

WIDTH

CURRENT

SETTING

CPI3CPI4

13-BIT B COUNTER

1

N COUNTER LATCH

FUNCTION LATCH

TIMER COUNTER

CONTROL

TC3 TC2 TC1

14-BIT REFERENCE COUNTER

R6

R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MODE

FASTLOCK

FASTLOCK

F4F5

ENABLE

PD

STATE

POLARITY

CP THREE-

6-BIT A COUNTER

MUXOUT

CONTROL

POWER-

DOWN 1

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

COUNTER

C2 (0) C1 (0)R1R2R3R4R5

C2 (0)

RESET

C2 (1) C1 (0)F1PD1M1M2M3F3P1P2 CPI1CPI2CPI5CPI6 TC4PD2 F2

CONTROL

BITS

CONTROL

BITS

C1 (1)

CONTROL

BITS

PRESCALER

VALUE

DB21

DB22DB23

P1P2 CPI1CPI2

CURRENT

SETTING

POWER-

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

CPI5

CPI6 TC4PD2

CPI3CPI4

CURRENT

SETTING

1

INITIALIZATION LATCH

TIMER COUNTER

CONTROL

TC3 TC2 TC1

FASTLOCK

Figure 22. Latch Summary

Rev. 0 | Page 11 of 20

MODE

F4F5

CP THREE-

ENABLE

FASTLOCK

B

8

D

F3

POLARITY

MUXOUT

CONTROL

POWER-

PD

STATE

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

F2

DOWN 1

COUNTER

F1PD1M1M2M3

CONTROL

RESET

C2 (1) C1 (1)

BITS

ADF4107

X

Reference Counter Latch Map

RESERVED

X

= DON’T CARE

DB21DB22DB23

00

TEST

MODE BITS

LOCK

DETECT

PRECISION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ANTI-

BACKLASH

WIDTH

ABP2 ABP1
0 0 2.9ns
0 1 1.3ns
1 0 6.0ns
1 1 2.9ns

ANTIBACKLASH PULSEWIDTH

14-BIT REFERENCE COUNTER

R14 R13 R12 .......... R3 R2 R1

0 0 0 .......... 0 0 1 1

0 0 0 .......... 0 1 0 2

0 0 0 .......... 0 1 1 3

0 0 0 .......... 1 0 0 4

. . . .......... . . . .

. . . .......... . . . .

. . . .......... . . . .

1 1 1 .......... 1 0 0 16380

1 1 1 .......... 1 0 1 16381

1 1 1 .......... 1 1 0 16382

1 1 1 .......... 1 1 1 16383

CONTROL

BITS

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP

DIVIDE RATIO

BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.

TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.

LDP

OPERATION

0

THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

1

FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

Figure 23. Reference Counter Latch Map

Rev. 0 | Page 12 of 20

ADF4107

AB Counter Latch Map

RESERVED

DB22DB23

XX

13-BIT B COUNTER

CP GAIN

DB21

G1

DB19

DB20

X = DON’T CARE

B13 B12 B11 B3 B2 B1

0 0 0 .......... 0 0 0

0 0 0 .......... 0 0 1

0 0 0 .......... 0 1 0

0 0 0 .......... 0 1 1

. . . .......... . . .

. . . .......... . . .

. . . .......... . . .

1 1 1 .......... 1 0 0

1 1 1 .......... 1 0 1

1 1 1 .......... 1 1 0

1 1 1 .......... 1 1 1

DB18 DB17

DB16 DB15 DB14

DB13 DB12 DB11

DB10 DB9

B COUNTER DIVIDE RATIO

NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
.

.
.
8188
8189
8190

8191

DB8 DB7

A6 A5 .......... A2 A1

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

. . .......... . . .

. . .......... . . .

1 1 .......... 0 0 60

1 1 .......... 0 1 61

1 1 .......... 1 0 62

1 1 .......... 1 1 63

6-BIT A COUNTER

DB6 DB5

DB4 DB3

CONTROL

DB2 DB1

C2 (0) C1 (1)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

A COUNTER
DIVIDE RATIO

BITS

DB0

F4 (FUNCTION LATCH)
FASTLOCK ENABLE

00

0

1

11

THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.

OPERATIONCP GAIN

CHARGE PUMP CURRENT

1

0

SETTING 1 IS PERMANENTLY USED.

CHARGE PUMP CURRENT
SETTING 2 IS PERMANENTLY USED.

CHARGE PUMP CURRENT
SETTING 1 IS USED.

CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION
LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR
CONTINUOUSLY ADJACENT VALUES OF (N
OUTPUT, N

IS (P2– P).

MIN

×

F

), AT THE

REF

Figure 24. AB Counter Latch Map

Rev. 0 | Page 13 of 20

ADF4107

Function Latch Map

PRESCALER

VALUE

DB22DB23

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPI6

CURRENT

SETTING

1

CPI3CPI4

TC4 TC3 TC2 TC1

00003
00017
001011
001115
010019
010123
011027
011131
100035
100139
101043
101147
110051
110155
111059
111163

TIMER COUNTER

CONTROL

TC3 TC2 TC1

TC4PD2 F2

MODE

FASTLOCK

F5

F4

0
1
1

TIMEOUT
(PFD CYCLES)

STATE

ENABLE

CP THREE-

FASTLOCK

F4

CHARGE PUMP

F3

OUTPUT

NORMAL

0

THREE-STATE

1

F5

FASTLOCK MODE

X

FASTLOCK DISABLED

0

FASTLOCK MODE 1

1

FASTLOCK MODE 2

MUXOUT

PD

CONTROL

POLARITY

M2M3F3P1P2 CPI1CPI2CPI5

PHASE DETECTOR

F2

POLARITY

NEGATIVE

0

POSITIVE

1

M3 M2 M1

000
001

010
011
100
101

110
111

M1

POWER-

PD1

DOWN 1

F1

0
1

COUNTER

F1

CONTROL

BITS

RESET

C2 (1) C1 (0)

COUNTER
OPERATION

NORMAL
R, A, B COUNTERS

HELD IN RESET

OUTPUT

THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)

N DIVIDER OUTPUT
DV

DD

R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN

LOCK DETECT
SERIAL DATA OUTPUT
DGND

CPI6 CPI5 CP14

CPI3 CPI2 CPI1

0 0 0 1.06 0.625 0.289
0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0.870
0 1 1 4.24 2.5 1.160
1 0 0 5.30 3.125 1.450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2.020
1 1 1 8.50 5.0 2.320

CE PIN

0
1
101
111

P2 P1

0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65

PRESCALER VALUE

PD2 PD1 MODE

X
X0

ASYNCHRONOUS POWER-DOWN

X

NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN

(mA)

I

3kΩ 5.1kΩ 11kΩ

CP

Figure 25. Function Latch Map

Rev. 0 | Page 14 of 20

ADF4107

Initialization Latch Map

PRESCALER

VALUE

DB22DB23

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPI6

CURRENT

SETTING

1

CPI3CPI4

TC4 TC3 TC2 TC1

00003
00017
001011
001115
010019
010123
011027
011131
100035
100139
101043
101147
110051
110155
111059
111163

TIMER COUNTER

CONTROL

TC3 TC2 TC1

TC4PD2 F2

MODE

FASTLOCK

F5

F4

0
1
1

TIMEOUT
(PFD CYCLES)

STATE

ENABLE

CP THREE-

FASTLOCK

F4

CHARGE PUMP

F3

OUTPUT

NORMAL

0

THREE-STATE

1

F5

FASTLOCK MODE

X

FASTLOCK DISABLED

0

FASTLOCK MODE 1

1

FASTLOCK MODE 2

MUXOUT

PD

CONTROL

POLARITY

M2M3F3P1P2 CPI1CPI2CPI5

PHASE DETECTOR

F2

POLARITY

NEGATIVE

0

POSITIVE

1

M3 M2 M1

000
001

010
011
100
101

110
111

M1

POWER-

PD1

DOWN 1

F1

0
1

COUNTER

F1

CONTROL

BITS

RESET

C2 (1) C1 (1)

COUNTER
OPERATION

NORMAL
R, A, B COUNTERS

HELD IN RESET

OUTPUT

THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)

N DIVIDER OUTPUT
DV

DD

R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN

LOCK DETECT
SERIAL DATA OUTPUT
DGND

CPI6 CPI5 CP14

CPI3 CPI2 CPI1

0 0 0 1.06 0.625 0.289
0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0.870
0 1 1 4.24 2.5 1.160
1 0 0 5.30 3.125 1.450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2.020
1 1 1 8.50 5.0 2.320

CE PIN

0
1
101
111

P2 P1

0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65

PRESCALER VALUE

PD2 PD1 MODE

X
X0

ASYNCHRONOUS POWER-DOWN

X

NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN

(mA)

I

3kΩ 5.1kΩ 11kΩ

CP

Figure 26. Initialization Latch Map

Rev. 0 | Page 15 of 20

ADF4107

Function Latch

The on-chip function latch is programmed with C2 and C1 set
to 1 and 0, respectively. Figure 25 shows the input data format
for programming the function latch.

Counter Reset

DB2 (F1) is the counter reset bit. When this bit is 1, the R
counter and the AB counters are reset. For normal operation,
this bit should be 0. Upon powering up, the F1 bit needs to be
disabled (s et to 0) . Then, the N counter resumes counting in
close alignment with the R counter. (The maximum error is one
prescaler cycle).

Fastlock Mode Bit

DB10 of the function latch is the fastlock mode bit. When
fastlock is enabled, this bit determines which fastlock mode is
used. If the fastlock mode bit is 0, then Fastlock Mode 1 is
selected; and if the fastlock mode bit is 1, then Fastlock Mode 2
is selected.

Fastlock Mode 1

The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain
bit in the AB counter latch. The device exits fastlock by having
a 0 written to the CP gain bit in the AB counter latch.

Power-Down

DB3 (PD1) and DB21 (PD2) provide programmable power­down modes. They are enabled by the CE pin.

When the CE pin is low, the device is immediately disabled
regardless of the states of PD2 and PD1.

In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into the PD1 bit,
with the condition that PD2 has been loaded with a 0.

In the programmed synchronous power-down, the device
power-down is gated by the charge pump to prevent unwanted
frequency jumps. Once the power-down is enabled by writing
a 1 into PD1 (on condition that a 1 has also been loaded to
PD2), then the device will go into power-down on the
occurrence of the next charge pump event.

When a power-down is activated (either synchronous or
asynchronous mode, including CE pin activated power-down),
the following events occur:

• All active dc current paths are removed.

• The R, N, and timeout counters are forced to their load state

conditions.

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry is reset.

• The RF

• The reference input buffer circuitry is disabled.

• The input register remains active and capable of loading and

latching data.

input is debiased.

IN

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4107. Figure 25 shows the truth table.

Fastlock Enable B t

DB9 of the function latch is the fastlock enable bit. Fastlock is
enabled only when this bit is 1.

i

Fastlock Mode 2

The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain
bit in the AB counter latch. The device exits fastlock under the
control of the timer counter. After the timeout period
determined by the value in TC4–TC1, the CP gain bit in the AB
counter latch is automatically reset to 0 and the device reverts to
normal mode instead of fastlock. See Figure 25 for the timeout
periods.

i

T mer Counter Control

The user has the option of programming two charge pump
currents. The intent is that Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic and in
a state of change (i.e., when a new output frequency is
programmed).

The normal sequence of events is as follows:

The user initially decides what the preferred charge pump
currents are going to be. For example, the choice may be 2.5 mA
as Current Setting 1 and 5 mA as Current Setting 2.

At the same time it must be decided how long the secondary
current is to stay active before reverting to the primary current.
This is controlled by the timer counter control bits, DB14–DB11
(TC4–TC1) in the function latch. The truth table is given in
Figure 25.

Now, to program a new output frequency, the user simply
programs the AB counter latch with new values for A and B. At
the same time, the CP gain bit can be set to 1, which sets the
charge pump with the value in CPI6–CPI4 for a period of time
determined by TC4–TC1. When this time is up, the charge
pump current reverts to the value set by CPI3–CPI1. At the
same time the CP gain bit in the AB counter latch is reset to 0
and is now ready for the next time that the user wishes to
change the frequency.

Rev. 0 | Page 16 of 20

ADF4107

Note that there is an enable feature on the timer counter. It is
enabled when Fastlock Mode 2 is chosen by setting the fastlock
mode bit (DB10) in the function latch to 1.

Charge Pump Currents

CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Figure 25.

Prescaler Value

P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 300 MHz. Thus, with
an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but
a value of 8/9 is not valid.

PD Polarity

This bit sets the phase detector polarity bit. See Figure 25.

CP Three-State

This bit controls the CP output pin. With the bit set high, the CP
output is put into three-state. With the bit set low, the CP output
is enabled.

Initialization Latch

The initialization latch is programmed when C2 and C1 are set
to 1 and 1. This is essentially the same as the function latch
(programmed when C2, C1 = 1, 0).

However, when the initialization latch is programmed an
additional internal reset pulse is applied to the R and AB
counters. This pulse ensures that the AB counter is at load point
when the AB counter data is latched and the device will begin
counting in close phase alignment.

If the latch is programmed for synchronous power-down (CE
pin is high; PD1 bit is high; PD2 bit is low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse
and so close phase alignment is maintained when counting
resumes.

When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.

Device Programming after Initial Power-Up

After initially powering up the device, there are three ways to
program the device.

Initialization Latch Method

Apply V
Program the initialization latch (11 in two LSBs of input word).
Make sure that the F1 bit is programmed to 0.

Next, do a function latch load (10 in two LSBs of the control
word), making sure that the F1 bit is programmed to a 0.
Then do an R load (00 in two LSBs).
Then do an AB load (01 in two LSBs).
When the Initialization Latch is loaded, the following occurs:

1. The function latch contents are loaded.

2. An internal pulse resets the R, AB, and timeout counters to

3. Latching the first AB counter data after the initialization

CE Pin Method

Apply V

Bring CE low to put the device into power-down. This is an
asychronous power-down in that it happens immediately.
Program the function latch (10).
Program the R counter latch (00).
Program the AB counter latch (01).

Bring CE high to take the device out of power-down. The R and
AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach steady state.

CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after V
initially applied.

Counter Reset Method

Apply VDD.

Do a Function Latch Load (10 in two LSBs). As part of this,
load 1 to the F1 bit. This enables the counter reset.
Do an R counter load (00 in two LSBs).
Do an AB counter load (01 in two LSBs).
Do a Function latch load (10 in two LSBs). As part of this,
load 0 to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the
initialization method. It offers direct control over the internal
reset. Note that counter reset holds the counters at load point
and three-states the charge pump, but does not trigger
synchronous power-down.

.

DD

load-state conditions and also three-states the charge
pump. Note that the prescaler band gap reference and the
oscillator input buffer are unaffected by the internal reset
pulse, allowing close phase alignment when counting
resumes.

word will activate the same internal reset pulse. Successive
AB loads will not trigger the internal reset pulse unless
there is another initialization.

.

DD

was

DD

Rev. 0 | Page 17 of 20

ADF4107

APPLICATIONS

Local Oscillator for LMDS Base Station Transmitter

Figure 27 below shows the ADF4107 being used with a VCO to
produce the LO for an LMDS base station.

The reference input signal is applied to the circuit at FREF
and, in this case, is terminated in 50 Ω. A typical base station
system would have either a TCXO or an OCXO driving the
reference input without any 50 Ω termination.

To have a channel spacing of 1 MHz at the output, the 10 MHz
reference input must be divided by 10, using the on-chip
reference divider of the ADF4107.

The charge pump output of the ADF4107 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for the
system would be 45°.

V

DD

IN

V

P

Other PLL system specifications are:

= 5.0 mA

K

D

KV = 80 MHz/V
Loop Bandwidth = 70 kHz

= 1 MHz

F

PFD

N = 6300
Extra Reference Spur Attenuation = 10 dB

All of these specifications are needed and used to derive the
loop filter component values shown in Figure 27.

Figure 27 gives a typical phase noise performance of

−83 dBc/Hz at 1 kHz offset from the carrier. Spurs are better
than −70 dBc.

The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the RF
terminal of the synthesizer.

In a PLL system, it is important to know when the system is in
lock. In Figure 27, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be
programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock detect signal.

RF

OUT

IN

100pF

18Ω

18Ω

18Ω

FREF

7

AV

1000pF

IN

1000pF

51Ω

8

REFIN

DDDVDD

16

15

CP

V

P

2

100pF

1.7kΩ

7.5kΩ

47pF

14

V

2

CC

V956ME01

100pF

10

ADF4107

1, 3, 4, 5, 7, 8,
9, 11, 12, 13

µF/10pF) ON AV

DD

, DVDD,

SPI COMPATIBLE SERIAL BUS

5.1kΩ

1

CE

CLK

DATA

LE

R

SET

CPGND

MUXOUT

AGND

43

RFINA

RF

DGND

9

820pF

LOCK

14

DETECT

100pF

6

B

IN

5

100pF

51Ω

NOTE
DECOUPLING CAPACITORS (0.1

OF THE ADF4107 AND ON VCC OF THE V956ME01 HAVE

V

P

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

Figure 27. 6.3 GHz Local Oscillator Using the ADF4107

Rev. 0 | Page 18 of 20

ADF4107

Interfacing

The ADF4107 has a simple SPI™ compatible serial interface for
writ ing to the device. CLK, DATA, and LE control the data
transfer. When LE (Latch Enable) goes high, the 24 bits that
have been clocked into the input register on each rising edge of
CLK will get transferred to the appropriate latch. See Figure 2
for the timing diagram and Table 5 for the Latch truth table.

The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
833 kHz or one update every 1.2 µs. This is certainly more than
adequate for systems that have typical lock times in hundreds of
microseconds.

ADSP2181 Interface

Figure 29 shows the interface between the ADF4107 and the
ADSP21xx Digital Signal Processor. The ADF4107 needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the autobuffered mode, and then write to the transmit
register of the DSP. This last operation initiates the autobuffer
transfer.

ADuC812 Interface

Figure 28 shows the interface between the ADF4107 and the
ADuC812 MicroConverter®. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4107 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte has
been written, the LE input should be brought high to complete
the transfer.

On first applying power to the ADF4107, it needs four writes
(one each to the initialization latch, function latch, R counter
latch, and N counter latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power­down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).

When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that the
maximum rate at which the output frequency can be changed
will be 166 kHz.

SCLOCK

MOSI

ADuC812

I/O PORTS

Figure 28. ADuC812 to ADF4107 Interface

CLK

DATA

LE

ADF4107

CE

MUXOUT
(LOCK DETECT)

ADSP21XX

I/O FLAGS

SCLK

DT

TFS

Figure 29. ADSP-21xx to ADF4107 Interface

CLK

DATA

LE

ADF4107

CE

MUXOUT
(LOCK DETECT)

PCB Design Guidelines for Chip Scale Package

The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad.
This will ensure that the solder joint size is maximized. The
bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This will ensure that
shorting is avoided.

Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and

0.33 mm and the via barrel should be plated with 1 oz. copper
to plug the via.

The user should connect the printed circuit board thermal pad
to AGND.

Rev. 0 | Page 19 of 20

ADF4107

0

0

Q

OUTLINE DIMENSIONS

5.10

5.00

4.90

.15

.05

4.50

4.40

4.30

PIN 1

16

0.65
BSC

COPLANARITY

COMPLIANT TOJEDEC STANDARDS MO-153AB

0.10

1.20
MAX

0.30

0.19

9

81

6.40
BSC

SEATIN G

PLA NE

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 30. 16-Lead Thin Shrink Small Outline Package [ TSSOP] (RU-16)—Dimensions shown in millimeters

0.60

MAX

0.60

MAX

0.75

0.55

0.35

COPLANARITY

0.08

16

15

11

10

BOTTOM

VIEW

0.30

0.23

0.18

20

1

2.25

2.10 S

1.95

5

6

PIN 1

INDICATOR

1.0 0

0.90

0.80

SEATING

PLANE

4.0

BSC SQ

TOP

VIEW

12° MAX

0.50
BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

1.00 MAX

0.65 NOM

0.20
REF

3.75

BSC SQ

0.05

0.02

0.00

Figure 31. 20-Lead Frame Chip Scale Package [LFCSP] (CP-20)—Dimensions shown in millimeters

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Range Package Option

ADF4107BRU –40°C to + 85°C RU-16
ADF4107BRU–REEL –40°C to + 85°C RU-16
ADF4107BRU–REEL7 –40°C to + 85°C RU-16
ADF4107BCP –40°C to + 85°C CP-20
ADF4107BCP–REEL –40°C to + 85°C CP-20
ADF4107BCP–REEL7 –40°C to + 85°C CP-20

RU = Thin Shrink Small Outline Package (TSSOP)
CP = Chip Scale Package
Contact the factory for chip availability.
Note that aluminum bond wire should not be used with the ADF4107 die.

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.

C03338-0-5/03(0)

Rev. 0 | Page 20 of 20