Datasheet ADE7760 Datasheet (Analog Devices)

Energy Metering IC with

V

V

V

V

FEATURES

High accuracy active energy measurement IC, supports

IEC 687/61036
Less than 0.1% error over a dynamic range of 500 to 1
Supplies active power on the frequency outputs F1 and F2
High frequency output CF is intended for calibration and

supplies instantaneous active power
Continuous monitoring of the phase and neutral current

allows fault detection in 2-wire distribution systems
Current channels input level best suited for current

transformer sensors
Uses the larger of the two currents (phase or neutral) to

bill—even during a fault condition
Two logic outputs (FAULT and REVP) can be used to indicate

a potential miswiring or fault condition
Direct drive for electromechanical counters and 2-phase

stepper motors (F1 and F2)
Proprietary ADCs and DSP provide high accuracy over large

variations in environmental conditions and time
Reference 2.5 V ± 8% (drift 30 ppm/°C typical) with external

overdrive capability
Single 5 V supply, low power

On-Chip Fault Detection

ADE7760

GENERAL DESCRIPTION

The ADE7760 is a high accuracy, fault tolerant, electrical energy
measurement IC intended for use with 2-wire distribution
systems. The part specifications surpass the accuracy require­ments as quoted in the IEC61036 standard.

The only analog circuitry used on the ADE7760 is in the ADCs
and reference circuit. All other signal processing (such as multi­plication and filtering) is carried out in the digital domain. This
approach provides superior stability and accuracy over extremes
in environmental conditions and over time.

The ADE7760 incorporates a fault detection scheme similar to
the ADE7751 by continuously monitoring both the phase and
neutral currents. A fault is indicated when these currents differ
by more than 6.25%.

The ADE7760 supplies average active power information on the
low frequency outputs F1 and F2. The CF logic output gives
instantaneous active power information.

The ADE7760 includes a power supply monitoring circuit on

supply pin. Internal phase-matching circuitry ensures

the V

DD

that the voltage and current channels are matched. An internal
no-load threshold ensures that the ADE7760 does not exhibit
any creep when there is no load.

FUNCTIONAL BLOCK DIAGRAM

AGND

2

1A

4

1N

3

1B

6

V

2P

5

2N

4kΩ

2.5V

REFERENCE

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

FAULT

158

ADC

A>B

ADC

B>A

ADC

OSCILLATOR

9 14 17 10 11 12

IN/OUT

HPF

A<>B

INTERNAL

V

DD
1

POWER

SUPPLY MONITOR

DIGITAL-TO-FREQUENCY CONVERTER

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADE7760

SIGNAL PROCESSING BLOCK

LPF

16 18 19 20

F1F2CFREVPS0S1SCFDGNDRCLKINREF

www.analog.com

04434-0-001

ADE7760

TABLE OF CONTENTS

Specifications..................................................................................... 3

Active Power Calculation ..........................................................13

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Te r m in o l o g y ...................................................................................... 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics........................................... 10

Operation.........................................................................................11

Power Supply Monitor ............................................................... 11

Analog Inputs.............................................................................. 11

Internal Oscillator...................................................................... 12

Analog-to-Digital Conversion.................................................. 12

REVISION HISTORY

Revision 0: Initial Version

Digital-to-Frequency Conversion............................................ 15

Transfer Fu nction ....................................................................... 16

Fault Detection ........................................................................... 17

Applications..................................................................................... 19

Interfacing to a Microcontroller for Energy Measurement.. 19

Selecting a Frequency for an Energy Meter Application....... 19

Negative Power Information..................................................... 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

Rev. 0 | Page 2 of 24

ADE7760

SPECIFICATIONS

VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, T

Table 1.

Parameter Value Unit Test Conditions/Comments

ACCURACY

Measurement Error

1

2

0.1 % of reading, typ Over a dynamic range of 500 to 1

Phase Error between Channels

(PF = 0.8 Capacitive) ±0.05 Degrees, max Phase lead 37°

(PF = 0.5 Inductive) ±0.05 Degrees, max Phase lag 60°
AC Power Supply Rejection2
Output Frequency Variation 0.01 %, typ V1A = V1B = V2P = ±100 mV rms
DC Power Supply Rejection2
Output Frequency Variation 0.01 %, typ V1A = V1B = V2P = ±100 mV rms

FAULT DETECTION

2, 3

See the Fault Detection section

Fault Detection Threshold

Inactive Input <> Active Input 6.25 %, typ (V1A or V1B active)
Input Swap Threshold

Inactive Input <> Active Input 6.25 % of larger, typ (V1A or V1B active)
Accuracy Fault Mode Operation

V1A Active, V1B = AGND 0.1 % of reading, typ Over a dynamic range of 500 to 1

V1B Active, V1A = AGND 0.1 % of reading, typ Over a dynamic range of 500 to 1
Fault Detection Delay 3 Seconds, typ
Swap Delay 3 Seconds, typ

ANALOG INPUTS V1A – V1N, V1B – V1N, V2P – V

Maximum Signal Levels ±660 mV peak, max Differential input
Input Impedance (DC) 400 kΩ, min
Bandwidth (–3 dB) 7 kHz, typ
ADC Offset Error2 10 mV, max Uncalibrated error, see the Terminology section for details
Gain Error ±4 %, typ External 2.5 V reference

REFERENCE INPUT

REF

Input Voltage Range 2.7 V, max 2.5 V + 8%

IN/OUT

2.3 V, min 2.5 V – 8%
Input Impedance 4 kΩ, min
Input Capacitance 10 pF, max

ON-CHIP REFERENCE

Reference Error ±200 mV, max
Temperature Coefficient 30 ppm/°C, typ
Current Source 20 µA, min

ON-CHIP OSCILLATOR

Oscillator Frequency 450 kHz
Oscillator Frequency Tolerance ±12 % of reading, typ
Temperature Coefficient 30 ppm/°C, typ

LOGIC INPUTS

4

SCF, S1, and S0

Input High Voltage, V

Input Low Voltage, V

Input Current, I

Input Capacitance, C

INH

INL

IN

IN

2.4 V, min VDD = 5 V ± 5%

0.8 V, max VDD = 5 V ± 5%
±3 µA, max Typical 10 nA, VIN = 0 V to V
10 pF, max

MIN

to T

= –40°C to +85°C.

MAX

2N

DD

Rev. 0 | Page 3 of 24

ADE7760

Parameter Value Unit Test Conditions/Comments

LOGIC OUTPUTS4

CF, REVP, and FAULT

Output High Voltage, V
Output Low Voltage, V

OH

OH

F1 and F2

Output High Voltage, V
Output Low Voltage, V

OH

OH

POWER SUPPLY For specified performance

V

DD

5.25 V, max 5 V + 5%
V

DD

1

See plots in the Ty section. pical Performance Characteristics

2

See the section for explanation of specifications. Terminology

3

See the section for explanation of fault detection functionality. Fault Detection

4

Sample tested during initial release and after any redesign or process change that may affect this parameter.

4 V, min VDD = 5 V ± 5%
1 V, max VDD = 5 V ± 5%

4 V, min VDD = 5 V ± 5%, I
1 V, max VDD = 5 V ± 5%, I

4.75 V, min 5 V – 5%

4 mA, max

= 10 mA

source

= 10 mA

sink

Rev. 0 | Page 4 of 24

ADE7760

C

TIMING CHARACTERISTICS

VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, T
Sample tested during initial release and after any redesign or process change that may affect this parameter.
See Figure 2.

Table 2.

Parameter Value Unit Test Conditions/Comments

1

t

1

t

2

t

3

1

t

4

t

5

t

6

120 ms F1 and F2 Pulse Width (Logic High).
See Table 6 s Output Pulse Period. See the Transfer Function section.
1/2 t

2

s Time between F1 Falling Edge and F2 Falling Edge.
90 ms CF Pulse Width (Logic High).
See Table 7 s CF Pulse Period. See the Transfer Function section.
CLKIN/4 s Minimum Time between F1 and F2 Pulse.

1

The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Transfer Function section.

t

1

F1

t

6

t

2

t

F2

t

4

F

3

t

5

Figure 2. Timing Diagram for Frequency Outputs

MIN

to T

= –40°C to +85°C.

MAX

04434-0-002

Rev. 0 | Page 5 of 24

ADE7760

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to AGND –0.3 V to +7 V
Analog Input Voltage to AGND

, V

1AP

, V1N, V2N, V

1BP

2P

V
Reference Input Voltage to AGND –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND –0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
20-Lead SSOP, Power Dissipation 450 mW
θJA Thermal Impedance 112°C/W
Lead Temperature, Soldering

Vapor Phase (60 s) 215°C

Infrared (15 s) 220°C

–6 V to +6 V

–40°C to +85°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 24

ADE7760

r

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the
ADE7760 is defined by the following formula:

Percentage

⎛
⎜
⎜
⎝

Phase Error between Channels

The high-pass filter (HPF) in the current channel has a phase
lead response. To offset this phase response and equalize the
phase response between channels, a phase correction network is
also placed in the current channel. The phase correction net­work ensures a phase match between the current channels and
voltage channels to within ±0.1° over a range of 45 Hz to 65 Hz
and ±0.2° over a range 40 Hz to 1 kHz.

Power Supply Rejection

This quantifies the ADE7760 measurement error as a percent­age of reading when the power supplies are varied. For the ac
PSR measurement, a reading at nominal supplies (5 V) is taken.
A second reading is obtained with the same input signal levels
when an ac (175 mV rms/100 Hz) signal is introduced onto the
supplies. Any error introduced by this ac signal is expressed as a
percentage of reading (see the Measurement Error definition
above).

Erro

=

−

7760

EnergyTrue

EnergyTrueADEbyregisteredEnergy

⎞
⎟

×

%100

⎟
⎠

For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. A second reading is obtained with the same input
signal levels when the power supplies are varied ±5%. Any error
introduced is again expressed as a percentage of reading.

ADC Offset Error

This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND the ADCs still see a dc analog input signal. The magni­tude of the offset depends on the input range selection (see the
Typical Performance Characteristics section). However, when
HPFs are switched on, the offset is removed from the current
channels and the power calculation is not affected by this offset.

Gain Error

The gain error in the ADE7760 ADCs is defined as the differ­ence between the measured output frequency (minus the offset)
and the ideal output frequency. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is
obtained from the transfer function (see the Transfer Function
section).

Rev. 0 | Page 7 of 24

ADE7760

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

DD

2

V

1A

V

3

1B

V

4

1N

ADE7760

V

5

2N

TOP VIEW

V

6

2P

(Not to Scale)

NC

7

AGND

8

REF

IN/OUT

SCF

9

10

NC = NO CONNECT

Figure 3. Pin Configuration (SSOP)

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD

Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7760. The supply
voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled with a
10 µF capacitor in parallel with a ceramic 100 nF capacitor.

2, 3 V1A, V

1B

Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with
maximum differential input signal levels of ±660 mV with respect to V
maximum signal level at these pins is ±1 V with respect to AGND. Both inputs have internal ESD
protection circuitry, and an overvoltage of ±6 V can also be sustained on these inputs without risk of
permanent damage.

4 V

1N

Negative Input Pin for Differential Voltage Inputs V1A and V1B. The maximum signal level at this pin is
±1 V with respect to AGND. The input has internal ESD protection circuitry, and an overvoltage of ±6 V
can also be sustained on these inputs without risk of permanent damage. The input should be directly
connected to the burden resistor and held at a fixed potential, that is, AGND. See the Analog Inputs
section.

5 V

2N

Negative Input Pin for Differential Voltage Input V2P. The maximum signal level at this pin is ±1 V with
respect to AGND. The input has internal ESD protection circuitry, and an overvoltage of ±6 V can also be
sustained on these inputs without risk of permanent damage. The input should be held at a fixed
potential, that is, AGND. See the Analog Inputs section.

6 V

2P

Analog Inputs for Channel 2 (Voltage Channel). This input is fully differential voltage input with
maximum differential input signal levels of ±660 mV with respect to V
maximum signal level at these pins is ±1 V with respect to AGND. This input has internal ESD protection
circuitry, and an overvoltage of ±6 V can also be sustained on these inputs without risk of permanent

damage.
7 NC Not Connected. Nothing should be connected to this pin.
8 AGND

This pin provides the ground reference for the analog circuitry in the ADE7760, that is, ADCs and

reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the

ground reference for all analog circuitry such as antialiasing filters, and current and voltage transducers.

For good noise suppression, the analog ground plane should be connected only to the digital ground

plane at the DGND pin.
9 REF

IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be

connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic

capacitor and 100 nF ceramic capacitor.
10 SCF

Select Calibration Frequency. This logic input is used to select the frequency on the calibration output

CF. Table 6 shows how the calibration frequencies are selected.
11, 12 S1, S0

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency

conversion. This offers the designer greater flexibility when designing the energy meter. See the

Selecting a Frequency for an Energy Meter Application section.
13 INT This pin is internally used and should be connected to DGND.
14 RCLKIN

To enable the internal oscillator as a clock source on the chip, a precise low temperature drift resistor at

nominal value of 6.2 kΩ must be connected from this pin to DGND.

20
19
18
17
16
15
14
13
12
11

F1
F2
CF
DGND
REVP
FAULT
RCLKIN
INT
S0
S1

04434-0-003

for specified operation. The

1N

for specified operation. The

2N

Rev. 0 | Page 8 of 24

ADE7760

Pin No. Mnemonic Description

15 FAULT

16 REVP

17 DGND

18 CF

19, 20 F2, F1

This logic output goes active high when a fault condition occurs. A fault is defined as a condition under
which the signals on V
condition is no longer detected. See the Fault Detection section.

This logic output goes logic high when negative power is detected, that is, when the phase angle
between the voltage and current signals is greater than 90°. This output is not latched and is reset when
positive power is once again detected. The output goes high or low at the same time as a pulse is issued
on CF.

This pin provides the ground reference for the digital circuitry in the ADE7760, that is, multiplier, filters,
and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The
digital ground plane is the ground reference for all digital circuitry such as counters (mechanical and
digital), MCUs, and indicator LEDs. For good noise suppression, the analog ground plane should be
connected only to the digital ground plane at the DGND pin.

Calibration Frequency Logic Output. The CF logic output, active high, gives instantaneous active power
information. This output is intended to be used for operational and calibration purposes. See the Digital­to-Frequency Conversion section.

Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs
can be used to directly drive electromechanical counters and 2-phase stepper motors.

and V1B differ by more than 6.25%. The logic output is reset to zero when a fault

1A

Rev. 0 | Page 9 of 24

ADE7760

TYPICAL PERFORMANCE CHARACTERISTICS

1.0
PF = 1

ON-CHIP REFERENCE

0.8

0.6

0.4

0.2

0

–0.2

% ERROR

–0.4

–0.6

–0.8

–1.0

CURRENT (% of Full Scale)

Figure 4. Active Power Error as a Percentage of Reading with

Internal Reference

1.5
PF = 0.5

ON-CHIP REFERENCE

1.0

–40°C; PF = 0.5

–40°C

+25°C

+85°C

100.00.1 1.0 10.0

04434-0-037

1.0
PF = 1

ON-CHIP REFERENCE

–0.2

% ERROR

–0.4

–0.6

–0.8

–1.0

0.8

0.6

0.4

0.2

0

5.25V

5.00V

4.75V

CURRENT (% of Full Scale)

Figure 6. Active Power Error as a Percentage of Reading over

Power Supply with Internal Reference

100.00.1 1.0 10.0

04434-0-039

0.5

+25°C; PF = 1

0

% ERROR

+85°C; PF = 0.5

–0.5

–1.0

CURRENT (% of Full Scale)

+25°C; PF = 0.5

Figure 5. Active Power Error as a Percentage of Reading over

Power Factor with Internal Reference

+

10µF

RB

RB

220V

40A TO 80mA

I

RB = 18Ω

1MΩ

33nF1kΩ

1kΩ

33nF

1kΩ

33nF

1kΩ

33nF

1kΩ

33nF

100.00.1 1.0 10.0

100nF

2

3

4

5

6

V

V

V

V

V

1A

1B

1N

2N

2P

04434-0-038

V

DD

1

V

DD

ADE7760

AGND DGNDINT

RCLKIN

REF

CF

FAULT

S0
S1

SCF

IN/OUT

1713 8

10kΩ

PS2501-1

1

2

+

10µF

4

3

TO FREQ.
COUNTER

2kΩ

18

2kΩ

15

6.2kΩ

14

12
11

10

9

100nF

Figure 7. Test Circuit for Performances Curves

Rev. 0 | Page 10 of 24

04434-0-036

ADE7760

-

–

–

OPERATION

POWER SUPPLY MONITOR

The ADE7760 contains an on-chip power supply monitor. The
power supply (V

) is continuously monitored by the ADE7760.

DD

If the supply is less than 4 V ± 5%, the ADE7760 goes into an
inactive state, that is, no energy is accumulated and the CF, F1,
and F2 outputs is disabled. This is useful to ensure correct
device operation at power-up and during power-down. The
power supply monitor has built-in hysteresis and filtering. This
gives a high degree of immunity to false triggering due to noisy
supplies.

The power supply and decoupling for the part should be such
that the ripple at V

does not exceed 5 V ± 5% as specified for

DD

normal operation.

V

DD

5V
4V

ADE7760

REVP - FAULT - CF

F1 - F2 OUTPUTS

0V

INACTIVE ACTIVE

TIME

INACTIVE

Figure 8. On-Chip Power Supply Monitoring

ANALOG INPUTS

Channel V1 (Current Channel)

The voltage outputs from the current transducers are connected
to the ADE7760 here. Channel V1 has two voltage inputs, V
and V

. These inputs are fully differential with respect to V1N.

1B

However, at any one time, only one is selected to perform the
power calculation (see the Fault Detection section).

The maximum peak differential signal on V

1A–V1N

and V1B–V1N
is ±660 mV. Figure 9 shows the maximum signal levels on V
V

, and V1N. The differential voltage signal on the inputs must

1B

be referenced to a common mode such as AGND.

V

1A

V1

V

1N

V1

V

1B

+660mV + V

660mV + V

DIFFERENTIAL INPUT A

V

, V

1A

1B

CM

V

CM

CM

±660mV MAX PEAK

COMMON MODE

±100mV MAX

AGND

DIFFERENTIAL INPUT B

±660mV MAX PEAK

V

CM

Figure 9. Maximum Signal Levels, Channel 1

1A

,

1A

04434-0-010

04434-0-011

Channel V2 (Voltage Channel)

The output of the line voltage transducer is connected to the
ADE7760 at this analog input. Channel V2 is a single-ended
voltage input. The maximum peak differential signal on
Channel 2 is ±660 mV with respect to V

. Figure 10 shows the

2N

maximum signal levels that can be connected to Channel 2.

+660mV + V

660mV + V

V2

CM

V

CM

CM

DIFFERENTIAL INPUT

±660mV MAX PEAK

COMMON MODE

±100mV MAX

Figure 10. Maximum Signal Levels, Channel 2

V

2P

V2

V

2N

V

CM

The differential voltage V2P–V2N must be referenced to a
common mode (usually AGND). The analog inputs of the
ADE7760 can be driven with common-mode voltages of up to
100 mV with respect to AGND. However, the best results are
achieved using a common mode equal to AGND.

Typical Connection Diagrams

Figure 11 shows a typical connection diagram for Channel V1.
The analog inputs are being used to monitor both the phase and
neutral currents. Because of the large potential difference
between the phase and neutral, two current transformers (CTs)
must be used to provide the isolation. Note that both CTs are
referenced to AGND (analog ground); the common-mode
voltage is, therefore, 0 V. The CT turns ratio and burden resistor
(RB) are selected to give a peak differential voltage of ±660 mV.

V

1A

C

F

V

1N

C

F

V

1B

04434-0-014

INIP

PHASE

R

CT

RB

AGND

RB

CT

NEUTRAL

F

R

F

Figure 11. Typical Connection for Channel 1

Figure 12 shows two typical connections for Channel V2. The
first option uses a potential transformer (PT) to provide
complete isolation from the main voltage. In the second option,
the ADE7760 is biased around the neutral wire, and a resistor
divider is used to provide a voltage signal that is proportional to
the line voltage. Adjusting the ratio of RA and RB + VR is a
convenient way of carrying out a gain calibration on the meter.

04434-0-012

Rev. 0 | Page 11 of 24

ADE7760

V

NEUTRAL

PHASE

RA*

NEUTRAL

PHASE

*RB + VR = RF

RB*
VR*

±660mV

AGND

R

R

C

F

R

2P

F

C

F

V

2N

F

C

F

V

2P

V

2N

F

C

T

04434-0-015

Figure 12. Typical Connection for Channel 2

INTERNAL OSCILLATOR

The nominal internal oscillator frequency is 450 kHz when
used with the recommended R

resistor value of 6.2 kΩ

OSC

between RCLKIN and DGND (see Figure 13).

The internal oscillator frequency is inversely proportional to the
value of this resistor. Although the internal oscillator operates
when used with a R

resistor value between 5 kΩ and 12 kΩ, it

OSC

is recommended to choose a value within the range of the
nominal value.

The output frequencies on CF, F1, and F2 are directly
proportional to the internal oscillator frequency; thus, the
resistor R

must have a low tolerance and low temperature

OSC

drift. A low tolerance resistor limits the variation of the internal
oscillator frequency. Small variation of the clock frequency and
consequently of the output frequencies from meter to meter
contributes to a smaller calibration range of the meter. A low
temperature drift resistor directly limits the variation of the
internal clock frequency over temperature. The stability of the
meter to external variation is then better ensured by design.

ADE7760

4kΩ

2.5V

REFERENCE

Figure 13. ADE7760 Internal Oscillator Connection

9

IN/OUT

INTERNAL

OSCILLATOR

14 17

R

OSC

DGNDRCLKINREF

04434-0-017

ANALOG-TO-DIGITAL CONVERSION

The analog-to-digital conversion in the ADE7760 is carried out
using second-order Σ-Δ ADCs. Figure 14 shows a first-order
(for simplicity) Σ-Δ ADC. The converter is made up of two
parts, the Σ-Δ modulator and the digital low-pass filter.

MCLK

ANALOG

LOW-PASS FILTER

R

C

INTEGRATOR

∫

V

REF

1-BIT DAC

LATCHED
COMPAR­ATOR

....10100101....

DIGITAL

LOW-PASS FILTER

1 24

04434-0-019

Figure 14. First-Order Σ-∆ ADC

A Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7760, the sampling clock is equal to CLKIN.
The 1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal. If
the loop gain is high enough, the average value of the DAC
output (and, therefore, the bit stream) approaches that of the
input signal level. For any given input value in a single sampling
interval, the data from the 1-bit ADC is virtually meaningless.
Only when a large number of samples are averaged is a
meaningful result obtained. This averaging is carried out in the
second part of the ADC, the digital low-pass filter. By averaging
a large number of bits from the modulator, the low-pass filter
can produce 24-bit data words that are proportional to the input
signal level.

The Σ-Δ converter uses two techniques to achieve high resolu­tion from what is essentially a 1-bit conversion technique. The
first is oversampling, which means that the signal is sampled at
a rate (frequency) that is many times higher than the bandwidth
of interest. For example, the sampling rate in the ADE7760 is
CLKIN (450 kHz) and the band of interest is 40 Hz to 1 kHz.
Oversampling has the effect of spreading the quantization noise
(noise due to sampling) over a wider bandwidth. With the noise
spread more thinly over a wider bandwidth, the quantization
noise in the band of interest is lowered (see Figure 15).

However, oversampling alone is not an efficient enough method
to improve the signal-to-noise ratio (SNR) in the band of inter­est. For example, an oversampling ratio of 4 is required just to
increase the SNR by only 6 dB (1 bit). To keep the oversampling
ratio at a reasonable level, it is possible to shape the quantization
noise so that the majority of the noise lies at the higher frequen­cies. This is what happens in the Σ-Δ modulator; the noise is
shaped by the integrator, which has a high-pass type response
for the quantization noise. The result is that most of the noise is
at the higher frequencies where it can be removed by the digital
low-pass filter. This noise shaping is also shown in Figure 15.

Rev. 0 | Page 12 of 24

ADE7760

S

S

ANTIALIAS FILTER (RC)

IGNAL

NOISE

0 1kHz 225kHz 450kHz

IGNAL

NOISE

0 1kHz 225kHz 450kHz

DIGITAL FILTER

FREQUENCY (Hz)

HIGH RESOLUTION

OUTPUT FROM

DIGITAL LFP

FREQUENCY (Hz)

SAMPLING FREQUENCY

SHAPED NOISE

Figure 15. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

Antialias Filter

Figure 15 also shows an analog low-pass filter (RC) on input to
the modulator. This filter is present to prevent aliasing. Aliasing
is an artifact of all sampled systems, which means that fre­quency components in the input signal to the ADC that are
higher than half the sampling rate of the ADC appear in the
sampled signal frequency below half the sampling rate.
Figure 16 illustrates the effect.

In Figure 16, frequency components (arrows shown in black)
above half the sampling frequency (also known as the Nyquist
frequency), that is, 225 kHz get imaged or folded back down
below 225 kHz (arrows shown in gray). This happens with all
ADCs no matter what the architecture. In the example shown, it
can be seen that only frequencies near the sampling frequency
(450 kHz) move into the band of interest for metering (40 Hz to
1 kHz). This fact allows the use of a very simple low-pass filter
to attenuate these frequencies (near 250 kHz) and thereby
prevent distortion in the band of interest. A simple RC filter
(single pole) with a corner frequency of 10 kHz produces an
attenuation of approximately 33 dB at 450 kHz (see Figure 16).
This is sufficient to eliminate the effects of aliasing.

04434-0-020

ACTIVE POWER CALCULATION

The ADCs digitize the voltage signals from the current and
voltage transducers. A high-pass filter in the current channel
removes any dc component from the current signal. This
eliminates any inaccuracies in the active power calculation due
to offsets in the voltage or current signals (see the HPF and
Offset Effects section).

The active power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals. To
extract the active power component (dc component), the
instantaneous power signal is low-pass filtered. Figure 17
illustrates the instantaneous active power signal and shows how
the active power information can be extracted by low-pass
filtering the instantaneous power signal. This scheme correctly
calculates active power for nonsinusoidal current and voltage
waveforms at all power factors. All signal processing is carried
out in the digital domain for superior stability over temperature
and time.

The low frequency output of the ADE7760 is generated by
accumulating this active power information. This low frequency
inherently means a long accumulation time between output
pulses. The output frequency is, therefore, proportional to the
average active power. This average active power information can
in turn be accumulated (for example, by a counter) to generate
active energy information. Because of its high output frequency
and therefore shorter integration time, the CF output is propor­tional to the instantaneous active power. This is useful for
system calibration purposes that would take place under steady
load conditions.

DIGITAL-TO-

CH1

CH2

ADC

HPF

MULTIPLIER

ADC

INSTANTANEOUS

POWER SIGNAL –p(t)

FREQUENCY

LPF

INSTANTANEOUS

ACTIVE POWER SIGNAL

DIGITAL-TO-

FREQUENCY

CF

F1
F2

ANTIALIASING EFFECTS

IMAGE

FREQUENCIES

0 1kHz 225kHz 450kHz

FREQUENCY (Hz)

SAMPLING

FREQUENCY

04434-0-021

V× I

TIME

p(t) = i(t).v(t)
WHERE:
v(t) = V × cos(ϖt)
i(t) = I × cos(ϖt)

V× I

p(t) =

{1 + cos (2ϖt)}

2

V× I

2

Figure 17. Signal Processing Block Diagram

04434-0-022

Figure 16. ADC and Signal Processing in Current Channel or Voltage Channel

Rev. 0 | Page 13 of 24

ADE7760

+

=

Φ×=

=

×

Power Factor Considerations

The method used to extract the active power information from
the instantaneous power signal (by low-pass filtering) is still
valid even when the voltage and current signals are not in
phase. Figure 18 displays the unity power factor condition and
a displacement power factor (DPF = 0.5), that is, current signal
lagging the voltage by 60°. If one assumes the voltage and
current waveforms are sinusoidal, the active power component
of the instantaneous power signal (dc term) is given by
(V × I/2) × cos(60°). This is the correct active power calculation.

INSTANTANEOUS
POWER SIGNAL

INSTANTANEOUS
ACTIVE POWER SIGNAL

where:

i(t) is the instantaneous current.
I

is the dc component.

O

I

is the rms value of current harmonic h.

h

β

is the phase angle of the current harmonic.

h

Using Equations 1 and 2, the active power
terms of its fundamental active power (
power (

P

):

H

PPP

1

H

P

where:

P can be expressed in

) and harmonic active

1

V× I

2

0V

CURRENT
VOLTAGE

V× I

× cos(60°)

2

INSTANTANEOUS
POWER SIGNAL

0V

VOLTAGE

Figure 18. Active Power Calculation over PF

INSTANTANEOUS
ACTIVE POWER SIGNAL

60°

CURRENT

Nonsinusoidal Voltage and Current

The active power calculation method also holds true for
nonsinusoidal current and voltage waveforms. All voltage and
current waveforms in practical applications have some har­monic content. Using the Fourier transform, instantaneous
voltage and current waveforms can be expressed in terms of
their harmonic content:

∞

o

∑

h

≠

0hh

(1)

)sin(2)(

thVVtV α+ω××+=

where:

v(t) is the instantaneous voltage.
V

is the rms value of voltage harmonic h.

h

α

is the phase angle of the voltage harmonic.

h

∞

o

∑

h

≠

0hh

(2)

)sin(2)(

thIIti β+ω××+=

04434-0-023

IVP

β−α=Φ

)cos(

1111

111

(3)

and

∞

IVP

∑

H

2

=

h

β−α=Φ

hhh

Φ××=

)cos(

hhh

(4)

As can be seen from Equation 4, a harmonic active power
component is generated for every harmonic, provided that
harmonic is present in both the voltage and current waveforms.
The power factor calculation has previously been shown to be
accurate in the case of a pure sinusoid; therefore, the harmonic
active power must also correctly account for power factor,
because it is made up of a series of pure sinusoids.

Note that the input bandwidth of the analog inputs is 7 kHz
with the internal oscillator frequency of 450 kHz.

HPF and Offset Effects

Equation 5 shows the effect of offset on the active power
calculation. Figure 19 shows the effect of offsets on the active
power calculation in the frequency domain.

)()(

tItV

))cos(())cos((

tIItVV

0

110

IV

×

IV

+×

11

2

=ω×+×ω×+

00

1110

(5)

)cos()cos(

tIVtIV

ω××+ω××+

As can be seen from Equation 5 and Figure 19, an offset on
Channel 1 and Channel 2 contributes a dc component after
multiplication. Because this dc component is extracted by the
LPF and used to generate the active power information, the
offsets contribute a constant error to the active power calcula­tion. This problem is easily avoided in the ADE7760 with the
HPF in Channel 1. By removing the offset from at least one
channel, no error component can be generated at dc by the
multiplication. Error terms at cos(ωt) are removed by the LPF
and the digital-to-frequency conversion (see the Digital-to­Frequency Conversion section).

Rev. 0 | Page 14 of 24

ADE7760

)

The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. Figure 20 and Figure 21 show the
phase error between channels with the compensation network
activated. The ADE7760 is phase compensated up to 1 kHz as
shown, which ensures correct active harmonic power
calculation even at low power factors.

DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR ACTIVE

V1× I

1

2

Figure 19. Effect of Channel Offsets on the Active Power Calculation

0.30

0.25

0.20

0.15

0.10

0.05

PHASE (Degrees)

0

–0.05

–0.10

0 100

Figure 20. Phase Error between Channels (0 Hz to 1 kHz)

0.30

POWER CALCULATION

V1× I

0

V0× I

1

0v

200 300 400 500 600 700 800 900 1000

FREQUENCY (RAD/S)

FREQUENCY (Hz)

2v

04434-0-024

04434-0-025

DIGITAL-TO-FREQUENCY CONVERSION

As previously described, the digital output of the low-pass filter
after multiplication contains the active power information.
However, because this LPF is not an ideal “brick wall” filter
implementation, the output signal also contains attenuated
components at the line frequency and its harmonics, that is,
cos(hωt), where h = 1, 2, 3, ..., and so on. The magnitude
response of the filter is given by

=

)(ffH

1

=

For a line frequency of 50 Hz, this gives an attenuation of the 2ω
(100 Hz) component of approximately –26.9 dB. The dominat­ing harmonic is at twice the line frequency, that is, cos(2ωt), due
to the instantaneous power signal.

Figure 22 shows the instantaneous active power signal output of
the LPF, which still contains a significant amount of instantane­ous power information, cos(2ωt). This signal is then passed to
the digital-to-frequency converter, where it is integrated
(accumulated) over time to produce an output frequency. This
accumulation of the signal suppresses or averages out any non­dc components in the instantaneous active power signal. The
average value of a sinusoidal signal is zero. Therefore, the
frequency generated by the ADE7760 is proportional to the
average active power.

Figure 22 also shows the digital-to-frequency conversion for
steady load conditions: constant voltage and current. As can be
seen in Figure 22, the frequency output CF varies over time,
even under steady load conditions. This frequency variation is
primarily due to the cos(2ωt) component in the instantaneous
active power signal.

(6)

2

)Hz5.4/(1

F1

0.25

0.20

0.15

0.10

0.05

PHASE (Degrees)

0

–0.05

–0.10

40

45 50 55 60 65 70

FREQUENCY (Hz)

04434-0-026

Figure 21. Phase Error between Channels (40 Hz to 70 Hz)

V

MULTIPLIER

I

LPF TO EXTRACT
ACTIVE POWER
(DC TERM)

0 ϖ 2ϖ

FREQUENCY (Rad/s)

INSTANTANEOUS ACTIVE POWER SIGNAL (FREQUENCY DOMAIN

LPF

Figure 22. Active Power to Frequency Conversion

DIGITAL-TO­FREQUENCY

DIGITAL-TO­FREQUENCY

F1
F2

CF

FOUT

FREQUENCY FREQUENCY

TIME

TIME

04434-0-027

Rev. 0 | Page 15 of 24

ADE7760

The output frequency on CF can be up to 2048 times higher
than the frequency on F1 and F2. This higher output frequency
is generated by accumulating the instantaneous active power
signal over a much shorter time while converting it to a
frequency. This shorter accumulation period means less
averaging of the cos(2ωt) component. As a consequence, some
of this instantaneous power signal passes through the digital-to­frequency conversion. This is not a problem in the application.
Where CF is used for calibration purposes, the frequency
should be averaged by the frequency counter, which removes
any ripple. If CF is being used to measure energy, such as in a
microprocessor-based application, the CF output should also be
averaged to calculate power. Because the outputs F1 and F2
operate at a much lower frequency, a lot more averaging of the
instantaneous active power signal is carried out. The result is a
greatly attenuated sinusoidal content and a virtually ripple-free
frequency output.

TRANSFER FUNCTION

Frequency Outputs F1 and F2

The ADE7760 calculates the product of two voltage signals (on
Channel 1 and Channel 2) and then low-pass filters this product
to extract active power information. This active power
information is then converted to a frequency. The frequency
information is output on F1 and F2 in the form of active high
pulses. The pulse rate at these outputs is relatively low, for
example, 0.34 Hz maximum for ac signals with S0 = S1 = 0
(see Table 7). This means that the frequency at these outputs is
generated from active power information accumulated over a
relatively long period of time. The result is an output frequency
that is proportional to the average active power. The averaging
of the active power signal is implicit to the digital-to-frequency
conversion. The output frequency or pulse rate is related to the
input voltage signals by the following equation:

FrequencyFF

2

1

70.5

=− (7)

V

REF

where:

− F2 Frequency is the output frequency on F1 and F2 (Hz).

F

1

V1

is the differential rms voltage signal on Channel 1 (V).

rms

V2

is the differential rms voltage signal on Channel 2 (V).

rms

V

is the reference voltage (2.5 V ± 8%) (V).

REF

F

is one of four possible frequencies selected by using the

1–4

logic inputs S0 and S1 (see Table 5).

FV2V1

×××

41rmsrms

2

−

Table 5. F

S1 S0 F

0 0 1.72 OSC/2
0 1 3.44 OSC/2
1 0 6.86 OSC/2
1 1 13.7 OSC/2

1

Values are generated using the nominal frequency of 450 kHz.

2

F

are a binary fraction of the master clock and, therefore, varies, if the

1–4

internal oscillator frequency (OSC).

Frequency Solution

1–4

(Hz)

1–4

1

OSC/CLKIN

2

18

17

16

15

Frequency Output CF

The pulse output calibration frequency (CF) is intended for use
during calibration. The output pulse rate on CF can be up to
2048 times the pulse rate on F1 and F2. The lower the F

1–4

frequency selected, the higher the CF scaling. Table 6 shows
how the two frequencies are related, depending on the states of
the logic inputs S0, S1, and SCF. Because of its relatively high
pulse rate, the frequency at this logic output is proportional to
the instantaneous active power. As with F1 and F2, the fre­quency is derived from the output of the low-pass filter after
multiplication. However, because the output frequency is high,
this active power information is accumulated over a much
shorter time. Therefore, less averaging is carried out in the
digital-to-frequency conversion. With much less averaging of
the active power signal, the CF output is much more responsive
to power fluctuations (see Figure 17).

Table 6. Relationship between CF and F1, F2 Frequency
Outputs

SCF S1 S0 F

(Hz) CF Frequency Output

1–4

1 0 0 1.72 128 × F1, F2
0 0 0 1.72 64 × F1, F2
1 0 1 3.44 64 × F1, F2
0 0 1 3.44 32 × F1, F2
1 1 0 6.86 32 × F1, F2
0 1 0 6.86 16 × F1, F2
1 1 1 13.7 16 × F1, F2
0 1 1 13.7 2048 × F1, F2

Example

In this example, if ac voltages of ±660 mV peak are applied to
V1 and V2, then the expected output frequency on CF, F1, and
F2 is calculated as follows:

F

= 1.7 Hz, SCF = S1 = S0 = 0

1–4

= rms of 660 mV peak ac = 0.66/√2 V

V1

rms

V2

V

REF

Rev. 0 | Page 16 of 24

= rms of 660 mV peak ac = 0.66/√2 V

rms

= 2.5 V (nominal reference value)

ADE7760

Note that if the on-chip reference is used, actual output
frequencies may vary from device to device due to reference
tolerance of ±8%.

Hz72.166.066.070.5

FrequencyFF

21

=−

FFFrequencyCF

=×−=

21

×××

2

5.222

××

Hz0.2264

Hz34.0

=

As can be seen from these two example calculations, the
maximum output frequency for ac inputs is always half of that
for dc input signals. Table 7 shows a complete listing of all
maximum output frequencies for ac signals.

Table 7. Maximum Output Frequency on CF, F1, and F2 for
AC Inputs

CF Maximum
Frequency
(Hz)

SCF S1 S0

F1, F2 Maximum
Frequency
(Hz)

1 0 0 0.34 43.52 128
0 0 0 0.34 21.76 64
1 0 1 0.68 43.52 64
0 0 1 0.68 21.76 32
1 1 0 1.36 43.52 32
0 1 0 1.36 21.76 16
1 1 1 2.72 43.52 16
0 1 1 2.72 5570 2048

CF to
F1
Ratio

FAULT DETECTION

The ADE7760 incorporates a novel fault detection scheme that
warns of fault conditions and allows the ADE7760 to continue
accurate billing during a fault event. The ADE7760 does this by
continuously monitoring both the phase and neutral (return)
currents. A fault is indicated when these currents differ by more
than 6.25%. However, even during a fault, the output pulse rate
on F1 and F2 is generated using the larger of the two currents.
Because the ADE7760 looks for a difference between the voltage
signals on V
transducers be closely matched.

On power-up, the output pulse rate of the ADE7760 is pro­portional to the product of the voltage signals on V
Channel 2. If there is a difference of greater than 6.25% between
V

and V1B on power-up, the fault indicator (FAULT) becomes

1A

active after about 1 s. In addition, if V
ADE7760 selects V
automatically disabled when the voltage signal on Channel 1 is
less than 0.3% of the full-scale input range. This eliminates false
detection of a fault due to noise at light loads.

Fault with Active Input Greater than Inactive Input

If V1A is the active current input (that is, is being used for
billing), and the voltage signal on V

93.75% of V
inputs are filtered and averaged to prevent false triggering of
this logic output.

and V1B, it is important that both current

1A

and

1A

is greater than V1A, the

1B

as the input. The fault detection is

1B

(inactive input) falls below

1B

, the fault indicator becomes active. Both analog

1A

As a consequence of the filtering, there is a time delay of
approximately 3 s on the logic output FAULT after the fault
event. The FAULT logic output is independent of any activity on
outputs F1 or F2. Figure 23 shows one condition under which
FAULT becomes active. Because V
still greater than V
swap to the V

V

1A

V

1B

0V

V1B < 93.75% OF V

FAULT

<0

6.25% OF ACTIVE INPUT

Figure 23. Fault Conditions for Active Input Greater than Inactive Input

, billing is maintained on V1A, that is, no

1B

input occurs. V1A remains the active input.

1B

V

V

1A

V

AGND

V

1B

1A

V

>0

is the active input and it is

1A

1A

1N

1B

ACTIVE POINT – INACTIVE INPUT

A

B

FILTER

AND

COMPARE

FAULT

TO
MULTIPLIER

Fault with Inactive Input Greater than Active Input

Figure 24 illustrates another fault condition. If the difference
between V
for billing), becomes greater than 6.25% of V
indicator goes active, and there is also a swap over to the V
input. The analog input V

, the inactive input, and V1A, the active input (used

1B

, the FAULT

1B

becomes the active input. Again,

1B

1B

there is a time constant of about 3 s associated with this swap.
V

does not swap back to being the active channel until V1A is

1A

greater than V
order—becomes greater than 6.25% of V
indicator, however, becomes inactive as soon as V

6.25% of V
between V

0V

V1A < 93.75% OF V

FAULT + SWAP

<0

6.25% OF INACTIVE INPUT

Figure 24. Fault Conditions for Inactive Input Greater than Active Input

and the difference between V1A and V1B—in this

1B

. The FAULT

1A

. This threshold eliminates potential chatter

1B

and V1B.

1A

A

B

FILTER

AND

COMPARE

V

1A

V

1B

AGND

1B

V

1A

V

1A

V

1N

V

1B

V

1B

>0

ACTIVE POINT – INACTIVE INPUT

is within

1A

FAULT

TO
MULTIPLIER

04434-0-028

04434-0-029

Rev. 0 | Page 17 of 24

ADE7760

C

Calibration Concerns

Typically, when a meter is being calibrated, the voltage and
current circuits are separated as shown in Figure 25. This means
that current passes through only the phase or neutral circuit.
Figure 25 shows current being passed through the phase circuit.
This is the preferred option, because the ADE7760 starts billing
on the input V
nected to V
neutral circuit, the FAULT indicator comes on under these
conditions. However, this does not affect the accuracy of the
calibration and can be used as a means to test the functionality
of the fault detection.

on power-up. The phase circuit CT is con-

1A

in the diagram. Because there is no current in the

1A

R

IB

CT

F

V

1A

If the neutral circuit is chosen for the current circuit in the
arrangement shown in Figure 25, this may have implications for
the calibration accuracy. The ADE7760 powers up with the V

1A

input active as normal. However, because there is no current in
the phase circuit, the signal on V
be flagged and the active input to be swapped to V

is zero. This causes a fault to

1A

(neutral).

1B

The meter can be calibrated in this mode, but the phase and
neutral CTs might differ slightly. Because under no-fault condi­tions all billing is carried out using the phase CT, the meter
should be calibrated using the phase circuit. Of course, both
phase and neutral circuits can be calibrated.

TEST

URRENT

IB

PHASE

240V RMS

V

AGND

NEUTRAL

RA*

CT

RB*

VR*

*RB + VR = RF

RB

RB

V

1A

0V

C

F

R

F

C

C

F

V

1N

C

F

R

F

T

V

1B

V

2P

V

2N

Figure 25. Fault Conditions for Inactive Input Greater than Active Input

04434-0-030

Rev. 0 | Page 18 of 24

ADE7760

APPLICATIONS

INTERFACING TO A MICROCONTROLLER FOR ENERGY MEASUREMENT

The easiest way to interface the ADE7760 to a microcontroller
is to use the CF high frequency output with the output fre­quency scaling set to 2048 × F1, F2. This is done by setting
SCF = 0 and S0 = S1 = 1 (see Table 7). With full-scale ac signals
on the analog inputs, the output frequency on CF is approxi­mately 5.5 kHz. Figure 26 illustrates one scheme that could be
used to digitize the output frequency and carry out the
necessary averaging mentioned in the previous section.

CF

AVERAGE

FREQUENCY

ADE7760

CF

REVP*

FAULT**

*REVP MUST BE USED IF THE METER IS BIDIRECTIONAL OR

DIRECTION OF ENERGY FLOW IS NEEDED.

**FAULT MUST BE USED TO RECORD ENERGY IN FAULT CONDITION.

Figure 26. Interfacing the ADE7760 to an MCU

As shown, the frequency output CF is connected to an MCU
counter or port, which counts the number of pulses in a given
integration time, determined by an MCU internal timer. The
average power, proportional to the average frequency, is given
by

The energy consumed during an integration period is given by

FREQUENCY

RIPPLE

TIME

TimePowerAverageEnergy =×=×=

COUNTER

UP/DOWN

PowerActiveAverageFrequencyAverage ==

Counter

Time

MCU

LOGIC

±10%

Counter

Timer

04434-0-035

CounterTime

For the purpose of calibration, this integration time could be
10 s to 20 s in order to accumulate enough pulses to ensure
correct averaging of the frequency. In normal operation, the
integration time could be reduced to 1 s or 2 s depending, for
example, on the required update rate of a display. With shorter
integration times on the MCU, the amount of energy in each
update might still have a small amount of ripple, even under
steady load conditions. However, over a minute or more, the
measured energy has no ripple.

SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION

As shown in Table 5, the user can select one of four frequencies.
This frequency selection determines the maximum frequency
on F1 and F2. These outputs are intended to be used to drive the
energy register (electromechanical or other). Because only four
different output frequencies can be selected, the available
frequency selection has been optimized for a meter constant of
100 impulses/kWh with a maximum current of between 10 A
and 120 A. Table 8 shows the output frequency for several
maximum currents (I
cases, the meter constant is 100 impulses/kWh.

Table 8. F1 and F2 Frequency at 100 Impulses/kWh

I

F1 and F2 (Hz)

MAX

12.5 A 0.083
25 A 0.166
40 A 0.266

60 A 0.4
80 A 0.533

120 A 0.8

The F

frequencies allow complete coverage of this range of

1–4

output frequencies on F1 and F2. When designing an energy
meter the nominal design voltage on Channel 2 (voltage)
should be set to half-scale to allow for calibration of the meter
constant. The current channel should also be no more than half­scale when the meter sees maximum load. This accommodates
overcurrent signals and signals with high crest factors. Table 9
shows the output frequency on F1 and F2 when both analog
inputs are half-scale. The frequencies listed in Table 9 align well
with those listed in Table 8 for maximum load.

) with a line voltage of 240 V. In all

MAX

Rev. 0 | Page 19 of 24

ADE7760

Table 9. F1 and F2 Frequency with Half-Scale AC Inputs

Frequency on F1 and F2,
CH1 and CH2,

S0 S1 F

0 0 1.72 0.085 Hz
0 1 3.44 0.17 Hz
1 0 6.86 0.34 Hz
1 1 13.5 0.68 Hz

1-4

When selecting a suitable F
frequency output at I
of 100 impulses /kWh should be compared with Column 4 of
Table 9. The frequency that is closest in Table 9 determines the
best choice of frequency (F
maximum current of 40 A is being designed, the output
frequency on F1 and F2 with a meter constant of
100 impulses /kWh is 0.266 Hz at 40 A and 240 V (from
Table 8). Looking at Table 9, the closest frequency to 0.266 Hz
in Column 4 is 0.17 Hz. Therefore, F2 (3.4 Hz; see Table 5) is
selected for this design.

Frequency Outputs

Figure 2 shows a timing diagram for the various frequency
outputs. The high frequency CF output is intended to be used
for communications and calibration purposes. CF produces a
90 ms wide, active high pulse (t
tional to active power. The CF output frequencies are given in
Table 7. As in the case of F1 and F2, if the period of CF (t
below 180 ms, the CF pulse width is set to half the period. For
example, if the CF frequency is 20 Hz, the CF pulse width is
25 ms.

Half-Scale AC Inputs

frequency for a meter design, the

1–4

(maximum load) with a meter constant

MAX

). For example, if a meter with a

1–4

) at a frequency that is propor-

4

) falls

5

No-Load Threshold

The ADE7760 also includes a no-load threshold and startup
current feature that eliminates any creep effects in the
meter. The ADE7760 is designed to issue a minimum output
frequency. Any load generating a frequency lower than this
minimum frequency does not cause a pulse to be issued on F1,
F2, or CF. The minimum output frequency is given as 0.0045%
of the full-scale output frequency. (See Table 7 for maximum
output frequencies for ac signals.)

For example, an energy meter with a meter constant of
100 impulses /kWh on F1, F2 using SCF = 1, S1 = 0, and S0 = 1,
the maximum output frequency at F1 or F2 would be 0.68 Hz
and 43.52 Hz on CF. The minimum output frequency at F1 or
F2 would be 0.0045% of 0.68 Hz or 3.06 × 10
be 1.96 × 10

–3

Hz at CF (64 × F1 Hz). In this example, the no-

–5

Hz. This would

load threshold would be equivalent to 1.1 W of load or a startup
current of 4.6 mA at 240 V. Compare this value to the IEC61036
specification, which states that the meter must start up with a
load equal to or less than 0.4% I

. For a 5 A (IB) meter, 0.4% of IB

B

is equivalent to 20 mA.

Note that the no-load threshold is not enabled when using the
high CF frequency mode: SCF = 0, S1 = S0 = 1.

NEGATIVE POWER INFORMATION

The ADE7760 detects when the current and voltage channels
have a phase shift greater than 90
wrong connection of the meter or generation of negative power.
The REVP pin output goes active high when negative power is
detected and active low, when positive power is detected. The
REVP pin output changes state as a pulse is issued on CF.

°. This mechanism can detect

Rev. 0 | Page 20 of 24

ADE7760

OUTLINE DIMENSIONS

7.50

7.20

6.90

20 11

5.60

5.30

8.20

5.00

0.05 MIN
COPLANARITY

0.10

1

2.00 MAX

0.65

BSC

COMPLIANT TO JEDEC STANDARDS MO-150AE

0.38

0.22

1.85

1.75

1.65

10

Figure 27. 20-Lead Shrink Small Outline Package [SSOP]

Dimensions shown in millimeters

SEATING
PLANE

(RS-20)

0.25

0.09

7.80

7.40

8°
4°
0°

0.95

0.75

0.55

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADE7760ARS –40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADE7760ARSRL –40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20

Rev. 0 | Page 21 of 24

ADE7760

NOTES

Rev. 0 | Page 22 of 24

ADE7760

NOTES

Rev. 0 | Page 23 of 24

ADE7760

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04434–0–1/04(0)

Rev. 0 | Page 24 of 24