Datasheet ADE7753 Datasheet (Analog Devices)

Page 1

Single-Phase Multifunction Metering IC

FEATURES

High accuracy; supports IEC 60687/61036/61268 and IEC 62053-21/62053-22/62053-23 On-chip digital integrator enables direct interface to current sensors with di/dt output Active, reactive, and apparent energy; sampled waveform; current and voltage rms Less than 0.1% error in active energy measurement over a dynamic range of 1000 to 1 at 25°C Positive-only energy accumulation mode available On-chip user programmable threshold for line voltage surge and SAG and PSU supervisory Digital calibration for power, phase, and input offset On-chip temperature sensor (±3°C typical) SPI® compatible serial interface Pulse output with programmable frequency Interrupt request pin ( Reference 2.4 V with external overdrive capability Single 5 V supply, low power (25 mW typical)

GENERAL DESCRIPTION

The ADE7753 features proprietary ADCs and DSP for high accuracy over large variations in environmental conditions and time. The ADE7753 incorporates two second-order 16-bit Σ-∆ ADCs, a digital integrator (on CH1), reference circuitry, temperature sensor, and all the signal processing required to perform active, reactive, and apparent energy measurements, line-voltage period measurement, and rms calculation on the

IRQ

) and status register

with di/dt Sensor Interface

ADE7753

voltage and current. The selectable on-chip digital integrator provides direct interface to di/dt current sensors such as Rogowski coils, eliminating the need for an external analog integrator and resulting in excellent long-term stability and precise phase matching between the current and voltage channels.

The ADE7753 provides a serial interface to read data, and a pulse output frequency (CF), which is proportional to the active power. Various system calibration features, i.e., channel offset correction, phase calibration, and power calibration, ensure high accuracy. The part also detects short duration low or high voltage variations.

The positive-only accumulation mode gives the option to accumulate energy only when positive power is detected. An internal no-load threshold ensures that the part does not exhibit any creep when there is no load. The zero-crossing output (ZX) produces a pulse that is synchronized to the zero-crossing point of the line voltage. This signal is used internally in the line cycle active and apparent energy accumulation modes, which enables faster calibration.

The interrupt status register indicates the nature of the interrupt, and the interrupt enable register controls which event produces

IRQ

an output on the

The ADE7753 is available in a 20-lead SSOP package.

pin, an open-drain, active low logic output.

FUNCTIONAL BLOCK DIAGRAM

AVDD

PGA V1P V1N

V2P

SENSOR

PGA

2.4V

REFERENCE

AGND

ADC

TEMP

ADC

IN/OUT

*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

RESET

HPF1

PHCAL[5:0]

INTEGRATOR



LPF1

CLKIN

CLKOUT

MULTIPLIER

IRMSOS[11:0]

VRMSOS[11:0]

Figure 1.

DVDD DGND

APOS[15:0]

VADIV[7:0]

WGAIN[11:0]

VAGAIN[11:0]

REGISTERS AND

SERIAL INTERFACE

DIN DOUT SCLKREF

% %

LPF2

DFC

WDIV[7:0]

CS IRQ

ADE7753

CFNUM[11:0]

CFDEN[11:0]

SAG

02875-A-001

www.analog.com

Page 2

ADE7753

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Te r m in o l o g y ...................................................................................... 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics........................................... 10

Theory of Operation ...................................................................... 15

Analog Inputs.............................................................................. 15

di/dt Current Sensor and Digital Integrator ...........................16

Zero-Crossing Detection........................................................... 17

Period Measurement.................................................................. 18

Power Supply Monitor ............................................................... 18

Line Voltage Sag Detection........................................................ 18

Peak Detection ............................................................................ 19

ADE7753 Interrupts................................................................... 20

Temperature Measurement ....................................................... 21

ADE7753 Analog-to-Digital Conversion................................ 21

Channel 1 ADC........................................................................... 22

Channel 2 ADC........................................................................... 24

Phase Compensation.................................................................. 26

Active Power Calculation .......................................................... 27

Energy Calculation..................................................................... 28

Power Offset Calibration ........................................................... 30

Energy-to-Frequency Conversion ........................................... 30

Line Cycle Energy Accumulation Mode ................................. 32

Positive-Only Accumulation Mode ......................................... 32

No-Load Threshold.................................................................... 32

Reactive Power Calculation ...................................................... 33

Sign of Reactive Power Calculation......................................... 34

Apparent Power Calculation ..................................................... 34

Apparent Energy Calculation ................................................... 35

Line Apparent Energy Accumulation...................................... 36

Energies Scaling.......................................................................... 37

Calibrating an Energy Meter Based on the ADE7753........... 37

CLKIN Frequency ...................................................................... 47

Suspending ADE7753 Functionality........................................ 47

Checksum Register..................................................................... 47

ADE7753 Serial Interface.......................................................... 48

ADE7753 Registers......................................................................... 51

ADE7753 Register Descriptions................................................... 54

Communications Register......................................................... 54

Mode Register (0x09)................................................................. 54

Interrupt Status Register (0x0B), Reset Interrupt Status

............... 56

CH1OS Register (0x0D)............................................................ 57

Outline Dimensions....................................................................... 58

Ordering Guide .......................................................................... 58

REVISION HISTORY

6/04—Changed from Rev. 0 to Rev A

Changes IEC Standards ................................................................... 1

Changes to Phase Error Between Channels Definition............... 7

Changes to Figure 24...................................................................... 13

Changes to CH2OS Register ......................................................... 16

Change to the Period Measurement Section............................... 18

Change to Temperature Measurement Section ..........................21

Changes to Figure 69...................................................................... 31

Rev. A | Page 2 of 60

Changes to Figure 71...................................................................... 33

Changes to the Apparent Energy Section.................................... 36

Changes to Energies Scaling Section ........................................... 37

Changes to Calibration Section.................................................... 37

8/03—Revision 0: Initial Version

Page 3

ADE7753

SPECIFICATIONS

AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, T

MIN

to T

= –40°C to +85°C.

MAX

Table 1.

Parameter

Spec Unit Test Conditions/Comments

ENERGY MEASUREMENT ACCURACY

Active Power Measurement Error CLKIN = 3.579545 MHz

Channel 1 Range = 0.5 V Full Scale Channel 2 = 300 mV rms/60 Hz, gain = 2

Gain = 1 0.1 % typ Over a dynamic range 1000 to 1 Gain = 2 0.1 % typ Over a dynamic range 1000 to 1 Gain = 4 0.1 % typ Over a dynamic range 1000 to 1 Gain = 8 0.1 % typ Over a dynamic range 1000 to 1

Channel 1 Range = 0.25 V Full Scale

Gain = 1 0.1 % typ Over a dynamic range 1000 to 1 Gain = 2 0.1 % typ Over a dynamic range 1000 to 1 Gain = 4 0.1 % typ Over a dynamic range 1000 to 1 Gain = 8 0.2 % typ Over a dynamic range 1000 to 1

Channel 1 Range = 0.125 V Full Scale

Gain = 1 0.1 % typ Over a dynamic range 1000 to 1 Gain = 2 0.1 % typ Over a dynamic range 1000 to 1 Gain = 4 0.2 % typ Over a dynamic range 1000 to 1

Gain = 8 0.2 % typ Over a dynamic range 1000 to 1 Active Power Measurement Bandwidth 14 kHz Phase Error 1 between Channels AC Power Supply Rejection

±0.05 max Line Frequency = 45 Hz to 65 Hz, HPF on AVDD = DVDD = 5 V + 175 mV rms/120 Hz

Output Frequency Variation (CF) 0.2 % typ Channel 1 = 20 mV rms, gain = 16, range = 0.5 V

Channel 2 = 300 mV rms/60 Hz, gain = 1

DC Power Supply Rejection

AVDD = DVDD = 5 V ± 250 mV dc Output Frequency Variation (CF) ±0.3 % typ Channel 1 = 20 mV rms/60 Hz, gain = 16, range = 0.5 V Channel 2 = 300 mV rms/60 Hz, gain = 1 IRMS Measurement Error 0.5 % typ Over a dynamic range 100 to 1 IRMS Measurement Bandwidth 14 kHz VRMS Measurement Error 0.5 % typ Over a dynamic range 20 to 1 VRMS Measurement Bandwidth 140 Hz

ANALOG INPUTS

See the Analog Inputs section

Maximum Signal Levels ±0.5 V max V1P, V1N, V2N, and V2P to AGND Input Impedance (dc) 390 k min Bandwidth 14 kHz CLKIN/256, CLKIN = 3.579545 MHz Gain Error

2, 3

External 2.5 V reference, gain = 1 on Channels 1 and 2 Channel 1

Range = 0.5 V Full Scale ±4 % typ V1 = 0.5 V dc Range = 0.25 V Full Scale ±4 % typ V1 = 0.25 V dc Range = 0.125 V Full Scale ±4 % typ V1 = 0.125 V dc

Channel 2 ±4 % typ V2 = 0.5 V dc

Offset Error

±32 mV max Gain 1 Channel 1 ±13 mV max Gain 16 ±32 mV max Gain 1 Channel 2 ±13 mV max Gain 16

WAVEFORM SAMPLING Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS

Channel 1 See the Channel 1 Sampling section

Signal-to-Noise Plus Distortion 62 dB typ 150 mV rms/60 Hz, range = 0.5 V, gain = 2 Bandwidth(–3 dB) 14 kHz CLKIN = 3.579545 MHz

Footnotes on next page.

Rev. A | Page 3 of 60

Page 4

ADE7753

Parameter Spec Unit Test Conditions/Comments

Channel 2 See the Channel 2 Sampling section

Signal-to-Noise Plus Distortion 60 dB typ 150 mV rms/60 Hz, gain = 2

Bandwidth (–3 dB) 140 Hz CLKIN = 3.579545 MHz REFERENCE INPUT REF

2.2 V min 2.4 V – 8% Input Capacitance 10 pF max

ON-CHIP REFERENCE Nominal 2.4 V at REF

Reference Error ±200 mV max Current Source 10 µA max Output Impedance 3.4 kΩ min Temperature Coefficient 30 ppm/°C typ

CLKIN All specifications CLKIN of 3.579545 MHz

Input Clock Frequency 4 MHz max

1 MHz min LOGIC INPUTS

RESET Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

LOGIC OUTPUTS

SAG Output High Voltage, V Output Low Voltage, V ZX and DOUT Output High Voltage, V Output Low Voltage, V CF Output High Voltage, V Output Low Voltage, V

POWER SUPPLY For specified performance

AVDD 4.75 V min 5 V – 5%

5.25 V max 5 V + 5% DVDD 4.75 V min 5 V – 5%

5.25 V max 5 V + 5% AI DI

_______________________________________________

See the plots in the Typical Performance Characteristics section.

See the Terminology section for explanation of specifications.

See the Analog Inputs section.

Input Voltage Range 2.6 V max 2.4 V + 8%

IN/OUT

, DIN, SCLK, CLKIN, and

IRQ

and

INH

INL

2.4 V min DVDD = 5 V ± 10%

0.8 V max DVDD = 5 V ± 10% ±3 µA max Typically 10 nA, VIN = 0 V to DV 10 pF max

Open-drain outputs, 10 kΩ pull-up resistor 4 V min I

0.4 V max I

4 V min I

0.4 V max I

4 V min I 1 V max I

3 mA max Typically 2.0 mA 4 mA max Typically 3.0 mA

200 µA

SOURCE

= 0.8 mA

SINK

SOURCE

= 0.8 mA

SINK

SOURCE

= 7 mA

SINK

= 5 mA

IN/OUT

OUTPUT

50pF

1.6mA

+2.1V

02875-0-002

Figure 2. Load Circuit for Timing Specifications

Rev. A | Page 4 of 60

Page 5

ADE7753

TIMING CHARACTERISTICS

AVDD = DV = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, T

DD MIN

Table 2.

Parameter

1, 2

Spec Unit Test Conditions/Comments

Write Timing

50 ns (min)

CS falling edge to first SCLK falling edge.

50 ns (min) SCLK logic high pulse width. 50 ns (min) SCLK logic low pulse width. 10 ns (min) Valid data setup time before falling edge of SCLK. 5 ns (min) Data hold time after SCLK falling edge. 400 ns (min) Minimum time between the end of data byte transfers. 50 ns (min) Minimum time between byte transfers during a serial write. 100 ns (min)

CS hold time after SCLK falling edge.

Read Timing

4 µs (min) Minimum time between read command (i.e., a write to

communication register) and data read.

50 ns (min) Minimum time between data byte transfers during a multibyte read. 30 ns (min) Data access time after SCLK rising edge following a write to the

communications register.

100 ns (max) Bus relinquish time after falling edge of SCLK.

10 ns (min)

100 ns (max)

Bus relinquish time after rising edge of

10 ns (min)

___________________________________

Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns

(10% to 90%) and timed from a voltage level of 1.6 V.

See Figure 3, Figure 4, and the ADE7753 Serial Interface section.

Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min.

Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

SCL

DIN

A4A5 A3

DB7

DB0

DB7

to T

= –40°C to +85°C.

MAX

DB0

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

02875-0-081

Figure 3. Serial Write Timing

SCLK

DIN

DOUT

A4A5 A3

COMMAND BYTE

DB7

MOST SIGNIFICANT BYTE

DB0

LEAST SIGNIFICANT BYTE

DB0DB7

02875-0-083

Figure 4. Serial Read Timing

Rev. A | Page 5 of 60

Page 6

ADE7753

ABSOLUTE MAXIMUM RATINGS

T = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to AGND –0.3 V to +7 V DVDD to DGND –0.3 V to +7 V DVDD to AVDD –0.3 V to +0.3 V Analog Input Voltage to AGND

V1P, V1N, V2P, and V2N

Reference Input Voltage to AGND –0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND –0.3 V to DVDD + 0.3 V Operating Temperature Range Industrial –40°C to +85°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C 20-Lead SSOP, Power Dissipation 450 mW θJA Thermal Impedance 112°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

–6 V to +6 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 6 of 60

Page 7

ADE7753

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the ADE7753 is defined by the following formula:

⎛ ⎜

ErrorPercentage

⎜ ⎝

EnergyTrue

7753

−

⎞

EnergyTrueADERegisterEnergy

⎟

%100

⎟ ⎠

supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see the Measurement Error definition.

For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading.

Phase Error between Channels

The digital integrator and the high-pass filter (HPF) in Channel 1 have a non-ideal phase response. To offset this phase response and equalize the phase response between channels, two phasecorrection networks are placed in Channel 1: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and ensure a phase match between Channel 1 (current) and Channel 2 (voltage) to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz.

Power Supply Rejection

This quantifies the ADE7753 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when an ac (175 mV rms/120 Hz) signal is introduced onto the

ADC Offset Error

The dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection—see the Typical Performance Characteristics section. However, when HPF1 is switched on, the offset is removed from Channel 1 (current) and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration—see the Analog Inputs section.

Gain Error

The difference between the measured ADC output code (minus the offset) and the ideal output code—see the Channel 1 ADC and Channel 2 ADC sections. It is measured for each of the input ranges on Channel 1 (0.5 V, 0.25 V, and 0.125 V). The difference is expressed as a percentage of the ideal code.

Rev. A | Page 7 of 60

Page 8

ADE7753

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RESET

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

RESET

Reset Pin for the ADE7753. A logic low on this pin holds the ADCs and digital circuitry (including the serial interface) in a reset condition.

2 DVDD

Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7753. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

3 AVDD

Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7753. The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The typical performance graphs show the power supply rejection performance. This pin should be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

4, 5 V1P, V1N

Analog Inputs for Channel 1. This channel is intended for use with a di/dt current transducer such as a Rogowski coil or another current sensor such as a shunt or current transformer (CT). These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the full-scale selection—see the Analog Inputs section. Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry, and, in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage.

6, 7 V2N, V2P

Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs are fully differential voltage inputs with a maximum differential signal level of ±0.5 V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry, and an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage.

8 AGND

Analog Ground Reference. This pin provides the ground reference for the analog circuitry in the ADE7753, i.e., ADCs and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, for example, anti-aliasing filters, current and voltage transducers, etc. To keep ground noise around the ADE7753 to a minimum, the quiet ground plane should connected to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane.

9 REF

IN/OUT

Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 µF ceramic capacitor.

10 DGND

Digital Ground Reference. This pin provides the ground reference for the digital circuitry in the ADE7753, i.e., multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7753 are small, it is acceptable to connect this pin to the analog ground plane of the system. However, high bus capacitance on the DOUT pin could result in noisy digital current, which could affect performance.

11 CF

Calibration Frequency Logic Output. The CF logic output gives active power information. This output is intended to be used for operational and calibration purposes. The full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM registers—see the Energy-to-Frequency Conversion section.

DVDD AVDD

3 4

V1P

ADE7753

V1N

TOP VIEW

(Not to Scale)

7 8 9

02875-0-005

REF

V2N V2P

AGND

IN/OUT

DGND

Figure 5. Pin Configuration (SSOP Package)

DIN

DOUT SCLK

CS CLKOUT

CLKIN

15 14

IRQ SAG

Rev. A | Page 8 of 60

Page 9

ADE7753

Pin No. Mnemonic Description

12 ZX

SAG This open-drain logic output goes active low when either no zero crossings are detected or a low voltage

IRQ Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include active

15 CLKIN

16 CLKOUT

CS Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7753 to share

18 SCLK

19 DOUT

20 DIN

Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the zero crossing of the differential signal on Channel 2—see the Zero-Crossing Detection section.

threshold (Channel 2) is crossed for a specified duration—see the Line Voltage Sag Detection section.

energy register rollover, active energy register at half level, and arrivals of new waveform samples—see the ADE7753 Interrupts section.

Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7753. The clock frequency for specified operation is 3.579545 MHz. Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for load capacitance requirements.

A crystal can be connected across this pin and CLKIN as described for Pin 15 to provide a clock source for the ADE7753. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used.

the serial bus with several other devices—see the ADE7753 Serial Interface section. Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this

clock—see the ADE7753 Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source that has a slow edge transition time, for example, opto-isolator output.

Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state unless it is driving data onto the serial data bus—see the ADE7753 Serial Interface section.

Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see the ADE7753 Serial Interface section.

Rev. A | Page 9 of 60

Page 10

ADE7753

TYPICAL PERFORMANCE CHARACTERISTICS

0.5

0.4

0.3

0.2

+25°C, PF = 1

0.1

–0.1

ERROR (%)

–0.2

–0.3 –0.4 –0.5

0.1

+85°C, PF = 0.5

1 10 100

FULL-SCALE CURRENT (%)

Figure 6. Active Energy Error as a Percentage of Reading (Gain = 1) over

Power Factor with Internal Reference and Integrator Off

GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE

–40°C, PF = 0.5

+25°C, PF = 0.5

02875-0-006

0.3

GAIN = 8

0.2

0.1

ERROR (%)

–0.1

–0.2

–0.3

0.1

+85°C, PF = 1

+25°C, PF = 1

–40°C, PF = 1

1 10 100

FULL-SCALE CURRENT (%)

INTEGRATOR OFF EXTERNAL REFERENCE

02875-0-010

Figure 9. Active Energy Error as a Percentage of Reading (Gain = 8) over

Temperature with External Reference and Integrator Off

0.4

0.3

0.2

0.1

ERROR (%)

–0.1

–0.2

–0.3

–0.4

0.1

+85°C, PF = 1

+25°C, PF = 1

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE

–40°C, PF = 1

02875-0-008

Figure 7. Active Energy as a Percentage of Reading (Gain = 8) over

Temperature with Internal Reference and Integrator Off

0.8

0.6

0.4

0.2

ERROR (%)

–0.2

–0.4

–0.6

0.1

+25°C, PF = 1

–40°C, PF = 0.5

+85°C, PF = 0.5

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE

+25°C, PF = 0.5

02875-0-009

Figure 8. Active Energy Error as a Percentage of Reading (Gain = 8) over

Power Factor with Internal Reference and Integrator Off

0.6 GAIN = 8

0.4

0.2

ERROR (%)

–0.2

–0.4

–0.6

0.1

+25°C, PF = 1

+25°C, PF = 0.5

+85°C, PF = 0.5

–40°C, PF = 0.5

1 10 100

FULL-SCALE CURRENT (%)

INTEGRATOR OFF EXTERNAL REFERENCE

02875-0-011

Figure 10. Active Energy Error as a Percentage of Reading (Gain = 8) over

Power Factor with External Reference and Integrator Off

0.5

0.4

0.3

0.2

0.1

–0.1

ERROR (%)

–0.2

–0.3 –0.4 –0.5

0.1

+25°C, PF = 0

–40°C, PF = 0.5

+85°C, PF = 0.5

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE

+25°C, PF = 0.5

02875-0-012

Figure 11. Reactive Energy Error as a Percentage of Reading (Gain = 1) over

Power Factor with Internal Reference and Integrator Off

Rev. A | Page 10 of 60

Page 11

ADE7753

0.5

0.4

0.3

0.2

0.1

–0.1

ERROR (%)

–0.2

–0.3 –0.4 –0.5

0.1

+25°C, PF = 0

+25°C, PF = 0.5

–40°C, PF = 0.5

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 1 INTEGRATOR OFF EXTERNAL REFERENCE

+85°C, PF = 0.5

02875-0-013

Figure 12. Reactive Energy Error as a Percentage of Reading (Gain = 1) over

Power Factor with External Reference and Integrator Off

0.35

0.25

0.15

0.05

–0.05

ERROR (%)

–0.15

–0.25

–0.35

0.1

+85°C, PF = 0

+25°C, PF = 0

–40°C, PF = 0

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE

02875-0-016

Figure 15. Reactive Energy Error as a Percentage of Reading (Gain = 8) over

Temperature with External Reference and Integrator Off

0.20

0.15 –40°C, PF = 0

0.10

0.05

ERROR (%)

–0.05

–0.10

–0.15

–0.20

0.1

+25°C, PF = 0

+85°C, PF = 0

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE

02875-0-014

Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 8) over

Temperature with Internal Reference and Integrator Off

0.3

GAIN = 8

0.2

0.1

ERROR (%)

–0.1

–0.2

–40°C, PF = 0.5

+25°C, PF = 0

+85°C, PF = 0.5

INTEGRATOR OFF INTERNAL REFERENCE

+25°C, PF = 0.5

0.5

0.4

0.3

0.2

0.1

–0.1

ERROR (%)

–0.2

–0.3 –0.4 –0.5

0.1

+25°C, PF = 0

+85°C, PF = 0.5

–40°C, PF = 0.5

+25°C, PF = 0.5

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE

02875-0-017

Figure 16. Reactive Energy Error as a Percentage of Reading (Gain = 8) over

Power Factor with External Reference and Integrator Off

0.3

0.2

0.1

ERROR (%)

–0.1

–0.2

5.25V

5.0V

GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE

4.75V

–0.3

0.1

1 10 100

FULL-SCALE CURRENT (%)

02875-0-015

Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 8) over

Power Factor with Internal Reference and Integrator Off

Rev. A | Page 11 of 60

–0.3

0.1

1 10 100

FULL-SCALE CURRENT (%)

02875-0-018

Figure 17. Active Energy Error as a Percentage of Reading (Gain = 8) over

Power Supply with Internal Reference and Integrator O ff

Page 12

ADE7753

0.1

0.8

0.6

0.4

0.2

–0.2

ERROR (%)

–0.4

–0.6 –0.8 –0.1

50 55 60 6

PF = 1

PF = 0.5

LINE FREQUENCY (Hz)

Figure 18. Active Energy Error as a Percentage of Reading (Gain = 8) over

Frequency with External Reference and Integrator O ff

GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE

02875-0-019

1.0

0.8

0.6

0.4

0.2

–0.2

ERROR (%)

–0.4

–0.6 –0.8 –1.0

0.1

–40°C, PF = 1

85°C, PF = 1

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE

25°C, PF = 1

02875-0-023

Figure 21. Active Energy Error as a Percentage of Reading (Gain = 8) over

Temperature with Internal Reference and Integrator On

0.5

0.4

0.3

0.2

0.1

–0.1

ERROR (%)

–0.2

–0.3 –0.4 –0.5

0.1

PF = 0.5

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE

PF = 1

02875-0-020

Figure 19. IRMS Error as a Percentage of Reading (Gain = 8) with

Internal Reference and Integrator Off

1.0

0.8

0.6

0.4

0.2

–0.2

ERROR (%)

–0.4

–0.6 –0.8 –1.0

0.1

–40°C, PF = 0.5

+25°C, PF = 0.5

+85°C, PF = 0.5

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE

+25°C, PF = 1

02875-0-022

Figure 20. Active Energy Error as a Percentage of Reading (Gain = 8) over

Power Factor with Internal Reference an

Integrator On

1.0

0.8

0.6

0.4

0.2

–0.2

ERROR (%)

–0.4

–0.6 –0.8 –1.0

0.1

+25°C, PF = 0

–40°C, PF = 0.5

+85°C, PF = 0.5

+25°C, PF = 0.5

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE

02875-0-024

Figure 22. Reactive Energy Error as a Percentage of Reading (Gain = 8) over

Power Factor with Internal Reference and Integrator On

1.0

0.8

0.6

0.4

0.2

–0.2

ERROR (%)

–0.4

–0.6 –0.8 –1.0

0.1

–40°C, PF = 0

+25°C, PF = 0

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE

+85°C, PF = 0

02875-0-025

Figure 23. Reactive Energy Error as a Percentage of Reading (Gain = 8) over

Temperature with Internal Reference and Integrator On

Rev. A | Page 12 of 60

Page 13

ADE7753

3.0

2.5

2.0

1.5

1.0

0.5

ERROR (%)

–0.5

–1.0

–1.5

–2.0

45 47 49 51 53 55 57 59 61 63 65

PF = 0.5

PF = 1

FREQUENCY (Hz)

GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE

02875-0-026

Figure 24. Active Energy Error as a Percentage of Reading (Gain = 8) over

Power Factor with Internal Reference and Integrator On

0.3

0.8

0.6

0.4

0.2

ERROR (%)

–0.2

–0.4

–0.6

–0.8

FULL-SCALE VOLTAGE

GAIN = 1 EXTERNAL REFERENCE

10 100

02875-0-029

Figure 27. VRMS Error as a Percentage of Reading (Gain = 1) with

External Reference

0.2

0.1

ERROR (%)

–0.1

–0.2

–0.3

0.1

5.25V

5.0V

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE

4.75V

02875-0-027

Figure 25. Active Energy Error as a Percentage of Reading (Gain = 8) over

Power Supply with Internal Reference and Integrator On

0.5

0.4

0.3

0.2

0.1

–0.1

ERROR (%)

–0.2

–0.3 –0.4 –0.5

0.1

PF = 1

PF = 0.5

1 10 100

FULL-SCALE CURRENT (%)

GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE

02875-0-028

Figure 26. IRMS Error as a Percentage of Reading (Gain = 8) with

Internal Reference and Integrator On

HITS

–15 –12 –9 –6 –3

CH1 OFFSET (0p5V_1X) (mV)

036

02875-0-087

Figure 28. Channel 1 Offset (Gain = 1)

Rev. A | Page 13 of 60

Page 14

ADE7753

di/dt CURRENT SENSOR

110V

CHANNEL 1 GAIN = 8 CHANNEL 2 GAIN = 1

10µF

100Ω 1kΩ

33nF 33nF

100Ω 1kΩ 33nF

1kΩ

600kΩ

1kΩ

10µF

100nF 100nF

AVDD DVDD

V1P

33nF

100nF

V1N

ADE7753

V2N

V2P

REF

IN/OUT

AGND DGND

RESET

DIN

DOUT

SCLK

CLKOUT

CLKIN

IRQ

SAG

ZX CF

TOSPI BUS (USED ONLY FOR CALIBRATION)

3.58MHz

NOT CONNECTED

Figure 29. Test Circuit for Performance Curves with Integrator On

10µF

22pF

PS2501-1

22pF

TO FREQUENCY COUNTER

02875-A-012

110V

CT TURN RATIO = 1800:1 CHANNEL 2 GAIN = 1 GAIN 1 (CH1)

10µF1µF

CURRENT TRANSFORMER

1kΩ

600kΩ

1kΩ

10µF

1 8

100nF 100nF

1kΩ

33nF

1kΩ

33nF

100nF

10Ω

1.21Ω

AVDD DVDD

V1P

V1N

V2N

V2P

REF

ADE7753

CLKOUT

IN/OUT

AGND DGND

RESET

DIN

DOUT SCLK

CLKIN

IRQ

SAG

ZX CF

TOSPI BUS (USED ONLY FOR CALIBRATION)

22pF

PS2501-1

22pF

TO FREQUENCY COUNTER

02875-0-030

3.58MHz

NOT CONNECTED

Figure 30. Test Circuit for Performance Curves with Integrator Off

Rev. A | Page 14 of 60

Page 15

ADE7753

THEORY OF OPERATION

ANALOG INPUTS

The ADE7753 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N is ±0.5 V. In addition, the maximum signal level on analog inputs for V1P/V1N and V2P/ V2N is ±0.5 V with respect to AGND.

Each analog input channel has a programmable gain amplifier (PGA) with possible gain selections of 1, 2, 4, 8, and 16. The gain selections are made by writing to the gain register—see Figure 32. Bits 0 to 2 select the gain for the PGA in Channel 1, and the gain selection for the PGA in Channel 2 is made via Bits 5 to 7. Figure 31 shows how a gain selection for Channel 1 is made using the gain register.

76 5 4 3 2 1 0 00 0 0 0 0 0 0

V1P

V1N

7654 3210 0000 0000

CH1OS[7:0] BITS 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION BIT 6: NOT USED BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT OFF)

In addition to the PGA, Channel 1 also has a full-scale input range selection for the ADC. The ADC analog input range selection is also made using the gain register—see Figure 32. As mentioned previously, the maximum differential input voltage is

0.5 V. However, by using Bits 3 and 4 in the gain register, the maximum ADC input voltage can be set to 0.5 V, 0.25 V, or

0.125 V. This is achieved by adjusting the ADC reference—see the ADE7753 Reference Circuit section. Table 5 summarizes the maximum differential input signal level on Channel 1 for the various ADC range and gain selections.

GAIN[7:0]

GAIN (K) SELECTION

K × V

Figure 31. PGA in Channel 1

OFFSET ADJUST (±50mV)

02875-0-031

Table 5. Maximum Input Signal Levels for Channel 1

Max Signal ADC Input Range Selection Channel 1 0.5 V 0.25 V 0.125 V

0.5 V Gain = 1 − −

0.25 V Gain = 2 Gain = 1 −

0.125 V Gain = 4 Gain = 2 Gain = 1

0.0625 V Gain = 8 Gain = 4 Gain = 2

0.0313 V Gain = 16 Gain = 8 Gain = 4

0.0156 V − Gain = 16 Gain = 8

0.00781 V − − Gain = 16

CHANNEL 1 AND CHANNEL 2 PGA CONTROL

PGA 2 GAIN SELEC 000 =× 1

001 =

010 =

011 =

100 =

*REGISTER CONTENTS

GAIN REGISTER*

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0

SHOW POWER-ON DEFAULTS

ADDR: 0AH

PGA 1 GAIN SELECT

000 =

001 =

010 =

011 =

100 =

CHANNEL 1 FULL-SCALE SELECT 00 = 0.5V 01 = 0.25V 10 = 0.125V

Figure 32. ADE7753 Analog Gain Register

1 2 4 8 16

02875-0-032

It is also possible to adjust offset errors on Channel 1 and Channel 2 by writing to the offset correction registers, CH1OS and CH2OS, respectively. These registers allow channel offsets in the range ±20 mV to ±50 mV (depending on the gain setting) to be removed. Channel 1 and 2 offset registers are sign magnitude coded. A negative number is applied to the Channel 1 offset register, CH1OS, for a negative offset adjustment. Note that the Channel 2 offset register is inverted. A negative number is applied to CH2OS for a positive offset adjustment. It is not necessary to perform an offset correction in an energy measurement application if HPF in Channel 1 is switched on. Figure 33 shows the effect of offsets on the real power calculation. As seen from Figure 33, an offset on Channel 1 and Channel 2 contributes a dc component after multiplication. Because this dc component is extracted by LPF2 to generate the active (real) power information, the offsets contribute an error to the active power calculation. This problem is easily avoided by enabling HPF in Channel 1. By removing the offset from at least one channel, no error component is generated at dc by the multiplication. Error terms at cos(ωt) are removed by LPF2 and by integration of the active power signal in the active energy register (AENERGY[23:0]) —see the Energy Calculation section.

Rev. A | Page 15 of 60

Page 16

ADE7753

DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL

× I

V × I

Figure 33. Effect of Channel Offsets on the Real Power Calculation

POWER CALCULATION

× V

× I

2ωω

FREQUENCY (RAD/S)

02875-0-033

di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR

A di/dt sensor detects changes in magnetic field caused by ac current. Figure 35 shows the principle of a di/dt current sensor.

MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT)

The contents of the offset correction registers are 6-bit, sign and magnitude coded. The weight of the LSB depends on the gain setting, i.e., 1, 2, 4, 8, or 16. Table 6 shows the correctable offset span for each of the gain settings and the LSB weight (mV) for the offset correction registers. The maximum value that can be written to the offset correction registers is ±31d—see Figure 34. Figure 34 shows the relationship between the offset correction register contents and the offset (mV) on the analog inputs for a gain setting of 1. In order to perform an offset adjustment, the analog inputs should be first connected to AGND, and there should be no signal on either Channel 1 or Channel 2. A read from Channel 1 or Channel 2 using the waveform register indicates the offset in the channel. This offset can be canceled by writing an equal and opposite offset value to the Channel 1 offset register, or an equal value to the Channel 2 offset register. The offset correction can be confirmed by performing another read. Note when adjusting the offset of Channel 1, one should disable the digital integrator and the HPF.

Table 6. Offset Correction Range—Channels 1 and 2

Gain Correctable Span LSB Size

1 ±50 mV 1.61 mV/LSB

2 ±37 mV 1.19 mV/LSB 4 ±30 mV 0.97 mV/LSB

8 ±26 mV 0.84 mV/LSB 16 ±24 mV 0.77 mV/LSB

CH1OS[5:0]

+ EMF (ELECTROMOTIVE FORCE)

– INDUCED BY CHANGES IN

MAGNETIC FLUX DENSITY (di/dt)

02875-0-035

Figure 35. Principle of a di/dt Current Sensor

The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal, which is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE7753 has a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is switched off by default when the ADE7753 is powered up. Setting the MSB of CH1OS register turns on the integrator. Figure 36 to Figure 39 show the magnitude and phase response of the digital integrator.

–10

01,1111b

0x1F

0x00

0x3F

0mV

11,1111b

–50mV

Figure 34. Channel 1 Offset Correction Range (Gain = 1)

SIGN + 5 BITS

+50mV

OFFSET ADJUST

SIGN + 5 BITS

02875-0-034

–20

GAIN (dB)

–30

–40

–50

FREQUENCY (Hz)

02875-0-036

Figure 36. Combined Gain Response of the

Digital Integrator and Phase Compensator

The current and voltage rms offsets can be adjusted with the IRMSOS and VRMSOS registers—see Channel 1 RMS Offset Compensation and Channel 2 RMS Offset Compensation sections.

Rev. A | Page 16 of 60

Page 17

ADE7753

–88.0

–88.5

–89.0

–89.5

PHASE (Degrees)

–90.0

Note that the integrator has a –20 dB/dec attenuation and an approximately –90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. The di/dt sensor has a 20 dB/dec gain associated with it. It also generates significant high frequency noise, therefore a more effective antialiasing filter is needed to avoid noise due to aliasing—see the Antialias Filter section.

When the digital integrator is switched off, the ADE7753 can be used directly with a conventional current sensor such as a current transformer (CT) or with a low resistance current shunt.

–90.5

FREQUENCY (Hz)

FREQ

Figure 37. Combined Phase Response of the

Digital Integrator and Phase Compensator

–1.0

–1.5 –2.0

–2.5 –3.0

–3.5

GAIN (dB)

–4.0 –4.5

–5.0 –5.5

–6.0

40 7045

50 55 60 65

FREQUENCY (Hz)

Figure 38. Combined Gain Response of the

Digital Integrator and Phase Compensator (40 Hz to 70 Hz)

–89.70

–89.75

02875-0-037

02875-0-038

ZERO-CROSSING DETECTION

The ADE7753 has a zero-crossing detection circuit on Channel 2. This zero crossing is used to produce an external zero-crossing signal (ZX), and it is also used in the calibration mode—see the Calibrating an Energy Meter Based on the ADE7753 section. The zero-crossing signal is also used to initiate a temperature measurement on the ADE7753—see the Temperature Measurement section.

Figure 40 shows how the zero-crossing signal is generated from the output of LPF1.

1,×2,×1,

×8,×

V2P

V2N

1.0

0.93

{GAIN [7:5]}

PGA2

REFERENCE

ADC 2

–

2.32° @ 60Hz

LPF1

= 140Hz

3dB

–63%TO +63% FS

ZERO

CROSS

TO MULTIPL IER

–89.80

–89.85

–89.90

–89.95

PHASE (Degrees)

–90.00

–90.05

40 45 7050 55 60 65

FREQUENCY (Hz)

Figure 39. Combined Phase Response of the

Digital Integrator and Phase Compensator (40 Hz to 70 Hz)

02875-0-039

Figure 40. Zero-Crossing Detection on Channel 2

The ZX signal goes logic high on a positive-going zero crossing and logic low on a negative-going zero crossing on Channel 2. The zero-crossing signal ZX is generated from the output of LPF1. LPF1 has a single pole at 140 Hz (at CLKIN = 3.579545 MHz). As a result, there is a phase lag between the analog input signal V2 and the output of LPF1. The phase response of this filter is shown in the Channel 2 Sampling section. The phase lag response of LPF1 results in a time delay of approximately

1.14 ms (@ 60 Hz) between the zero crossing on the analog inputs of Channel 2 and the rising or falling edge of ZX.

LPF1

02875-0-040

Rev. A | Page 17 of 60

Page 18

ADE7753

The zero-crossing detection also drives the ZX flag in the

IRQ

interrupt status register. An active low in the appears if the corresponding bit in the interrupt enable register is set to Logic 1.

The flag in the interrupt status register as well as the are reset to their default values when the interrupt status register with reset (RSTSTATUS) is read.

Zero-Crossing Timeout

The zero-crossing detection also has an associated timeout register, ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) every 128/CLKIN seconds. The register is reset to its user programmed full-scale value every time a zero crossing is detected on Channel 2. The default power on value in this register is 0xFFF. If the internal register decrements to 0 before a zero crossing is detected and the DISSAG bit in the mode

SAG

pin goes active low. The absence of a

IRQ

enable bit in the interrupt enable register is set to Logic 1. Irrespective of the enable bit setting, the ZXTO flag in the interrupt status register is always set when the internal ZXTOUT register is decremented to 0—see the ADE7753 Interrupts section.

The ZXOUT register can be written/read by the user and has an address of 1Dh—see the ADE7753 Serial Interface section. The resolution of the register is 128/CLKIN seconds per LSB. Thus the maximum delay for an interrupt is 0.15 second (128/CLKIN

× 2

Figure 41 shows the mechanism of the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than CLKIN/128 × ZXTOUT seconds.

output also

IRQ

pin if the ZXTO

output

The resolution of this register is 2.2 ms/LSB when CLKIN =

3.579545 MHz, which represents 0.013% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the period register is approximately 7576d. The length of the register enables the measurement of line frequencies as low as

13.9 Hz.

The period register is stable at ±1 LSB when the line is established and the measurement does not change. A settling time of 1.8 seconds is associated with this filter before the measurement is stable.

POWER SUPPLY MONITOR

The ADE7753 also contains an on-chip power supply monitor. The analog supply (AVDD) is continuously monitored by the ADE7753. If the supply is less than 4 V ± 5%, then the ADE7753 goes into an inactive state, that is, no energy is accumulated when the supply voltage is below 4 V. This is useful to ensure correct device operation at power-up and during power-down. The power supply monitor has built-in hysteresis and filtering, which give a high degree of immunity to false triggering due to noisy supplies.

5V 4V

ADE7753

POWER-ON

INACTIVE

STATE

INACTIVE

TIME

ACTIVE INACTIVE

12-BIT INTERNAL

ZXTOUT

CHANNEL 2

ZXTO

DETECTION

BIT

Figure 41. Zero-Crossing Timeout Detection

02875-0-041

PERIOD MEASUREMENT

The ADE7753 also provides the period measurement of the line. The period register is an unsigned 16-bit register and is updated every period. The MSB of this register is always zero.

Rev. A | Page 18 of 60

SAG

02875-0-042

Figure 42. On-Chip Power Supply Monitor

As seen in Figure 42, the trigger level is nominally set at 4 V. The

SAG

tolerance on this trigger level is about ±5%. The

pin can also be used as a power supply monitor input to the MCU. The SAG

pin goes logic low when the ADE7753 is in its inactive state. The power supply and decoupling for the part should be such that the ripple at AVDD does not exceed 5 V ±5%, as specified for normal operation.

LINE VOLTAGE SAG DETECTION

In addition to the detection of the loss of the line voltage signal (zero crossing), the ADE7753 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles. This condition is illustrated in Figure 43.

Page 19

ADE7753

)

FULL SCALE

GLVL [7:0]

SAG

CHANNEL 2

SAGCYC [7:0] = 0x04

3 LINE CYCLES

Figure 43. ADE7753 Sag Detection

SAG RESET HIGH WHEN CHANNEL 2 EXCEEDS SAGLVL [7:0]

02875-0-043

Figure 43 shows the line voltage falling below a threshold that is set in the sag level register (SAGLVL[7:0]) for three line cycles. The quantities 0 and 1 are not valid for the SAGCYC register, and the contents represent one more than the desired number of full line cycles. For example, when the sag cycle (SAGCYC[7:0])

SAG

contains 0x04, the

pin goes active low at the end of the third line cycle for which the line voltage (Channel 2 signal) falls below the threshold, if the DISSAG bit in the mode register is Logic 0. As is the case when zero crossings are no longer detected, the sag event is also recorded by setting the SAG flag in the interrupt status register. If the SAG enable bit is set to

IRQ

Logic 1, the Interrupts section. The

logic output goes active low—see the ADE7753

SAG

pin goes logic high again when the absolute value of the signal on Channel 2 exceeds the sag level set in the sag level register. This is shown in Figure 43 when the SAG

pin goes high again during the fifth line cycle from the time when the signal on Channel 2 first dropped below the threshold level.

Sag Level Set

The contents of the sag level register (1 byte) are compared to the absolute value of the most significant byte output from LPF1 after it is shifted left by one bit, thus, for example, the nominal maximum code from LPF1 with a full-scale signal on Channel 2 is 0x2518—see the Channel 2 Sampling section. Shifting one bit left gives 0x4A30. Therefore writing 0x4A to the SAG level register puts the sag detection level at full scale. Writing 0x00 or 0x01 puts the sag detection level at 0. The SAG level register is compared to the most significant byte of a waveform sample after the shift left and detection is made when the contents of the sag level register are greater.

PEAK DETECTION

The ADE7753 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. Figure 44 illustrates the behavior of the peak detection for the voltage channel. Both Channel 1 and Channel 2 are monitored at the same time.

VPKLVL[7:0]

PKV RESET LOW WHEN RSTSTATUS REGISTER IS READ

PKV INTERRUPT

FLAG (BIT 8 OF

STATUS REGISTER

READ RSTSTATUS

Figure 44. ADE7753 Peak Level Detection

02875-0-088

Figure 44 shows a line voltage exceeding a threshold that is set in the voltage peak register (VPKLVL[7:0]). The voltage peak event is recorded by setting the PKV flag in the interrupt status register. If the PKV enable bit is set to Logic 1 in the interrupt mask register, the

IRQ

logic output goes active low. Similarly, the current peak event is recorded by setting the PKI flag in the interrupt status register—see the ADE7753 Interrupts section.

Peak Level Set

The contents of the VPKLVL and IPKLVL registers are respectively compared to the absolute value of Channel 1 and Channel 2 after they are multiplied by 2. Thus, for example, the nominal maximum code from the Channel 1 ADC with a fullscale signal is 0x2851EC—see the Channel 1 Sampling section. Multiplying by 2 gives 0x50A3D8. Therefore, writing 0x50 to the IPKLVL register, for example, puts the Channel 1 peak detection level at full scale and sets the current peak detection to its least sensitive value. Writing 0x00 puts the Channel 1 detection level at 0. The detection is done by comparing the contents of the IPKLVL register to the incoming Channel 1

IRQ

sample. The

pin indicates that the peak level is exceeded if the PKI or PKV bits are set in the interrupt enable register (IRQEN[15:0]) at Address 0x0A.

Peak Level Record

The ADE7753 records the maximum absolute value reached by Channel 1 and Channel 2 in two different registers—IPEAK and VPEAK, respectively. VPEAK and IPEAK are 24-bit unsigned registers. These registers are updated each time the absolute value of the waveform sample from the corresponding channel is above the value stored in the VPEAK or IPEAK register. The contents of the VPEAK register correspond to 2× the maximum absolute value observed on the Channel 2 input. The contents of IPEAK represent the maximum absolute value observed on the Channel 1 input. Reading the RSTVPEAK and RSTIPEAK registers clears their respective contents after the read operation.

Rev. A | Page 19 of 60

Page 20

ADE7753

ADE7753 INTERRUPTS

ADE7753 interrupts are managed through the interrupt status register (STATUS[15:0]) and the interrupt enable register (IRQEN[15:0]). When an interrupt event occurs in the ADE7753, the corresponding flag in the status register is set to Logic 1— see the Interrupt Status Register section. If the enable bit for this interrupt in the interrupt enable register is Logic 1, then the IRQ

logic output goes active low. The flag bits in the status

To determine the source of the interrupt, the system master (MCU) should perform a read from the status register with reset (RSTSTATUS[15:0]). This is achieved by carrying out a

IRQ

read from Address 0x0C. The completion of the interrupt status register read command—see the Interrupt Timing section. When carrying out a read with reset, the ADE7753 is designed to ensure that no interrupt events are missed. If an interrupt event occurs just as the status register is being read, the event is not lost and the output is guaranteed to go high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt. See the next section for a more detailed description.

IRQ

output goes logic high on

IRQ

logic

Using the ADE7753 Interrupts with an MCU

Figure 46 shows a timing diagram with a suggested implementation of ADE7753 interrupt management using an MCU. At

IRQ

, the line goes active low indicating that one or more

time t

IRQ

interrupt events have occurred in the ADE7753. The

logic output should be tied to a negative edge-triggered external interrupt on the MCU. On detection of the negative edge, the MCU should be configured to start executing its interrupt service routine (ISR). On entering the ISR, all interrupts should be disabled by using the global interrupt enable bit. At this point, the MCU external interrupt flag can be cleared to capture interrupt events that occur during the current ISR. When the MCU interrupt flag is cleared, a read from the status register

IRQ

with reset is carried out. This causes the logic high (t

)—see the Interrupt Timing section. The status

line to be reset

register contents are used to determine the source of the interrupt(s) and therefore the appropriate action to be taken. If a subsequent interrupt event occurs during the ISR, that event is recorded by the MCU external interrupt flag being set again (t

On returning from the ISR, the global interrupt mask is cleared (same instruction cycle), and the external interrupt flag causes the MCU to jump to its ISR once a gain. This ensures that the MCU does not miss any external interrupts.

MCU INTERRUPT

FLAG SET

MCU

PROGRAM

SEQUENCE

SCLK

DIN

DOUT

IRQ

JUMP

ISR

GLOBAL

INTERRUPT

MASK SET

CLEAR MCU INTERRUPT

FLAG

READ

STATUS WITH

RESET (0x05)

Figure 45. ADE7753 Interrupt Management

000 00101

READ STATUS REGISTER COMMAND

Figure 46. ADE7753 Interrupt Timing

ISR ACTION

(BASED ON STATUS CONTENTS)

DB7 DB7DB0

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

STATUS REGISTER CONTENTS

DB0

02875-0-045

JUMP

ISR

02875-0-044

Rev. A | Page 20 of 60

Page 21

ADE7753

Interrupt Timing

The ADE7753 Serial Interface section should be reviewed first before reviewing the interrupt timing. As previously described,

IRQ

when the

output goes low, the MCU ISR must read the interrupt status register to determine the source of the interrupt. When reading the status register contents, the

IRQ

output is set high on the last falling edge of SCLK of the first byte transfer (read interrupt status register command). The

IRQ

output is held high until the last bit of the next 15-bit transfer is shifted out (interrupt status register contents)—see Figure 45. If an interrupt is pending at this time, the If no interrupt is pending, the

IRQ

output goes low again.

IRQ

output stays high.

TEMPERATURE MEASUREMENT

The ADE7753 also includes an on-chip temperature sensor. A temperature measurement can be made by setting Bit 5 in the mode register. When Bit 5 is set logic high in the mode register, the ADE7753 initiates a temperature measurement on the next zero crossing. When the zero crossing on Channel 2 is detected, the voltage output from the temperature sensing circuit is connected to ADC1 (Channel 1) for digitizing. The resulting code is processed and placed in the temperature register (TEMP[7:0]) approximately 26 µs later (24 CLKIN cycles). If

IRQ

enabled in the interrupt enable register (Bit 5), the

output

goes active low when the temperature conversion is finished.

The contents of the temperature register are signed (twos complement) with a resolution of approximately 1.5 LSB/°C. The temperature register produces a code of 0x00 when the ambient temperature is approximately −25°C. The temperature measurement is uncalibrated in the ADE7753 and has an offset tolerance as high as ±25°C.

ADE7753 ANALOG-TO-DIGITAL CONVERSION

The analog-to-digital conversion in the ADE7753 is carried out using two second-order Σ-∆ ADCs. For simplicity, the block diagram in Figure 47 shows a first-order Σ-∆ ADC. The converter is made up of the Σ-∆ modulator and the digital lowpass filter.

REF

1-BIT DAC

MCLK/4

LATCHED COMPARATOR

+ –

.....10100101.....

-∆ ADC

02875-0-046

DIGITAL

LOW-PASS

FILTER

ANALOG

LOW-PASS FILTER

INTEGRATOR

–

Figure 47. First-Order

A Σ-∆ modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE7753, the sampling clock is equal to CLKIN/4. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC output (and therefore the bit stream) can approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. Only when a large number of samples are averaged is a meaningful result obtained. This averaging is carried out in the second part of the ADC, the digital low-pass filter. By averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit data-words that are proportional to the input signal level.

The Σ-∆ converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency), which is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7753 is CLKIN/4 (894 kHz) and the band of interest is 40 Hz to 2 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered—see Figure 48. However, oversampling alone is not efficient enough to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling ratio of 4 is required just to increase the SNR by only 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. In the Σ-∆ modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. The result is that most of the noise is at the higher frequencies where it can be removed by the digital low-pass filter. This noise shaping is shown in Figure 48.

ANTILALIAS

FILTER (RC)

IGNAL

NOISE

IGNAL

NOISE

DIGITAL

FILTER

FREQUENCY (kHz)

HIGH RESOLUTION

OUTPUT FROM DIGITAL

LPF

FREQUENCY (kHz)

Figure 48. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

SHAPED

4470 8942

NOISE

SAMPLING

FREQUENCY

02875-0-047

Rev. A | Page 21 of 60

Page 22

ADE7753

Antialias Filter

Figure 47 also shows an analog low-pass filter (RC) on the input to the modulator. This filter is present to prevent aliasing. Aliasing is an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC, which are higher than half the sampling rate of the ADC, appear in the sampled signal at a frequency below half the sampling rate. Figure 49 illustrates the effect. Frequency components (arrows shown in black) above half the sampling frequency (also know as the Nyquist frequency, i.e., 447 kHz) are imaged or folded back down below 447 kHz. This happens with all ADCs regardless of the architecture. In the example shown, only frequencies near the sampling frequency, i.e., 894 kHz, move into the band of interest for metering, i.e., 40 Hz to 2 kHz. This allows the use of a very simple LPF (low-pass filter) to attenuate high frequency (near 900 kHz) noise, and prevents distortion in the band of interest. For conventional current sensors, a simple RC filter (single-pole LPF) with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 894 kHz—see Figure 49. The 20 dB per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors. However, for a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per decade gain. This neutralizes the –20 dB per decade attenuation produced by one simple LPF. Therefore, when using a di/dt sensor, care should be taken to offset the 20 dB per decade gain. One simple approach is to cascade two RC filters to produce the –40 dB per decade attenuation needed.

ALIASING EFFECTS

ADE7753 Reference Circuit

Figure 50 shows a simplified version of the reference output circuitry. The nominal reference voltage at the REF

IN/OUT

pin is

2.42 V. This is the reference voltage used for the ADCs in the ADE7753. However, Channel 1 has three input range selections that are selected by dividing down the reference value used for the ADC in Channel 1. The reference value used for Channel 1 is divided down to ½ and ¼ of the nominal value by using an internal resistor divider, as shown in Figure 50.

OUTPUT IMPEDANCE 6kΩ

REF

IN/OUT

2.42V

REFERENCE INPUT TO ADC CHANNEL 1 (RANGE SELECT)

2.42V, 1.21V, 0.6V

02875-0-049

The REF

MAXIMUM

LOAD = 10µA

PTAT

60µA

Figure 50. ADE7753 Reference Circuit Output

pin can be overdriven by an external source, for

IN/OUT

2.5V

1.7kΩ

12.5kΩ

example, an external 2.5 V reference. Note that the nominal reference value supplied to the ADCs is now 2.5 V, not 2.42 V, which has the effect of increasing the nominal analog input signal range by 2.5/2.42 × 100% = 3% or from 0.5 V to 0.5165 V.

SAMPLING

IMAGE

FREQUENCIES

0 2 447 894

Figure 49. ADC and Signal Processing in Channel 1 Outline Dimensions

FREQUENCY (kHz)

FREQUENCY

02875-0-048

ADC Transfer Function

The following expression relates the output of the LPF in the Σ-∆ ADC to the analog input signal level. Both ADCs in the ADE7753 are designed to produce the same output code for the same input signal level.

( ) 3.0492 262,144

Code ADCV=××

OUT

(1)

Therefore with a full-scale signal on the input of 0.5 V and an internal reference of 2.42 V, the ADC output code is nominally 165,151 or 2851Fh. The maximum code from the ADC is ±262,144; this is equivalent to an input signal level of ±0.794 V. However, for specified performance, it is recommended that the full-scale input signal level of 0.5 V not be exceeded.

The voltage of the ADE7753 reference drifts slightly with temperature—see the ADE7753 Specifications for the temperature coefficient specification (in ppm/°C). The value of the temperature drift varies from part to part. Since the reference is used for the ADCs in both Channels 1 and 2, any x% drift in the reference results in 2×% deviation of the meter accuracy. The reference drift resulting from temperature changes is usually very small and it is typically much smaller than the drift of other components on a meter. However, if guaranteed temperature performance is needed, one needs to use an external voltage reference. Alternatively, the meter can be calibrated at multiple temperatures. Real-time compensation can be achieved easily by using the on-chip temperature sensor.

CHANNEL 1 ADC

Figure 51 shows the ADC and signal processing chain for Channel 1. In waveform sampling mode, the ADC outputs a signed twos complement 24-bit data-word at a maximum of

27.9 kSPS (CLKIN/128). With the specified full-scale analog input signal of 0.5 V (or 0.25 V or 0.125 V—see the Analog Inputs section) the ADC produces an output code that is approximately between 0x2851EC (+2,642,412d) and 0xD7AE14 (–2,642,412d)—see Figure 51.

Rev. A | Page 22 of 60

Page 23

ADE7753

0.5V, 0.25V,

0.125V, 62.5mV,

31.3mV, 15.6mV,

2.42V, 1.21V, 0.6V

×1, ×2, ×4, ×8, ×16

{GAIN[2:0]}

V1P

PGA1

V1N

ANALOG INPUT RANGE

*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED

DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.

0x2851EC

0x00000

0xD7AE4

REFERENCE

ADC 1

ADC OUTPUT WORD RANGE

Figure 51. ADC and Signal Processing in Channel 1

{GAIN[4:3]}

HPF

0x2851EC

0x000000

0xD7AE4

DIGITAL

INTEGRATOR*

CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE

CURRENT RMS (IRMS) CALCULATION

WAVEFORM SAMPLE REGISTER

ACTIVE AND REACTIVE POWER CALCULATION

CHANNEL 1

50Hz

0x1EF73C

0x000000

0xEI08C4

60Hz

0x19CE08

0x000000

0xE631F8

(CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (50Hz)

CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (60Hz)

02875-0-052

Channel 1 Sampling

The waveform samples can also be routed to the waveform register (MODE[14:13] = 1,0) to be read by the system master (MCU). In waveform sampling mode, the WSMP bit (Bit 3) in the interrupt enable register must also be set to Logic 1. The active, apparent power, and energy calculation remain uninterrupted during waveform sampling.

When in waveform sampling mode, one of four output sample rates can be chosen by using Bits 11 and 12 of the mode register (WAVSEL1,0). The output sample rate can be 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see the Mode Register (0X09) section. The

IRQ

interrupt request output,

, signals a new sample availability by going active low. The timing is shown in Figure 52. The 24-bit waveform samples are transferred from the ADE7753 one byte (eight bits) at a time, with the most significant byte shifted out first. The 24-bit data-word is right justified—see the ADE7753

IRQ

Serial Interface section. The interrupt request output

stays low until the interrupt routine reads the reset status register— see the ADE7753 Interrupts section.

IRQ

SCLK

READ FROM WAVEFORM

0 0 01 HEX

DIN

DOUT

SIGN

CHANNEL 1 DATA

(24 BITS)

Figure 52. Waveform Sampling Channel 1

02875-0-050

Channel 1 RMS Calculation

Root mean square (rms) value of a continuous signal V(t) is defined as

VRMS =

rms

×=

dttV

)(

∫

(2)

For time sampling signals, rms calculation involves squaring the signal, taking the average and obtaining the square root:

VRMS =

rms

×=

∑

(3)

)(

The ADE7753 simultaneously calculates the rms values for Channel 1 and Channel 2 in different registers. Figure 53 shows the detail of the signal processing chain for the rms calculation on Channel 1. The Channel 1 rms value is processed from the samples used in the Channel 1 waveform sampling mode. The Channel 1 rms value is stored in an unsigned 24-bit register (IRMS). One LSB of the Channel 1 rms register is equivalent to one LSB of a Channel 1 waveform sample. The update rate of the Channel 1 rms measurement is CLKIN/4.

Rev. A | Page 23 of 60

Page 24

ADE7753

CURRENT SIGNAL (i(t))

0x2851EC

0x00

0xD7AE14

CHANNEL 1

24 24

Figure 53. Channel 1 RMS Signal Processing

With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately ±2,642,412d—see the Channel 1 ADC section. The equivalent rms value of a full-scale ac signal are 1,868,467d (0x1C82B3). The current rms measurement provided in the ADE7753 is accurate to within 1% for signal input between full scale and full scale/100. The conversion from the register value to amps must be done externally in the microprocessor using an amps/LSB constant. To minimize noise, synchronize the reading of the rms register with the zero crossing of the voltage input and take the average of a number of readings.

Channel 1 RMS Offset Compensation

The ADE7753 incorporates a Channel 1 rms offset compensation register (IRMSOS). This is a 12-bit signed register that can be used to remove offset in the Channel 1 rms calculation. An offset could exist in the rms calculation due to input noises that

are integrated in the dc component of V

(t). The offset calibration allows the content of the IRMS register to be maintained at 0 when no input is present on Channel 1.

One LSB of the Channel 1 rms offset is equivalent to 32,768 LSB of the square of the Channel 1 rms register. Assuming that the maximum value from the Channel 1 rms calculation is 1,868,467d with full-scale ac inputs, then 1 LSB of the Channel 1 rms offset represents 0.46% of measurement error at –60 dB down of full scale.

32768

IRMS =

where IRMS

is the rms measurement without offset correction.

×+ IRMSOSIRMS (4)

To measure the offset of the rms measurement, two data points are needed from non-zero input values, for example, the base current, I

, and I

/100. The offset can be calculated from these

max

measurements.

IRMSOS[11:0]

26225

sgn 2272172162

LPF3HPF1

0x1C82B3

0x00

RMS

(t)

IRMS

02875-0-0051

CHANNEL 2 ADC

Channel 2 Sampling

In Channel 2 waveform sampling mode (MODE[14:13] = 1,1 and WSMP = 1), the ADC output code scaling for Channel 2 is not the same as Channel 1. The Channel 2 waveform sample is a 16-bit word and sign extended to 24 bits. For normal operation, the differential voltage signal between V2P and V2N should not exceed 0.5 V. With maximum voltage input (±0.5 V at PGA gain of 1), the output from the ADC swings between 0x2852 and 0xD7AE (±10,322d). However, before being passed to the waveform register, the ADC output is passed through a single-pole, low-pass filter with a cutoff frequency of 140 Hz. The plots in Figure 54 show the magnitude and phase response of this filter.

–10

–20

50Hz, –19.7°

–30

–40

–50

PHASE (Degrees)

–60

–70

–80

–90

Figure 54. Magnitude and Phase Response of LPF1

50Hz, –0.52dB

60Hz, –23.2°

FREQUENCY (Hz)

The LPF1 has the effect of attenuating the signal. For example, if the line frequency is 60 Hz, then the signal at the output of LPF1 is attenuated by about 8%.

fH 73.0919.0

)(

⎛

⎜

140

⎝

⎞ ⎟

⎟ ⎠

60Hz, –0.73dB

−==

(5)

–2

–4

–6

–8

–10

–12

–14

–16

–18

02875-0-053

GAIN (dB)

Note LPF1 does not affect the active power calculation. The signal processing chain in Channel 2 is illustrated in Figure 55.

Rev. A | Page 24 of 60

Page 25

ADE7753

V2P

V2N

ANALOG INPUT RANGE

0.5V, 0.25, 0.125,

62.5mV, 31.25mV 0V

×1, ×2, ×4, ×8, ×16

PGA2

{GAIN [7:5]}

REFERENCE

ADC 2

Figure 55. ADC and Signal Processing in Channel 2

VOLTAGE SIGNAL (V(t))

0x2518

0x0

0xDAE8

CHANNEL 2

Figure 56. Channel 2 RMS Signal Processing

Channel 2 has only one analog input range (0.5 V differential). Like Channel 1, Channel 2 has a PGA with gain selections of 1, 2, 4, 8, and 16. For energy measurement, the output of the ADC is passed directly to the multiplier and is not filtered. An HPF is not required to remove any dc offset since it is only required to remove the offset from one channel to eliminate errors due to offsets in the power calculation. When in waveform sampling mode, one of four output sample rates can be chosen by using Bits 11 and 12 of the mode register. The available output sample rates are 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see the Mode

IRQ

Register (0x09) section. The interrupt request output signals that a sample is available by going active low. The timing is the same as that for Channel 1, as shown in Figure 52.

Channel 2 RMS Calculation

Figure 56 shows the details of the signal processing chain for the rms calculation on Channel 2. The Channel 2 rms value is processed from the samples used in the Channel 2 waveform sampling mode. The rms value is slightly attenuated because of LPF1. Channel 2 rms value is stored in the unsigned 24-bit VRMS register. The update rate of the Channel 2 rms measurement is CLKIN/4.

With the specified full-scale ac analog input signal of 0.5 V, the output from the LPF1 swings between 0x2518 and 0xDAE8 at 60 Hz—see the Channel 2 ADC section. The equivalent rms value of this full-scale ac signal is approximately 1,561,400 (0z17D338) in the VRMS register. The voltage rms measurement provided in the ADE7753 is accurate to within ±0.5% for signal input between full scale and full scale/20. The conversion

2.42V

0xDAE8

0xD7AE

0x2852 0x2581

0x0000

LPF3LPF1

ACTIVE AND REACTIVE

LPF1

LPF OUTPUT

WORD RANGE

ENERGYCALCULATION VRMS CALCULATIO N

AND WAVEFORM SAMPLING (PEAK/SAG/ZX )

02875-0-054

VRMOS[11:0]

sgn 2822212

VRMS[23:0]

0x17D338

0x00

02875-0-0055

from the register value to volts must be done externally in the microprocessor using a volts/LSB constant. Since the low-pass filtering used for calculating the rms value is imperfect, there is some ripple noise from 2

ω term present in the rms measure-

ment. To minimize the noise effect in the reading, synchronize the rms reading with the zero crossings of the voltage input.

Channel 2 RMS Offset Compensation

The ADE7753 incorporates a Channel 2 rms offset compensation register (VRMSOS). This is a 12-bit signed register that can be used to remove offset in the Channel 2 rms calculation. An offset could exist in the rms calculation due to input noises and dc offset in the input samples. The offset calibration allows the contents of the VRMS register to be maintained at 0 when no voltage is applied. One LSB of the Channel 2 rms offset is equivalent to one LSB of the rms register. Assuming that the maximum value from the Channel 2 rms calculation is 1,561,400d with full-scale ac inputs, then one LSB of the Channel 2 rms offset represents 0.064% of measurement error at –60 dB down of full scale.

VRMS = VRMS

where VRMS

+ VRMSOS (6)

is the rms measurement without offset correction. The voltage rms offset compensation should be done by testing the rms results at two non-zero input levels. One measurement can be done close to full scale and the other at approximately full scale/10. The voltage offset compensation can be derived from these measurements. If the voltage rms offset register does not have enough range, the CH2OS register can also be used.

Rev. A | Page 25 of 60

Page 26

ADE7753

PHASE COMPENSATION

When the HPF is disabled, the phase error between Channel 1 and Channel 2 is 0 from dc to 3.5 kHz. When HPF is enabled, Channel 1 has the phase response illustrated in Figure 58 and Figure 59. Also shown in Figure 60 is the magnitude response of the filter. As can be seen from the plots, the phase response is almost 0 from 45 Hz to 1 kHz. This is all that is required in typical energy measurement applications. However, despite being internally phase compensated, the ADE7753 must work with transducers, which could have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7753 provides a means of digitally calibrating these small phase errors. The ADE7753 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors. Because the compensation is in time, this technique should be used only for small phase errors in the range of 0.1° to 0.5°. Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics.

The phase calibration register (PHCAL[5:0]) is a twos complement signed single-byte register that has values ranging from 0x21 (–31d) to 0x1F (31d).

The register is centered at 0x0D, so that writing 0x0D to the register gives 0 delay. By changing the PHCAL register, the time delay in the Channel 2 signal path can change from –102.12 µs to +39.96 µs (CLKIN = 3.579545 MHz). One LSB is equivalent to 2.22 µs (CLKIN/8) time delay or advance. A line frequency of 60 Hz gives a phase resolution of 0.048° at the fundamental (i.e., 360° × 2.22 µs × 60 Hz). Figure 57 illustrates how the phase compensation is used to remove a 0.1° phase lead in Channel 1 due to the external transducer. To cancel the lead (0.1°) in Channel 1, a phase lead must also be introduced into Channel 2. The resolution of the phase adjustment allows the introduction of a phase lead in increment of 0.048°. The phase lead is achieved by introducing a time advance into Channel 2. A time advance of 4.48 µs is made by writing −2 (0x0B) to the time delay block, thus reducing the amount of time delay by 4.48 µs, or equivalently, a phase lead of approximately 0.1° at line frequency of 60 Hz. 0x0B represents –2 because the register is centered with 0 at 0x0D.

V1P

PGA1

V1N

V2P

PGA2

V2N

ADC 1

ADC 2

0.1°

60Hz

HPF

DELAY BLOCK

4.48µs/LSB

110100

PHCAL [5:0]

--100µs TO +34µs

CHANNEL 2 DELAY REDUCED BY 4.48µs (0.1°LEAD AT 60Hz) 0Bh IN PHCAL [5.0]

60Hz

LPF2

02875-0-056

Figure 57. Phase Calibration

0.9

0.8

0.7

0.6

0.5

0.4

0.3

PHASE (Degrees)

0.2

0.1 0

–0.1

FREQUENCY (Hz)

02875-0-057

Figure 58. Combined Phase Response of the HPF and

Phase Compensation (10 Hz to 1 kHz)

0.20

0.18

0.16

0.14

0.12

0.10

0.08

PHASE (Degrees)

0.06

0.04

0.02 0

45 50 55 60 65 70

FREQUENCY (Hz)

02875-0-058

Figure 59. Combined Phase Response of the HPF and

Phase Compensation (40 Hz to 70 Hz)

Rev. A | Page 26 of 60

Page 27

ADE7753

0.4

0.3

0.2

0.1

0.0

ERROR (%)

–0.1

–0.2

–0.3

–0.4

54 56 58 60 62 64 66

FREQUENCY (Hz)

02875-0-059

Figure 60. Combined Gain Response of the HPF and Phase Compensation

ACTIVE POWER CALCULATION

Power is defined as the rate of energy flow from source to load. It is defined as the product of the voltage and current waveforms. The resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at every instant of time. The unit of power is the watt or joules/sec. Equation 9 gives an expression for the instantaneous power signal in an ac system.

v(t) =

i(t) =

where:

V is the rms voltage. I is the rms current.

)sin(2 tV ω× (7)

)sin(2 tI ω× (8)

The instantaneous power signal p(t) is generated by multiplying the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (low-pass filter) to obtain the active power information. This process is illustrated in Figure 61.

0x19999A

0xCCCCD

0x00000

INSTANTANEOUS POWER SIGNAL

CURRENT i(t) = 2

×i×

sin(ωt)

VOLTAGE

×v×

v(t) = 2

Figure 61. Active Power Calculation

p(t) = v

sin(ωt)

i-v×i×cos(2ωt)

ACTIVE REAL POWER

SIGNAL= v

02875-0-060

Since LPF2 does not have an ideal “brick wall” frequency response—see Figure 62, the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated to calculate energy—see the Energy Calculation section.

–4

)()()( titvtp ×=

)2cos()( tVIVItp ω−= (9)

The average power over an integral number of line cycles (n) is given by the expression in Equation 10.

P =

∫

=nTVIdttp

)(

(10)

where:

T is the line cycle period. P is referred to as the active or real power.

Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 8, i.e., VI. This is the relationship used to calculate active power in the ADE7753.

Rev. A | Page 27 of 60

–8

–12

–16

–20

–24

3 10 30 100

FREQUENCY (Hz)

02875-0-061

Figure 62. Frequency Response of LPF2

Page 28

ADE7753

CURRENT

CHANNEL

VOLTAGE CHANNEL

OUTPUT LPF2

APOS[15:0]

LPF2

ACTIVE POWER

SIGNAL

CLKIN

TIME (nT)

WGAIN[11:0]

WAVEFORM

VALUES

Figure 63. ADE7753 Active Energy Calculation

Figure 63 shows the signal processing chain for the active power calculation in the ADE7753. As explained, the active power is calculated by low-pass filtering the instantaneous power signal. Note that when reading the waveform samples from the output of LPF2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (WGAIN[11:0]). The gain is adjusted by writing a twos complement 12-bit word to the watt gain register. Equation 11 shows how the gain adjustment is related to the contents of the watt gain register:

⎛ ⎜

⎜ ⎝

PowerActiveWGAINOutput

⎧

⎨ ⎩

WGAIN

+×=

⎞

⎫

⎟

(11)

⎬

⎟

⎭

⎠

For example, when 0x7FF is written to the watt gain register, the power output is scaled up by 50%. 0x7FF = 2047d, 2047/2

0.5. Similarly, 0x800 = –2048d (signed twos complement) and power output is scaled by –50%. Each LSB scales the power output by 0.0244%. Figure 64 shows the maximum code (in hex) output range for the active power signal (LPF2). Note that the output range changes depending on the contents of the watt gain register. The minimum output range is given when the watt gain register contents are equal to 0x800, and the maximum range is given by writing 0x7FF to the watt gain register. This can be used to calibrate the active power (or energy) calculation in the ADE7753.

WDIV[7:0]

AENERGY [23:0]

23 0

48 0

OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL ACTIVE ENERGY REGISTER

0x13333

0xCCCD

0x6666

0x00000

0xF999A

0xF3333

ACTIVE POWER OUTPUT

0xECCCD

Figure 64. Active Power Calculation Output Range

UPPER 24 BITS ARE ACCESSIBLETHROUGH AENERGY[23:0] REGISTER

02875-0-063

0x000 0x7FF 0x800

{WGAIN[11:0]}

ACTIVE POWER

CALIBRATION RANGE

POSITIVE POWER

NEGATIVE POWER

ENERGY CALCULATION

As stated earlier, power is defined as the rate of energy flow. This relationship can be expressed mathematically in Equation 12.

P =

where:

P is power. E is energy.

Conversely, energy is given as the integral of power.

(12)

02875-0-062

= PdtE

(13)

∫

Rev. A | Page 28 of 60

Page 29

ADE7753

HPF

CURRENT SIGNAL – i(t)

MULTIPLIER

VOLTAGE SIGNAL– v(t)

INSTANTANEOUS POWER SIGNAL – p(t)

0x19999A

0x000000

Figure 65. Active Power Signal Processing

LPF2

sgn 252-62-72

The ADE7753 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal nonreadable 49-bit energy register. The active energy register (AENERGY[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 14 expresses the relationship.

∞

== ×

() ( )

ptdt Lim pnT T

∫

⎧⎫ ⎨

∑

→

⎩

(14)

⎬ ⎭

where:

n is the discrete time sample number. T is the sample period.

The discrete time sample period (T) for the accumulation register in the ADE7753 is 1.1µs (4/CLKIN). As well as calculating the energy, this integration removes any sinusoidal components that might be in the active power signal. Figure 65 shows this discrete time integration or accumulation. The active power signal in the waveform register is continuously added to the internal active energy register. This addition is a signed addition; therefore negative energy is subtracted from the active energy contents. The exception to this is when POAM is selected in the MODE[15:0] register. In this case, only positive energy contributes to the active energy accumulation—see the Positive-Only Accumulation Mode section.

The output of the multiplier is divided by WDIV. If the value in the WDIV register is equal to 0, then the internal active energy register is divided by 1. WDIV is an 8-bit unsigned register. After dividing by WDIV, the active energy is accumulated in a 49-bit internal energy accumulation register. The upper 24 bits of this register are accessible through a read to the active energy register (AENERGY[23:0]). A read to the RAENERGY register returns the content of the AENERGY register and the upper 24 bits of the internal register are cleared. As shown in Figure 65, the active power signal is accumulated in an internal 49-bit signed register. The active power signal can be read from the waveform register by setting MODE[14:13] = 0,0 and setting the WSMP bit (Bit 3) in the interrupt enable register to 1. Like the Channel

APOS [15:0]

FORWAVEF0RM

-8

WGAIN[11:0]

0x19999

FOR WAVEFORM ACCUMULATIOIN

0xCCCCD

SAMPLIN G

02875-0-064

1 and Channel 2 waveform sampling modes, the waveform date is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or

3.5 kSPS—see Figure 52.

Figure 66 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three curves displayed illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are 0x7FF, 0x000, and 0x800. The watt gain register is used to carry out power calibration in the ADE7753. As shown, the fastest integration time occurs when the watt gain register is set to maximum full scale, i.e., 0x7FF.

AENERGY [23:0]

0x7F,FFFF

0x3F,FFFF

0x00,0000

0x40,0000

0x80,0000

Figure 66. Energy Register Rollover Time for Full-Scale Power

6.248

(Minimum and Maximum Power Gain)

12.5

02875-0-065

WGAIN = 0x7FF WGAIN = 0x000 WGAIN = 0x800

TIME (minutes)

Note that the energy register contents rolls over to full-scale negative (0x800000) and continues to increase in value when the power or energy flow is positive—see Figure 66. Conversely, if the power is negative, the energy register underflows to fullscale positive (0x7FFFFF) and continues to decrease in value.

By using the interrupt enable register, the ADE7753 can be

IRQ

configured to issue an interrupt (

) when the active energy register is half-full (positive or negative) or when an overflow or underflow occurs.

Rev. A | Page 29 of 60

Page 30

ADE7753

Integration Time under Steady Load

value that can be stored in the internal 49-bit register is 2

or 0xFFFF,FFFF,FFFF before it overflows. The integration time under these conditions with WDIV = 0 is calculated as follows:

FFFFFFFF,xFFFF,0

Tim e =

xCCCCD0

× 1.12 µs = 375.8 s = 6.26 min (15)

When WDIV is set to a value different from 0, the integration time varies, as shown in Equation 16.

WDIVTimeTime

WDIV×==0

(16)

POWER OFFSET CALIBRATION

The ADE7753 also incorporates an active power offset register (APOS[15:0]). This is a signed twos complement 16-bit register that can be used to remove offsets in the active power calculation—see Figure 65. An offset could exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed.

CFNUM[11:0]

11 0

DFC

48 0

AENERGY[48:0]

11 0

Figure 67. ADE7753 Energy-to-Frequency Conversion

CFDEN[11:0]

02875-0-066

A digital-to-frequency converter (DFC) is used to generate the CF pulsed output. The DFC generates a pulse each time 1 LSB in the active energy register is accumulated. An output pulse is generated when (CFDEN + 1)/(CFNUM + 1) number of pulses are generated at the DFC output. Under steady load conditions, the output frequency is proportional to the active power.

The maximum output frequency, with ac input signals at full scale and CFNUM = 0x00 and CFDEN = 0x00, is approximately 23 kHz.

The ADE7753 incorporates two registers, CFNUM[11:0] and CFDEN[11:0], to set the CF frequency. These are unsigned 12-bit registers, which can be used to adjust the CF frequency to a wide range of values. These frequency-scaling registers are

12-bit registers, which can scale the output frequency by 1/2

1 with a step of 1/2

The 256 LSBs (APOS = 0x0100) written to the active power offset register are equivalent to 1 LSB in the waveform sample register. Assuming the average value, output from LPF2 is 0xCCCCD (838,861d) when inputs on Channels 1 and 2 are both at full scale. At −60 dB down on Channel 1 (1/1000 of the Channel 1 full-scale input), the average word value output from LPF2 is 838.861 (838,861/1,000). One LSB in the LPF2 output has a measurement error of 1/838.861 × 100% = 0.119% of the average value. The active power offset register has a resolution equal to 1/256 LSB of the waveform register, therefore the power offset correction resolution is 0.00047%/LSB (0.119%/256) at –60 dB.

ENERGY-TO-FREQUENCY CONVERSION

ADE7753 also provides energy-to-frequency conversion for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verify the energy meter calibration. One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency, which is proportional to the energy or active power under steady load conditions. This output frequency can provide a simple, singlewire, optically isolated interface to external calibration equipment. Figure 67 illustrates the energy-to-frequency conversion in the ADE7753.

If the value 0 is written to any of these registers, the value 1 would be applied to the register. The ratio (CFNUM + 1)/ (CFDEN + 1) should be smaller than 1 to ensure proper operation. If the ratio of the registers (CFNUM + 1)/(CFDEN + 1) is greater than 1, the register values would be adjusted to a ratio (CFNUM + 1)/(CFDEN + 1) of 1. For example, if the output frequency is 1.562 kHz while the contents of CFDEN are 0 (0x000), then the output frequency can be set to 6.1 Hz by writing 0xFF to the CFDEN register.

The output frequency has a slight ripple at a frequency equal to twice the line frequency. This is due to imperfect filtering of the instantaneous power signal to generate the active power signal— see the Active Power Calculation section. Equation 9 from the Active Power Calculation section gives an expression for the instantaneous power signal. This is filtered by LPF2, which has a magnitude response given by Equation 17.

fH+=

)(

(17)

9.8

Rev. A | Page 30 of 60

Page 31

ADE7753

The active power signal (output of LPF2) can be rewritten as

⎤ ⎥ ⎥

⎛ ⎜

⎝

× cos(4πfLt) (18)

⎥

⎞

⎥

⎟

9.8

⎠

⎥

⎦

p(t) = VI −

where f

⎡ ⎢ ⎢ ⎢ ⎢

⎢ ⎢

⎣

is the line frequency, for example, 60 Hz.

From Equation 13,

⎤ ⎥ ⎥

× sin(4πfLt) (19)

⎥

⎞

⎥

⎟

9.8

⎠

⎥

⎦

E(t) = VIt −

⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢

⎣

⎛

+π

⎜

⎝

From Equation 19 it can be seen that there is a small ripple in the energy calculation due to a sin(2 ωt) component. This is shown graphically in Figure 68. The active energy calculation is shown by the dashed straight line and is equal to V × I × t. The sinusoidal ripple in the active energy calculation is also shown.

WGAIN[11:0]

OUTPUT

FROM

LPF2

Since the average value of a sinusoid is 0, this ripple does not contribute to the energy calculation over time. However, the ripple can be observed in the frequency output, especially at higher output frequencies. The ripple gets larger as a percentage of the frequency at larger loads and higher output frequencies. The reason is simply that at higher output frequencies the integration or averaging time in the energy-to-frequency conversion process is shorter. As a consequence, some of the sinusoidal ripple is observable in the frequency output. Choosing a lower output frequency at CF for calibration can significantly reduce t he ripple. Als o, averaging the output fre quency by using a longer gate time for the counter achieves the same results.

E(t)

Figure 68. Output Frequency Ripple

48 0

–

4×π×f

Vlt

(1+2×fL/8.9Hz)

sin(4×π×f

02875-0-067

×t)

WDIV[7:0]APOS[15:0]

ACCUMULATE ACTIVE

FROM

CHANNEL 2

ADC

LPF1

23 0

ZERO CROSS

DETECTION

Figure 69. Energy Calculation Line Cycle Energy Accumulation Mode

CALIBRATION

CONTROL

LINECYC [15:0]

LAENERGY [23:0]

ENERGY IN INTERNAL REGISTER AND UPDATE THE LAENERGY REGISTER AT THE END OF LINECYC LINE CYCLES

02875-0-068

Rev. A | Page 31 of 60

Page 32

ADE7753

LINE CYCLE ENERGY ACCUMULATION MODE

In line cycle energy accumulation mode, the energy accumulation of the ADE7753 can be synchronized to the Channel 2 zero crossing so that active energy can be accumulated over an integral number of half line cycles. The advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates any ripple in the energy calculation. Energy is calculated more accurately and in a shorter time because the integration period can be shortened. By using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. The ADE7753 is placed in line cycle energy accumulation mode by setting Bit 7 (CYCMODE) in the mode register. In line cycle energy accumulation mode, the ADE7753 accumulates the active power signal in the LAENERGY register (Address 0x04) for an integral number of line cycles, as shown in Figure 69. The number of half line cycles is specified in the LINECYC register (Address 0x1C). The ADE7753 can accumulate active power for up to 65,535 half line cycles. Because the active power is integrated on an integral number of line cycles, at the end of a line cycle energy accumulation cycle the CYCEND flag in the interrupt status register is set (Bit 2). If the CYCEND enable bit in the interrupt enable

IRQ

line can also be used to signal the completion of the line cycle energy accumulation. Another calibration cycle can start as long as the CYCMODE bit in the mode register is set.

output also goes active low. Thus the

Note that in this mode, the 16-bit LINECYC register can hold a maximum value of 65,535. In other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration over 65,535 half line cycles. At 60 Hz line frequency, it translates to a total duration of 65,535/120 Hz = 546 seconds.

POSITIVE-ONLY ACCUMULATION MODE

In positive-only accumulation mode, the energy accumulation is done only for positive power, ignoring any occurrence of negative power above or below the no-load threshold, as shown in Figure 70. The CF pulse also reflects this accumulation method when in this mode. The ADE7753 is placed in positiveonly accumulation mode by setting the MSB of the mode register (MODE[15]). The default setting for this mode is off. Transitions in the direction of power flow, going from negative

IRQ

to positive or positive to negative, set the if the interrupt enable register is enabled. The interrupt status registers, PPOS and PNEG, show which transition has occurred—see the ADE7753 register descriptions in Table 10.

CTIVE ENERG

pin to active low

From Equations 13 and 18,

⎧ ⎪ ⎪

⎪

dtVI

E(t) =

−

⎨

⎪

⎪ ⎪

⎩

where:

⎛ ⎜

⎝

⎫ ⎪

nTnT

⎪

cos

(2πft)dt (20)

⎬

∫∫

⎪

⎞

⎟

⎪

9.8

⎪

⎠

⎭

NO-LOAD

THRESHOLD

ACTIVE POWER

NO-LOAD

THRESHOLD

IRQ

PPOS PNEGPNEG

INTERRUPT STATUS REGISTERS

n is an integer. T is the line cycle period.

Since the sinusoidal component is integrated over an integer number of line cycles, its value is always 0. Therefore,

VIdt

E =

+ 0 (21)

∫

E(t) = VInT (22)

Figure 70. Energy Accumulation in Positive-Only Accumulation Mode

NO-LOAD THRESHOLD

The ADE7753 includes a no-load threshold feature on the active energy that eliminates any creep effects in the meter. The ADE7753 accomplishes this by not accumulating energy if the multiplier output is below the no-load threshold. This threshold is 0.001% of the full-scale output frequency of the multiplier. Compare this value to the IEC1036 specification, which states that the meter must start up with a load equal to or less than

0.4% Ib. This standard translates to .0167% of the full-scale output frequency of the multiplier.

PNEGPPOSPPOS

02875-0-069

Rev. A | Page 32 of 60

Page 33

ADE7753

REACTIVE POWER CALCULATION

Reactive power is defined as the product of the voltage and current waveforms when one of these signals is phase-shifted by 90°. The resulting waveform is called the instantaneous reactive power signal. Equation 25 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by +90°.

The average reactive power over an integral number of lines (n) is given in Equation 26.

∫

VIdttRp

)sin()(

(26)

where:

v(t) =

i(t) =

′

sin2)(

)sin(2 θ+ωtV (23)

)sin(2 tI ω

⎞

⎛

tIti (24)

+ω=

⎟

⎜

⎠

⎝

where:

θ is the phase difference between the voltage and current channel.

V is the rms voltage. I is the rms current.

Rp(t) = v(t) × i’(t) (25)

90 DEGREE

PHASE SHIFT

MULTIPLIER

)2( θ+ωt

INSTANTANEOUS REACTIVE

ZERO-CROSSING

POWER SIGNAL (Rp(t))

DETECTION

LPF2

Rp(t) = VI sin (

CHANNEL 2

θ) + VI sin

FROM

ADC

LPF1

CALIBRATION

CONTROL

T is the line cycle period. RP is referred to as the reactive power.

Note that the reactive power is equal to the dc component of the instantaneous reactive power signal Rp(t) in Equation 25. This is the relationship used to calculate reactive power in the ADE7753. The instantaneous reactive power signal Rp(t) is generated by multiplying Channel 1 and Channel 2. In this case, the phase of Channel 1 is shifted by +90°. The dc component of the instantaneous reactive power signal is then extracted by a low-pass filter in order to obtain the reactive power information. Figure 71 shows the signal processing in the reactive power calculation in the ADE7753.

49 0

ACCUMULATE REACTIVE ENERGY IN INTERNAL

23 0

LVARENERGY [23:0]

LINECYC [15:0]

Figure 71. Reactive Power Signal Processing

Rev. A | Page 33 of 60

02875-0-070

Page 34

ADE7753

The features of the line reactive energy accumulation are the same as the line active energy accumulation. The number of half line cycles is specified in the LINECYC register. LINECYC is an unsigned 16-bit register. The ADE7753 can accumulate reactive power for up to 65535 combined half cycles. At the end of an energy calibration cycle, the CYCEND flag in the interrupt status register is set. If the CYCEND mask bit in the interrupt

IRQ

mask register is enabled, the

IRQ

Thus the

line can also be used to signal the end of a calibration. The ADE7753 accumulates the reactive power signal in the LVARENERGY register for an integer number of half cycles, as shown in Figure 71.

SIGN OF REACTIVE POWER CALCULATION

Note that the average reactive power is a signed calculation. The phase shift filter has –90° phase shift when the integrator is enabled, and +90° phase shift when the integrator is disabled. Table 7 summarizes the relationship between the phase difference between the voltage and the current and the sign of the resulting VAR calculation.

Table 7. Sign of Reactive Power Calculation

Angle Integrator Sign

Between 0° to 90° Between –90° to 0° Between 0° to 90° Between –90° to 0°

APPARENT POWER CALCULATION

The apparent power is defined as the maximum power that can be delivered to a load. V current delivered to the load; the apparent power (AP) is defined

× I

as V

rms

. The angle θ between the active power and the

rms

apparent power generally represents the phase shift due to nonresistive loads. For single-phase applications, θ represents the angle between the voltage and the current signals—see Figure 72. Equation 28 gives an expression of the instantaneous power signal in an ac system with a phase shift.

REACTIVE

POWER

rms

Figure 72. Power Triangle

output also goes active low.

Off Positive Off Negative On Positive On Negative

and I

are the effective voltage and

rms

APPARENT

POWER

ACTIVE

POWER

02875-0-071

() 2 sin( )

vt V t

rms

i(t) =

rms

p(t) =

The apparent power is defined as V

)sin(2 θ+ωtI

(27)

)()()( titvtp

(28)

rmsrmsrmsrms

× I

rms rms

)2cos()cos( θ+ω−θ tIVIV

. This expression is independent from the phase angle between the current and the voltage.

Figure 73 illustrates the signal processing in each phase for the calculation of the apparent power in the ADE7753.

rms

CURRENT RMS SIGNAL – i(t)

0x1C82B3

0x00

rms

VOLTAGE RMSSIGNAL– v(t)

0x17D338

0x00

Figure 73. Apparent Power Signal Processing

MULTIPLIER

VAGAIN

APPARENT POWER

SIGNAL(P)

0xAD055

02875-0-072

The gain of the apparent energy can be adjusted by using the multiplier and VAGAIN register (VAGAIN[11:0]). The gain is adjusted by writing a twos complement, 12-bit word to the VAGAIN register. Equation 29 shows how the gain adjustment is related to the contents of the VAGAIN register.

⎛ ⎜

⎜ ⎝

PowerApparentINOutputVAGA

⎧

⎨ ⎩

VAGAIN

+×=

⎞

⎫

⎟

(29)

⎬

⎟

⎭

⎠

For example, when 0x7FF is written to the VAGAIN register, the power output is scaled up by 50%. 0x7FF = 2047d, 2047/2

0.5. Similarly, 0x800 = –2047d (signed twos complement) and power output is scaled by –50%. Each LSB represents 0.0244% of the power output. The apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ADE7753. Figure 74 shows the maximum code (hexadecimal) output range of the apparent power signal. Note that the output range changes depending on the contents of the apparent power gain registers. The minimum output range is given when the apparent power gain register content is equal to 0x800 and the maximum range is given by writing 0x7FF to the apparent power gain register. This can be used to calibrate the apparent power (or energy) calculation in the ADE7753.

Rev. A | Page 34 of 60

Page 35

ADE7753

APPARENT POWER 100% FS

0x103880

0xAD055

0x5682B

0x00000

Figure 74. Apparent Power Calculation Output Range

APPARENT POWER 150% FS

0x000 0x7FF 0x800

{VAGAIN[11:0]}

APPARENT POWER

CALIBRATION RANGE

VOLTAGE AND CURRENT

CHANNEL INPUTS: 0.5V/GAIN

APPARENT POWER 50% FS

02875-0-073

Apparent Power Offset Calibration

Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value—see Channel 1 RMS Calculation and Channel 2 RMS Calculation sections. The Channel 1 and Channel 2 rms values are then multiplied together in the apparent power signal processing. Since no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. The offset compensation of the apparent power measurement is done by calibrating each individual rms measurement.

APPARENT ENERGY CALCULATION

The apparent energy is given as the integral of the apparent power.

The 49 bits of the internal register are divided by VADIV. If the value in the VADIV register is 0, then the internal active energy register is divided by 1. VADIV is an 8-bit unsigned register. The upper 24 bits are then written in the 24-bit apparent energy register (VAENERGY[23:0]). RVAENERGY register (24 bits long) is provided to read the apparent energy. This register is reset to 0 after a read operation.

Figure 76 shows this apparent energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three curves displayed illustrate the minimum time it takes the energy register to roll over when the VAGAIN registers content is equal to 0x7FF, 0x000, and 0x800. The VAGAIN register is used to carry out an apparent power calibration in the ADE7753. As shown, the fastest integration time occurs when the VAGAIN register is set to maximum full scale, i.e., 0x7FF.

VAENERGY [23:0]

23 0

48 0

APPARENT POWER

VADIV

48 0

= dttPowerApparentEnergyApparent )(

∫

(30)

The ADE7753 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48-bit register. The apparent energy register (VAENERGY[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 31 expresses the relationship

∞

⎧

⎪ ⎨

∑

⎪

=→0

⎩

×=

)(

⎫

⎪

(31)

TnTPowerApparentLimEnergyApparent

⎬ ⎪

⎭

where:

n is the discrete time sample number. T is the sample period.

The discrete time sample period (T) for the accumulation register in the ADE7753 is 1.1 µs (4/CLKIN).

Figure 75 shows this discrete time integration or accumulation. The apparent power signal is continuously added to the internal register. This addition is a signed addition even if the apparent energy remains theoretically always positive.

ACTIVEPOWER

SIGNAL= P

TIME (nT)

Figure 75. ADE7753 Apparent Energy Calculation

VAENERGY[23:0]

xFF,FFFF

0x80,0000

0x40,0000

0x20,0000

0x00,0000

Figure 76. Energy Register Rollover Time for Full-Scale Power

6.26 12.52 18.78 25.04

(Maximum and Minimum Power Gain)

APPARENTPOWERARE ACCUMULATED(INTEGRATED) IN THEAPPARENTENERGY REGISTER

02875-0-074

VAGAIN = 0x7FF VAGAIN = 0x000 VAGAIN = 0x800

TIME (minutes)

02875-0-075

Rev. A | Page 35 of 60

Page 36

ADE7753

Note that the apparent energy register is unsigned—see Figure 76. By using the interrupt enable register, the ADE7753 can be configured to issue an interrupt ( register is half full or when an overflow occurs. The half full interrupt for the unsigned apparent energy register is based on 24 bits as opposed to 23 bits for the signed active energy register.

Integration Times under Steady Load

As mentioned in the last section, the discrete time sample period (T) for the accumulation register is 1.1 µs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the VAGAIN register set to 0x000, the average word value from apparent power stage is 0xAD055—see the Apparent Power Calculation section. The maximum value that can be stored in the apparent energy register before it overflows is 2 0xFF,FFFF. The average word value is added to the internal register, which can store 2 overflows. Therefore, the integration time under these conditions with VADIV = 0 is calculated as follows:

Time =

When VADIV is set to a value different from 0, the integration time varies, as shown in Equation 33.

Time = Ti me

WDIV = 0

IRQ

) when the apparent energy

or 0xFFFF,FFFF,FFFF before it

FFFFFFFF,xFFFF,0

055xD0

× 1.2 µs = 888 s = 12.52 min (32)

× VA DI V (33)

LINE APPARENT ENERGY ACCUMULATION

The ADE7753 is designed with a special apparent energy accumulation mode, which simplifies the calibration process. By using the on-chip zero-crossing detection, the ADE7753 accumulates the apparent power signal in the LVAENERGY register for an integral number of half cycles, as shown in Figure 77. The line apparent energy accumulation mode is always active.

The number of half line cycles is specified in the LINCYC register, which is an unsigned 16-bit register. The ADE7753 can accumulate apparent power for up to 65535 combined half cycles. Because the apparent power is integrated on the same integral number of line cycles as the line active energy register, these two values can be compared easily. The active energy and the apparent energy are calculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation. At the end of an energy calibration cycle, the CYCEND flag in the interrupt status register is set. If the CYCEND mask bit in the

IRQ

interrupt mask register is enabled, the

IRQ

active low. Thus the

line can also be used to signal the end

of a calibration.

The line apparent energy accumulation uses the same signal path as the apparent energy accumulation. The LSB size of these two registers is equivalent.

output also goes

48 0

23 0

LVAENERGY [23:0]

LVAENERGY REGISTER IS UPDATED EVERY LINECYC ZERO CROSSINGS WITH THE TOTAL APPARENT ENERGY DURING THAT DURATION

02875-0-076

FROM

CHANNEL 2

ADC

LPF1

APPARENT

POWER

ZERO-CROSSING

DETECTION

Figure 77. ADE7753 Apparent Energy Calibration

VADIV[7:0]

CALIBRATION

LINECYC [15:0]

CONTROL

Rev. A | Page 36 of 60

Page 37

ADE7753

ENERGIES SCALING

The ADE7753 provides measurements of active, reactive, and apparent energies. These measurements do not have the same scaling and thus cannot be compared directly to each other.

Table 8. Energies Scaling

PF = 1 PF = 0.707 PF = 0

Integrator On at 50 Hz

Active Wh Wh × 0.707 0 Reactive 0 Wh × 0.508 Wh × 0.719 Apparent Wh × 0.848 Wh × 0.848 Wh × 0.848

Integrator Off at 50 Hz

Active Wh Wh × 0.707 0 Reactive 0 Wh × 0.245 Wh × 0.347 Apparent Wh × 0.848 Wh × 0.848 Wh × 0.848

Integrator On at 60 Hz

Active Wh Wh × 0.707 0 Reactive 0 Wh × 0.610 Wh × 0.863 Apparent Wh × 0.827 Wh × 0.827 Wh × 0.827

Integrator Off at 60 Hz

Active Wh Wh × 0.707 0 Reactive 0 Wh × 0.204 Wh × 0.289 Apparent Wh × 0.827 Wh × 0.827 Wh × 0.827

When using a reference meter, the ADE7753 calibration output frequency, CF, is adjusted to match the frequency output of the reference meter. A pulse output is only provided for the active energy measurement in the ADE7753. If it is desired to use a reference meter for calibrating the VA and VAR, then additional code would have to be written in a microprocessor to produce a pulsed output for these quantities. Otherwise, VA and VAR calibration require an accurate source.

The ADE7753 provides a line cycle accumulation mode for calibration using an accurate source. In this method, the active energy accumulation rate is adjusted to produce a desired CF frequency. The benefit of using this mode is that the effect of the ripple noise in the active energy is eliminated. Up to 65535 half line cycles can be accumulated, thus providing a stable energy value to average. The accumulation time is calculated from the line cycle period, measured by the ADE7753 in the PERIOD register, and the number of half line cycles in the accumulation, fixed by the LINECYC register.

Current and voltage rms offset calibration removes any apparent energy offset. A gain calibration is also provided for apparent energy. Figure 79 shows an optimized calibration flow for active energy, rms, and apparent energy.

CALIBRATING AN ENERGY METER BASED ON THE ADE7753

The ADE7753 provides gain and offset compensation for active and apparent energy calibration. Its phase compensation corrects phase error in active, apparent and reactive energy. If a shunt is used, offset and phase calibration may not be required. A reference meter or an accurate source can be used to calibrate the ADE7753.

WATT/VA GAIN CALIBRATION

RMS CALIBRATION

Figure 79. Apparent and Active Energy Calibration

Active and apparent energy gain calibrations can take place concurrently, with a read of the accumulated apparent energy register following that of the accumulated active energy register.

Figure 78 shows the calibration flow for the active energy portion of the ADE7753.

WATT GAIN CALIBRATION WATT OFFSET CALIBRATION PHASE CALIBRATION

Figure 78. Active Energy Calibration

The ADE7753 does not provide means to calibrate reactive energy gain and offset. The reactive energy portion of the ADE7753 can be calibrated externally, through a MCU.

WATT OFFSET CALIBRATION

PHASE CALIBRATION

02875-A-002

02875-A-005

Rev. A | Page 37 of 60

Page 38

ADE7753

Watt Gain

The first step of calibrating the gain is to define the line voltage, base current and the maximum current for the meter. A meter constant needs to be determined for CF, such as 3200 imp/kWh or 3.2 imp/Wh. Note that the line voltage and the maximum current scale to half of their respective analog input ranges in this example.

The expected CF in Hz is

(Hz) =

expected

(W)(imp/Wh)ϕ×× LoadantMeterConst

s/h3600

where

is the angle between I and V, and cos is the power

factor.

The ratio of active energy LSBs per CF pulse is adjusted using the CFNUM, CFDEN, and WDIV registers.

expected

onTimeAccumulati

WDIV

(s) +

LAENERGY

The relationship between watt-hours accumulated and the quantity read from AENERGY can be determined from the amount of active energy accumulated over time with a given load:

LSB

s/3600

where Accumulation Time can be determined from the value in the line period and the number of half line cycles fixed in the LINECYC register.

Accumulation time(s) =

The line period can be determined from the PERIOD register:

Line Period(s) = PERIOD ×

CLKIN

The AENERGY Wh/LSB ratio can also be expressed in terms of the meter constant:

)1(

(imp/Wh)

antMeterConst

WDIV

LSB

CFNUM

CFDEN

In a meter design, WDIV, CFNUM, and CFDEN should be kept constant across all meters to ensure that the Wh/LSB constant is maintained. Leaving WDIV at its default value of 0 ensures maximum resolution. The WDIV register is not included in the CF signal chain so it does not affect the frequency pulse output.

)cos(

(34)

)(ϕ

)1(

(35)

)1(

(36)

(s)PeriodLineLINECYC

(37)

TimeonAccumulatiLoad

hLAENERGY

××

CFNUM

CFDEN

(s)(W)

(38)

(39)

The WGAIN register is used to finely calibrate each meter. Calibrating the WGAIN register changes both CF and AENERGY for a given load condition.

AENERGY

expected

= AENERGY × (40)

expected

(Hz) = CF × (41)

nominal

CFNUM

CFDEN

nominal

⎛

⎜

⎜ ⎝

)1( WGAIN

)1(

WGAIN

⎛

+×

⎜

⎜ ⎝

⎞ ⎟

⎟ ⎠

⎞ ⎟

⎟

⎠

When calibrating with a reference meter, WGAIN is adjusted until CF matches the reference meter pulse output. If an accurate source is used to calibrate, WGAIN is modified until the active energy accumulation rate yields the expected CF pulse rate.

The steps of designing and calibrating the active energy portion of a meter with either a reference meter or an accurate source are outlined in the following examples. The specifications for this example are

Meter Constant: MeterConstant(imp/Wh) = 3.2 Base Current: I Maximum Current: I Line Voltage: V Line Frequency: f

= 10 A

= 60 A

MAX

= 220 V

nominal

= 50 Hz

The first step in calibration with either a reference meter or an accurate source is to calculate the CF denominator, CFDEN. This is done by comparing the expected CF pulse output to the nominal CF output with the default CFDEN = 0x3F and CFNUM = 0x3F and when the base current is applied.

The expected CF output for this meter with the base current applied is 1.9556 Hz using Equation 34.

IB(expected)

(Hz) =

V220A10imp/Wh200.3

××

s/h3600

can be measured from a reference meter

expected

=ϕ×

Hz9556.1)cos(

Alternatively, CF pulse output if available.

(Hz) = CF (42)

expected

ref

The maximum CF frequency measured without any frequency division and with ac inputs at full scale is 23 kHz. For this example, the nominal CF with the test current, I

, applied is

958 Hz. In this example the line voltage and maximum current scale half of their respective analog input ranges. The line voltage and maximum current should not be fixed at the maximum analog inputs to account for occurrences such as spikes on the line.

(Hz) = (43)

nominal

kHz23

×××

MAX

Rev. A | Page 38 of 60

(Hz) =

IB(nominal)

kHz23 =×××

Hz958

Page 39

ADE7753

The nominal CF on a sample set of meters should be measured using the default CFDEN, CFNUM, and WDIV to ensure that the best CFDEN is chosen for the design.

With the CFNUM register set to 0, CFDEN is calculated to be 489 for the example meter:

CFDEN =

INT

⎛

⎜ ⎜

expectedIB

⎝

958

⎛ ⎜

9556.1

⎝

⎞

)(

nominalIB

⎟

−

(44)

⎟

)(

⎠

⎞ ⎟

489)1490(1

=−=−

⎠

This value for CFDEN should be loaded into each meter before calibration. The WGAIN and WDIV registers can then be used to finely calibrate the CF output. The following sections explain how to calibrate a meter based on ADE7753 when using a reference meter or an accurate source.

Calibrating Watt Gain Using a Reference Meter Example

The CFDEN and CFNUM values for the design should be written to their respective registers before beginning the calibration steps shown in Figure 80. When using a reference meter, the %ERROR in CF is measured by comparing the CF output of the ADE7753 meter with the pulse output of the reference meter with the same test conditions applied to both meters. Equation 45 defines the percent error with respect to the pulse outputs of both meters (using the base current, I

For this example:

Meter Constant: MeterConstant(imp/Wh) = 3.2 CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 % Error measured at Base Current: %ERROR

CF(IB)

= -3.07%

One LSB change in WGAIN changes the active energy registers and CF by 0.0244%. WGAIN is a signed twos complement register and can correct for up to a 50% error. Assuming a

−3.07% error, WGAIN is 126:

WGAIN = INT

⎛ ⎜

−

⎜ ⎝

−

⎛ ⎜

⎝

%07.3

−

%0244.0

⎞

)(IBCF

⎟

(46)

⎟

%0244.0

⎠

⎞

126

⎟ ⎠

ERROR

When CF is calibrated, the AENERGY register has the same Wh/LSB constant from meter to meter if the meter constant, WDIV, and the CFNUM/CFDEN ratio remain the same. The

−4

Wh/LSB ratio for this meter is 6.378 × 10

using Equation 39

with WDIV at the default value.

)1(

(imp/Wh)

antMeterConst

WDIV

LSB

CFNUM

CFDEN

−

%ERROR

Figure 80. Calibrating Watt Gain Using a Reference Meter

= (45)

CF(IB)

CALCULATE CFDEN VALUE FOR DESIGN

WRITE CFDEN VALUE TO CFDEN REGISTER

SET I

MEASURE THE % ERROR BETWEEN

REFERENCE METER OUTPUT

CALCULATE WGAIN. SEE EQUATION 46.

WRITE WGAIN VALUE TO THE WGAIN

CFCF

ADDR. 0x15 = CFDEN

= Ib, V

TEST

THE CF OUTPUT AND THE

IBref

TEST

)(

IBrefIB

100

)(

= V

, PF = 1

NOM

02875-A-006

LSB

)1490(

imp/Wh200.3

2.3490

−

10378.6

×=

Calibrating Watt Gain Using an Accurate Source Example

The CFDEN value calculated using Equation 44 should be written to the CFDEN register before beginning calibration and zero should be written to the CFNUM register. First, the line accumulation mode and the line accumulation interrupt should be enabled. Next, the number of half line cycles for the energy accumulation is written to the LINECYC register. This sets the accumulation time. Reset the interrupt status register and wait for the line cycle accumulation interrupt. The first line cycle accumulation results may not have used the accumulation time set by the LINECYC register and should be discarded. After resetting the interrupt status register, the following line cycle readings will be valid. When LINECYC half line cycles have

IRQ

elapsed, the with the test current applied can be read. This LAENERGY value is compared to the expected LAENERGY value to deter-

pin goes active low and the nominal LAENERGY

mine the WGAIN value. If apparent energy gain calibration is performed at the same time, LVAENERGY can be read directly after LAENERGY. Both registers should be read before the next

IRQ

interrupt is issued on the

pin. Refer to the Apparent Energy Calculation section for more details. Figure 81 details the steps that calibrate the watt gain using an accurate source.

Rev. A | Page 39 of 60

Page 40

ADE7753

CALCULATE CFDEN VALUE FOR DESIGN

WRITE CFDEN VALUE TO CFDEN REGISTER

SET HALF LINECYCLES FOR ACCUMULATION

ADDR. 0x15 = CFDEN

SET I

= Ib, V

TEST

IN LINECYC REGISTER ADDR. 0x1C

TEST

= V

NOM

, PF = 1

The nominal LAENERGY reading, LAENERGY

IB(nominal)

, is the LAENERGY reading with the test current applied. The expected LAENERGY reading is calculated from the following equation:

LAENERGY

⎛ ⎜

⎜

INT

⎜ ⎜ ⎝

expectedIB

IB(expected)

CFNUM

CFDEN

⎞

)(

WDIV

⎟

(s)

TimeonAccumulatiCF

⎟

(48)

⎟ ⎟ ⎠

SET MODE FOR LINE CYCLE

ACCUMULATION ADDR. 0x09 = 0x0080

ENABLE LINE CYCLE ACCUMULATION

INTERRUPT ADDR. 0x0A = 0x04

RESET THE INTERRUPT STATUS

READ REGISTER ADDR. 0x0C

INTERRUPT?

YES

RESET THE INTERRUPT STATUS

READ REGISTER ADDR. 0x0C

INTERRUPT?

YES

READ LINE ACCUMULATION ENERGY

CALCULATE WGAIN. SEE EQUATION 47.

WRITE WGAIN VALUE TO THE WGAIN

Figure 81. Calibrating Watt Gain Using an Accurate Source

ADDR. 0x04

02875-A-007

Equation 47 describes the relationship between the expected LAENERGY value and the LAENERGY measured in the test condition:

WGAIN = INT

⎛

LAENERGY

⎜

LAENERGY

⎝

)(

expectedIB

nominalIB

−

)(

⎞

⎟

(47)

⎟

⎟ ⎠

⎠

where CF

(Hz) is calculated from Equation 34, accumula-

IB(expected)

tion time is calculated from Equation 37, and the line period is determined from the PERIOD register according to Equation 38.

For this example:

Meter Constant: MeterConstant(imp/Wh) = 3.2 Tes t Cu r re n t: I Line Voltage: V Line Frequency: f Half Line Cycles: LINECYC

= 10 A

= 220 V

nominal

= 50 Hz

= 2000

CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Energy Reading at Base Current: LAENERGY

IB (nominal)

= 17174

Period Register Reading: PERIOD = 8959 Clock Frequency: CLKIN = 3.579545 MHz

is calculated to be 1.9556 Hz according to Equation 34.

expected

LAENERGY

IB(expected)

LAENERGY

⎛ ⎜

⎜

INT

⎜ ⎜ ⎝

LAENERGY

⎛ ⎜

⎜

INT

⎜ ⎜ ⎝

is calculated to be 19186 using Equation 48.

expected

(Hz) =

A10V220imp/Wh200.3

s/h3600

IB(expected)

××

)(

CFNUM

CFDEN

)(cos(

ϕ×

= 1.9556 Hz

IBexpectedIB

WDIV

××××

1489

19186)4.19186(=INT

×××

CLKINPERIODLINECYCCF

/82/

⎞ ⎟

)10579545.3/(889592/20009556.1

⎟

⎟ ⎟ ⎠

⎞ ⎟

⎟ ⎟

⎟ ⎠

WGAIN is calculated to be 480 using Equation 47.

Note that WGAIN is a signed twos complement register.

Rev. A | Page 40 of 60

WGAIN = INT

⎛

⎜

⎝

19186 17174

⎞

−

⎟

48021

⎟ ⎠

Page 41

ADE7753

With WDIV and CFNUM set to 0, LAENERGY can be expressed as

LAENERGY =

The calculated Wh/LSB ratio for the active energy register, using Equation 39 is 6.378 × 10

IB(expected)

)(

))1(/82/(

IBexpectedIB

−

+×××× CFDENCLKINPERIODLINECYCCFINT

LSB

)1489(

imp/Wh200.3

−

10378.6

×=

For this example:

Meter Constant: Minimum Current: I Load at Minimum Current: W CF Error at Minimum Current: %ERROR

MeterConstant(imp/Wh) = 3.2

= 40 mA

MIN

= 9.6 W

IMIN

= 1.3%

CF(IMIN)

CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Clock Frequency: CLKIN = 3.579545 MHz

Using Equation 49, APOS is calculated to be −522 for this example.

Watt Offset

Offset calibration allows outstanding performance over a wide dynamic range, for example, 1000:1. To do this calibration two measurements are needed at unity power factor, one at I

and

the other at the lowest current to be corrected. Either calibration frequency or line cycle accumulation measurements can be used to determine the energy offset. Gain calibration should be performed prior to offset calibration.

Offset calibration is performed by determining the active energy error rate. Once the active energy error rate has been determined, the value to write to the APOS register to correct the offset is calculated.

APOS = −

RateErrorAENERGY

CLKIN

(49)

2×

The AENERGY registers update at a rate of CLKIN/4. The twos complement APOS register provides a fine adjustment to the active power calculation. It represents a fixed amount of power offset to be adjusted every CLKIN/4. The 8 LSBs of the APOS register are fractional such that one LSB of APOS represents 1/256 of the least significant bit of the internal active energy register. Therefore, one LSB of the APOS register represents 2

−

of the AENERGY[23:0] active energy register.

The steps involved in determining the active energy error rate for both line accumulation and reference meter calibration options are shown in the following sections.

Calibrating Watt Offset Using a Reference Meter Example

Figure 82 shows the steps involved in calibrating watt offset with a reference meter.

SET I

= I

, V

= V

TEST

MIN

TEST

MEASURE THE % ERROR BETWEEN THE

CF OUTPUT AND THE REFERENCE METER

OUTPUT, AND THE LOAD IN WATTS

NOM

, PF = 1

CF Absolute Error = CF

IMIN(nominal) IMIN(expected)

− CF

(50)

CF Absolute Error =

(%ERROR

) × W

CF(IMIN) IMIN

× (51)

(imp/Wh)antMeterConst

3600

CF Absolute Error =

%3.1

⎛

⎞

⎜

⎟

100

⎝

⎠

200.3

6.9 3600

=××

Hz000110933.0

Then,

AENERGY Error Rate (LSB/s) =

CF Absolute Error ×

CFDEN

CFNUM

(52)

11+

AENERGY Error Rate (LSB/s) =

0.000110933 ×

490

05436.0

Using Equation 49, APOS is −522.

205436.0

APOS = −

522

−=

10579545.3

APOS can be represented as follows with CFNUM and WDIV set at 0:

APOS =

(imp/Wh)

CLKIN

antMeterConst

3600

CFDEN

)(% ×+×××

WERROR

−

IMINIMINCF35)(

2)1(

CALCULATE APOS. SEE EQUATION 49.

WRITE APOS VALUE TO THE APOS

Figure 82. Calibrating Watt Offset Using a Reference Meter

02875-A-008

Rev. A | Page 41 of 60

Page 42

ADE7753

Calibrating Watt Offset with an Accurate Source Example

Figure 83 is the flowchart for watt offset calibration with an accurate source.

SET I

= I

, V

= V

TEST

MIN

TEST

NOM

, PF = 1

The LAENERGY

LAENERGY

⎛

MIN

⎜

INT

⎜

⎝

at I

expected

IMIN(expected)

LAENERGY

is 1370 using Equation 53.

MIN

LINECYCI

××

)(

expectedIB

LINECYC

MIN

⎞ ⎟ ⎟ ⎠

(53)

SET HALF LINE CYCLES FOR ACCUMULATION

IN LINECYC REGISTER ADDR. 0x1C

SET MODE FOR LINE CYCLE

ACCUMULATION ADDR. 0x09 = 0x0080

ENABLE LINE CYCLE ACCUMULATION

INTERRUPT ADDR. 0x0A = 0x04

RESET THE INTERRUPT STATUS

READ REGISTER ADDR. 0x0C

INTERRUPT?

YES

RESET THE INTERRUPT STATUS

READ REGISTER ADDR. 0x0C

INTERRUPT?

READ LINE ACCUMULATION ENERGY

CALCULATE APOS. SEE EQUATION 49.

YES

ADDR. 0x04

LAENERGY

04.0

⎛

INT

⎜

⎝

IMIN(expected)

19186

35700

2000

⎞ ⎟

⎠

×× INT

1370)80.1369(

where:

LAENERGY

is the expected LAENERGY reading at Ib

IB(expected)

from the watt gain calibration.

LINECYC

accumulated over when measuring at I

is the number of half line cycles that energy is

IMIN

MIN

More line cycles could be required at the minimum current to minimize the effect of quantization error on the offset calibration. For example, if a test current of 40 mA results in an active energy accumulation of 113 after 2000 half line cycles, one LSB variation in this reading represents an 0.8% error. This measurement does not provide enough resolution to calibrate out a <1% offset error. However, if the active energy is accumulated over 37,500 half line cycles, one LSB variation results in 0.05% error, reducing the quantization error.

APOS is −672 using Equations 55 and 49.

LAENERGY Absolute Error =

LAENERGY

IMIN(nominal)

− LAENERGY

IMIN(expected)

WRITE APOS VALUE TO THE APOS

Figure 83. Calibrating Watt Offset with an Accurate Source

02875-A-009

For this example:

Meter Constant: MeterConstant(imp/Wh) = 3.2 Line Voltage: V Line Frequency: f

= 220 V

nominal

= 50 Hz

CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Base Current: I

= 10 A

Half Line Cycles Used at Base Current: LINECYC

= 2000

(IB)

Period Register Reading: PERIOD = 8959 Clock Frequency: CLKIN = 3.579545 MHz Expected LAENERGY Register Value at Base Current (from the Watt Gain section):LAENERGY Minimum Current: I

= 40 mA

MIN

IB(expected)

= 19186

Number of Half Line Cycles used at Minimum Current: LINECYC

(IMIN)

= 35700 Active energy Reading at Minimum Current: LAENERGY

IMIN(nominal)

= 1395

LAENERGY Absolute Error = 1395 − 1370 = 25 (54)

AENERGY Error Rate (LSB/s) =

ErrorAbsoluteLAENERGY

LINECYC

CLKIN

PERIOD

××82/

(55)

AENERGY Error Rate (LSB/s) =

89598

10579545.3

CLKIN

2069948771.0

10579545.3

069948771.0

RateErrorAENERGY

672

−=

2×

2/35700

APOS = −

Rev. A | Page 42 of 60

Page 43

ADE7753

Phase Calibration Calibrating Phase Using a Reference Meter Example

The PHCAL register is provided to remove small phase errors. The ADE7753 compensates for phase error by inserting a small time delay or advance on the voltage channel input. Phase leads up to 1.84° and phase lags up to 0.72° at 50 Hz can be corrected. The error is determined by measuring the active energy at I

and two power factors, PF = 1 and PF =0.5 inductive.

A power factor of 0.5 inductive can be assumed if the pulse output rate of the reference meter is half of its PF = 1 rate. Then the %ERROR between CF and the pulse output of the reference meter can be used to perform the preceding calculations.

SET I

TEST

= Ib, V

TEST

= V

NOM

, PF = 0.5

Some CTs may introduce large phase errors that are beyond the range of the phase calibration register. In this case, coarse phase compensation has to be done externally with an analog filter.

The phase error can be obtained from either CF or LAENERGY measurements:

Error =

LAENERGY

LAENERGYLAENERGY −

expectedIB

expectedIBPFIB

)(

)(5.,

(56)

If watt gain and offset calibration have been performed, there should be 0% error in CF at unity power factor and then:

Error = %ERROR

CF(IB,PF = .5)

/100 (57)

The phase error is

Phase Error (°) = −Arcsin

⎜ ⎜ ⎝

(58)

⎟

⎠

⎞

⎛

Error

⎟

The relationship between phase error and the PHCAL phase correction register is

PHCAL=

INT

⎛

ErrorPhase 0x0D (59)

⎜ ⎝

()

PERIOD

⎞

⎟

°×°360

⎠

MEASURE THE % ERROR BETWEEN

THE CF OUTPUT AND THE

REFERENCE METER OUTPUT

CALCULATE PHCAL. SEE EQUATION 59.

WRITE PHCAL VALUE TO THE PHCAL

Figure 84. Calibrating Phase Using a Reference Meter

02875-A-010

For this example:

CF % Error at PF = .5 Inductive: %ERROR

CF(IB,PF = .5)

PERIOD Register Reading: PERIOD = 8959

Then PHCAL is 11 using Equations 57 through 59:

Error = 0.215% / 100 = 0.00215

Phase Error (°) = −Arcsin

⎛

PHCAL = INT

07.0

⎜ ⎝

×°−

⎛ ⎜ ⎜ ⎝

8959 360

⎞

00215.0

⎟ ⎟

⎠

⎞

+0x0D = −2 + 13 = 11

⎟

⎠

°−=

07.0

PHCAL can be expressed as follows:

= 0.215%

The expression for PHCAL can be simplified using the assumption that at small x:

Arcsin(x) ≈ x

The delay introduced in the voltage channel by PHCAL is

Delay = (PHCAL

− 0x0D) × 8/CLKIN (60)

The delay associated with the PHCAL register is a time delay if (PHCAL − 0x0D) is positive but represents a time advance if this quantity is negative. There is no time delay if PHCAL = 0x0D.

The phase correction is in the opposite direction of the phase error.

Phase Correction (°) = −(PHCAL

− 0x0D) (61)

°×360

PERIOD

Rev. A | Page 43 of 60

PHCAL =

INT

⎛ ⎜ ⎜ ⎝

−

Arcsin

⎞

⎛ ⎜ ⎜ ⎝

PERIODError

⎟

⎠

⎞ ⎟

+ 0x0D (62)

⎟

⎠

Note that PHCAL is a signed twos complement register.

Setting the PHCAL register to 11 provides a phase correction of 0.08° to correct the phase lead:

360

8960

×−−

)(

PERIOD

360

°=

Phase Correction (°) =

PHCAL

0x0D

)11(

×−− 08.0

Page 44

ADE7753

Calibrating Phase with an Accurate Source Example

With an accurate source, line cycle accumulation is a good method of calibrating phase error. The value of LAENERGY must be obtained at two power factors, PF = 1 and PF = 0.5 inductive.

SET I

TEST

= Ib, V

TEST

= V

NOM

, PF = 0.5

The error using Equation 56 is

191869613 −

Error =

Phase Er

19186

ror (°) = −Arcsin

0021.0

⎛ ⎜ ⎜ ⎝

⎞

0021.0

⎟ ⎟

⎠

°−=

07.0

SET HALF LINE CYCLES FOR ACCUMULATION

Figure 85. Calibrating Phase with an Accurate Source

For this example:

IN LINECYC REGISTER ADDR. 0x1C

SET MODE FOR LINE CYCLE

ACCUMULATION ADDR. 0x09 = 0x0080

ENABLE LINE CYCLE ACCUMULATION

INTERRUPT ADDR. 0x0A = 0x04

RESET THE INTERRUPT STATUS

READ REGISTER ADDR. 0x0C

INTERRUPT?

YES

RESET THE INTERRUPT STATUS

READ REGISTER ADDR. 0x0C

INTERRUPT?

YES

READ LINE ACCUMULATION ENERGY

CALCULATE PHCAL. SEE EQUATION 59.

WRITE PHCAL VALUE TO THE PHCAL

ADDR. 0x04

02875-A-011

Usin alculated to be 11g Equation 59, PHCAL is c .

8959

⎞⎛

×°−

07.0 +−=+

⎜ ⎝

Note a signed twos complement register.

that PHCAL is

360

0x0DPHCAL = INT

⎟

⎠

11132

The phase lead is corrected by 0.08° when the PHCAL register is set to 11:

360 8960

×−−

)(

PERIOD

360

°=

Phase Correction (°) =

PHCAL

0x0D

)11(

×−− 08.0

VRMS and IRMS Calibration

VRM ted by squaring the input in a S and IRMS are calcula digital multiplier.

222

The square of the rms value is extracted from v

(t) by a low-pass

filter. The square root of the output of this low-pass filter

ω×−=ω×ω=

)2cos()sin(V2)sin(V2)( tVVtttv

gives

(63)

the rms value. An offset correction is provided to cancel noise and offset contributions from the input.

There is ripple noise from the 2ω term because the low-pass filter does not completely attenuate the si

gnal. This noise can be

minimized by synchronizing the rms register readings with the

IRQ

zero crossing of the voltage signal. The

output can be

configured to indicate the zero crossing of the voltage signal.

This flowchart demonstrates how VRMS and IRMS readings ar synchronized to the zero crossings of the voltage input.

SET INTERRUPT ENABLE FOR ZERO

CROSSING ADDR. 0x0A = 0x0010

Meter Constant: MeterConstant(imp/Wh) = 3.2 Line Voltage: V Line Frequency: f

= 220 V

nominal

= 50 Hz

CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Base Current: I

= 10 A

Half Line Cycles Used at Base Current: LINECYC

= 2000

PERIOD Register: PERIOD = 8959 Expected Line Accumulation at Unity Power Factor (from Watt Gain Section: LAENERGY = 19186

IB(expected)

Active Energy Reading at PF = .5 inductive: LAENERGY

IB, PF = .5

= 9613

Rev. A | Page 44 of 60

RESET THE INTERRUPT STATUS

READ REGISTER ADDR. 0x0C

INTERRUPT?

YES

READ VRMS OR IRMS

ADDR. 0x17; 0x16

RESET THE INTERRUPT STATUS

READ REGISTER ADDR. 0x0C

02875-A-003

Figure 86. Synchronizing VRMS and IRMS Readings with Zero Crossings

Page 45

ADE7753

Voltage rms compensation is done after the square root.

VRMS = VRMS0 + VRMSOS (64)

where:

VRMS0 is the rms measurement without offset correction. VRMS is linear from full-scale to full-scale/20.

To calibrate the offset, two VRMS measurements are required, for example, at V

nominal

and V

nominal

/10. V

is set at half of the

nominal

full-scale analog input range so the smallest linear VRMS reading is at V

VRMSOS =

where VRMS correction for input V

If th plement VRMSOS regist

e range of the 12-bit, twos com er is

not enou

gh, the voltage channel offset register, CH2OS, can be

/10.

nominal

and VRMS

1 2

and V , respectively.

1 2

VRMSVVRMSV

×−×

1221

−

(65)

are rms register values without o

ffset

used to correct the VRMS offset.

Current rms compensation is performed before th

2 2

IRMS

= IRMS0

+ 32768 × IRMSOS (66

e square root:

where IRMS0 is the rms measurement without offset correction The current rms calculation is linear from full-scale to full

scale/100.

To c ffset, two IRMS measurem

alibrate this o ents are required,

for example, at I

and I

MAX

/50. I

is set at half of the full-scale

MAX

analog input range so the smallest linear IRMS reading is at

/50.

MAX

IRMSOS =

where IRMS

32768

and IRMS

1 2

correction for input I

×−×

−

are rms register values without offset

and I , respectively.

1 2

IRMSIIRMSI

(67)

)

Apparent Energy

Apparent energy gain calibration is provided for both meter-tometer gain adjustment and for setting the VAh/LSB constant.

VAENERGY =

VAENERGY

initial

1 VAGAIN

⎛

+××

VADIV

⎜ ⎝

⎞

(68)

⎟

⎠

VA DI V is similar to the CFDEN for the watt hour calibration. It should be the same across all meters and determines the VAh/LSB constant. VA G AI N is used to calibrate individual meters.

Apparent energy gain calibration should be performed before rms offset correction to make most efficient use of the current test points. Apparent energy gain and watt gain compensation require testing at I

while rms and watt offset correction require

a lower test current. Apparent energy gain calibration can be done at the same time as the watt-hour gain calibration using line cycle accumulation. In this case, LAENERGY and LVA E N E RG Y , the line cycle accumulation apparent energy register, are both read following the line cycle accumulation interrupt. Figure 87 shows a flowchart for calibrating active and apparent energy simultaneously.

VAG A IN = INT

LVA E N E RG Y

⎛ ⎜

⎜

INT

VAh

⎜

constant

⎜

LSB

⎝

⎛

LVAENERGY

⎜

LVAENERGY

⎝

IB(expected)

)(

expectedIB

nominalIB

−

)(

Bnominal

s/h3600

⎞

⎟

(69)

⎟

⎟ ⎠

⎠

⎞ ⎟

⎟

(70)

(s)

timeonAccumulati

⎟ ⎟ ⎠

The accumulation time is determined from Equation 37 and the line period can be determined from the PERIOD register according to Equation 38. The VA h represented by the VAENERGY register is

VA h = VAENERGY × VAh /LSB constant (71)

The VA h/ L SB constant can be verified using this equation:

Rev. A | Page 45 of 60

VAh

LSB

constant

timeonAccumulati

LVAENERGY

(s)

3600

(72)

Page 46

ADE7753

CALCULATE CFDEN VALUE FOR DESIGN

WRITE CFDEN VALUE TO CFDEN REGISTER

SET HALF LINE CYCLES FOR ACCUMULATION

ADDR. 0x15 = CFDEN

SET I

= Ib, V

TEST

IN LINECYC REGISTER ADDR. 0x1C

SET MODE FOR LINE CYCLE

ACCUMULATION ADDR. 0x09 = 0x0080

ENABLE LINE CYCLE ACCUMULATION

INTERRUPT ADDR. 0x0A = 0x04

RESET THE INTERRUPT STATUS

READ REGISTER ADDR. = 0x0C

RESET THE INTERRUPT STATUS

READ REGISTER ADDR. = 0x0C

= V

TEST

INTERRUPT?

YES

NOM

, PF = 1

INTERRUPT?

YES

READ LINE ACCUMULATION ENERGY

ACTIVE ENERGY: ADDR. 0x04

APPARAENT ENERGY: ADDR. 0x07

CALCULATE WGAIN. SEE EQUATION 47.

CALCULATE VAGAIN. SEE EQUATION 69. WRITE VGAIN VALUE TO ADDR. 0x1A

Figure 87. Active/Apparent Gain Calibration

Reactive Energy

Reactive energy is only available in line accumulation mode in the ADE7753. The accumulated reactive energy over LINECYC number of half line cycles is stored in the LVARENERGY register.

In the ADE7753, a low-pass filter at 2 Hz on the current channel is implemented for the reactive power calculation. This provides the 90 degree phase shift needed to calculate the reactive power. This filter introduces 1/f attenuation in the reactive energy accumulated. Compensation for this attenuation can be done externally in a microcontroller. The microcontroller can use the LVARENERGY register in order to produce a pulse output similar to the CF pulse for reactive energy.

WRITE WGAIN VALUE TO ADDR. 0x12

02875-A-004

To create a VAR pulse, an impulse/VARh constant must be determined. The 1/f attenuation correction factor is determined by comparing the nominal reactive energy accumulation rate to the expected value. The attenuation correction factor is multiplied by the contents of the LVARENERGY register, with the ADE7753 in line accumulation mode.

Rev. A | Page 46 of 60

Page 47

ADE7753

The impulse/LSB ratio used to convert the value in t LVARENERGY register into a pulse output can be expressed in terms of impulses/VA

imp/LSB =

VA RC F

IB(expected)

R h and VA R h /LSB.

LSBVARhVARhimp

// =×

)/(

VARCF

××

IVVARhimptVARConstan

bnominal

s/h3600

PERIODLVARENERGY

VA RC F

IB(nominal)

××(s)

where the accumulation time is calculated from Equation 37 The line period can be determined from the PERI

the LVARENERGY register value:

VA Rh =

IB Hz50

/ ××

PERIOD

VA R =

PERIODLSBVARhLVARENERGY

s/h3600/

PERIODtimeonAccumulati

×××(s)

The PERIOD

/PERIOD factor in the preceding VAR equations

50 Hz

is the correction factor for the 1/f frequency attenuation of the low-pass filter. The PERIOD

term refers to the line period at

50 Hz

calibration and could represent a frequency other than 50 Hz.

CLKIN FREQUENCY

In this data sheet, the characteristics of the ADE7753 are shown when CLKIN frequency is equal to 3.579545 MHz. However, the ADE7753 is designed to have the same accuracy at any CLKIN frequency within the specified range. If the CLKIN frequency is not 3.579545 MHz, various timing and filter characteristics need to be redefined with the new CLKIN frequency. For example, the cutoff frequencies of all digital filters such as LPF1, LPF2, or HPF1, shift in proportion to the change in CLKIN frequency according to the following equation:

FrequencyOriginalFrequencyNew

The change of CLKIN frequency does not affect the timing characteristics of the serial interface because the data transfer is synchronized with serial clock signal (SCLK). But one needs to observe the read/write timing of the serial data transfer—see the ADE7753 timing characteristics in Table 2. Table 9 lists various timing changes that are affected by CLKIN frequency.

×=

579545.3

PERIODtimeonAccumulati

PERIODLSBVARhLVARENERGY

FrequencyCLKIN

)(

expected

nominal

ϕ×

(73)

)sin(

(74)

Hz50

OD register

m according to Equation 38. Then VAR can be determined fro

(76

)

Hz50

(77)

(78)

MHz

Table 9. Frequen

cy Dependencies of the ADE7753 Parameters

Parameter CLKIN Dependency

Nyquist Frequency for CH 1 and CH 2 ADCs CLKIN/8 PHCAL Resolution (Seconds per LSB) 4/CLKIN Active Energy Register Update Rate (Hz) CLKIN/4 Waveform Sampling Rate (per Second) WAVSEL 1,0 = 0 0 CLKIN/128 0 1 CLKIN/256 1 0 CLKIN/512 1 1 CLKIN/1024 Maximum ZXTOUT Period 524,288/CLKIN

SUSPENDING ADE7753 FUNCTIONALITY

The analog and the digital circuit can be suspended separately. The analog portion of the ADE7753 can be suspended by setting the ASUSPEND bit (Bit 4) of the mode register to logic high— see the Mode Register (0x9) section. In suspend mode, all waveform samples from the ADCs are set to 0. The digital circuitry can be halted by stopping the CLKIN input and maintaining a logic high or low on the CLKIN pin. The ADE7753 can be reactivated by restoring the CLKIN input and setting the ASUSPEND bit to logic low.

CHECKSUM REGISTER

The ADE7753 has a checksum register (CHECKSUM[5:0]) to ensure the data bits received in the last serial read operation are not corrupted. The 6-bit checksum register is reset before the first bit (MSB of the register to be read) is put on the DOUT pin. During a serial read operation, when each data bit becomes available on the rising edge of SCLK, the bit is added to the checksum register. In the end of the serial read operation, the content of the checksum register is equal to the sum of all ones in the register previously read. Using the checksum register, the user can determine if an error has occurred during the last read operation. Note that a read to the checksum register also generates a checksum of the checksum register itself.

DOUT

Figure 88. Checksum Register for Serial Interface Read

CONTENT OF REGISTER (n-bytes)

CHECKSUM REGISTER ADDR:0x3E

02875-0-077

Rev. A | Page 47 of 60

Page 48

ADE7753

ADE7753 SERIAL INTERFACE

All ADE7753 functionality is accessible via several on-chip registers—see Figure 89. The contents of t updated or read using the on-chip serial interface. After poweron o e

r toggling th

RESET

pin low or a falling edge on CS, t ADE7753 is placed in communications mode. In communications he AD ects a write to its communications

mode, t E7753 exp

regis n to the communications register

ter. The data writte determines whether the next data transfer operation a write and also which register is accessed. Therefore all data transfer operations with the ADE7753, whether a read or a writ a write to the communications r

e, must begin with egister.

COMMUNICATIONS

DIN

DOUT

Figure 89. Addressing ADE7753 Registers via the Communications Register

The communications reg determines whether the n

ister is an 8-bit wide register. The MSB

ext data transfer operation is a read or a write. The six LSBs contain the address of the register to be accessed—see the Communications Register section for a more detailed description.

Figure 90 and Figure 91 show the data transfer sequences for a read and write operation, respectively. On completion of a data transfer (read or write), the ADE7753 once again enters communications mode. A data transfer is complete when the LSB of the ADE7753 register being addressed (for a write or a read) is transferred to or from the AD

hese registers can be

is a read or

OUT

ADDRESS

DECODE

02875-0-078

E7753.

SCLK

COMMUNICATIONS REGISTER WRITE

DIN

DOU

Figure 90. Reading the Serial Inter

SCLK

COMMUNICATIONS REGISTER WRITE

DIN

Figure 91. Writing Data to the ADE7753 via the Serial Interface

ADDRESS00

MULTIBYTE

Data from the ADE7753 via face

ADDRESS01

MULTIBYTE READ DA

READ DATA

02875-0-079

02875-0-08

The serial interface of the ADE7753 is made up of four signals: SCLK, DIN, D OUT, and

. The serial clock for a data transfer is applied at the SCLK logic input. This logic input has a Schmitt-trigger input structure that allows slow rising (and falling) clock edges to be used. All data transfer operations

are synchronized to the serial clock. Data is shifted into the ADE7753 at the DIN logic in

put on the falling edge of SCLK.

753 at the DOUT logic output Data is shifted out of the ADE7

on a rising edge of SCLK. The

logic input is the chip-select input. This input is used when multiple devices share the serial bus. A falling edge on places the ADE7753 into communications mode. The

also resets the serial interface and

inpu

t should be driven low for the entire data transfer operation. Bringing

high during a data transfer operation aborts the transfer and places the serial bus in a high impedance state. The CS

logic input can be tied low if the ADE7753 is the only device

on the serial bus. However, with

tied low, all initiated data transfer operations must be fully completed, i.e., the LSB of each register must be transferred because there is no other way bringing the ADE7753 back into communications mo without resetting the entire device by using

RESET

Rev. A | Page 48 of 60

Page 49

ADE7753

ADE7753 Serial Write Operation

The serial write sequence takes place as follows. With the ADE7753 in communications mode (i.e., the

input logic low), a write to the communications register first takes place. The MSB of this byte transfer is a 1, indicating that the data transfer operation is a write. The LSBs of this byte contain the address of the register to be written to. The ADE7753 starts shifting in the register data on the next falling edge of SCL

K. All remaining bits of register data are shifted in on the falling edge of subsequent SCLK pulses—see Figure 92. As explained earlie the data write is initiated by a write to the communications register followed by the data. During a data write operation to the ADE7753, data is transferred to all on-chip registers one byte at a time. After a byte is transferred into the serial port, there is a finite time before it is transferred to one of the ADE7753 on-chip registers. Although another byte transfer to the serial port can start while the previous byte is being transferred to an on-chip register, this second byte transfer

SCL

DIN

A4A5 A3

should not finish until at least 4 µs after the end of the previous byte transfer. This functionality is expressed in the timing specification t during a byte transfer (

—see Figure 92. If a write operation is aborted

brought high), then that byte cannot

be written to the destination register.

Destination registers can be up to 3 bytes wide—see the ADE

7753 Register Description tables. Therefore the first byte

shifted into the serial port at DI is transferred to the MSB

N (most significant byte) of the destination register. If, for example, the addressed register is 12 bits wide, a 2-byte data transfer must take place. The data is always assumed to be right justified, therefore in this case, the four MSBs of the first byte would be ignored and the four LSBs of the first byte written to the A

DE7753 would be the four MSBs of the 12-bit word.

Figure 93 illustrates this example.

DB0

DB7

DB0

COMMAND BYTE

SCLK

DIN X X X X DB11 DB10 DB9

MOST SIGNIFICANT BYTE

Figure 93. 12-Bit Serial Write Operation

MOST SIGNIFICANT BYTE

e Write Timing Figure 92. Serial Interfac

DB8

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LEAST SIGNIFICANT BYTE

02875-0-082

02875-0-081

Rev. A | Page 49 of 60

Page 50

ADE7753

ADE7753 Serial Read Operation

During a data read operation from the ADE7753, data is sh out at the DOUT logic output on the rising edge of SCLK. As the case with the data write operation, a data read must be preceded with a write to the communications register.

ifted

high impedance state on the falling edge of the last SCLK pulse.

The read operation can be aborted by bringing the

logic input high before the data transfer is complete. The DOUT output enters a high impedance state on the rising edge of

With the ADE7753 in communications mode (i.e.,

logic low), an 8-bit write to the communications register first takes place. The MSB of this byte transfer is a 0, indicating that the next data transfer operation is a read. The LSBs of this byte contain the address of the register that is to be read. The ADE7753 starts shifting out of the register data on the next rising edge of SCLK—see Figure 94. At this point, the DOUT logic output leaves its high impedance state and starts driving the data bus. All remaining bits of register data are shifted ou on subsequent SCLK rising edges. The serial interface also enters communications mode again as soon as the read has been completed. At this point, the DOUT logic output enters

SCLK

DIN

DOUT

A4A5 A3

COMMAND BYTE

Figure 94. Serial Interface Read Timing

When an ADE7753 register is addresse the entire contents of that register are transferred to the s

d for a read operation,

erial port. This allows the ADE7753 to modify its on-chip registers without the risk of corrupting data during a multibyte transf

Note that when a read operation follows a write operation, th

er.

read command (i.e., write to communications register) should

not happen for at least 4 µs after the end of the write operation. If the read command is sent within 4 µs of the write operation, the last byte of the write operation could be lost. This timing constraint is given as timing specification t

DB7

MOST SIGNIFICANT BYTE

DB0

DB7

LEAST SIGNIFICANT BYTE

DB0

02875-0-083

Rev. A | Page 50 of 60

Page 51

ADE7753

ADE7753 REGISTERS

Table 10. Summary of Registers by Address

Address Name R/W No. Bits Default Type

0x01 WAVEFORM R 24 0x0 S

0x02 AENERGY R 24 0x0 S

0x03 RAENERGY R 24 0x0 S

0x04 LAENERGY R 24 0x0 S

0x05 VAENERGY R 24 0x0 U

0x06 RVAENERGY R 24 0x0 U

0x07 LVAENERGY R 24 0x0 U

0x08 LVARENERGY R 24 0x0 S

0x09 MODE R/W 16 0x000C U

0x0A IRQEN R/W 16 0x40 U

0x0B STATUS R 16 0x0

0x0C RSTSTATUS R 16 0x0 U

0x0D CH1OS R/W 8 0x00 S

0x0E CH2OS R/W 8 0x0 S

0x0F GAIN R/W 8 0x0 U

0x10 PHCAL R/W 6 0x0D S

0x11 APOS R/W 16 0x0 S

Descriptio

Waveform data from either Channel 1, Channel 2, or the active power signal. The data source an Bits 14 an Channel 2

Active Ene in this 24-

Same as t following

Line Accu is accumu line cycles

Apparent his read-only

Same as the VAENERGY register except that the register is reset to 0 following a read operation.

Line Accumulation Apparent Energy Register. The instantaneous real power is accumulated in this read-only register over the LINECYC number of half line cycles.

Line Accumulation Reactive Energy Register. The instantaneous reactive power is accumulated in this read-only register over the LINECYC number of half line cycles.

Mode Register. This is a 16-bit register through which most of the ADE7753 functionality is accessed. Signal sample rates, filter enabling, and calibration modes are selected by writing to this register. The contents can be read at any time—see the Mode Register (0x9) section.

Interrupt Enable Register. ADE7753 interrupts can be deactivated at any time by setting the corresponding bit in this 16- bit enable register to Logic 0. The status register continues to register an interrupt event even if disabled. However, the section.

Interrupt Status Regist register contains information regarding the source of ADE7753 interrupts—the see ADE7753 Interrupts section.

Same as the interrupt status register except that the register contents are reset to 0 (all flags cleared) after a read operation.

Channel 1 Offset Adjust. Bit 6 is not used. Writing to Bits 0 to 5 allows offsets on Channel 1 to be removed—see the Analog Inputs and CH1OS Register (0x0D) sections. Writing a Logic 1 to the MSB of this register enables the digital integrator on Channel 1, a Logic 0 disables the integrator. The default value of this bit is 0.

Channel 2 Offset Adjust. Bits 6 and 7 are not used. Writing to Bits 0 to 5 of this register allows any offsets on Channel 2 to be removed—see the Analog Inputs section. Note that the CH2OS register is inverted. To apply a positive offset, a negative number is written to this register.

PGA Gain Adjust. This 8-bit register is used to adjust the gain selection for the PGA in Channels 1 and 2—see the Analog Inputs section.

Phase Calibration Register. The phase relationship between Channel 1 and 2 can be adjusted by writing to this 6-bit register. The valid content of this twos compliment register is between 0x1D to 0x21. At a line frequency of 60 Hz, this is a range from –2.06° to +0.7°—see the Phase Compensation section.

Active Power Offset Correction. This 16-bit register allows small offsets in the active power calculation to be removed—see the Active Power Calculation section.

d the length of the waveform registers are selected by data d 13 in the mode register—see the Channel 1 Sampling and

Sampling sections.

rgy Register. Active power is accumulated (integrated) over time

bit, read-only register—see the Energy Calculation section.

he active energy register except that the register is reset to 0

a read operation.

mulation Active Energy Register. The instantaneous active power

lated in this read-only register over the LINCYC number of half .

Energy Register. Apparent power is accumulated over time in t register.

IRQ

output is not activated—see the ADE7753 Interrupts

er. This is an 16-bit read-only register. The status

Rev. A | Page 51 of 60

Page 52

ADE7753

o. Bits Default Type1Description Address Name R/W N

0x12 WGAIN R/W 12 0x0 S

0x13 WDIV R/W 8 0x0 U

0x14 CFNUM R/W 12 0x3F U

0x15 CFDEN R/W 12 0x3F U

0x16 IRMS R 24 0x0 U Channel 1 RMS Value (Current Channel). 0x17 VRMS R 24 0x0 U Channel 2 RMS Value (Voltage Channel). 0x18 IRMSOS R/W 12 0x0 S et Correction Register. Channel 1 RMS Offs 0x19 VRMSOS R/W 12 0x0 S Channel 2 RMS Offset Correction Register. 0x1A VAGAIN R/W 12 0x0 S

0x1B VADIV R/W 8 0x0 U

0x1C LINECYC R/W 16 0xFFFF U

0x1D ZXTOUT R/W 12 0xFFF U

0x1E SAGCYC R/W 8 0xFF U

0x1F SAGLVL R/W 8 0x0 U

0x20 IPKLVL R/W 8 0xFF U

0x21 VPKLVL R/W 8 0xFF U

0x22 IPEAK R 24 0x0 U

0x23 RSTIPEAK

0x24 VPEAK R 24 0x0 U

0x25 RSTVPEAK R 24 0x0 U

0x26 TEMP R 8 0x0 S

R 24 0x0 U

Power Gain Adjust. This is a 12-bit register. The active power calculation can be calibrated by writing to this register. The calibration range is ±50% of the nomin

0.0244%/LSB —see the Calibrating an Energy Meter Based on the ADE7753 section.

Active Energy Divider Register. The internal active energy register is divided by the value of this register before being stored in the AENERG register.

CF Frequency Divider Numerator Register. The output frequency on the CF pin is adjusted by writing to this 12-bit read/write register—see the Energy-to-Frequency Conversion section.

CF Frequency Divider Denominator Register. The output frequency on the CF pin is adjusted by writing to this 12-bit read/write register—see the Energy-to-Frequency Conversion section.

Apparent Gain Register. App writing to this register. The calibration range is 50% of the nominal ful scale real power. The resolution of the gain adjust is 0.02444%/LSB.

Apparent Energy D divided by the value of this register before being stored in the VAENERGY register.

register is used during line cycle energy accumulation mode to set the number of half line cycles for energy accumulation—see the Line Cycle Energy Accumulation Mode section.

within a time period specified by this 12-bit register, the interrupt request line (

Sag Line Cycle Register. This 8-bit register specifies the number of consecutive line cycles the signal on Channel 2 must be below SAGLVL before th section.

signal level on Channel 2 the remain low for the number of cycles specified in the SAGCYC register before the section.

Channel 1 Peak Level Threshold (Current Channel). This register sets the level of the current peak detection. If the Channel 1 input exceeds this level, the PKI flag in the status register is set.

Channel 2 Peak Level Threshold (Voltage Ch level of the voltage peak detection. If the Channel 2 input exceeds this level, the PKV flag in the status register is set.

Channel 1 Peak Register. The maximum input value of the current channel since the last read of the register is stored in this register.

Same as Channel 1 Peak Register except that the register contents are rese to 0 after read.

Channel 2 Peak Register. The maximum input value of the voltage channel since the last read of the register is stored in this register.

Same as Channel 2 Peak Register except that the register contents are rese to 0 after a read.

Temperature Register. This is an 8-bit register which contains the result of the latest temperature conversion—see the Temperature Measurement section.

al full-scale active power. The resolution of the gain adjust is

arent power calculation can be calibrated by

ivider Register. The internal apparent energy register is

ccumulation Mode Line-Cycle Register. This 16-bit Line Cycle Energy A

IRQ) is activated—see the Zero-Crossing Detection section.

e SAG output is activated—see the Line Voltage Sag Detection

SAG pin becomes active. The signal must

SAG pin is activated—see the Line Voltage Sag Detection

Channel 2 Zero-Crossing Timeout. If no zero crossings are detected on

hat peak Sag Voltage Level. An 8-bit write to this register determines at w

annel). This register sets the

Rev. A | Page 52 of 60

Page 53

ADE7753

Address Name R/W No. Bits Default Type1Description

0x27 PERIOD R 16 0x0 U

0x28– 0x3C

0x3D TMODE R/W 8 – U e Register. Test Mod 0x3E CHKSUM R 6 0x0 U

0x3F DIEREV R 8 – U

Type decoder: U = unsigned, S = signed by twos complement method, and S* = signed by sign magnitude method.

Period of the Channel 2 (Voltage Channel) Input Estimated by ZeroCrossing Processing. The MSB of this register is always zero.

Reserved.

Checksum Register. This 6-bit read-only register is equal to the sum of all the ones in the previous read—see the ADE7753 Serial Read Operation section.

Die Revision Register. This 8-bit read-only register contains the revision number of the silicon.

Rev. A | Page 53 of 60

Page 54

ADE7753

ADE7753 REGISTER DESCRIPTIONS

All ADE7753 functionality is accessed via the on-chip registers. ions register

en transferring the r ister data. A ful escription the face protocol is given in the ADE7753 Serial Interface section.

and th eg l d of serial inter

MU ONS R

COM NICATI EGISTER

omm regis is a -bit, wri ly regis wh

The c unications ter n 8 te-on ter ich controls the serial data transfer between the ADE7753 and the host processor. All data transfer operations must begin with a write t regist desig

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W/R 0 A5 A4 A3 A2 A1 A0

ermines

er det whether the n peration is a read o wr

s for th

nation e comm catio s register

ext o

uni .

Table 11. Communications Register

Bit Location

0 to 5 A0 to A5

6 RESERVED This bit is unused and should be set to 0. 7 W/R

Bit Mnemonic Description

The six LSBs of the communications register specify the register for the data transfer operation. Table 10 lists the address of each ADE7753 on-chip register.

When this bit is a Logic 1, the data transfer operation immediately following the write to the communications register is interpreted as a write to the ADE7753.

When this bit is a Logic 0, the data transfer operation immediately following the write to the communications register is interpreted as a read operation.

MODE REGISTER (0x09)

The ADE7753 functionality is configured by writing to the mode register. Table 12 describes the functionality of each bit in the register.

Each register is accessed by first writing to the communicat

o the communications register. The data written to the communications

r a ite and which register is being accessed. Table 11 outlines the bit

Table 12. Mode Register

Bit Location

0 DISHPF 0 HPF (high-pass filter) in Channel 1 is disabled when this bit is set. 1 DISLPF2 0 LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set. 2 DISCF 1 Frequency output CF is disabled when this bit is set. 3 DISSAG 1 Line voltage sag detection is disabled when this bit is set. 4 ASUSPEND 0

5 TEMPSEL 0

6 SWRST 0

7 CYCMODE 0 Setting this bit to Logic 1 places the chip into line cycle energy accumulation mode. 8 DISCH1 0 ADC 1 (Channel 1) inputs are internally shorted together. 9 DISCH2 0 ADC 2 (Channel 2) inputs are internally shorted together. 10 SWAP 0

12, 11 DTRT1, 0 00

Bit Mnemonic

Default Value

Description

By setting this bit to Logic 1, both ADE7753 A/D converters can be turned off. In normal operation, this bit should be left at Logic 0. All digital functionality can be stopped by suspending the clock signal at CLKIN pin.

Temperature conversion starts when this bit is set to 1. This bit is automatically reset to 0 when the temperature conversion is finished.

Software Chip Reset. A data transfer should not take place to the ADE7753 for at least 18 µs after a software reset.

By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the analog inputs V1P and V1N are connected to ADC 2.

These bits are used to select the waveform register update rate. DTRT 1 DTRT0 Update Rate 0 0 27.9 kSPS (CLKIN/128) 0 1 14 kSPS (CLKIN/256) 1 0 7 kSPS (CLKIN/512) 1 1 3.5 kSPS (CLKIN/1024)

Rev. A | Page 54 of 60

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ADE7753

Bit Location

14, 13

15 POAM 0 Writing Logic 1 to this bit allows only positive power to be accumulated in the ADE7753.

(WAVEFORM SELECTION FOR SAMPLE MODE)

(SHORT THE ANALOG INPUTS ON CHANNEL 2)

(SHORT THE ANALOG INPU

Bit Mnemonic

WAVSEL1, 0 00

TIVE ONLY AC MULATION)

(POSI CU

(WAVEFOR PLES OUTPU

M SAM

00 = 27.9kSP 01 = 14.4kSP

10 = 7.2kSP

11 = 3.6kSP

(SWAP CH1 AND CH2 ADCs)

TS ON CHANNEL 1)

Default Value

WAVSEL

00 = LPF2

= RESERVED

10 = CH1 11 = CH2

T DATA RATE)

S (CLKIN/128) S (CLKIN/256) S (CLKIN/512)

S (CLKIN/1024)

SWAP

DISCH2

DISCH1

Description

These bits are used to select the source of the sampled data for the waveform register.

WAVSEL1, 0 Length Source 0 0 24 bits active power signal (output of LPF2) 0 1 Reserved

1 0 24 bits Channel 1 1 1 24 bits Channel 2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000001100

DTRT

ADDR: 0x09

DISHPF (DISABLE HPF1 IN CHANNEL 1)

DISLPF2 (DISABLE LPF2 AFTER MULTIPLIER)

DISCF (DISABLE FREQUENCY OUTPUT CF)

DISSAG (DISABLE SAG OUTPUT)

ASUSPEND (SUSPEND CH1 AND CH2 ADCs)

TEMPSEL (START TEMPERATURE SENSING)

SWRST (SOFTWARE CHIP RESET)

CYCMODE (LINE CYCLE ENERGY ACCUMULATION MODE)

NOTE: REG

ISTER CONTENTS SHOW POWER-ON DEFAULTS

Figure 95. Mode Register

02875-0-084

Rev. A | Page 55 of 60

Page 56

ADE7753

)

INTERRU RESET IN INTER T ENABLE EGI x0A)

The status register is used by the MCU to e source o rupt req ADE7753, the corresponding flag in the i rrupt status register i t to logic high e interrupt enable register, the interrupt status register to determine the rce of the interrupt.

P R (0

T STATUS

T TA EGI ,

ERRUPT S

EGISTER

TUS R

x0B),

STER (0x0C)

RUP R STER (0

determine th f an inter uest (

nte s se . If the ena

IRQ

logic output goes active low. When the MCU services the i rupt, it must first carry out a read from the

sou

nter

IRQ

). When an interrupt event occurs

ble bit for this flag is Logic 1 in th

in the

Table 13. Interrupt Status Register, Rese terrupt Status Register, and Interrup

Bit Interru

ocation

0 AEHF

Flag Description

Indicates that an interrupt was caused by the 0-to-1 transition of the MSB of the active energy register, i.e., the

t In t Enable Register

AENERGY register is half full. 1 SAG Indicates that an interrupt was caused by a SAG on the line voltage. 2 CYCEND

Indicates the end of energy accumulation over an integer number of half line cycles as defined by the content

of the LINECYC register—see the Line Cycle Energy Accumulation Mode section. 3 WSMP Indicates that new data is present in the waveform register. 4 ZX This status bit reflects the status of the ZX logic ouput—see the Zero-Crossing Detection section. 5 TEMP Indicates that a temperature conversion result is available in the temperature register. 6 RESET

Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has no

function in the interrupt enable register, i.e., this status bit is set at the end of a reset, but it cannot be enabled

to cause an interrupt. 7 AEOF Indicates that the active energy register has overflowed. 8 PKV Indicates that waveform sample from Channel 2 has exceeded the VPKLVL value. 9 PKI Indicates that waveform sample from Channel 1 has exceeded the IPKLVL value. A VAEHF

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the apparent energy register, i.e.,

the VAENERGY register is half full. B VAEOF Indicates that the apparent energy register has overflowed. C ZXTO

Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the specified number

of line cycles—see the Zero-Crossing Timeout section. D PPOS Indicates that the power has gone from negative to positive. E PNEG Indicates that the power has gone from positive to negative. F RESERVED Reserved.

897 4562301

ADDR: 0x0A, 0x0B, 0x0C

AEHF (ACTIVE ENERGY HALF-FULL)

SAG (SAG ONLINE VOLTAGE)

CYCEND (END OF LINECYC HALF LINE CYCLES)

WSMP (WAVEFORM SAMPLES DATA READY)

ZX (ZERO CROSSING)

TEMPL (TEMPERATURE DATA READY)

RESET (END OF SOFTWARE/HARDWARE RESET)

AEOF (ACTIVE ENERGY REGISTER OVERFLOW)

02875-A-013

RESERVED

(POWER POSITIVE TO NEGATIVE)

(POWER NEGATIVE TO POSITIVE)

(ZERO-CROSSING TIMEOUT)

(VAENERGY OVERFLOW)

(VAENERGY IS HALF-FULL)

(CHANNEL 1 SAMPLE ABOVE IPKLVL)

(CHANNEL 2 SAMPLE ABOVE VPKLVL

PNEG

PPOS

ZXTO

VAEOF

VAEHF

PK1

PKV

15 14 13 12 11 10

00000 00000000000

Figure 96. Interrupt Status/Interrupt Enable Register

Rev. A | Page 56 of 60

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ADE7753

CH1OS REGISTER (0x0D)

The CH1OS register is an 8-bit, read/write enabled register Channel 1, and Bits 0 to 5 indicates the amount o

f the offset correction in Channel 1. Table 14 summarizes the function of this register.

Table 14. CH1OS Register

Bit Location

0 to 5 OFFSET

Bit Mnemonic Description

The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1 ADC. The 6-bit offset correction is sign and magnitude coded. Bits 0 to 4 indicate the magnitude of the offset correction. Bit 5 shows the sign of the offset correction. A 0 in Bit 5 means the offset

indicates the offset correction is negative. 6 Not Used used. This bit is un 7 INTEGRATOR

This bit is used to activate the digital integrator on Channel 1. The digital integrator is switched on by setting

this bit. This bit is set to be 0

DIGITAL INTEGRATOR SELECTION

1 = ENABLE

0 = DISABLE

NOT USED

. The MSB of this register is used to switch on/off the digital integrator in

correction is positive and a 1

on default.

76543210

00000000

Figure 97. Channel 1 Offset Register

ADDR: 0x0D

SIGN AND MAGNITUDE CODED OFFSET CORRECTION BITS

02875-0-086

Rev. A | Page 57 of 60

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ADE7753

S OUTLINE DIMENSION

2.00 MAX

0.05 MIN

COPLANARITY

0.10

Figure 98. 20-Lead Shrink Small Outline Package [SSOP]

7.50

7.20

6.90

20 11

5.60

5.30

8.20

5.00

0.25

0.09

SEATING PLANE

7.80

7.40

8° 4° 0°

0.65

BSC

COMPLIANT TO JEDEC STANDARDS MO-150AE

1.85

1.75

1.65

0.38

0.22

0.95

0.75

0.55

ORDERING GUIDE

Model Package Description Package Option Temperature Range

ADE7753ARS 20-Lead SSOP RS-20 −40°C to +85°C ADE7753ARSRL 20-Lead SSOP RS-20 −40°C to +85°C ADE7753ARSZ ADE7753ARSZRL1 20-Lead SSOP RS-20 −40°C to +85°C EVAL-ADE7753EB Evaluation Board

Z = Pb-free part.

20-Lead SSOP RS-20 −40°C to +85°C

Rev. A | Page 58 of 60

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ADE7753

NOTES

Rev. A | Page 59 of 60

Page 60

ADE7753

NOTES

D02875–0–6/04(A)

Rev. A | Page 60 of 60

Datasheet ADE7753 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

TERMINOLOGY

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

ANALOG INPUTS

di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR

ZERO-CROSSING DETECTION

Zero-Crossing Timeout

POWER SUPPLY MONITOR

PERIOD MEASUREMENT

LINE VOLTAGE SAG DETECTION

Sag Level Set

PEAK DETECTION

Peak Level Set

Peak Level Record

ADE7753 INTERRUPTS

Using the ADE7753 Interrupts with an MCU

Interrupt Timing

TEMPERATURE MEASUREMENT

ADE7753 ANALOG-TO-DIGITAL CONVERSION

Antialias Filter

ADE7753 Reference Circuit

ADC Transfer Function

CHANNEL 1 ADC

Channel 1 Sampling

Channel 1 RMS Calculation

Channel 1 RMS Offset Compensation

CHANNEL 2 ADC

Channel 2 Sampling

Channel 2 RMS Calculation

Channel 2 RMS Offset Compensation

PHASE COMPENSATION

ACTIVE POWER CALCULATION

ENERGY CALCULATION

Integration Time under Steady Load

POWER OFFSET CALIBRATION

ENERGY-TO-FREQUENCY CONVERSION

LINE CYCLE ENERGY ACCUMULATION MODE

POSITIVE-ONLY ACCUMULATION MODE

NO-LOAD THRESHOLD

REACTIVE POWER CALCULATION

SIGN OF REACTIVE POWER CALCULATION

APPARENT POWER CALCULATION

Apparent Power Offset Calibration

APPARENT ENERGY CALCULATION

Integration Times under Steady Load

LINE APPARENT ENERGY ACCUMULATION

ENERGIES SCALING

CALIBRATING AN ENERGY METER BASED ON THE ADE7753

Watt Gain

Calibrating Watt Gain Using a Reference Meter Example

Calibrating Watt Gain Using an Accurate Source Example

Watt Offset

Calibrating Watt Offset Using a Reference Meter Example

Calibrating Watt Offset with an Accurate Source Example

Phase Calibration Calibrating Phase Using a Reference Meter Example

Calibrating Phase with an Accurate Source Example

VRMS and IRMS Calibration

Apparent Energy

Reactive Energy

CLKIN FREQUENCY

SUSPENDING ADE7753 FUNCTIONALITY

CHECKSUM REGISTER

ADE7753 SERIAL INTERFACE

ADE7753 Serial Write Operation

ADE7753 Serial Read Operation

ADE7753 REGISTERS

ADE7753 REGISTER DESCRIPTIONS

MODE REGISTER (0x09)