Datasheet ADE7752EB, ADE7752AR Datasheet (Analog Devices)

PRELIMINARY TECHNICAL DATA

Three Phase Energy Metering IC

=

Preliminary Technical Data

FEATURES
High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036

Less than 0.1% Error Over a Dynamic Range of
500 to 1

Compatible with 3-phase/3-wire and 3-phase/4-wire

configurations

The ADE7752 Supplies Average Real Power on the

Frequency Outputs F1 and F2

The High Frequency Output CF Is Intended for

Calibration and Supplies

The Logic Output REVP indicates a Potential Miswiring or

Negative Power for each phase

Direct Drive for Electromechanical Counters and

Two Phase Stepper Motors (F1 and F2)

Proprietary ADCs and DSP Provide High Accuracy over

Large Variations in Environmental Conditions and

Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V ± 8% (30 ppm/8C Typical)

with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low Cost CMOS Process

Instantaneous Real Power

with Pulse Output

ADE7752*

GENERAL DESCRIPTION

The ADE7752 is a high accuracy three phase electrical
energy measurement IC. The part specifications surpass the
accuracy requirements as quoted in the IEC1036 standard.
The only analog circuitry used in the ADE7752 is in the
ADCs and reference circuit. All other signal processing (e.g.,
multiplication, filtering and summation) is carried out in the
digital domain. This approach provides superior stability and
accuracy over extremes in environmental conditions and over
time.
The ADE7752 supplies average real power information on
the low frequency outputs F1 and F2. These logic outputs
may be used to directly drive an electromechanical counter or
interface with an MCU. The CF logic output gives instan­taneous real power information. This output is intended to be
used for calibration purposes, or as interface with an MCU.
The ADE7752 includes a power supply monitoring circuit
on the AV
until the supply voltage on V
below 4 V, the ADE7752 will also be reset and no pulses will
be issued on F1, F2 and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched. An internal no-load
threshold ensures that the ADE7752 does not exhibit any
creep when there is no load.
The ADE7752 is available in 24-lead SOIC packages.

supply pin. The ADE7752 will remain inactive

DD

reaches 4 V. If the supply falls

DD

FUNCTIONAL BLOCK DIAGRAM

5

*Patents pending

IAP
IAN

VAP

IBP
IBN

VBP

ICP
ICN

VCP

VN

6

16

7

8

15

10

14

13

2.5V
REF

11 12 4 18 21 22 23 24 1

AGND

4kΩ

ADC

ADC

ADC

ADC

ADC

ADC

REF

CORRECTION

CORRECTION

CORRECTION

IN/OUT

HPF

Φ

PHASE

HPF

Φ

PHASE

HPF

Φ

PHASE

REV. PrB 08/01

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

VDD

Power
Supply
Monitor

LPF

RESET

17 3

ADE7752

LPF

LPF

DIGITAL-TO-FREQUENCY

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

Σ

CONVERTER

S0SCFREVP

CFS1 F1F2

2

DGND

19

CLKIN

20

CLKOUT

PRELIMINARY TECHNICAL DATA

(VDD = 5 V ⴞ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz,
T

to T

ADE7752–SPECIFICATIONS

MIN

Parameter Units Test Conditions/Comments

ACCURACY

1, 2

Measurement Error1 on Current Channel Voltage Channel with Full-Scale Signal (±500 mV),

0.1 % Reading typ Over a Dynamic Range 500 to 1

Phase Error

1

Between Channels Line Frequency = 45 Hz to 65 Hz
(PF = 0.8 Capacitive) ±0.1 Degrees(°) max
(PF = 0.5 Inductive) ±0.1 Degrees(°) max

AC Power Supply Rejection

1

Output Frequency Variation (CF) 0.01 % Reading typ V1 = 100 mV rms, V2 = 100 mV rms, @ 50 Hz

DC Power Supply Rejection

1

Output Frequency Variation (CF) 0.01 % Reading typ V1 = 100 mV rms, V2 = 100 mV rms,

ANALOG INPUTS See Analog Inputs Section

Maximum Signal Levels ±0.125 V max VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN, ICP and

Input Impedance (DC) 400 kΩ min CLKIN = 10 MHz
Bandwidth (–3 dB) TBD kHz typ CLKIN/256, CLKIN = 10 MHz
ADC Offset Error
Gain Error

Gain Error Match

1, 2

1

1

±15 mV max See Terminology and
±4 % Ideal typ External 2.5 V Reference,

±0.2 % Ideal typ External 2.5 V Reference

REFERENCE INPUT

REF

Input Voltage Range 2.7 V max 2.5 V + 8%

IN/OUT

2.3 V min 2.5 V – 8%

Input Impedance 3.7 kΩ min
Input Capacitance 10 pF max

ON-CHIP REFERENCE Nominal 2.5 V

Reference Error ±200 mV m ax
Temperature Coefficient 30 ppm/°C typ

CLKIN Note All Specifications for CLKIN of 10 MHz

Input Clock Frequency 15 MHz max

5 MHz min

LOGIC INPUTS

3

SCF, S0, S1, and 4-5-6

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

LOGIC OUTPUTS

INH

INL

IN

IN

3

2.4 V min VDD = 5 V ± 5%

0.8 V max VDD = 5 V ± 5%
±3 µA max Typically 10 nA, VIN = 0 V to V
10 pF max

F1 and F2

Output High Voltage, V

OH

4.5 V min V

Output Low Voltage, V

OL

0.5 V max V

CF and REVP

Output High Voltage, V
Output Low Voltage, V

OL

OH

4 V min VDD = 5 V, I

0.5 V max VDD = 5 V, I

POWER SUPPLY For Specified Performance

V

DD

4.75 V min 5 V – 5%

5.25 V max 5 V + 5%

I

DD

NOTES

1

See Terminology Section for explanation of specifications.

2

See Plots in Typical Performance Graphs.

3

Sample tested during initial release and after any redesign or process change that may affect this parameter.

Specifications subject to change without notice.

4 mA typ

= –40ⴗC to +85ⴗC)

MAX

+25°C

S0 = S1 = 1

Ripple on V

of 200 mV rms @ 100 Hz

DD

S0 = S1 = 1

VDD = 5 V ± 250 mV

ICN to AGND

V1 = 125 mV dc, V2 = 125 mV dc

DD

I

= 10 mA

SOURCE

= 5 V

DD

I

= 10 mA

SINK

= 5 V

DD

= 5 mA

SOURCE

= 5 mA

SINK

–2–

REV. PrB 08/01

PRELIMINARY TECHNICAL DATA

(VDD = 5 V ⴞ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz,

TIMING CHARACTERISTICS

Parameter Units Test Conditions/Comments

3

t

1

t

2

t

3

3, 4

t

4

t

5

t

6

NOTES

1

Sample tested during initial release and after any redesign or process change that may affect this parameter.

2

See Figure 1.

3

The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section.

4

The CF pulse is always 1 µs in the high frequency mode. See Frequency Outputs section and Table IV.

Specifications subject to change without notice.

275 ms F1 and F2 Pulsewidth (Logic High)
See Table III sec Output Pulse Period. See Transfer Function Section
1/2 t

2

90 ms CF Pulsewidth (Logic High)
See Table IV sec CF Pulse Period. See Transfer Function Section
CLKIN/4 sec Minimum Time Between F1 and F2 Pulse

1, 2

T

to T

MIN

sec Time Between F1 Falling Edge and F2 Falling Edge

= –40ⴗC to +85ⴗC)

MAX

ADE7752

t

1

F1

t

t

6

2

t

F2

t

4

CF

3

t

5

Figure 1. Timing Diagram for Frequency Outputs

ORDERING GUIDE

Model Package Description Package Option

ADE7752AR SOIC Package R-24
EVAL-ADE7752EB ADE7752 Evaluation

Board

REV. PrB 08/01

3–

ADE7752

WARNING!

ESD SENSITIVE DEVICE

PRELIMINARY TECHNICAL DATA

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

DD

Analog Input Voltage to AGND

VAP, VBP, VCP, VN, IAP, IAN, . . . . . . . . . . . . . . . . . .

IBP, IBN, ICP and ICN . . . . . . . . . . . . . –6 V to +6 V

Reference Input Voltage to AGND –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . –0.3 V to V
Digital Output Voltage to DGND –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

24-Lead SOIC, Power Dissipation . . . . . . . . . TBD mW

Thermal Impedance . . . . . . . . . . . . . . . . . . 250 °C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Operating Temperature Range

Industrial . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADE7752 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

TERMINOLOGY

MEASUREMENT ERROR

The error associated with the energy measurement made by
the ADE7752 is defined by the following formula:

ErrorPercentage

EnergyTrue

EnergyTrue–ADE7752thebyRegisteredEnergy

×=

ADC OFFSET ERROR

This refers to the dc offset associated with the analog inputs
to the ADCs. It means that with the analog inputs connected
to AGND the ADCs still see an analog input signal of 1 mV
to 10 mV, depending on gain setting. However, as the HPF

%100

is always present, the offset is removed from the current
channel and the power calculation is not affected by this

PHASE ERROR BETWEEN CHANNELS

offset.

The HPF (High Pass Filter) in the current channel has a
phase lead response. To offset this phase response and
equalize the phase response between channels a phase correc­tion network is also placed in the current channel. The phase
correction network ensures a phase match between the
current channels and voltage channels to within ±0.1° over a
range of 45Hz to 65Hz and ±0.2° over a range 40Hz to 1kHz.
This phase mismatch between the voltage and the current

GAIN ERROR

The gain error of the ADE7752 is defined as the difference
between the measured output frequency (minus the offset) and
the ideal output frequency. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is
obtained from the ADE7752 transfer function—see Transfer
Function section.

channels can be further reduced with the phase calibration
register in each phase.
See Figures 18 and 19.

POWER SUPPLY REJECTION

This quantifies the ADE7752 measurement error as a per­centage of reading when the power supplies are varied.

For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then
introduced onto the supplies and a second reading obtained
under the same input signal levels. Any error introduced is
expressed as a percentage of reading—see Measurement Error
definition.

For the dc PSR measurement a reading at nominal supplies
(5 V) is taken. The supply is then varied ±5% and a second
reading is obtained with the same input signal levels. Any
error introduced is again expressed as a percentage of
reading.

–4–

REV. PrB 08/01

PRELIMINARY TECHNICAL DATA

ADE7752

PIN FUNCTION DESCRIPTION

Pin No. MNEMONIC DESCRIPTION

1 C F Calibration Frequency Logic Output. The CF logic output gives instantaneous real

power information. This output is intended to be used for calibration purposes. Also see
SCF pin description.

2 DGND This provides the ground reference for the digital circuitry in the ADE7752, i.e. multi-

plier, filters and digital-to-frequency converter. Because the digital return currents in
the ADE7752 are small, it is acceptable to connect this pin to the analog ground plane
of the whole system - see Applications Information. However high bus capacitance on the
DOUT pin may result in noisy digital current which could affect performance.

3 V

DD

4 REVP This logic output will go logic high when negative power is detected on any of the three

5,6; I
7,8; I
9,10 I

, IAN; Analog inputs for current channel. This channel is intended for use with the current

AP

, IBN; transducer and is referenced in this document as the current channel. These inputs are

BP

, I

CP

CN

11 AGND This pin provides the ground reference for the analog circuitry in the ADE7754, i.e.

12 REF

13-16 V

17

IN/OUT

, Analog inputs for the voltage channel. This channel is intended for use with the voltage

N,VCP

, V

V

BP

AP

RESET Reset pin for the ADE7752. A logic low on this pin will hold the ADCs and digital

18 S CF Select Calibration Frequency. This logic input is used to select the frequency on the

Power supply. This pin provides the supply voltage for the digital circuitry in the
ADE7752. The supply voltage should be maintained at 5V ± 5% for specified opera­tion. This pin should be decoupled to DGND with a 10µF capacitor in parallel with a
ceramic 100nF capacitor.

phase inputs, i.e., when the phase angle between the voltage and the current signals is
greater that 90°. This output is not latched and will be reset when positive power is
once again detected. The output will go high or low at the same time as a pulse is is­sued on CF.

fully differential voltage inputs with maximum differential input signal levels of
±0.125V -See Analog Inputs. Both inputs have internal ESD protection circuitry, and in
addition an overvoltage of ±6V can be sustained on these inputs without risk of perma
nent damage.

ADCs, temperature sensor, and reference. This pin should be tied to the analog ground
plane or the quietest ground reference in the system. This quiet ground reference
should be used for all analog circuitry, e.g. anti aliasing filters, current and voltage
transducers etc. In order to keep ground noise around the ADE7754 to a minimum, the
quiet ground plane should only connected to the digital ground plane at one point. It is
acceptable to place the entire device on the analog ground plane - see Applications Informa-

tion.

This pin provides access to the on-chip voltage reference. The on-chip reference has a
nominal value of 2.5V ± 8% and a typical temperature coefficient of 30ppm/°C. An
external reference source may also be connected at this pin. In either case this pin
should be decoupled to AGND with a 1µF ceramic capacitor.

transducer and is referenced as the voltage channel in this document. These inputs are
single-ended voltage inputs with maximum signal level of ±0.125V with respect to V

N

for specified operation. All inputs have internal ESD protection circuitry, and in addi
tion an over voltage of ±6V can be sustained on these inputs without risk of permanent
damage.

circuitry (including the Serial Interface) in a reset condition.

calibration output CF. Table IV shows how the calibration frequencies are selected.

REV. PrB 08/01

–5–

PRELIMINARY TECHNICAL DATA

T

ADE7752

Pin No. MNEMONIC DESCRIPTION

19 CLKIN Master clock for ADCs and digital signal processing. An external clock can be pro-

vided at this logic input. Alternatively, a parallel resonant AT crystal can be connected
across CLKIN and CLKOUT to provide a clock source for the ADE7752. The clock
frequency for specified operation is 10MHz. Ceramic load capacitors of between 22pF
and 33pF should be used with the gate oscillator circuit. Refer to crystal manufacturers
data sheet for load capacitance requirements

20 CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a

clock source for the ADE7752. The CLKOUT pin can drive one CMOS load when
either an external clock is supplied at CLKIN or a crystal is being used.

21, 22 S0, S1 These logic inputs are used to select one of four possible frequencies for the digital-to-

frequency conversion. This offers the designer greater flexibility when designing the
energy meter. See Selecting a Frequency for an Energy Meter Application section.

23, 24 F2, F1 Low Frequency Logic Outputs. F1 and F2 supply average real power information. The

logic outputs can be used to directly drive electromechanical counters and two phase
stepper motors. See Transfer Function section.

PIN CONFIGURATION

SOIC Package

REF

CF

DGND

VDD

REVP

IAP

IAN

IBP

IBN

ICP

ICN

AGND

In/Out

1

2

3

4

5

ADE7752

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

F1

F2

S1

S0

CLKOU

CLKIN

SCF

RESET

VAP

VBP

VCP

VN

–6–

REV. PrB 08/01

PRELIMINARY TECHNICAL DATA

Meter connections

In three phase service, two main power distribution services
exist: 3-phase 4-wire or 3-phase 3-wire. The additional wire
in the 3-phase 4-wire arrangement is the Neutral wire. The
voltage lines have a phase difference of ±120° (± 2π/3
radians) between each other - See Equation 5.

2

π

cos(2)(;)cos(2)(

ωω

4

π

cos(2)(

ω

)

tVtV

+⋅⋅=

lCC

3

Where: VA, VB and VC represent the voltage RMS value of the
different phases

The current inputs are represented by Equations 6,

cos(2)(;)cos(2)(

ωϕω

tItItItI

4

π

cos(2)(

ω

tItI

)

++⋅⋅=

ϕ

ClCC

3

Where: IA, IB and IC represent the RMS value of the current
of each phase and φ

, φB and φC the phase difference of the

A

current and voltage channel of each phase.

The instantaneous powers can then be calculated as follows:

)()()(

tItVtP

⋅=

AAA

)()()(

tItVtP

⋅=

BBB

)()()(

tItVtP

⋅=

CCC

Then,

ϕωϕ

+⋅⋅−⋅⋅=

)2cos()cos()(

tIVIVtP

AlAAAAAA

π

4

ωϕ

2cos()cos()(

tIVIVtP

3

π

8

ωϕ

2cos()cos()(

tIVIVtP

3

(7)

ϕ

++⋅⋅−⋅⋅=

)

BlBBBBBB

ϕ

++⋅⋅−⋅⋅=

)

ClCCCCCC

As can be seen from Equation 7, in the ADE7752 the real
power calculation per phase is made when current and voltage
inputs of the one phase are connected to the same channel (A,
B or C). Then, the summation of each individual real power
calculation gives the total Real Power information. P(t) =

(t) + PB(t) + PC(t)

P

A

Figure 14 demonstrates the connections of the analog inputs
of the ADE7752 with the power lines in a 3-phase 3-wire
Delta service.

)

tVtVtVtV

+⋅⋅=⋅⋅=

lBBlAA

(5)

3

2

π

)

++⋅⋅=+⋅⋅=

ϕ

BlBBAlAA

(6)

3

ADE7752

Cf

*

Ra

*

Rb

*

VR

Anti-aliasing

Filters

Rf

Anti-aliasing

Filters

Phase A

Source

Phase B

Rb

CT

Phase C

CT

Cf

*

Ra

*

Rb

*

VR

Rb

Figure 14 - 3-phase 3-wire meter connection with ADE7752

Note: Only 2 current inputs and 2 voltage inputs of the
ADE7752 are used in this case. The Real power calculated
by the ADE7752 does not depend on the selected channel.

Figure 15 demonstrates the connections of the analog inputs
of the ADE7752 with the power lines in a 3-phase 4-wire Wye
service.

Cf

*

Ra

*

Rb

*

VR

Anti-aliasing

*

*

Cf

Anti-aliasing

Filters

Filters

Phase A

Source

Rf

Phase C

*

Ra

*

Rb

*

VR

Cf

Phase B

Cf

VN

Rb

CT

*

Ra

Rb

VR

CT

Rb

VAP

IAP

IAN

IBP

IBN

VBP

Load

VN

Cf

IBP

IBN

VBP

VAP

IAP

IAN

CT

Rb

Anti-aliasing

Filters

ICP

ICN

VCP

Load

REV. PrB 08/01

Figure 15 - 3-phase 4-wire meter connection with ADE7752

–7–

ADE7752

gy

PRELIMINARY TECHNICAL DATA

TRANSFER FUNCTION
Frequency Outputs F1 and F2

The ADE7752 calculates the product of six voltage signals
(on Current channel and Voltage channel) and then low-pass
filters this product to extract real power information. This
real power information is then converted to a frequency. The
frequency information is output on F1 and F2 in the form of
active high pulses. The pulse rate at these outputs is relatively
low, e.g., 0.08 Hz maximum for AC signals with SCF = S0
= S1 = 1—see Table III. This means that the frequency at
these outputs is generated from real power information
accumulated over a relatively long period of time. The result
is an output frequency that is proportional to the average real
power. The averaging of the real power signal is implicit to
the digital-to-frequency conversion. The output frequency or
pulse rate is related to the input voltage signals by the
following equation.

Freq

=

()

2

V

REF

××+×+××

FIVIVIV

CCNBBNAAN

51

−

2.109

where:

Freq = Output frequency on F1 and F2 (Hz)

V

, VBN and VCN = Differential rms voltage signal on Volt-

AN

age channels (volts)

I

, IB and IC= Differential rms voltage signal on Current

A

channels (volts)

V

= The reference voltage (2.5 V ± 8%) (volts)

REF

F

= One of five possible frequencies selected by

1–5

using the logic inputs SCF, S0 and S1—see
Table II.

Table II. F

SCF S1 S0 F

1 1 1 0.596 10 MHz/2
0 1 1 76.3 10 MHz/2

- 1 0 19.07 10 MHz/2

- 0 1 4.77 10 MHz/2

- 0 0 1.19 10 MHz/2

NOTE
*F

is a binary fraction of the master clock and therefore will vary if the specified

1–5

CLKIN frequency is altered.

Frequency Selection

1–5

(Hz) XTAL/CLKIN*

1–5

24

17

19

21

23

Example 1

Thus if full-scale differential DC voltages of +125 mV and –
125 mV are applied to VA, VB, VC, IA, IB and IC respec­tively (125 mV is the maximum differential voltage that
can be connected to Current and Voltage channels), the
expected output frequency is calculated as follows:

F

V

= 0.596 Hz, SCF = S0 = S1 = 1

1–5

= VBN = VCN = IA = IB = IC

AN

= +125 mV dc = 0.125 V (rms of dc = dc)

V

= 2.5 V (nominal reference value).

REF

NOTE: If the on-chip reference is used, actual
output frequencies may vary from device to device
due to reference tolerance of ±8%.

×××

596.0125.0125.02.109

=

HzFreq

488.0

Example 2

×=

3

2

5.2

In this example, with AC voltages of ±500 mV peak ap­plied to the Voltage channels and Current channels, the
expected output frequency is calculated as follows:

F

1–5

V

AN

V

REF

= 0.596 Hz, SCF = S0 = S1 = 1

= VBN = VCN = IA = IB = IC

= 125 mV peak AC = 0.125/

= 2.5 V (nominal reference value).

volts rms

2

NOTE: If the on-chip reference is used, actual
output frequencies may vary from device to device
due to reference tolerance of ±8%.

596.0125.0125.02.109

3

×=

×××

2

5.222

××

HzFreq

24.0

=

As can be seen from these two example calculations, the
maximum output frequency for AC inputs is always half of
that for DC input signals. The maximum frequency depends
also on the number of phases connected to the ADE7752. In
a 3-phase 3-wire delta service the maximum output frequency
is different from the maximum output frequency in a 3-phase
4-wire Wye service. The reason is that there are only 2 phases
connected to the analog inputs but also that in a delta service,
the Current channel input and Voltage channel input of the
same phase are not in phase in normal operation.

Example 3

In this example, the ADE7752 is connected to a 3-phase 3­wire delta service as shown in Figure 14. The total real energy
calculation processed in the ADE7752 can be expressed as:

Re

alTotal

()()

×−+×−=

IVVIVVEner

BCBACA

Where VA, VB and VC represent respectively the voltage on
phase A, B and C. IA and IB represent respectively the current
on phase A and B.
As the voltage and current inputs respect Equations 5 and 6,
the Total Real Energy (P) is:

–8–

REV. PrB 08/01

PRELIMINARY TECHNICAL DATA

ADE7752

−×−+−×−=

)()()()(

IBNIBPVCVBIANIAPVCVAP









() ()

2



+⋅⋅+

ω

cos2






cos2cos2




π





3



π

4



+⋅⋅−⋅⋅=

ωω




3



ω

cos2




⋅⋅⋅

ω

cos2




π

4

+⋅⋅−

3

tItVtVP

lAlClA












cos2

π

2



+⋅⋅⋅

ω

tItVtV



lBlClB



3

For simplification, we assume that φA = φB = φC = 0 and V
= VB =VC = V. The equation above becomes:

π

2





⋅⋅⋅=

sin2




3

π





⋅⋅⋅+

sin2









3



sin









()

π

2

ω




3



+⋅

cossin

⋅

cos

()

ω



ωπω

+⋅+⋅

ttIV



llB



ttIVP

llA

(9)

π

2






3

P then becomes:



2

π





sin

⋅⋅=











3




π





sin

⋅⋅+











3





2sin

ω



lAAN





2sin

tIV

ω



lBBN





2

π



++

tIVP






3





π



++







3



(10)

Where:

V

= V . sin(2π/3) represents the RMS voltage between

AN

VAP and VN pins of the ADE7752

= V . sin (π/3) represents the RMS voltage between

V

BN

VBP and VN pins of the ADE7752.

Table III. Maximum Output Frequency on F1 and F2

Max Frequency Max Frequency

SCF S1 S0 for DC Inputs (Hz) for AC Inputs (Hz)




1 1 1 0.48 0.24



0 1 1 62.52 31.26

A

- 1 0 15.6 7.8

- 0 1 3.9 1.95

- 0 0 0.96 0.48

Frequency Output CF

The pulse output CF (Calibration Frequency) is intended for
use during calibration. The output pulse rate on CF can be
up to 160 times the pulse rate on F1 and F2. The lower the

frequency selected, the higher the CF scaling. Table IV

F

1–5

shows how the two frequencies are related, depending on the
states of the logic inputs S0, S1 and SCF. Because of its
relatively high pulse rate, the frequency at this logic output
is proportional to the instantaneous real power. As is the case
with F1 and F2, the frequency is derived from the output of
the low-pass filter after multiplication. However, because the
output frequency is high, this real power information is
accumulated over a much shorter time. Hence less averaging
is carried out in the digital-to-frequency conversion. With
much less averaging of the real power signal, the CF output
is much more responsive to power fluctuations—see Signal
Processing Block in Figure 8.

As the LPF on each channel eliminates the 2ω

component of

l

the equation, the Real power measured by the ADE7752 is:

3

2

3

⋅⋅+⋅⋅=

IVIVP

BBNAAN

2

Where:

V

and VBN are the voltage RMS at the voltage inputs of

AN

the ADE7752 after voltage sensing

I

and IB are the voltage RMS at the current input of the

A

ADE7752 after current sensing

If full scale AC voltage of ±125 mV peak are applied to the
Voltage channels and Current channels, the expected output
frequency is calculated as follows:

F

1–5

= 0.596 Hz, SCF = S0 = S1 = 1

VAN = VBN = IA = IB

= 125 mV peak AC = 0.125/2 volts rms

VCN = IC = 0

V

REF

= 2.5 V (nominal reference value).

NOTE: If the on-chip reference is used, actual
output frequencies may vary from device to
device due to reference tolerance of ±8%.

Freq

596.0125.0125.02.109

2

×=

×××

2

5.222

××

3

14.0

=×

2

Table III shows a complete listing of all maximum output
frequencies when using all three channels inputs.

Table IV. Maximum Output Frequency on CF

SCF S1 S0 F

(Hz) CF Max for AC Signals (Hz)

1–5

0 0 0 1.19 160 x F1, F2 = 78.12
1 0 0 1.19 8 x F1, F2 = 3.90
0 0 1 4.77 160 x F1, F2 = 312.51
1 0 1 4.77 16 x F1, F2 = 31.26
0 1 0 19.07 16 x F1, F2 = 130.56
1 1 0 19.07 8 x F1, F2 = 62.49
0 1 1 76.29 8 x F1, F2 = 250
1 1 1 0.596 16 x F1, F2 = 3.90 Hz

Frequency Outputs

Figure 1 shows a timing diagram for the various frequency
outputs. The outputs F1 and F2 are the low frequency
outputs that can be used to directly drive a stepper motor or
electromechanical impulse counter. The F1 and F2 outputs
provide two alternating high going pulses. The pulsewidth

) is set at 275 ms and the time between the rising edges of

(t

1

F1 and F2 (t

) is approximately half the period of F1 (t2). If

3

however the period of F1 and F2 falls below 550 ms (1.81 Hz)
the pulsewidth of F1 and F2 is set to half of their period. The
maximum output frequencies for F1 and F2 are shown in
Table III.

The high frequency CF output is intended to be used for
communications and calibration purposes. CF produces a
90 ms-wide active high pulse (t

) at a frequency proportional

4

to active power. The CF output frequencies are given in
Table IV. As in the case of F1 and F2, if the period of CF

) falls below 180 ms, the CF pulsewidth is set to half the

(t

5

period. For example, if the CF frequency is 20 Hz, the CF
pulsewidth is 25 ms.

REV. PrB 08/01

–9–

ADE7752

PRELIMINARY TECHNICAL DATA

NO LOAD THRESHOLD

The ADE7752 also includes a “no load threshold” and
“start-up current” feature that will eliminate any creep
effects in the meter. The ADE7752 is designed to issue a
minimum output frequency. Any load generating a frequency
lower than this minimum frequency will not cause a pulse to
be issued on F1, F2 or CF. The minimum output frequency
is given as 0.0007% of the full-scale output frequency for
each of the F

frequency selections—see Table II. For

1–5

example, an energy meter with a meter constant of 100 imp/
kWhr on F1, F2 using F
frequency at F1 or F2 would be 0.0007% of 4.77 Hz or 33.3

–6

Hz. This would be 533 x 10–6Hz at CF (16 x F1 Hz).

x 10

(4.77 Hz), the minimum output

2

In this example the no load threshold would be equivalent to

1.2 W of load or a start-up current of 5.5 mA at 220 V.

REVERSE POWER INFORMATION

The ADE7752 detects when the current and voltage channels
of any of the three phase inputs have a phase difference
greater than 90° i.e. Φ

or ΦB or ΦC > 90°. This mechanism

A

can detect wrong connection of the meter or generation of
Active Energy.
The REVP pin output will go active high when negative
power is detected on any of the three phase inputs. If positive
Active Energy is detected on all the three phases, REVP pin
output is Low. The REVP pin output changes state at the
same time as a pulse is issued on CF. If several phases
measure negative power, the REVP pin output will stay low
until all the phases measure positive power.

NOTE

For a complete datasheet of the ADE7752, please contact us
on our website at:

http://forms.analog.com/Form_Pages/energymeter/
contact.asp

0.6141 (15.60)

0.5985 (15.20)

24 13

1

PIN 1

0.0118 (0.30)

0.0040 (0.10)

0.0500
(1.27)

BSC

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-SOIC Outline Package

(AR-24)

0.2992 (7.60)

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

8ⴗ
0ⴗ

0.0192 (0.49)

0.0138 (0.35)

12

0.1043 (2.65)

0.0926 (2.35)

SEATING
PLANE

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

0.0157 (0.40)

ⴛ 45ⴗ

–10–

REV. PrB 08/01