Page 1
+V
OUT
RETURN
–V
IN
+V
IN
RETURN
RETURN
+V
OUT
+V
OUT
ADJUST
STATUS
V
AUX
INHIBIT
SYNC
I
SHARE
TEMP
FIXED
FREQUENCY
DUAL
INTERLEAVED
POWER TRAIN
+SENSE
OUTPUT
FILTER
INPUT SIDE
CONTROL
CIRCUIT
EMI FILTER
ADDC02808PB
–SENSE
OUTPUT SIDE
CONTROL
CIRCUIT
28 V, 200 W Pulsed DC/DC Converter
a
FEATURES
28 V dc Input, 8 V dc @ 25 A, 200 W Pulse Output
Integral EMI Filter
Ultrafast Transient Response
Minimal Output Voltage Deviation
Low Weight: 80 Grams
NAVMAT Derated
Many Protection and System Features
APPLICATIONS
Distributed Power Architecture for Driving T/R Modules
Motor and Actuator Drivers
GENERAL DESCRIPTION
The ADDC02808PB hybrid military dc/dc converter is compensated specifically for pulse applications where fast transient
response and minimum output voltage deviation are required.
It is also designed to deliver very high, pulsed output power.
The unit is designed for high reliability and high performance
applications where saving space and/or weight are critical.
The ADDC02808PB has been characterized over a wide variety
of load conditions. Its transient response has been set to insure
output stability over a broad range of load capacitance. For
applications that require factory modified compensation
optimized for a specific load, or for applications that require a
different output voltage than 8 V dc, contact the factory.
The ADDC02808PB is available in a hermetically sealed,
molybdenum based hybrid package and is easily heatsink
mountable. Three screening levels are available, including
military SMD.
with Integral EMI Filter
ADDC02808PB
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. 120 W/cubic inch pulsed power density with an integral EMI
filter
2. Ultrafast transient response time with minimum output
voltage deviation
3. Light weight: 85 grams
4. Operational and survivable over a wide range of input conditions: 16 V–50 V dc; survives low line, high line
5. High reliability; NAVMAT derated
6. Protection features include:
Output Overvoltage Protection
Output Short Circuit Current Protection
Thermal Monitor/Shutdown
Input Overvoltage Shutdown
Input Transient Protection
7. System level features include:
Current Sharing for Parallel Operation
Logic Level Disable
Output Status Signal
Synchronization for Multiple Units
Input Referenced Auxiliary Voltage Supply
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
␣␣
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
Page 2
ADDC02808PB–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(TC = +25ⴗC, VIN = 28 V dc ⴞ0.5 V dc, unless otherwise noted; full temperature range is
–55ⴗC to +90ⴗC; all temperatures are case and TC is the temperature measured at the center of the package bottom.)
Parameter Temp Level Conditions Min Typ Max Units
INPUT CHARACTERISTICS
Steady State Operating Input Voltage Range1Full VI IO = 1.25 A to 25 A Pulsed 18 28 40 V
Abnormal Operating Input Voltage Range
(Per MIL-STD-704D)
1
Input Overvoltage Shutdown +25°C I 50 52.5 55 V
No Load Input Current +25°CVI 45 90 mA
Disabled Input Current +25°CVI 1 2 mA
OUTPUT CHARACTERISTICS
Output Voltage (V
) +25°CI I
O
2, 3
Line Regulation +25°CVI I
Load Regulation +25°CVI V
Output Ripple/Noise
Output Current (IO)
4
5
Output Overvoltage Protection +25°CV I
Output Current Limit +25°CV V
Output Short Circuit Current +25°CI 40 A
ISOLATION CHARACTERISTICS
Isolation Resistance +25°C I Input to Output or Any Pin to Case at 500 V dc 100 MΩ
DYNAMIC CHARACTERISTICS
4
Step Changes In Load (min to max) +25°C I (Reference Section Entitled “Transient Response”)
Step Changes In Load (max to min) (Reference Section Entitled “Response at End
Soft Start Turn-On Time +25°CI I
THERMAL CHARACTERISTICS
Efficiency +25°CI I
Hottest Junction Temperature
5
CONTROL CHARACTERISTICS
Clock Frequency Full VI IO = 2 A 0.85 0.99 MHz
ADJUST (Pin 3) V ADJ +25°C I 3.1 3.2 3.3 V
STATUS (Pin 4)
V
OH
V
OL
V
(Pin 5)
AUX
V
(nom) +25°CI I
O
INHIBIT (Pin 6)
V
IL
I
IL
V
(Open Circuit) +25°CI 15 V
I
SYNC (Pin 7)
V
IH
I
IH
I
SHARE
6
(Pin 8) +25°CI I
TEMP (Pin 9) +25°C V 3.90 V
NOTES
1
50 V dc upper limit rated for transient condition of up to 50 ms. 16 V dc lower limit rated for continuous operation during emergency condition. Steady state and
abnormal input voltage range require source impedance sufficient to insure input stability at low line. See sections entitled System Instability Considerations and Input
Voltage Range.
2
Measured at the remote sense points.
3
Unit regulates output voltage to zero load; tests performed at low continuous load and 200 W pulsed load.
4
C
= 1,000 µF. Output ripple/noise measured at converter output; may be smaller at external load capacitance. Unit is stable for C
LOAD
4,000 µF.
5
Refer to section entitled “Pulse Output Power vs. Pulse Length” for more information.
6
Unit has internal pull-down; refer to section entitled Pin 7 (SYNC).
Specifications subject to change without notice.
Case Test ADDC02808PB
Full VI IO = 1.25 A to 25 A Pulsed 16 50 V
= 1.25 A to 25 A, VIN = 18 V to 40 V dc 7.92 8.00 8.08 V
O
Full VI IO = 1.25 A to 25 A, VIN = 18 V to 40 V dc 7.84 8.16 V
Full VI IO = 1.25 A to 20 A, VIN = 16 V to 50 V dc 7.84 8.16 V
= 25 A Pulsed, VIN = 18 V to 40 V dc 1 5 mV
O
= 28 V dc, IO = 1.25 A to 25 A Pulsed 2.5 10 mV
+25°CI I
IN
= 25 A, 5 kHz – 2 MHz BW 10 30 mV p-p
O
Full VI VIN = 18 V to 40 V dc, Pulsed 1.25 25 A
= 25 A, Open Remote Sense Connection 125 % VO nom
O
= 90% V
O
Nom 130 % IO max
OUT
of Pulse”)
= 25 A, From Inhibit High to Status High 6 10 ms
O
= 12.5 A 77.5
O
Min VI IO = 12.5 A 77.5 80 %
Max VI IO = 12.5 A 76 %
+25°CI I
= 25 A 73.5 76 %
O
Min VI IO = 25 A 73.5 %
Max VI IO = 25 A 71 %
+90°CV IO = 25 A 110 °C
+25°CI IOH = 400 µA2.44.0V
+25°CI I
= 1 mA 0.15 0.7 V
OL
= 5 mA, Load Current = 12.5 A 14.65 15.15 15.65 V
AUX
+25°CI 0.5 V
+25°CI V
= 0.5 V 1.2 mA
IL
+25°CI 4.0 V
+25°CI VIH = 7.0 V 175 µA
= 20 A 2.45 2.55 2.65 V
O
ranging from 500 µF to
LOAD
REV. A–2–
Page 3
ADDC02808PB
1
11
12
17
TOP
VIEW
ABSOLUTE MAXIMUM RATINGS*
INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V dc, –0.5 V dc
SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 V dc, –0.5 V dc
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V dc, –0.5 V dc
I
SHARE
TEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V dc, –0.3 V dc
Common-Mode Voltage, Input to Output . . . . . . . . . 500 V dc
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C
Maximum Case Operating Temperature . . . . . . . . . . . +125°C
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
ORDERING GUIDE
Operating
Temperature
Device Range (Case) Description
ADDC02808PBKV –40°C to +85°C Hermetic Package
ADDC02808PBTV –55°C to +90°C Hermetic Package
5962-9763401HXC –55°C to +125°C Hermetic Package
(ADDC02808PBTV/QMLH)
EXPLANATION OF TEST LEVELS
Test Level
I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for military
temperature devices; guaranteed by design and characterization testing for industrial devices.
PIN FUNCTION DESCRIPTIONS
Pin
No. Name Function
1 –SENSE Feedback loop connection for remote sensing
output voltage. Must always be connected to
output return for proper operation.
2 +SENSE Feedback loop connection for remote sensing
output voltage. Must always be connected to
+V
for proper operation.
OUT
3 ADJUST Adjusts output voltage setpoint.
4 STATUS Indicates output voltage is within ±5% of
nominal. Active high referenced to –SENSE
(Pin 1).
5V
AUX
Low level dc auxiliary voltage supply referenced to input return (Pin 10).
6 INHIBIT Power Supply Inhibit. Active low and refer-
enced to input return (Pin 10).
7 SYNC Clock synchronization input for multiple
units; referenced to input return (Pin 10).
8I
SHARE
Current share pin which allows paralleled
units to share current typically within ±5% at
full load; referenced to input return (Pin 10).
9 TEMP Case temperature indicator and temperature
shutdown override; referenced to input return
(Pin 10).
10 –V
11 +V
12 +V
13 +V
14 +V
IN
IN
OUT
OUT
OUT
Input Return.
+28 V Nominal Input Bus.
+8 V dc Output.
+8 V dc Output.
+8 V dc Output.
15 RETURN Output Return.
16 RETURN Output Return.
17 RETURN Output Return.
PIN CONFIGURATION
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss
of functionality.
REV. A –3–
WARNING!
ESD SENSITIVE DEVICE
Page 4
ADDC02808PB–Typical Performance Curves
9
16.0
2V
10V
10
0%
100
90
1ms
V
O
V
INHIBIT
100mV
10
0%
100
90
100ms
V
O
82
80
78
76
74
PERCENTAGE
72
70
68
020
40 60 80 100
OUTPUT POWER – Watts
120 140 160 180 200
40V
28V
18V
Figure 1. Efficiency vs. Line and Load at +25°C
(Load Pulsewidth of 50 ms)
7
79
78
28VIN, 150W PEAK
1.0
28VIN, 150W PEAK
0.5
0.0
DEVIATION – %
OUT
V
–0.5
–1.0
–55 95–45 –35 –25 –15 –5
5 1525354555657585
T
CASE
Figure 4. Output Voltage vs. Case Temperature (°C)
78
77
EFFICIENCY – Percentage
77
76
–55 95–45
–35 –25 –15 –5
5 1525354555657585
T
CASE
Figure 2. Efficiency vs. Case Temperature (°C)
(at Nominal V
, 75% Max Load, Load Pulsewidth
IN
Figure 5. Output Voltage Transient During Turn-On with
0.1 A Load Displaying Soft Start When Supply Is Enabled
of 50 ms)
15.5
15.0
14.5
INPUT VOLTAGE
14.0
13.5
13.0
140 200150
Figure 3. Low Line Dropout vs. Load at 90°C Case
Temperature (Load Pulsewidth of 50 ms)
160 170 180 190
PEAK OUTPUT POWER – Watts
–4–
Figure 6. Output Voltage Transient Response to
a 1 A to 25 A Step Change in Load, di/dt = 12 A/
with 1,000
µ
F Load Capacitance (R
= 10 mΩ)
ESR
µ
s,
REV. A
Page 5
0
1
0.001
|Z
OUT
| – V
0.1
0.01
FREQUENCY – Hz
10 100k100 1k 10k
–10
–20
–30
–40
–50
|AS| – dB
–60
–70
–80
–90
–100
10 50k100
1k 10k
FREQUENCY – Hz
Figure 7. Audio Susceptibility (Magnitude of V
OUT/VIN
ADDC02808PB
)
Figure 9. Incremental Output Impedance (Magnitude)
1k
100
| – V
10
IN
|Z
1
0.1
10 100k100 1k 10k
FREQUENCY – Hz
Figure 8. Incremental Input Impedance (Magnitude)
5mV
1mV
0.5mV
VOLTS
100mV
50mV
020
10
FREQUENCY – MHz
Figure 10. Output Frequency Spectrum
REV. A –5–
Page 6
ADDC02808PB–Typical EMI Curves & Test Setup for 28 VIN, 5 V dc Out, 100 W Converter
FREQUENCY – MHz
166
0.10.0001 0.001
106
126
66
EMISSION LEVEL – dB/pT
146
86
0.01
RE101 MIL-STD-461D
RE101–1
130
110
90
70
EMISSION LEVEL – dB mV
50
30
CONDUCTED EMISSIONS CE101
CE101–1 4.5 AMPS
FREQUENCY – MHz
0.010.0001 0.001
Figure 11. Conducted Emissions, MIL-STD-461D, CE101,
+28 V Hot Line 100 W Load
130
110
90
CONDUCTED EMISSIONS CE102
Figure 13. Radiated Emissions, MIL-STD-461D, RE101,
100 W Load
90
70
50
RADIATED EMISSIONS RE102
70
EMISSION LEVEL – dB mV
50
30
FREQUENCY – MHz
LIMIT 28VDC
1
Figure 12. Conducted Emissions, MIL-STD-461D, CE102,
+28 V Hot Line 100 W Load
LISN
LISN
TWO METERS OF
TWISTED CABLE
NOTE: 100mF CAPACITOR AND 1V RESISTOR PROVIDE STABILIZATION FOR 100mH DIFFERENTIAL SOURCE INDUCTANCE
INTRODUCED BY THE LISNs. REFER TO SECTION ON EMI CONSIDERATIONS FOR MORE INFORMATION.
Figure 15. Schematic of Test Setup for EMI Measurements
1V
100mF
100.01 0.1
2mF
82nF
82nF
EMISSION LEVEL – dB mV/m
–30
30
10
1 100 1000
FREQUENCY – MHz
RE102–2
100.01 0.1
Figure 14. Radiated Emissions, MIL-STD-461D, RE102,
Vertical Polarity, 100 W Load
+V
IN
–V
IN
GROUND PLANE
CASE
+V
OUT
RETURN
1/4V0.1mF
–6–
REV. A
Page 7
ADDC02808PB
BASIC OPERATION
The ADDC02808PB converter uses a flyback topology with
dual interleaved power trains operating 180° out of phase. Each
power train switches at a fixed frequency of 500 kHz, resulting
in a 1 MHz fixed switching frequency as seen at the input and
output of the converter. In a flyback topology, energy is stored
in the inductor during one half portion of the switching cycle
and is then transferred to the output filter during the next half
portion. With two interleaved power trains, energy is transferred
to the output filter during both halves of the switching cycle,
resulting in smaller filters to meet the required ripple.
A five pole differential input EMI filter, along with a commonmode EMI capacitor and careful attention to layout parasitics, is
designed to meet all applicable requirements in MIL-STD-461D
when installed in a typical system setup. Due to the higher output
level in this product compared to the 100 W continuous output
products, input stability is more of a concern. As a result, the two
inductors in the internal input EMI filter have smaller values of
inductance to mitigate input stability concerns. The effectiveness of
the internal input EMI filter is, therefore, slightly diminished
compared to these other products. A more detailed discussion
of CE102 and other EMI issues is included in the section
entitled “EMI Considerations.”
The maximum available peak power out is 200 W and is based
on a combination of maximum junction temperatures, maximum
pulsewidth, and maximum duty cycle. Refer to section entitled,
“Pulsed Output Power vs. Pulse Length,” for peak power derating curves for varying conditions.
The unit is compensated for ultrafast transient response with
minimum output voltage deviation. The compensation has been
optimized and output stability insured for an external load
capacitance in the range of 500 µF, 20 mΩ ESR to 4,000 µF,
ESR. Peak performance and output stability are depen-
2.5 mΩ
dent on minimizing parasitic inductance and resistance in the connection from the converter to the load.
The converter uses current mode control and employs a high
performance opto-isolator in its feedback path to maintain isolation between input and output. The control circuit is designed
to give a nearly constant output current as the output voltage
drops from V
nom to VSC during a short circuit condition. It
O
does not let the current fold back below the maximum rated
output current. The output overvoltage protection circuitry,
which is independent from the normal feedback loop, protects
the load against a break in the remote sense leads. Remote
sense connections, which can be made at the load, can adjust
for voltage drops of as much as 0.25 V dc between the converter
and the load, thereby maintaining an accurate voltage level at
the load.
An input overvoltage protection feature shuts down the converter when the input voltage exceeds (nominally) 52.5 V dc.
An internal temperature sensor shuts down the unit and prevents it from becoming too hot if the heat removal system fails.
The temperature sensed is the case temperature and is factory
set to trip at a nominal case temperature of 110°C to 115°C.
The shut down temperature setting can be raised externally or
disabled by the user.
Each unit has an INHIBIT pin that can be used to turn off the
converter. This feature can be used to sequence the turn-on of
multiple converters and to reduce input power draw during
extended time in a no load condition.
A SYNC pin, referenced to the input return line (Pin 10), is
available to synchronize multiple units to one switching frequency. This feature is particularly useful in eliminating beat
frequencies which may cause increased output ripple on paralleled units. A current share pin (I
) is available which
SHARE
permits paralleled units to share current typically within 5% at
full load.
A low level dc auxiliary voltage supply referenced to the input
return line is provided for miscellaneous system use.
PULSED OUTPUT POWER VS. PULSE LENGTH
The maximum specified pulsed output power in the standard
configuration of the ADDC02808PB is 200 W. This limit is
based on issues of working down to the minimum input voltage, of providing a reasonable short circuit current limit, and so
on. However, this power level assumes that the junction temperatures of the converter’s power semiconductor devices have
not exceeded 110°C. For short pulse lengths and low duty
cycles, this condition will be met. Otherwise, the pulsed output
power will have to be reduced to keep the junction tempera-
tures below 110°C if NAVMAT guidelines are to be followed.
Figures 16 and 17 show the tradeoff that must be made between the highest allowable pulsed output power and the pulse
length. Notice that for each curve, as the pulse length is made
longer, the pulsed power that causes a 110°C junction tem-
perature to be reached is lower. The curves are provided for
two baseplate temperatures (25°C and 90°C) and three average
output powers. The duty cycle that corresponds to any point
on a curve can be calculated by dividing the average power by
the pulsed power for that point. The curves represent typical
upper limits; operation anywhere below the curves is acceptable and will result in cooler junctions.
The ADDC02808PB is designed to deliver a continuous 100
watts to its output while keeping its hottest junction tempera-
ture below 110°C with a baseplate temperature of 90°C.
250
200
150
100
PEAK POWER – W
50
0
0 700100 200 300 400 500 600
100W ave
MAXIMUM CONTINUOUS
POWER LIMIT
PULSEWIDTH – ms
50W ave
MAXIMUM PEAK
POWER LIMIT
10W ave
Figure 16. Largest On-State Power vs. Pulsewidth that
Maintains T
≤ 110°C at 25°C Baseplate
JMAX
REV. A –7–
Page 8
ADDC02808PB
8.1
7.4
–200 800–100
V
O
– V
0 100 200 300 400 500 600 700
8
7.9
7.8
7.7
7.6
7.5
TIME – ms
250
200
150
100
PEAK POWER – W
100W ave
MAXIMUM CONTINUOUS
50
0
0 15050 100
POWER LIMIT
25 75 125
MAXIMUM PEAK
POWER LIMIT
10W ave
50W ave
PULSEWIDTH – ms
Figure 17. Largest On-State Power vs. Pulsewidth that
Maintains T
≤ 110°C at 90°C Baseplate
JMAX
TRANSIENT RESPONSE
The standard ADDC02808PB is designed to deliver large
changes, or pulses, in load current with minimum output voltage deviation and an ultrafast return to the nominal output
voltage. The compensation of the feedback loop is optimized,
and output stability is insured, for a broad range of external load
capacitance extending from 500 µF (R
= 2.5 mΩ). The variables that impact pulse performance
(R
ESR
= 20 mΩ) to 4,000 µF
ESR
(the maximum output voltage deviation and the settling time)
are:
1. Size of step change in the output current.
2. Amount of external load capacitance.
3. Internal compensation of the feedback loop (factory set).
4. Connection from converter output to load.
Extensive modeling of the converter with ADI proprietary software permits analysis and prediction of the impact each of these
parameters has on the pulse response. The analyses in this data
sheet are based on the load capacitance being comprised of
100 µF, 100 mΩ tantalum load capacitors such as the CSR21
style. Figure 18 is the prediction of the standard converter’s
response to a 24 A step change in load current (from 1 A to
25 A) with a load capacitance of 1,000 µF (R
= 10 mΩ).
ESR
This is very close to the measured pulse response under the
same conditions shown in Figure 6.
8.1
8.1
8
7.9
7.8
– V
O
V
7.7
7.6
7.5
7.4
–200 800–100
12A STEP CHANGE
24A STEP CHANGE
0 100 200 300 400 500 600 700
TIME – ms
Figure 19. Predicted Response to 12 A and 24 A Step
Change in Load Current, di/dt = 12 A/
1000
µ
F and R
= 10 m
ESR
Ω
µ
s, for C
LOAD
=
Step Change
If the step change is less than 24 A, the pulse response will
improve. For instance, with a 12 A step change, Figure 19
shows a comparison of the response for a 24 A step change and
a 12 A step change in load.
Load Capacitance
Varying the external load capacitance and associated R
tween the range of C
= 4,000 µF (R
= 2.5 mΩ) results in the predicted waveforms
ESR
= 500 µF (R
LOAD
= 20 mΩ) and C
ESR
ESR
be-
LOAD
shown in Figures 20, 21, and 22. As can be seen, the larger the
capacitor, the smaller the deviation, but the longer the settling
time. Table I lists the maximum output voltage deviations and
settling times for the four combinations of C
LOAD
and R
ESR
mentioned above. Note that these are based on the standard
compensation for the feedback loop.
Table I. Output Response to a 24 A (1 A–25 A) Step in Load
Current (Standard Compensation)
Typical Settling Time See
C
LOAD
R
ESR
Deviation (Within 1%) Figure
500 µF 20 mΩ –7% 150 µs20
1,000 µF 10 mΩ –6% 175 µs18
2,000 µF5 mΩ –5% 200 µs21
4,000 µF 2.5 mΩ –4% 250 µs22
8
7.9
7.8
– V
O
V
7.7
7.6
7.5
7.4
–200 800–100
0 100 200 300 400 500 600 700
TIME – ms
Figure 18. Predicted Response to 24 A Step Change in
Load Current, di/dt = 12 A/
R
= 10 m
ESR
Ω
µ
s, for C
= 1,000µF and
LOAD
Figure 20. Predicted Response for 24 A Step Load
Change in Load Current, di/dt = 12 A/
= 500 µF and R
= 20 m
ESR
Ω
µ
s, for C
LOAD
REV. A–8–
Page 9
ADDC02808PB
8.1
7.4
–200 800–100
V
O
– V
0 100 200 300 400 500 600 700
8
7.9
7.8
7.7
7.6
7.5
TIME – ms
8.1
7.4
–200 800–100
V
O
– V
0 100 200 300 400 500 600 700
8
7.9
7.8
7.7
7.6
7.5
TIME – ms
8.1
8
7.9
7.8
– V
O
V
7.7
7.6
7.5
7.4
–200 800–100
0 100 200 300 400 500 600 700
TIME – ms
Figure 21. Predicted Response for 24 A Step Load
Change in Load Current, di/dt = 12 A/
2,000
µ
– V
O
V
8.1
7.9
7.8
7.7
F and R
8
ESR
= 5 m
Ω
µ
s, for C
LOAD
=
Table II.
Output Response to a 24 A (1 A-25 A) Step in
Load Current (Compensation Optimized)
Typical Settling Time See
C
LOAD
R
ESR
Deviation (Within 1%) Figure
1,000 µF 10 mΩ –4% 125 µs23
2,000 µF5 mΩ –2.5% 100 µs24
4,000 µF 2.5 mΩ –1% 0 µs25
Connection to Load
Pulse performance is dependent on minimizing the parasitic
impedances in the connection between the converter output and
the load and external capacitors. Low inductance and low resistance connections should be used. Multilayer connections should
be avoided to minimize stray capacitance. The converter should
be placed as close to the load and external capacitors as possible.
7.6
7.5
7.4
–200 800–100 0 100 200 300 400 500 600 700
TIME – ms
Figure 22. Predicted Response for 24 A Step Load
Change in Load Current, di/dt = 12 A/
4,000
µ
F and R
= 2.5 m
ESR
Ω
µ
s, for C
LOAD
=
Figure 23. Predicted Response for 24 A Step Load Change,
di/dt = 12 A/
Optimized for C
µ
s, with Factory Set Internal Compensation
= 1,000 µF and R
LOAD
= 10 m
ESR
Ω
Factory Set Internal Compensation
If the user knows the external load capacitance and R
ESR
to be
used in the application and if the application requires better
pulse response than is summarized in Table I, then the internal
feedback compensation can be modified at the factory to improve the transient response. In these instances, the compensation is optimized for a particular C
performing well over a broader range of C
at the expense of
LOAD
. The predicted
LOAD
maximum output voltage deviation and settling times for factory-modified feedback compensation are shown in Figures 23,
24, and 25, and summarized in Table II, for three combinations
of C
LOAD
and R
. As can be seen, optimizing the compensa-
ESR
tion for a given load capacitance gives the best transient response in terms of both voltage deviation and settling time.
Figure 24. Predicted Response for 24 A Step Load Change,
di/dt = 12 A/
Optimized for C
µ
s, with Factory Set Internal Compensation
= 2,000 µF and R
LOAD
ESR
= 5 m
Ω
REV. A –9–
Page 10
ADDC02808PB
100mV
10
0%
100
90
100ms
V
O
8.1
8.0
7.9
7.8
– V
O
V
7.7
7.6
7.5
7.4
–200 800–100
Figure 25. Predicted Response for 24 A Step Load Change,
di/dt = 12 A/
Optimized for C
RESPONSE AT END OF PULSE
The previous section describes how the ADDC02808PB converter responds to the positive step change in load current that
occurs at the beginning of a power pulse. This section will
discuss the converter’s response at the end of the power pulse
when the load current is abruptly returned to a small value.
Figures 26-29 show the converter’s measured output voltage as
the load current is stepped from 25 A down to 4 A, 2 A, 1 A, and
0.1 A, respectively. The load capacitance is 1,000 µF with
0 100 200 300 400 500 600 700
TIME – ms
µ
s, with Factory Set Internal Compensation
= 4,000 µF and R
LOAD
= 2.5 m
ESR
Ω
R
= 10 mΩ. The di/dt is 12 A/µs. As can be seen, the peak
ESR
deviations for these curves are close to each other and comparable to the negative deviation shown in Figure 6 for a similarly sized positive step change in load current.
Figure 28. Output Voltage Transient Response to a 25 A
to 1 A Step Change in Load, di/dt/ = 12 A/
1,000
µ
F Load Capacitance (R
100
90
100mV
10
0%
= 10 mΩ)
ESR
V
O
µ
1ms
s, with
100
90
100mV
10
0%
V
O
100ms
Figure 26. Output Voltage Transient Response to a 25 A
to 4 A Step Change in Load, di/dt/ = 12 A/
Load Capacitance (R
100
90
100mV
10
0%
= 10 mΩ)
ESR
V
O
µ
s, with 1,000 µF
100ms
Figure 27. Output Voltage Transient Response to a 25 A
to 2 A Step Change in Load, di/dt/ = 12 A/
Load Capacitance (R
= 10 mΩ)
ESR
µ
s, with 1,000 µF
Figure 29. Output Voltage Transient Response to a 25 A
to 0.1 A Step Change in Load, di/dt/ = 12 A/
1,000
µ
F Load Capacitance (R
= 10 mΩ)
ESR
µ
s, with
What is different about these curves is the settling time. Once
the converter’s output voltage rises above nominal, the converter cannot help to discharge the load capacitor. It can only
reduce its output current to zero; it cannot draw a negative
current. As such, the time it takes to bring the output voltage
back down to its nominal value depends on the load current
during the low load portion of the cycle. The rate at which the
output voltage falls to its nominal value is the load current
divided by the load capacitance (including the 150 µF capaci-
tance that is inside the converter). The smaller the load current,
the longer it takes to get the output voltage back to its nominal
value.
During the time that the output voltage is too high, the integrator in the converter’s feedback circuitry is continuing to ramp
out of range. As the output voltage then falls below its nominal
value, it must have an undershoot error to bring the integrator
back into range. As can be seen from these figures, the lower
the load current, the longer the output voltage remains too
high, and the longer and the greater the output voltage undershoot is.
REV. A–10–
Page 11
ADDC02808PB
OUTPUT VOLTAGE – %
5
4
RESISTANCE – MV
0
101 105102 103 104
3
2
1
IOH – mA
5
4
0
0.2 1.60.4
V
OH
– V
0.6 0.8 1.0 1.2 1.4
3
2
1
Even when the load current steps down to 0.1 A, the maximum
8
deviation of the output voltage is only about 400 mV, or 5%.
However, it is important to realize that if the next power pulse
occurs before this transient is over, then the output voltage will
not have the response depicted in the last section. This is because the feedback integrator will not have had time to return
to its normal state, and so the converter’s ability to respond to a
positive step change in load current will be reduced. The maximum negative going deviation in the output voltage under this
circumstance will then be greater than is shown in the figures of
that section.
Should this situation arise, one approach would be to step the
load current down to an intermediate value (e.g., 4 A) at the
end of the power pulse, and then let this current decay to a
smaller value (e.g., 0.1 A) with a time constant in the 100 µs to
200 µs range. This should permit a rapid return to a steady state
condition at the end of the power pulse without requiring a large
Figure 30. External Resistor Value for Reducing Output
Voltage
7
6
5
4
RESISTANCE – MV
3
2
1
99 9598 97 96
OUTPUT VOLTAGE – %
average load current during the low power portion of the cycle.
PIN CONNECTIONS
Pins 1 and 2 (ⴞSENSE)
Pins 1 and 2 must always be connected for proper operation,
although failure to make these connections will not be catastrophic to the converter under normal operating conditions.
Pin 1 must always be connected to the output return and Pin 2
must always be connected to +V
. These connections can
OUT
be made at any one of the output pins of the converter, or
remotely at the load. A remote connection at the load can
adjust for voltage drops of as much as 0.25 V dc between the
converter and the load.
Long remote sense leads can affect converter stability, although
this condition is rare. The impedance of the long power leads
between the converter and the remote sense point could affect
the converter’s unity gain crossover frequency and phase margin.
Consult factory if long remote sense leads are to be used.
Pin 3 (ADJUST)
An adjustment pin is provided so that the user can change the
nominal output voltage during the prototype stage. Since very
low temperature coefficient resistors are used to set the output
voltage and maintain tight regulation over temperature, using
standard external resistors to adjust the output voltage will
Figure 31. External Resistor for Increasing Output Voltage
Pin 4 (STATUS)
Pin 4 is active high referenced to –SENSE (Pin 1), indicating
that the output voltage is typically within ±5%. The pin is both
pulled up and down by internal circuitry. Figures 32 and 33
show the typical source and sink capabilities of the status output. Refer to the paragraphs describing Pin 3 (ADJUST) for
effect on status trip point.
loosen output regulation over temperature. Furthermore, since
the status trip point is not changed when the output voltage is
adjusted using external resistors, the status line will no longer
trip at the standard levels of the newly adjusted output voltage.
If necessary, modified standard units can be ordered with the
necessary changes made inside the package at the factory. The
ADJUST function is sensitive to noise, and care should be
taken in the routing of connections.
To make the output voltage higher, place a resistor from ADJUST (Pin 3) to –SENSE (Pin 1). To make the output voltage
lower, place a resistor from ADJUST (Pin 3) to +SENSE (Pin
2). Figures 30 and 31 show resistor values for a ±5% change in
output voltage.
With regard to the range that the output voltage can be adjusted
by the user, there are two concerns. As the output voltage is
raised it may become difficult to maintain regulation at full
power and low input voltage. As the output voltage is lowered,
it may become difficult to maintain regulation at minimum
power and high input line.
Figure 32. Source Capability of Status Output
REV. A –11–
Page 12
ADDC02808PB
1.0
0.8
0.6
– V
OL
V
0.4
0.2
0.0
1.0 19.04.0 7.0
10.0 13.0 16.0
IOL – mA
Figure 33. Sink Capability of Status Output
Pin 5 (V
AUX
)
Pin 5 is referenced to the input return and provides a semiregulated 14 V to 16 V dc voltage supply for miscellaneous
system use. The maximum permissible current draw is 5 mA
and the voltage varies with the output load of the converter
shown in Figure 34.
16
15
14
– V
13
AUX
V
12
11
10
0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0
CONVERTER OUTPUT CURRENT – A
Figure 34.
Pin 6 (INHIBIT)
Pin 6 is active low and is referenced to the input return of the
converter. Connecting it to the input return will turn the
converter off. For normal operation, the inhibit pin is internally pulled up to 12 V. Use of an open collector circuit is
recommended.
1.2
1.1
1.0
– mA
IL
I
0.9
0.8
0.7
0.5 2.0
1.0 1.5
V
– V
IL
When Pin 6 is disconnected from input return, the converter
will restart in the soft-start mode. Pin 6 must be kept low for at
least 2 milli- seconds to initiate a full soft start. Shorter off times
will result in a partial soft start. Figure 35 shows the input characteristics of Pin 6.
Pin 7 (SYNC)
Pin 7 can be used for connecting multiple converters to a master
clock. This master clock can be either an externally user-supplied clock or it can be a converter that has been modified and
designated as a master unit. Consult factory for availability of
these devices. Capacitive coupling of the clock signal will insure
that if the master clock stops working the individual units will
continue to operate at their own internal clock frequency,
thereby eliminating a potential single point failure. Capacitive
coupling will also permit a wider duty cycle to be used. Consult
factory for more information. The SYNC pin has an internal
pull-down so it is not necessary to sink any current when driving
the pin low.
For user-supplied master clocks with no external circuitry, the
following specifications must be met:
a. Frequency: 1.00 MHz min
b. Duty cycle: 7% min, 14% max
c. High state voltage high level: 4 V min to 7 V max
d. Low state voltage low level: 0 V min to 3.0 V max
Users should note that the SYNC pin is referenced to the input
return of the converter. If the user-supplied master clock is
generated on the output side of the converter, the signal should
be isolated.
Users should be careful about the frequency selected for the
external master clock. Higher switching frequencies will reduce
efficiency and may reduce the amount of output power available
at minimum input line. Consult factory for modified standard
switching frequency to accommodate system clock characteristics.
Pin 8 (I
SHARE
)
Pin 8 allows paralleled converters to share the total load cur-
rent, typically within ±5% at full load. To use the current share
feature, connect all current share pins to each other and connect the SENSE pins on each of the converters. The current
sharing function is sensitive to the differential voltage between the
input return pins of paralleled converters. The current sharing
function is also sensitive to noise, and care should be taken in
the routing of connections. Refer to Figure 45 for typical application circuits using paralleled converters.
Pin 9 (TEMP)
Pin 9 can be used to indicate case temperature or to raise or
disable the temperature at which thermal shutdown occurs.
Typically, 3.90 V corresponds to +25°C, with a +13.1 mV/°C
change for every 1°C rise. The sensor IC (connected from Pin
9 to the input return (Pin 10)) has a 13.1 kΩ impedance.
The thermal shutdown feature has been set to shut down the
converter when the case temperature is nominally 110°C to
115°C. To raise the temperature at which shutdown occurs,
connect a resistor with the value shown in Figure 36 from Pin 9
to the input return (Pin 10). To completely disable the tem-
perature shutdown feature, connect a 50 kΩ resistor from Pin 9
to the input return (Pin 10).
Figure 35. Input Characteristics of Pin 6 When Pulled Low
REV. A–12–
Page 13
ADDC02808PB
1400
1200
1000
800
600
RESISTANCE – kV
400
200
0
120 150125 130 135 140 145
SHUTDOWN CASE TEMPERATURE – 8C
Figure 36. External Resistor Value for Raising
Temperature Shutdown Point
INPUT VOLTAGE RANGE
The steady state operating input voltage range for the converter
is defined as 18 V to 40 V. The abnormal operating input voltage range is defined as 16 V to 50 V. In accordance with MILSTD-704D, the converter can operate up to 50 V dc input for
transient conditions as long as 50 milliseconds, and it can operate down to 16 V dc input for continuous operation during
emergency conditions. Figure 3 (typical low line dropout vs.
load) shows that the converter can work continuously down to
and below 16 V dc under reduced load conditions.
The ADDC02808PB can be modified to survive, but not work
through, the upper limit input voltages defined in MIL-STD704A (aircraft) and MIL-STD-1275A (military vehicles). MILSTD-704A defines an 80 V surge that lasts for 1 second before
it falls below 50 V, while MIL-STD-1275A defines a 100 V
surge that lasts for 200 milliseconds before it falls below 50 V.
In both cases, the ADDC02808PB can be modified to operate
to specification up to the 50 V input voltage limit and to shut
down and protect itself during the time the input voltage exceeds 50 V. When the input voltage falls below 50 V as the
surge ends, the converter will automatically initiate a soft start.
In order to survive these higher input voltage surges, the modified
converter will no longer have input transient protection, however, as described below.
Contact the factory for information on units surviving high
input voltage surges.
Input Voltage Transient Protection: The converter has a
transient voltage suppressor connected across its input leads to
protect the unit against high voltage pulses (both positive and
negative) of short duration. With the power supply connected
in the typical system setup shown in Figure 15, a transient voltage pulse is created across the converter in the following man-
ner. A 20 µF capacitor is first charged to 400 V. It is then
connected directly across the converter’s end of the two meter
power lead cable through a 2 Ω on-state resistance MOSFET.
The duration of this connection is 10 µs. The pulse is repeated
every second for 30 minutes. This test is repeated with the
connection of the 20 µF capacitor reversed to create a negative
pulse on the supply leads. (If continuous reverse voltage protection is required, a diode can be added externally in series at the
expense of lower efficiency for the power system.)
The converter responds to this input transient voltage test by
shutting down due to its input overvoltage protection feature.
Once the pulse is over, the converter initiates a soft-start, which
is completed before the next pulse. No degradation of converter
performance occurs.
THERMAL CHARACTERISTICS
Junction and Case Temperatures: It is important for the
user to know how hot the hottest semiconductor junctions
within the converter get and to understand the relationship
between junction, case, and ambient temperatures. The hottest
semiconductors in the 100 W product line of Analog Devices’
high density power supplies are the switching MOSFETs and
the output rectifiers. There is an area inside the main power
transformers that is hotter than these semiconductors, but it is
within NAVMAT guidelines and well below the Curie temperature of the ferrite. (The Curie temperature is the point at which
the ferrite begins to lose its magnetic properties.)
Since NAVMAT guidelines require that the maximum junction
temperature be 110°C, the power supply manufacturer must
specify the temperature rise above the case for the hottest semiconductors so the user can determine what case temperature
is required to meet NAVMAT guidelines. The thermal characteristics section of the specification table states the hottest junction
temperature for maximum output power at a specified case
temperature. The unit can operate to higher case temperatures
than 90°C, but 90°C is the maximum temperature that permits
NAVMAT guidelines to be met.
Case and Ambient Temperatures: It is the user’s responsibility to properly heat sink the power supply in order to maintain the appropriate case temperature and, in turn, the maximum
junction temperature. Maintaining the appropriate case temperature is a function of the ambient temperature and the mechanical heat removal system. The static relationship of these
variables is established by the following formula:
T
where
T
= case temperature measured at the center of the package
C
C=TA
+( PD× R
)
θ
CA
bottom,
= ambient temperature of the air available for cooling,
T
A
= the power, in watts, dissipated in the power supply,
P
D
= the thermal resistance from the center of the package
R
θ
CA
to free air, or case to ambient.
The power dissipated in the power supply, P
from the efficiency,
output power, P
, given in the data sheets and the actual
, in the user’s application by the following
O
, can be calculated
D
formula:
= P
1
–1
O
η
P
D
For example, at 80 W of output power and 80% efficiency, the
power dissipated in the power supply is 20 W. If under these
conditions, the user wants to maintain NAVMAT deratings
(i.e., a case temperature of approximately 90°C) with an ambient temperature of 75°C, the required thermal resistance, case
to ambient, can be calculated as
90 = 75 + (20 × R
)orR
θ
CA
= 0.75°C/W
θ
CA
This thermal resistance, case to ambient, will determine what
kind of heat sink and whether convection cooling or forced air
cooling is required to meet the constraints of the system.
REV. A –13–
Page 14
ADDC02808PB
SYSTEM INSTABILITY CONSIDERATIONS
In a distributed power supply architecture, a power source provides power to many “point-of-load” (POL) converters. At low
frequencies, the POL converters appear incrementally as nega-
tive resistance loads. This negative resistance could cause system instability problems.
Incremental Negative Resistance: A POL converter is designed to hold its output voltage constant no matter how its
input voltage varies. Given a constant load current, the power
drawn from the input bus is therefore also a constant. If the
input voltage increases by some factor, the input current must
decrease by the same factor to keep the power level constant. In
incremental terms, a positive incremental change in the input
voltage results in a negative incremental change in the input
current. The POL converter therefore looks, incrementally, as a
negative resistor.
The value of this negative resistor at a particular operating
point, V
IN
, I
IN
, is:
–V
R
IN
=
N
I
IN
Note that this resistance is a function of the operating point. At
full load and low input line, the resistance is its smallest, while
at light load and high input line, it is its largest.
Potential System Instability: The preceding analysis assumes
dc voltages and currents. For ac waveforms the incremental
input model for the POL converter must also include the effects
of its input filter and control loop dynamics. When the POL
converter is connected to a power source, modeled as a voltage
source, V
resistor, R
in series with an inductor, LS, and some positive
S,
, the network of Figure 37 results.
S
L
R
V
S
S
TERMINALS
S
INPUT
L
P
C
ADI DC/DC CONVERTER
–|RN|
P
Figure 37. Model of Power Source and POL Converter
Connection
The network shown in Figure 37 is second order and has the
following characteristic equation:
s2(L
+ LP)C +s
S
+ L
S
–|R
)
P
+ R
|
N
(L
SCP
+1 =0
For the power delivery to be efficient, it is required that RS <<
. For the system to be stable, however, the following rela-
R
N
tionship must hold:
CR
||
PN
LL
()or()
+
SP
>
R
S
R
>
S
LL
+
SP
CR
||
PN
Notice from this result that if (LS + LP) is too large, or if RS is
too small, the system might be unstable. This condition would
first be observed at low input line and full load since the absolute value of R
is smallest at this operating condition.
N
If an instability results and it cannot be corrected by changing
L
or RS, such as during the MIL-STD-461D tests due to the
S
LISN requirement, one possible solution is to place a capacitor
across the input of the POL converter. Another possibility is to
place a small resistor in series with this extra capacitor.
The analysis so far has assumed the source of power was a voltage source (e.g., a battery) with some source impedance. In
some cases, this source may be the output of a front-end (FE)
converter. Although each FE converter is different, a model for
a typical one would have an LC output filter driven by a voltage
source whose value was determined by the feedback loop. The
LC filter usually has a high Q, so the compensation of the feedback loop is chosen to help dampen any oscillations that result
from load transients. In effect, the feedback loop adds “positive
resistance” to the LC network.
When the POL converter is connected to the output of this FE
converter, the POL’s “negative resistance” counteracts the effects of the FE’s “positive resistance” offered by the feedback
loop. Depending on the specific details, this might simply mean
that the FE converter’s transient response is slightly more oscillatory, or it may cause the entire system to be unstable.
For the ADDC02808PB, L
is approximately 0.5 µH and C
P
is
P
approximately 4 µF. Figure 8 shows a more accurate depiction
of the input impedance of the converter as a function of frequency. The negative resistance is, itself, a very good incremental model for the power state of the converter for frequencies
into the several kHz range (see Figure 8).
NAVMAT DERATING
NAVMAT is a Navy power supply reliability manual that is
frequently cited by specifiers of power supplies. A key section
of NAVMAT P4855-1A discusses guidelines for derating designs
and their components. The two key derating criteria are voltage
derating and power derating. Voltage derating is done to reduce
the possibility of electrical breakdown, whereas power derating
is done to maintain the component material below a specified
maximum temperature. While power deratings are typically
stated in terms of current limits (e.g., derate to x% of maximum
rating), NAVMAT also specifies a maximum junction temperature of the semiconductor devices in a power supply. The
NAVMAT component deratings applicable to the ADDC02808PB
are as follows:
Resistors
80% voltage derating
50% power derating
Capacitors
50% voltage and ripple voltage derating
70% ripple current derating
Transformers and Inductors
60% continuous voltage and current derating
90% surge voltage and current derating
20°C less than rated core temperature
30°C below insulation rating for hot spot temperature
25% insulation breakdown voltage derating
40°C maximum temperature rise
Transistors
50% power derating
60% forward current (continuous) derating
75% voltage and transient peak voltage derating
110°C maximum junction temperature
REV. A–14–
Page 15
ADDC02808PB
Diodes (Switching, General Purpose, Rectifiers)
70% current (surge and continuous) derating
65% peak inverse voltage derating
110°C maximum junction temperature
Diodes (Zeners)
70% surge current derating
60% continuous current derating
50% power derating
110°C maximum junction temperature
Microcircuits (Linears)
70% continuous current derating
75% signal voltage derating
110°C maximum junction temperature
The ADDC02808PB can meet all the derating criteria listed
above. However, there are a few areas of the NAVMAT
deratings where meeting the guidelines unduly sacrifices performance of the circuit. Therefore, the standard unit makes the
following exceptions.
Common-Mode EMI Filter Capacitors: The standard supply uses 500 V capacitors to filter common-mode EMI.
NAVMAT guidelines would require 1000 V capacitors to meet
the 50% voltage derating (500 V dc input to output isolation),
resulting in less common-mode capacitance for the same space.
In typical electrical power supply systems, where the load
ground is eventually connected to the source ground, commonmode voltages never get near the 500 V dc rating of the standard
supply. Therefore, a lower voltage rating capacitor (500 V)
was chosen to fit more capacitance in the same space in order
to better meet the conducted emissions requirement of MILSTD-461D (CE102). For those applications which require
250 V or less of isolation from input to output, the present
designs would meet NAVMAT guidelines.
Switching Transistors: 100 V MOSFETs are used in the
standard unit to switch the primary side of the transformers.
Their nominal off-state voltage meets the NAVMAT derating
guidelines. When the MOSFETs are turned off, however, momentary spikes occur that reach 100 V. The present generation
of MOSFETs are rated for repetitive avalanche, a condition that
was not considered by the NAVMAT deratings. In the worst
case condition, the energy dissipated during avalanche is 1% of
the device’s rated repetitive avalanche energy. To meet the
NAVMAT derating, 200 V MOSFETs could be used. The
100 V MOSFETs are used instead for their lower on-state resistance, resulting in higher efficiency for the power supply.
NAVMAT Junction Temperatures: The two types of power
deratings (current and temperature) can be independent of one
another. For instance, a switching diode can meet its derating
of 70% of its maximum current, but its junction temperature
can be higher than 110°C if the case temperature of the con-
verter, which is not controlled by the manufacturer, is allowed
to go higher. Since some users may choose to operate the power
supply at a case temperature higher than 90°C, it then becomes
important to know the temperature rise of the hottest semiconductors. This is covered in the specification table in the section
entitled “Thermal Characteristics”.
EMI CONSIDERATIONS
Figures 11 through 14 show the results of EMI measurements
conducted in accordance with MIL-STD-461D/462D for the
ADDC02805SA dc/dc converter (28 V
IN
, 5 V
OUT
, 100 W)
using the test setup shown in Figure 15. The EMI performance
of the ADDC02808PB dc/dc converter will be different for
several reasons. The purpose of this section is to describe the
various MIL-STD-461D baseline tests and the ADDC02805SA
converter’s corresponding performance and then explain how
the EMI performance of the ADDC02808PB will differ from
this baseline.
28 V
, 100 W Out, Baseline Performance: The
IN
ADDC02805SA has an integral differential- and commonmode EMI filter that is designed to meet all applicable requirements in MIL-STD-461D when the power converter is
installed in a typical system setup (described below). The
converter also contains transient protection circuitry that permits the unit to survive short, high voltage transients across its
input power leads.
Electromagnetic interference (EMI) is governed by MIL-STD461D, which establishes design requirements, and MIL-STD462D, which defines test methods. EMI requirements are
categorized as follows (xxx designates a three digit number):
• CExxx: conducted emissions (EMI produced internal to the
power supply which is conducted externally through its input
power leads)
• CSxxx: conducted susceptibility (EMI produced external to
the power supply which is conducted internally through the
input power leads and may interfere with the supply’s operation)
• RExxx: radiated emissions (EMI produced internal to the
power supply which is radiated into the surrounding space)
• RSxxx: radiated susceptibility (EMI produced external to
the power supply which radiates into or through the power
supply and may interfere with its proper operation)
It should be noted that there are several areas of ambiguity with
respect to CE102 measurements that may concern the systems
engineer. One area of ambiguity in this measurement is the
nature of the load. If it is constant, then the ripple voltage on
the converter’s input leads is due only to the operation of the
converter. If, on the other hand, the load is changing over
time, this variation causes an additional input current and
voltage ripple to be drawn at the same frequency. If the frequency is high enough, the converter’s filter will help attenuate
this second source of ripple, but if it is below approximately
100 kHz, it will not. The system may then not meet the CE102
requirement, even though the converter is not the source of the
EMI. If this is the case, additional capacitance may be needed
across the load or across the input to the converter.
Another ambiguity in the CE102 measurement concerns common-mode voltage. If the load is left unconnected from the
ground plane (even though the case is grounded), the commonmode ripple voltages will be smaller than if the load is grounded.
The test specifications do not state which procedure should be
used. However, in neither case (load grounded or floating) will
the typical EMI test setup described below be exactly representative of the final system configuration EMI test. For the following reasons, the same is true if separately packaged EMI
filters are used.
REV. A –15–
Page 16
ADDC02808PB
In almost all systems the output ground of the converter is
ultimately connected to the input ground of the system. The
parasitic capacitances and inductances in this connection will
affect the common-mode voltage and the CE102 measurement. In addition, the inductive impedance of this ground
connection can cause resonances, thereby affecting the performance of the common-mode filter in the power supply.
In response to these ambiguities, the Analog Devices’ converter has been tested for CE102 under a constant load and
with the output ground floating. While these measurements
are a good indication of how the converter will operate in the
final system configuration, the user should confirm CE102
testing in the final system configuration.
CE101: This test measures emissions on the input leads in the
frequency range between 30 Hz and 10 kHz. The intent of
this requirement is to ensure that the dc/dc converter does not
corrupt the power quality (allowable voltage distortion) on the
power busses present on the platform. There are several
CE101 limit curves in MIL-STD-461D. The most stringent
one app-licable for the converter is the one for submarine
applications. Figure 11 shows that the converter easily meets
this requirement (the return line measurement is similar). The
components at 60 Hz and its harmonics are a result of ripple in
the output of the power source used to supply the converter.
CE102: This test measures emissions in the frequency range
between 10 kHz and 10 MHz. The measurements are made
on both of the input leads of the converter which are connected to the power source through LISNs. The intent of this
requirement in the lower frequency portion of the requirement
is to ensure that the dc/dc converter does not corrupt the
power quality (allowable voltage distortion) on the power
busses present on the platform. At higher frequencies, the
intent is to serve as a separate control from RE102 on potential
radiation from power leads which may couple into sensitive
electronic equipment.
Figure 12 shows the CE102 limit and the measurement taken
from the +V
input return line is slightly different, both comfortably meet
the MIL-STD-461D, CE102 limit.
CS101: This test measures the ability of the converter to
reject low frequency differential signals, 30 Hz to 50 kHz,
injected on the dc inputs. The measurement is taken on the
output power leads. The intent is to ensure that equipment
performance is not degraded from ripple voltages associated
with allowable distortion of power source voltage waveforms.
Figure 7 shows a typical audio susceptibility graph. Note that
according to the MIL-STD-461D test requirements, the injected signal between 30 Hz and 5 kHz has an amplitude of
2 V rms and from 5 kHz to 50 kHz the amplitude decreases
inversely with frequency to 0.2 V rms. The curve of the injected signal should be multiplied by the audio susceptibility
curve to determine the output ripple at any frequency. When
this is done, the worst case output ripple at the frequency of
the input ripple occurs at 5 kHz, at which point there is typically a 25 mV peak-to-peak output ripple.
It should be noted that MIL-STD-704 has a more relaxed
requirement for rejection of low frequency differential signals
injected on the dc inputs than MIL-STD-461D. MIL-STD704 calls for a lower amplitude ripple to be injected on the
input in a narrower frequency band, 10 Hz to 20 kHz.
line. While the measurement taken from the
IN
CS114: This test measures the ability of the converter to operate correctly during and after being subjected to currents injected into bulk cables in the 10 kHz to 400 MHz range. Its
purpose is to simulate currents that would be developed in these
cables due to electromagnetic fields generated by antenna transmissions. The converter is designed to meet the requirements
of this test when the current is injected on the input power leads
cable. Consult factory for more information.
CS115: This test measures the ability of the converter to operate correctly during and after being subjected to 30 ns long
pulses of current injected into bulk cables. Its purpose is to
simulate transients caused by lightning or electromagnetic
pulses. The converter is designed to meet this requirement
when applied to its input power leads cable. Consult factory for
more information.
CS116: This test measures the ability of the converter to operate correctly during and after being subjected to damped sinusoid transients in the 10 kHz to 100 MHz range. Its purpose is
to simulate current and voltage waveforms that would occur
when natural resonances in the system are excited. The converter is designed to meet this requirement when applied to its
input power leads cable. Consult factory for more information.
RE101: This requirement limits the strength of the magnetic
field created by the converter in order to avoid interference with
sensitive equipment located nearby. The measurement is made
from 30 Hz to 100 kHz. The most stringent requirement is for
the Navy. Figure 13 shows the test results when the pickup coil
is held 7 cm above the converter. As can be seen, the converter
easily meets this requirement.
RE102: This requirements limits the strength of the electric
field emissions from the power converter to protect sensitive
receivers from interference. The measurement is made from
10 kHz to 18 GHz with the antenna oriented in the vertical
plane. For the 30 MHz and above range the standard calls for
the measurement to be made with the antenna oriented in the
horizontal plane, as well.
In a typical power converter system setup, the radiated emissions can come from two sources: 1) the input power leads as
they extend over the two meter distance between the LISNs and
the converter, as required for this test, and 2) the converter
output leads and load. The latter is likely to create significant
emissions if left uncovered since minimal EMI filtering is
provided at the converter’s output. It is typical, however,
that the power supply and its load would be contained in a
conductive enclosure in applications where this test is applicable.
A metal screen enclosure was therefore used to cover the converter and its load for this test.
Figure 14 shows test results for the vertical measurement and
compares them against the most stringent RE102 requirement;
the horizontal measurement (30 MHz and above) was similar.
As can be seen, the emissions just meet the standard in the
18 MHz–28 MHz range. This component of the emissions is
due to common-mode currents flowing through the input power
leads. As mentioned in the section on CE102 above, the level
of common-mode current that flows is dependent on how the
load is connected. This measurement is therefore a good indication of how well the converter will perform in the final configuration, but the user should confirm RE102 testing in the
final system.
REV. A–16–
Page 17
ADDC02808PB
G(S) – Transfer Function (Dimensionless)
FREQUENCY – Hz
1•10
4
1•10
7
1•10
5
1•10
6
100
10
1
0.1
0.01
0.001
10
–4
10
–5
10
–6
10
–7
10
–8
ADDC02808PB
ADDC02805SA
RS101: This requirement is specialized and is intended to check
for sensitivity to low frequency magnetic fields in the 30 Hz to
50 kHz range. The converter is designed to meet this requirement. Consult factory for more information.
RS103: This test calls for correct operation during and after the
unit under test is subjected to radiated electric fields in the 10 kHz
to 40 GHz range. The intent is to simulate electromagnetic
fields generated by antenna transmissions. The converter is
designed to meet this requirement. Consult factory for more
information.
Circuit Setup for EMI Test
Figure 15 shows a schematic of the test setup used for the EMI
measurements discussed above. The output of the converter is
connected to a resistive load designed to draw full power. There
is a 0.1 µF capacitor placed across this resistor that typifies by-
pass capacitance normally used in this application. At the input
of the converter there are two differential capacitors (the larger
one having a series resistance) and two small common-mode
capacitors connected to case ground. The case itself was connected to the metal ground plane in the test chamber. For the
RE102 test, a metal screen box was used to cover both the converter and its load (but not the two meters of input power lead
cables). This box was also electrically connected to the metal
ground plane.
With regard to the components added to the input power lines,
the 100 µF capacitor with its 1 Ω series resistance is required to
achieve system stability when the unit is powered through the
LISNs, as the MIL-STD-461D standard requires. These
LISNs have a series inductance of 50 µH at low frequencies,
giving a total differential inductance of 100 µH. As explained
earlier in the System Instability section, such a large series
source inductance will cause an instability as it interacts with the
converter’s negative incremental input resistance unless some
corrective action is taken. The 100 µF capacitor and 1 Ω resis-
tor provide the stabilization required.
It should be noted that the values of these stabilization components
are appropriate for a single converter load. If the system makes
use of several converters, the values of the components will need
to be changed slightly, but not such that they are repeated for
every converter. It should also be noted that most system appli-
cations will not have a source inductance as large as the 100 µH
built into the LISNs. For those systems, a much smaller input
capacitor could be used.
The 2 µF differential-mode capacitor and the two 82 nF com-
mon-mode capacitors were added to achieve the results shown
in the EMI measurement figures described above.
ADDC02808PB EMI Performance
The EMI performance of the ADDC02808PB power converter
will be different from the ADDC02805SA baseline previously
discussed for several reasons:
1. Its maximum power is 200 W, or twice that of the
ADDC02805SA converter.
2. Its differential input filter inductors are smaller in value by a
factor of two compared to those in the ADDC02805SA
converter to accommodate input stability at the higher power
level.
REV. A –17–
3. A repetitively pulsed load will cause large input currents at
the fundamental frequency (and harmonics) of the pulse
waveform.
The result of Items 1 and 2 is that the ADDC02808PB converter will have higher conducted and radiated emissions in the
1/2 MHz to 10 MHz range. The emissions in this range are
dominated by differential currents. These currents are proportional to power, so we would expect a factor of two increase in
emissions due to the 200 W operating level. It does not matter
that the average power of this pulsed unit is 100 W or lower.
MIL-STD-462D calls for measurements to be made with peak
detectors that will determine the emissions during the 200 W
pulse, and not average them in any way with the lower power
part of the cycle.
In addition, the differential EMI filter in the ADDC02808PB
converter is less effective at attenuating the ripple currents than
is the filter in the ADDC02805SA converter due to smaller
value inductors. Figure 38 shows the transfer functions of these
two filters in the frequency range of interest.
Combining the factor of two and the reduced filter attenuation,
Figure 39 shows the ratio, in dB, by which the emissions of
Figures 12 and 14 should be increased to estimate the emissions
of the ADDC02808PB converter in this frequency range. From
this curve the 1/2 MHz component should increase by 25 dB,
and the 1 MHz and higher components should increase by 22 dB.
For both conducted and radiated tests, this increase would
require some additional differential filtering to meet the most
stringent MIL-STD-461D levels shown in the figures. This
could be done, for example, by increasing the 2 µF ceramic (low
parasitic inductance) capacitor placed across the input of the
converter in Figure 15 to 30 µF or, a small 0.5 µH, 16 A induc-
tor could be placed in series between the top of the 2 µF capaci-
tor and the +V
pin. Figures 40 and 41 show the ratios, in
IN
Figure 38. Comparison of Transfer Functions for the Input
EMI Filters in ADDC02805SA and ADDC02808PB
Page 18
ADDC02808PB
30
20
10
dB
0
–10
–20
1•10
5
6
1•10
FREQUENCY – Hz
1•10
7
Figure 39. Change in ADDC02808PB Differential Emissions vs. ADDC02805SA Emissions with the Same Test
Setup
dB, by which the differential emissions would change if either of
these approaches were followed. Notice that the inductor solution provides substantial attenuation in the 1 MHz and higher
frequency range, while the larger capacitor solution has a more
uniform effect. These proposed solutions are suggestions; they
have not been tested.
30
20
10
dB
0
–10
–20
1•10
5
6
1•10
FREQUENCY – Hz
1•10
7
Figure 40. Change in ADDC02808PB Differential Emissions
vs. the ADDC02805SA Emissions with External 30
µ
F
Capacitor
30
20
10
dB
0
–10
–20
1•10
5
6
1•10
FREQUENCY – Hz
1•10
7
Figure 41. Change in ADDC02808PB Differential Emissions
vs. the ADDC02805SA Emissions with External 0.5
µ
H,
16 A Inductor
The peak in the radiated emissions in the 20 MHz–30 MHz
range of Figure 14 is dominated by common-mode noise. This
common-mode noise emission is changed only slightly between
the ADDC02808PB and the ADDC02805SA converters since it
does not depend on the power level or the differential input
filter. The turns ratio on the transformer has been changed, so
we expect the common-mode emissions might be 2–4 times
larger. This increase could be countered by increasing the 82 nF
common-mode capacitors of Figure 15 correspondingly. Again,
this solution is a suggestion; it has not been tested.
Finally, the pulsed nature of the load means there will be a
substantial ripple in the input current at the fundamental pulse
rate and its harmonics. This ripple can be calculated once the
power is known as a function of time by dividing by the input
voltage. For instance, if the load switches between zero and
200 W (260 W at the input) at 1 kHz with a duty ratio of 50%,
the current drawn by the converter will have a 9.3 A on, 0 A off,
50% duty ratio input current waveform (260 W/28 V = 9.3 A).
This waveform has an average of 4.65 A and a square wave of
plus and minus 4.65 A around this average. This square wave of
current has a fundamental component as well as odd harmonics
(3rd, 5th, 7th, . . .). The peak of the fundamental component is
(4/π) 4.65. The rms value of this component is .707 times the
peak, or 4.2 A.
With the test setup in Figure 15, given the impedances of the
LISNs and the 100 µF capacitor with its 1 Ω series resistance, a
3.6 V rms waveform would result from this fundamental
component of the input current. The MIL-STD-461D limit
shown in Figure 11 calls for approximately 100 mV at the 1 kHz
frequency. If this limit is to be met, substantial filtering at the
lower frequencies will have to be added to the system.
RELIABILITY CONSIDERATIONS
MTBF (Mean Time Between Failure) is a commonly used
reliability concept that applies to repairable items in which
failed elements are replaced upon failure. The expression for
MTBF is
MTBF = T/r
where
T = total operating time
r = number of failures
In lieu of actual field data, MTBF can be predicted per
MIL-HDBK-217.
MTBF, Failure Rate, and Probability of Failure: A proper
understanding of MTBF begins with its relationship to lambda
(λ), which is the failure rate. If a constant failure rate is assumed,
then MTBF = 1/λ, or λ = 1/MTBF. If a power supply has an
MTBF of 1,000,000 hours, this does not mean it will last
1,000,000 hours before it fails. Instead, the MTBF describes
the failure rate. For 1,000,000 hours MTBF, the failure rate
during any hour is 1/1,000,000, or 0.0001%. Thus, a power
supply with an MTBF of 500,000 hours would have twice the
failure rate (0.0002%) of one with 1,000,000 hours.
What users should be interested in is the probability of a power
supply not failing prior to some time t. Given the assumption of
a constant failure rate, this probability is defined as
R(t ) = e
–λt
REV. A–18–
Page 19
ADDC02808PB
C1
+28VDC
28RTN
1
2
10
11
17
16
15
14
13
12
ADDC02808PB
PS1
RLOAD
NOTE: VALUE OF C1 IS DEPENDENT ON SOURCE IMPEDANCE.
REFER TO SECTION ON SYSTEM INSTABILITY CONSIDERATIONS.
+SENSE PS1
+SENSE PS2
–SENSE PS1
–SENSE PS2
RLOAD
V
OUT
+
V
OUT
–
1
2
8
10
11
17
16
15
14
13
12
ADDC02808PB
1
2
8
10
11
17
16
15
14
13
12
ADDC02808PB
PS2
PS1
I SHARE
C1
+28VDC
28RTN
NOTE: VALUE OF C1 IS DEPENDENT ON SOURCE IMPEDANCE.
REFER TO SECTION ON SYSTEM INSTABILITY CONSIDERATIONS.
where R(t) is the probability of a device not failing prior to some
time t.
If we substitute λ = 1/MTBF in the above formula, then the
expression becomes
–t
R(t ) = e
MTBF
This formula is the correct way to interpret the meaning of
MTBF.
If we assume t = MTBF = 1,000,000 hours, then the probability
that a power supply will not fail prior to 1,000,000 hours of use
–1
is e
, or 36.8%. This is quite different from saying the power
supply will last 1,000,000 hours before it fails. The probability
that the power supply will not fail prior to 50,000 hours of use is
–.05
, or 95%. For t = 10,000 hours, the probability of no failure
e
–.01
, or 99%.
is e
Temperature and Environmental Factors: Although the
calculation of MTBF per MIL-HDBK-217 is a detailed process,
there are two key variables that give the manufacturer significant leeway in predicting an MTBF rating. These two variables are temperature and environmental factor. Therefore, for
users to properly compare MTBF numbers from two different
manufacturers, the environmental factor and the temperature
must be identical. Contact the factory for MTBF calculations
for specific environmental factors and temperatures.
circuit board through holes. In order to maintain the hermetic
integrity of the seals around the pins, a fixture should be used
for bending the pins without stressing the pin-to-sidewall seals.
It is recommended that the minimum distance between the
package edge and the inside of the pin be 100 mils (2.54 mm)
for the 40 mil (1.02 mm) diameter pins; 120 mils (3.05 mm)
from the package edge to the center of the pin as shown in
Figure 43.
0.100"
(2.54mm)
0.120"
(3.05mm)
Figure 43. Minimum Bend Radius of 40 Mil (1.02 mm)
Pins
MECHANICAL CONSIDERATIONS
When mounting the converter into the next higher level assembly, it is important to insure good thermal contact is made between the converter and the external heat sink. Poor thermal
connection can result in the converter shutting off, due to the
temperature shutdown feature (Pin 9), or reduced reliability for
the converter due to higher than anticipated junction and case
temperatures. For these reasons the mounting tab locations
were selected to insure good thermal contact is made near the
hot spots of the converter which are shown in the shaded areas
of Figure 42.
Figure 42. Hot Spots (Shaded Areas) of DC/DC Converter
The pins of the converter are typically connected to the next
higher level assembly by bending them at right angles, either
down or up, and cutting them shorter for insertion in printed
REV. A –19–
Figure 44. Typical Power Connections and External Parts
for Converter
Figure 45. Typical Connections for Paralleling Two
Converters
Page 20
ADDC02808PB
Screening Levels for ADDC02808PB
Screening Steps Industrial (KV) Ruggedized Industrial (TV) MIL-STD-883B/SMD (TV/QMLH)
Pre-Cap Visual 100% MIL-STD-883, TM2017
Temp Cycle N/A N/A
Constant Acceleration N/A N/A
Fine Leak Guaranteed to Meet Guaranteed to Meet
MIL-STD-883, TM1014 MIL-STD-883, TM1014
Gross Leak Guaranteed to Meet Guaranteed to Meet
MIL-STD-883, TM1014 MIL-STD-883, TM1014
Burn-In N/A MIL-STD-883, TM1015,
96 Hrs at +125°C Case
Final Electrical Test At +25°C, Per Specification At +25°C, Per Specification
Table Table
NOMINAL CASE DIMENSIONS IN INCHES AND (mm).
[All tolerances ±0.005" (±.13 mm) unless otherwise specified]
Compliant to MIL-PRF-38534
C2183a–4–11/98
0.300 (7.62) SQ
TOP VIEW
1.145 (29.08)
2 PLCS
0.150 (3.81)
0.200 (5.08)
0.390 6 0.010
(9.91 6 0.25)
0.100 (2.54)
8 PLCS
0.200 (5.08)
0.150 (3.81)
0.150 (3.81)
4 PLCS
0.800 6 0.010
(20.32 6 0.25)
4 PLCS
0.149 (3.78)
DIA TYP
2.745 6 0.010
(69.72 6 0.25)
NOTES
1. The final product weight is 85 grams maximum.
2. The package base material is made of molybdenum and is
nominally 40 mils (1.02 mm) thick. The “runout” is less
than 2 mils per inch (0.02 mm per cm).
3. The high current pins (10–17) are 40 mil (1.02 mm) diameter;
are 99.8% copper; and are plated with gold over nickel.
4. The signal carrying pins (1–9) are 18 mil (0.46 mm) diameter; are Kovar; and are plated with gold over nickel.
6 0.010
4 PLCS
1.500 6 0.010
0.200 (5.08) 5 PLCS
0.250 (6.35)
2 PLCS
(38.10 6 0.25)
1.800
(45.72)
TYP
2.100 6 0.010
(53.34 6 0.25)
0.040 6 0.003
(1.02 6 0.08)
0.090 6 0.010
(2.29 6 0.25)
5. All pins are a minimum length of 0.740 inches (18.80 mm)
when the product is shipped. The pins are typically bent up
or down and cut shorter for proper connection into the user’s
system.
6. All pin-to-sidewall spacings are guaranteed for a minimum of
500 V dc breakdown at standard air pressure.
7. The case outline was originally designed using the inch-pound
units of measurement. In the event of conflict between the
metric and inch-pound units, the inch-pound shall take
precedence.
PRINTED IN U.S.A.
REV. A–20–
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