Page 1
May 2001
ADCV08832
Low Voltage, 8-Bit Serial I/O CMOS A/D Converter with
Sample/Hold Function
General Description
The ADCV08832 is a low voltage, 8-Bit successive approximation analog-to-digital converter with a 3-wire serial interface. The serial I/O will interface to microcontrollers, PLD’s,
microprocessors, DSPs or shift registers. The serial I/O is
configured to comply with the NSC MICROWIRE
data exchange standard.
To minimize total power consumption, the ADCV08832 can
be set to go into low power mode whenever it is not performing conversions.
A sample/hold function allows the analog voltage at the
positive input to vary during the actual A/D conversion. The
analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential
modes.
™
serial
Features
n 3-wire serial digital data link requires few I/O pins
n Single supply 2.7V to 5V
n Analog input track/hold function
n Analog input voltage range from GND to V
n No zero or full scale adjustment required
CC
n TTL/CMOS input/output compatible
n Superior pin compatible replacement for TLV0832 and
ADC0832
Applications
n Digitizing sensors and waveforms
n Process control monitoring
n Remote sensing in noisy environments
n Instrumentation
n Embedded systems
n Low power circuits
Key Specifications
(For 3.3V supply, typical, unless otherwise noted)
n Resolution 8 bits
n Conversion time (f
n Power dissipation 1.7 mW
n Power down mode
n Total Unadjusted Error
n No missing codes over temperature (−40˚C to +125˚C)
= 500 kHz) 16 µs (max)
CLK
<
±
0.8 LSB
ADCV08832 Low Voltage, 8-Bit Serial I/O CMOS A/D Converter with Sample/Hold Function
0.1 µW
Connection Diagram
Ordering Information
Temperature Range
Industrial (−40˚C ≤ T
ADCV08832CIM M08A ADC08832I 95 Units in Rail
ADCV08832CIMX M08A ADC08832I 2500 Units in
≤ +125˚C)
J
ADCV08832
SOIC-8 Package
Package
DS200084-1
Package
Marking
Transport
Media
Tape and Reel
COPS™and MICROWIRE™are trademarks of National Semiconductor Corporation.
© 2001 National Semiconductor Corporation DS200084 www.national.com
Page 2
Absolute Maximum Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ADCV08832
Supply Voltage (V
Voltage at Inputs and Outputs −0.3V to V
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
ESD Susceptibility (Note 6)
Human Body Model 2500V
Machine Model 250V
) 6.5V
CC
CC
+ 0.3V
±
5mA
±
20 mA
Storage Temperature Range −65˚C to +150˚C
Mounting Temperature
Infrared 235˚C
Operating Ratings (Notes 2, 3)
Temperature Range −40˚C
Supply Voltage 2.7V to 5.5V
Thermal Resistance (θ
SO Package,
8-pin Surface Mount 190˚C/W
Clock Frequency 10 kHz ≤ f
Junction Temperature (Note 5) 150˚C
Electrical Characteristics
The following specifications apply for VCC= 3.3VDCand f
face limits apply for T
A=TJ=TMIN
to T
; all other limits TA=TJ= 25˚C.
MAX
Symbol Parameter Conditions Typical
CONVERTER AND MULTIPLEXED CHARACTERISTICS
TUE Total Unadjusted Error (Note 9)
V
OFF
Offset Error 0.03
DNL Differential Nonlinearity 0.1
INL Integral Nonlinearity 0.1
FS Full Scale Error 0.06
V
IN
Analog Input Voltage (Note 10) (VCC+ 0.05)
DC Common Mode Error
Analog Input Leakage Current
(Note 11)
On Channel
Off Channel
DC CHARACTERISTICS
V
IN(1)
V
IN(0)
I
IN
V
OUT(1)
V
OUT(0)
I
OUT
I
SOURCE
Logical “1” Input Voltage 1.0 2.0 V (min)
Logical “0” Input Voltage 1.1 0.8 V (max)
Digital Input Current
Logical “1” Output Voltage VCC= 2.7V
I
OUT
Logical “0” Output Voltage VCC= 2.7V
I
OUT
TRI-STATE Output Current V
Digital Output Short Circuit
V
V
OUT
OUT
OUT
Current
I
I
SINK
CC
Digital Output Sink Circuit V
OUT=VCC
Supply Current (Note 15) CS = V
CS = Low,
CLK=V
= 500 kHz, 50% Duty Cycle, unless otherwise specified. Bold-
CLK
= −360 µA 3.3 2.4 V (min)
= 1.6 mA
=0V
= 3.3V
= 0V −13 mA
CC
CC
<
T
J
)
jA
≤ 1000 kHz
CLK
(Note 7)
±
0.1
Limits
(Note 8)
±
0.8 LSB (max)
±
0.5 LSB
±
0.5 LSB
±
0.5 LSB
±
0.8 LSB
Units
V (max)
(GND − 0.05)
±
0.02 LSB (max)
±
11.0 nA
±
3.0 nA
±
2 µA (max)
V (min)
0.2 0.4 V (max)
−2.0
2.0
9.6 mA
0.1 nA
330 500 µA (max)
<
+125˚C
µA
µA
Electrical Characteristics
The following specifications apply for VCC= 3.3V, 50% Duty Cycle, and tr=tf= 20 ns unless otherwise specified. Boldface
limits apply for T
A=TJ=TMIN
Symbol Parameter Conditions Typical Limits Units
f
CLK
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Max Clock Frequency VCC= 5 1000 kHz
to T
; all other limits TA=TJ= 25˚C.
MAX
V
= 3.3 700 500 kHz
CC
V
= 2.7 400 kHz
CC
Page 3
Electrical Characteristics (Continued)
The following specifications apply for VCC= 3.3V, 50% Duty Cycle, and tr=tf= 20 ns unless otherwise specified. Boldface
limits apply for T
A=TJ=TMIN
Symbol Parameter Conditions Typical Limits Units
Clock Duty Cycle
(Note 12)
t
CONV
Conversion Time (Not Including MUX
Addressing Time) f
t
ca
t
SET-UP
Acquisition Time
Set Up Time Required from Falling CS
to Rising Clock Edge
t
HOLD
Data Input Valid after CLK
Rising Edge
t
pd1,tpd0
CLK Falling Edge to Output
Data Valid (Note 13)
t
1H,t0H
TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z
C
IN
Input Capacitance of CH0,CH
(Note 14)
C
IN
C
OUT
Input Capacitance of CLK, D1 5 pF
Output Capacitance of Logic Outputs
D0 (in TRI-STATE)
to T
; all other limits TA=TJ= 25˚C.
MAX
= 500 kHz
CLK
CL= 100 pF:
Data MSB First
Data LSB First
CL= 100 pF, RL=10kΩ
(see TRI-STATE Test Circuit)
1
40
60
8
% (min)
% (max)
1/f
16
1
⁄
2
1/f
CLK
15 ns (min)
20 ns (min)
150
100
ns (max)
ns (max)
35 ns
13 pF
5pF
ADCV08832
CLK
µs
(max)
Dynamic Characteristics
The following specifications apply for VCC= 3.3V, f
non-coherent 2048 samples.
Symbol Parameter Conditions Typical Limits Units
f
S
Sampling Rate f
SNR Signal-to-Noise Ratio (Note 16) 49.5 dB
THD Total Harmonic Distortion (Note 17) −66 dB
SINAD Signal-to-Noise and Distortion 49.4 dB
ENOB Effective Number Of Bits (Note 15) 7.9 Bits
SFDR Spurious Free Dynamic Range −67.6 dB
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND = 0 V
Note 4: Whenthe input voltage V
maximum package input current rating limits the number of pins that can safely exceed V
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor. The machine mode is a 200 pF capacitor discharged directly into each pin.
Note 7: Typical are at T
Note 8: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
Note 10: For V
forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than V
analog inputs (e.g., 3.3V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode; this means that as long as the analog V
will be correct. Exceeding the range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V
voltage range will therefore require a minimum supply voltage of 3.25 V
Note 11: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (3.3V
is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channel is again measured. The two cases
considered for determining the on channel leakage current are the same except total current flow through the selected channel is measured.
Note 12: A 40% to 60% duty cycle range insures proper operation at all clock frequencies.
Note 13: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow for comparator
response time.
IN(−)
≥ V
J
IN(+)
at any pin exceeds the power supplies (V
IN
=(T
D
JMAX−TA
= 25˚C and represent the most likely parametric norm.
the digital output will be 0000 0000. Two on-chip diodes are tied to each analog input (see Functional Block Diagram) which will
= 500 kHz, TA= 25˚C, R
CLK
, unless otherwise specified.
DC
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower.
<
(GND) or V
IN
over temperature variations, initial tolerance and loading.
DC
) and the remaining off channel tied low (0 VDC), total current flow through the off channel
DC
CC
does not exceed the supply voltage by more than 50 mV,the output code
IN
SOURCE
>
VCC,) the current at that pin should be limited to 5 mA. The 20 mA
IN
with an input current of 5 mA to four pins.
=25Ω,fIN= 9.6 kHz, VIN= 3.3V
/13 ksps
CLK
, θJAand the ambient temperature, TA. The maximum
JMAX
. During testing at low VCClevels (e.g., 2.7V), high level
CC
to 3.30 VDCinput
DC
P-P
,
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Page 4
Dynamic Characteristics (Continued)
Note 14: Analog inputs are typically 300Ω input resistance in series with a 13 pF sample and hold.
Note 15: Effective Number Of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB = (SINAD
−1.76)/6.02.
ADCV08832
Note 16: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in its calculation.
Note 17: The contributions of the first 6 harmonics are to calculate THD.
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Page 5
ADCV08832 Functional Block Diagram
ADCV08832
DS200084-12
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Page 6
Typical Performance Characteristics The following specifications apply for T
unless otherwise specified.
= 25˚C, VCC= 3.3V,
A
TUE vs Clock Frequency
ADCV08832
DNL vs Output Codes
DS200084-48
INL vs Output Codes
ICC(operating) vs V
DS200084-49
CC
DS200084-50
Typical Digital Output Current vs Temperature
DS200084-52
DS200084-51
ICC(operating) vs Temperature
DS200084-53
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Page 7
ADCV08832
Typical Performance Characteristics The following specifications apply for T
unless otherwise specified. (Continued)
Spectral Response with 1.9 kHz
Sine Wave Input, f
CLK
= 500 kHz
Spectral Response with 18.8 kHz
Sine Wave Input, f
CLK
= 500 kHz
DS200084-54
Spectral Response with 9.6 kHz
Sine Wave Input, f
CLK
= 500 kHz
= 25˚C, VCC= 3.3V,
A
DS200084-55
DS200084-56
Leakage Current Test Circuit
DS200084-5
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Page 8
TRI-STATE Test Circuits and Waveforms
ADCV08832
Timing Diagrams
DS200084-20
DS200084-21
Data Input Timing
DS200084-22
Data Output Timing
DS200084-23
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Page 9
Timing Diagrams (Continued)
ADCV08832
ADCV08832 Timing
DS200084-26
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a comparator structure with built-in sample-and-hold which provides for a differential analog input to be converted by a successive approximation routine.
In differential mode the voltage converted is always the
difference between the assigned “+” input terminal and the
“−” input terminal. The polarity of each input terminal of the
pair indicates which line the converter expects to be the most
positive. If the assigned “+” input voltage is less than the “−”
input voltage the converter responds with an all zeros output
code.
The multiplexor at the analog inputs of the converter provides for the software-configurable single-ended or differential operation. The analog signal conditioning required in
transducer-based data acquisition systems is significantly
simplified with this type of input flexibility. A single
ADCV08832 can handle ground referenced inputs, differential inputs, as well as signals with some arbitrary reference
voltage.
The input configuration is assigned during the MUX addressing sequence, prior to the start of a conversion. The MUX
address selects which of the analog inputs will be enabled,
and whether this input is single-ended or differential. In
addition to selecting the differential mode, the polarity may
also be selected. Channel 0 may be selected as the positive
input and channel 1 as the negative input or vice versa. This
programmability is illustrated in the MUX addressing tables.
MUX Addressing: ADCV08832
Single-Ended MUX Mode
MUX Address Channel
Start
SGL/
Bit
110+
111 +
DIF
ODD/
SIGN
01
#
Differential MUX Mode
MUX Address Channel
Start
Since the input configuration is under software control, it can
be modified as required before each conversion. A channel
could be treated as a single-ended, ground referenced input
for one conversion; then, it could be reconfigured as part of
a differential channel for another conversion.
The analog input voltages for each channel can range from
50mV below ground to 50mV above Vcc without degrading
conversion accuracy.
2.0 THE DIGITAL INTERFACE
An important characteristic of this converter is the serial
communication interface with the controlling processor. The
serial interface facilitates versatile operation in a small package. The small converter can be placed close to the analog
source, converting a low level signal into a noise immune bit
stream.
To understand the operation of these converters, it is best to
refer to the Timing Diagrams and Functional Block Diagram
and follow a complete conversion sequence.
1. A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire conversion (13 Clock Cycles). The converter is now waiting
for a start bit and its MUX assignment word.
2. On each rising edge of the clock the data on the DI line
is clocked into the MUX address shift register. The start
bit is the first logic ″1″ that appears on this line (all
leading zeros are ignored). Following the start bit the
converter expects the next 2 bits to be the MUX address.
3. A conversion begins
latched. An interval of
happens) is automatically inserted to allow the selected
MUX channel to settle to a final analog input value. The
DI line is ignored for the remainder of the conversion.
4. On the falling edge of the 3rd clock. DO exits TRI-STATE
and provides a leading zero for this one clock period of
MUX settling time.
SGL/
Bit
100+−
101−+
ODD/
DIF
SIGN
1
⁄2clock after the odd/sign bit is
1
⁄2clock period (where nothing
01
#
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Page 10
Functional Description (Continued)
5. During the conversion, the output of the SAR compara-
ADCV08832
tor indicates whether the successive analog input is
greater than (high) or less than (low) a series of voltages
generated internally from a ratioed capacitor array (first
5 bits) and a resistor ladder (last 3 bits). After each
comparison, the output of the comparator is clocked to
DO on the falling edge of CLK.
6. After 8 clock periods the successive approximation routine is completed.
7. Next, the stored data in the successive approximation
register is loaded into an internal shift register and
shifted out LSB first. The DO line then goes low until CS
is returned high.
8. The DI and DO lines may be tied together and controlled
through a bi-directional processor I/O bit with one wire.
This is possible because the DI input is valid only during
the MUX addressing interval, while the DO line is still in
a high impedance state.
Where f
V
PEAK
version time (t
For a 60 Hz common-mode signal to generate a
is the frequency of the common-mode signal,
CM
is its peak voltage value, and t
conv
= 13/f
CLK
).
is the A/D’s con-
conv
1
⁄4LSB error
(5 mV) with the converter running at 500 kHz, its peak value
would have to be 0.328V.
4.1 Sample and Hold
The ADCV08832 provides a built-in sample-and-hold to acquire the input signal. The sample and hold can sample input
signals in either single-ended or pseudo differential mode.
4.2 Input Op Amps
When driving the analog inputs with an op amp it is important
that the op amp settle within the allowed time. Toachieve the
full sampling rate, the analog input should be driven with a
low impedance source (100Ω) or a high-speed op amp such
as the LM6142. Higher impedance sources or slower op
amps can easily be accommodated by allowing more time
for the analog input to settle.
3.0 Reducing Power Consumption
At 3.3V supply, the ADCV08832 consumes about 330 µA
when CS is logic low. When CS is pulled high the device will
enter a low power mode to minimize total power consumption.
In low power mode some analog circuitry and digital logic are
put in a static, low power condition. Also, DO, the output
driver is taken into a TRI-STATE mode.
To optimize static power consumption, special attention must
be given to the digital input logic signals: CLK, CS, DI. Each
digital input has a large CMOS buffer between V
and
CC
GND. A traditional TTL level high (2.4V) will be sufficient for
each input to read a logical “1”. However, there could be a
large V
to VCCvoltage difference at each input. Such a
IH
voltage difference would cause excessive static power dissipation, even when CS is high and the part is low power
mode.
Therefore, to minimize the static power dissipation, it is
recommended that all digital logic levels should equal the
converter’s supply. Various CMOS logic is particularly well
suited for this application.
4.0 THE ANALOG INPUTS
The most important feature of the ADCV08832 is that it can
be located right at the analog signal source and through just
a few wires can communicate with a controlling processor.
This in itself greatly minimizes circuitry to maintain analog
signal accuracy which otherwise is most susceptible to noise
pickup. However, the following must be considered for situations in which the analog input sources are noisy or riding
on a large common-mode voltage.
In a true differential input stage, any signal that is common to
both “+” and “-” inputs is cancelled. For the ADCV08832 the
positive input of a selected channel pair is only sampled
once before the start of a conversion during the acquisition
time (t
). The negative input needs to be stable during the
ca
complete conversion sequence because it is sampled before
every decision in the SAR sequence. Therefore, any AC
common-mode signal present on the analog inputs will not
be completely cancelled and will cause some conversion
errors. The linear worse case approximation of a common
mode sinusoidal signal error is:
V
(MAX) = V
error
PEAK
(2πfCM)(t
conv
)
4.3 Source Resistance
The analog inputs of the ADCV08832 appears as a 13 pF
capacitor (C
) in series with a 300Ω resistor (RON). CINgets
IN
switched between the selected “+” and “-” inputs during each
conversion cycle. Large external source resistors will slow
the settling of the inputs. It is important that the overall RC
time constants be short enough to allow the analog input to
completely settle.
4.4 Board Layout Considerations, Grounding and
Bypassing
The ADCV08832 should be used with an analog ground
plane and single-point grounding techniques. The GND pin
should be tied directly to the ground plane.
The supply pin should be bypassed to the ground plane with
a ceramic capacitor with leads as short as possible in single
ended mode. All analog inputs should be referenced directly
to the single-point ground.
5.0 OPTIONAL ADJUSTMENTS
5.1 Zero Error
The offset of the A/D does not require adjustment. If the
minimum analog input voltage value, V
, is not ground
IN(MIN)
a zero offset can be done. In differential mode the converter
can be made to output 0000 0000 digital code for this
minimum input voltage by biasing any V
V
IN(MIN)
value.
(−) input at this
IN
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V
positive voltage to the V
(−) input and applying a small magnitude
IN
(+) input. Zero error is the differ-
IN
ence between the actual DC input voltage which is necessary to just cause an output digital code transition from 0000
0000 to 0000 0001 and the ideal
1
⁄2LSB value (1⁄2LSB =
6.4 mV).
6.0 DYNAMIC PERFORMANCE
Dynamic performance specifications are often useful in applications requiring waveform sampling and digitization.
Typically, a memory buffer is used to capture a stream of
consecutive digital outputs for post processing. Capturing a
number of samples that is a power of 2 (ie, 1024, 2048,
4096) allows the Fast Fourier Transform (FFT) to be used to
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Page 11
Functional Description (Continued)
digitally analyze the frequency components of the signal.
Depending on the application, further digital processing can
be applied.
6.1 Sampling Rate
The Sampling Rate, sometimes referred to as the Throughput Rate, is the time between repetitive samples by an
Analog-to-Digital Converter. The sampling rate includes the
conversion time, as well as other factors such a MUX setup
time, acquisition time, and interfacing time delays. Typically,
the sampling rate is specified in the number of samples
taken per second, at the maximum analog-to-digital converter clock frequency.
Signals with frequencies exceeding the Nyquist frequency
(1/2 the sampling rate), will be aliased into frequencies below the Nyquist frequency. To prevent signal degradation,
sample at twice (or more) than the highest frequency component of the input signal and/or use of a low pass
(anti-aliasing) filter on the front-end. Sampling at a much
higher rate than the input signal will reduce the requirements
of the anti-aliasing filter.
6.2 Signal-to-Noise Ratio
Signal-to-Noise Ratio (SNR) is the ratio of RMS magnitude
of the fundamental to the RMS sum of all the
non-fundamental signal, excluding the harmonics, up to 1/2
of the sampling frequency (Nyquist).
6.3 Total Harmonic Distortion
Total Harmonic distortion is the ratio of the RMS sum of the
amplitude of the harmonics to the fundamental input frequency.
THD = 20 log [(V
Where V
V
2,V3,V4,V5,V6
is the RMS amplitude of the fundamental and
1
2
2
3
+V
4
2
+V
5
+V
2
are the RMS amplitudes of the individual
2
+V
1/2
2
)
/V1]
6
ADCV08832
harmonics. In theory, all harmonics are included in THD
calculations, but in practice only about the first 6 make
significant contributions and require measurement.
6.4 Signal-to-Noise and Distortion
Signal-to-Noise And Distortion ratio (SINAD) is the ratio of
RMS magnitude of the fundamental to the RMS sum of all
the non-fundamental signals, including the noise and harmonics, up to 1/2 of the sampling frequency (Nyquist), excluding DC.
SINAD is also dependent on the number of quantization
levels in the A/D Converter used in the waveform sampling
process. The more quantization levels, the smaller the quantization noise and theoretical noise performance. The theoretical SINAD for a n-BitAnalog-to-Digital Converter is given
by:
SINAD = (6.02 n + 1.76) dB
Thus, for an 8-bit converter, the ideal SINAD = 49.92 dB
6.5 Effective Number of Bits
Effective Number Of Bits (ENOB) is another specification to
quantify dynamic performance. The equation for ENOB is
given by:
ENOB = [(SINAD - 1.76) / 6.02]
Like SINAD, the Effective Number Of Bits combines the
cumulative effect of several errors, including quantization,
ADC non-linearities, noise, and distortion.
6.6 Spurious Free Dynamic Range
Spurious Free Dynamic Range (SFDR) is the ratio of the
signal amplitude to the amplitude of the highest harmonic or
spurious noise component. If the amplitude is at full scale,
the specification is simply the reciprocal of the peak harmonic or spurious noise.
Applications
Protecting the Input
DS200084-9
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Page 12
Applications (Continued)
ADCV08832
Isolated Data Converter
DS200084-40
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Page 13
Applications (Continued)
ADCV08832
A “Stand-Alone” Hook-Up for ADCV08832 Evaluation
DS200084-39
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Page 14
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADCV08832CIM
NS Package Number M08A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
ADCV08832 Low Voltage, 8-Bit Serial I/O CMOS A/D Converter with Sample/Hold Function
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National Semiconductor
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