Datasheet ADCMP565 Datasheet (Analog Devices)

Dual Ultrafast

FEATURES

300 ps propagation delay input to output
50 ps propagation delay dispersion
Differential ECL compatible outputs
Differential latch control
Robust input protection
Input common-mode range −2.0 V to +3.0 V
Input differential range ±5 V
Power supply sensitivity greater than 65 dB
200 ps minimum pulsewidth
5 GHz equivalent input rise time bandwidth
Typical output rise/fall of 160 ps
SPT 9689 replacement

APPLICATIONS

High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers and signal restoration
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Clock drivers
Automatic test equipment

Voltage Comparator

ADCMP565

FUNCTIONAL BLOCK DIAGRAM

NONINVERTING
INPUT

INVERTING
INPUT

LATCH ENABLE
INPUT

ADCMP565

LATCH ENABLE
INPUT

Figure 1.

GENERAL DESCRIPTION

The ADCMP565 is an ultrafast voltage comparator fabricated
on Analog Devices’ proprietary XFCB process. The device
features 300 ps propagation delay with less than 50 ps overdrive
dispersion. Overdrive dispersion, a particularly important
characteristic of high speed comparators, is a measure of the
difference in propagation delay under differing overdrive
conditions.

A fast, high precision differential input stage permits consis­tent propagation delay with a wide variety of signals in the
common-mode range from −2.0 V to +3.0 V. Outputs are
complementary digital signals fully compatible with ECL 10 K
and 10 KH logic families. The outputs provide sufficient drive
current to directly drive transmission lines terminated in 50 Ω
to −2 V. A latch input is included, which permits tracking,
track-and-hold, or sample-and-hold modes of operation.

The ADCMP565 is available in a 20-lead PLCC package.

Q OUTPUT

Q OUTPUT

02820-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADCMP565

TABLE OF CONTENTS

Specifications..................................................................................... 3

Optimizing High Speed Performance ........................................9

Absolute Maximum Ratings............................................................ 5

Thermal Considerations.............................................................. 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Timing Information......................................................................... 8

Application Information.................................................................. 9

Clock Timing Recovery ............................................................... 9

REVISION HISTORY

Revision 0: Initial Version

Comparator Propagation Delay Dispersion ..............................9

Comparator Hysteresis .............................................................. 10

Minimum Input Slew Rate Requirement................................ 10

Typical Application Circuits ..................................................... 11

Typical Performance Characteristics........................................... 12

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

ADCMP565

SPECIFICATIONS

Table 1. ADCMP565 ELECTRICAL CHARACTERISTICS (V

Parameter Symbol Condition Min Typ Max Unit

DC INPUT CHARACTERISTICS (See Note)

Input Common-Mode Range VCM −2.0 +3.0 V
Input Differential Voltage −5 +5 V
Input Offset Voltage VOS −6.0 ±1.5 +6.0 mV
Input Offset Voltage Channel Matching −8 +1 +8 mV
Offset Voltage Tempco DVOS/dT 5.0 µV/°C
Input Bias Current IBC −10.0 +24 +40.0 µA
Input Bias Current Tempco 17 nA/°C
Input Offset Current −5.0 ±0.5 +5.0 µA
Input Capacitance CIN 1.75 pF
Input Resistance, Differential Mode 100 kΩ
Input Resistance, Common Mode 600 kΩ
Open Loop Gain 60 dB
Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +3.0 V 69 dB
Hysteresis ±1.0 mV

LATCH ENABLE CHARACTERISTICS

Latch Enable Common-Mode Range V

−2.0 0 V

LCM

Latch Enable Differential Input Voltage VLD 0.4 2.0 V
Input High Current @ 0.0 V −10 +6 +10 µA
Input Low Current @ −2.0 V −10 +6 +10 µA
Latch Setup Time tS 250 mV overdrive 50 ps
Latch to Output Delay t

PLOH, tPLOL

Latch Pulse Width tPL 250 mV overdrive 150 ps
Latch Hold Time tH 250 mV overdrive 10 ps

OUTPUT CHARACTERISTICS

Output Voltage—High Level VOH ECL 50 Ω to −2.0 V −1.08 −0.81 V
Output Voltage—Low Level VOL ECL 50 Ω to −2.0 V −1.95 −1.61 V
Rise Time tR 20% to 80% 160 ps
Fall Time tF 20% to 80% 145 ps

AC PERFORMANCE

Propagation Delay tPD 1 V overdrive 310 ps
Propagation Delay tPD 20 mV overdrive 375 ps
Propagation Delay Tempco 0.5 ps/°C
Prop Delay Skew—Rising Transition to

±10 ps

Falling Transition
Within Device Propagation Delay Skew—

±10 ps

Channel to Channel
Propagation Delay Dispersion vs.

1 MHz, 1 ns t

Duty Cycle
Propagation Delay Dispersion vs. Overdrive 50 mV to 1.5 V 50 ps
Propagation Delay Dispersion vs. Overdrive 20 mV to 1.5 V 50 ps
Propagation Delay Dispersion vs.

Slew Rate

Propagation Delay Dispersion vs.

1 V swing,

Common-Mode Voltage

Equivalent Input Rise Time Bandwidth BW

= +5.0 V, VEE = −5.2 V, TA = 25°C, unless otherwise noted.)

CC

250 mV overdrive 280 ps

, tF ±10 ps

R

0 V to 1 V swing,

50 ps
20% to 80%,
50 ps and 600 ps t

R

, tF

5 ps

−1.5 V to 2.5 V
0 V to 1 V swing,

CM

5000 MHz
20% to 80%,

, tF

50 ps t

R

Rev. 0 | Page 3 of 16

ADCMP565

Parameter Symbol Condition Min Typ Max Unit

AC PERFORMANCE (continued)

Toggle Rate >50% output swing 5 Gbps
Minimum Pulse Width PW

from 10 ns to

∆t

PD

200 ps

200 ps < ±50 ps

Unit to Unit Propagation Delay Skew ±10 ps

POWER SUPPLY

Positive Supply Current I

Negative Supply Current I

@ +5.0 V 10 13 18 mA

V

CC

@ −5.2 V 60 70 80 mA

V

EE

Positive Supply Voltage VCC Dual 4.75 5.0 5.25 V
Negative Supply Voltage VEE Dual −4.96 −5.2 −5.45 V
Power Dissipation Dual, without load 370 435 490 mW
Power Dissipation Dual, with load 550 mW
Power Supply Sensitivity—VCC PSS

Power Supply Sensitivity—VEE PSS

67 dB

V

CC

83 dB

V

EE

NOTE: Under no circumstances should the input voltages exceed the supply voltages.

Rev. 0 | Page 4 of 16

ADCMP565

ABSOLUTE MAXIMUM RATINGS

Table 2. ADCMP565 Absolute Maximum Ratings

Parameter Rating
Supply

Voltages

Input
Voltages

Output
Temperature

Positive Supply Voltage

to GND)

(V

CC

Negative Supply Voltage

to GND)

(V

EE

Ground Voltage Differential −0.5 V to +0.5 V
Input Common-Mode

Voltage
Differential Input Voltage −7.0 V to +7.0 V
Input Voltage,

Latch Controls
Output Current 30 mA
Operating Temperature,

Ambient
Operating Temperature,

Junction
Storage Temperature Range −55°C to +125°C

−0.5 V to +6.0 V

−6.0 V to +0.5 V

−3.0 V to +4.0 V

to 0.5 V

V

EE

−40°C to +85°C

125°C

Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

THERMAL CONSIDERATIONS

The ADCMP565 20-lead PLCC package option has a θJA
(junction-to-ambient thermal resistance) of 89.4°C/W in
still air.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 16

ADCMP565

G

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

QANCQB

QA

3 2 1 20 19

4

ND

5

LEA

6

NC

LEA LEB

V

EE

ADCMP565

TOP VIEW

7

(Not to Scale)

8

910111213

QB

PIN 1
IDENTIFIER

18

GND

17

LEB

16

NC

15

14

V

CC

–INA

+INANC+INB

NC = NO CONNECT

Figure 2. ADCMP565 Pin Configuration

–INB

02820-0-002

Table 3. ADCMP565 Pin Descriptions

Pin No. Mnemonic Function

1 NC No Connect. Leave pin unconnected.
2 QA

One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 5) for more information.

3

QA

One of two complementary outputs for Channel A.

QA

will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 5) for more information.

4 GND Analog Ground
5 LEA

One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will

reflect the input state just prior to the comparator’s being placed in the latch mode.
in conjunction with LEA.

6 NC No Connect. Leave pin unconnected or attach to GND (internally connected to GND).
7

LEA

One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven

in conjunction with

LEA

.
8 VEE Negative Supply Terminal
9 −INA

Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven
in conjunction with the noninverting A input.

10 +INA

Noninverting analog input of the differential input stage for Channel A. The noninverting A input must

be driven in conjunction with the inverting A input.
11 NC No Connect. Leave pin unconnected.
12 +INB

Noninverting analog input of the differential input stage for Channel B. The noninverting B input must

be driven in conjunction with the inverting B input.
13 −INB

Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven

in conjunction with the noninverting B input.
14 VCC Positive Supply Terminal
15

LEB

One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the

output will track changes at the input of the comparator. In the latch mode (logic high), the output will

reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven

in conjunction with

LEB

.
16 NC No Connect. Leave pin unconnected or attach to GND (internally connected to GND).
17 LEB

One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will

reflect the input state just prior to the comparator’s being placed in the latch mode.
in conjunction with LEB.

LEA

must be driven

LEB

must be driven

Rev. 0 | Page 6 of 16

ADCMP565

Pin No. Mnemonic Function

18 GND Analog Ground
19

20 QB

QB

One of two complementary outputs for Channel B.
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 17) for more information.

One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 17) for more information.

QB

will be at logic low if the analog voltage at the

Rev. 0 | Page 7 of 16

ADCMP565

TIMING INFORMATION

LATCH ENABLE

LATCH ENABLE

50%

t

S

t

V

DIFFERENTIAL

INPUT VOLTAGE

Q OUTPUT

Q OUTPUT

IN

V

OD

t

PDL

t

PDH

Figure 3. System Timing Diagram

The timing diagram in Figure 3 shows the ADCMP565 compare
and latch features. Table 4 describes the terms in the diagram.

Table 4. Timing Descriptions

Symbol Timing Description

t

PDH

Input to output
high delay

Propagation delay measured from
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output low-to-high transition

t

PDL

Input to output
low delay

Propagation delay measured from
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output high-to-low transition

t

PLOH

Latch enable
to output high
delay

Propagation delay measured from
the 50% point of the Latch Enable
signal low-to-high transition to
the 50% point of an output low­to-high transition

t

PLOL

Latch enable
to output low
delay

Propagation delay measured from
the 50% point of the Latch Enable
signal low-to-high transition to
the 50% point of an output high­to-low transition

t

PL

H

± V

V

REF

OS

t

PLOH

50%

t

F

50%

t

PLOL

t

R

02820-0-003

Symbol Timing Description

tH

Minimum
hold time

Minimum time after the negative
transition of the Latch Enable
signal that the input signal must
remain unchanged to be acquired
and held at the outputs

tPL

tS

Minimum
latch enable
pulse width

Minimum
setup time

Minimum time that the Latch
Enable signal must be high to
acquire an input signal change

Minimum time before the
negative transition of the Latch
Enable signal that an input signal
change must be present to be
acquired and held at the outputs

tR

Output rise
time

Amount of time required to
transition from a low to a high
output as measured at the 20%
and 80% points

tF

Output fall
time

Amount of time required to
transition from a high to a low
output as measured at the 20%
and 80% points

VOD

Voltage
overdrive

Difference between the
differential input and reference
input voltages

Rev. 0 | Page 8 of 16

ADCMP565

APPLICATION INFORMATION

The ADCMP565 comparators are very high speed devices.
Consequently, high speed design techniques must be employed
to achieve the best performance. The most critical aspect of any
ADCMP565 design is the use of a low impedance ground plane.
A ground plane, as part of a multilayer board, is recommended
for proper high speed performance. Using a continuous con­ductive plane over the surface of the circuit board can create
this, allowing breaks in the plane only for necessary signal
paths. The ground plane provides a low inductance ground,
eliminating any potential differences at different ground points
throughout the circuit board caused by ground bounce. A
proper ground plane also minimizes the effects of stray
capacitance on the circuit board.

It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 µF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors will reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close as possible from the
power supply pins on the ADCMP565 to ground. These
capacitors act as a charge reservoir for the device during high
frequency switching.

The LATCH ENABLE input is active low (latched). If the
latching function is not used, the LATCH ENABLE input
should be grounded (ground is an ECL logic high), and the
complementary input,

V. This will disable the latching function.

−2.0

Occasionally, one of the two comparator stages within the
ADCMP565 will not be used. The inputs of the unused com­parator should not be allowed to float. The high internal gain
may cause the output to oscillate (possibly affecting the
comparator that is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two
inputs are at least one diode drop apart, while also appropriately
connecting the LATCH ENABLE and
as described above.

The best performance is achieved with the use of proper ECL
terminations. The open emitter outputs of the ADCMP565 are
designed to be terminated through 50 Ω resistors to −2.0 V, or
any other equivalent ECL termination. If a −2.0 V supply is not
available, an 82 Ω resistor to ground and a 130 Ω resistor to

−5.2 V provide a suitable equivalent. If high speed ECL signals
must be routed more than a centimeter, microstrip or stripline
techniques may be required to ensure proper transition times
and prevent output ringing.

LATCH ENABLE

, should be tied to

LATCH ENABLE

inputs

CLOCK TIMING RECOVERY

Comparators are often used in digital systems to recover clock
timing signals. High speed square waves transmitted over a
distance, even tens of centimeters, can become distorted due to
stray capacitance and inductance. Poor layout or improper
termination can also cause reflections on the transmission line,
further distorting the signal waveform. A high speed com­parator can be used to recover the distorted waveform while
maintaining a minimum of delay.

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator amplifier, proper design and
layout techniques should be used to ensure optimal perform­ance from the ADCMP565. The performance limits of high
speed circuitry can easily be a result of stray capacitance,
improper ground impedance, or other layout issues.

Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
ADCMP565. Source resistance in combination with equivalent
input capacitance could cause a lagged response at the input,
thus delaying the output. The input capacitance of the
ADCMP565 in combination with stray capacitance from an
input pin to ground could result in several picofarads of
equivalent capacitance. A combination of 3 kΩ source resistance
and 5 pF of input capacitance yields a time constant of 15 ns,
which is significantly slower than the sub 500 ps capability of
the ADCMP565. Source impedances should be significantly less
than 100 Ω for best performance.

Sockets should be avoided due to stray capacitance and induc­tance. If proper high speed techniques are used, the ADCMP565
should be free from oscillation when the comparator input
signal passes through the switching threshold.

COMPARATOR PROPAGATION DELAY DISPERSION

The ADCMP565 has been specifically designed to reduce
propagation delay dispersion over an input overdrive range of
100 mV to 1 V. Propagation delay overdrive dispersion is the
change in propagation delay that results from a change in the
degree of overdrive (how far the switching point is exceeded by
the input). The overall result is a higher degree of timing
accuracy since the ADCMP565 is far less sensitive to input
variations than most comparator designs.

Propagation delay dispersion is a specification that is important
in critical timing applications such as ATE, bench instruments,
and nuclear instrumentation. Overdrive dispersion is defined

Rev. 0 | Page 9 of 16

ADCMP565

as the variation in propagation delay as the input overdrive
conditions are changed (Figure 4). For the ADCMP565,
overdrive dispersion is typically 50 ps as the overdrive is
changed from 100 mV to 1 V. This specification applies for
both positive and negative overdrive since the ADCMP565 has
equal delays for positive and negative going inputs.

The 50 ps propagation delay dispersion of the ADCMP565
offers considerable improvement of the 100 ps dispersion of
other similar series comparators.

1.5V OVERDRIVE

INPUT VOLTAGE

20mV OVERDRIVE

V

± V

REF

OS

DISPERSION

Q OUTPUT

02820-0-004

Figure 4. Propagation Delay Dispersion

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often useful in a
noisy environment or where it is not desirable for the com­parator to toggle between states when the input signal is at the
switching threshold. The transfer function for a comparator
with hysteresis is shown in Figure 5. If the input voltage
approaches the threshold from the negative direction, the
comparator will switch from a 0 to a 1 when the input crosses

/2. The new switching threshold becomes −VH/2. The

+V

H

comparator will remain in a 1 state until the threshold −V
crossed coming from the positive direction. In this manner,
noise centered on 0 V input will not cause the comparator to
switch states unless it exceeds the region bounded by ±V

Positive feedback from the output to the input is often used to
produce hysteresis in a comparator (Figure 9). The major
problem with this approach is that the amount of hysteresis
varies with the output logic levels, resulting in a hysteresis that
is not symmetrical around zero.

Another method to implement hysteresis is generated by
introducing a differential voltage between the LATCH ENABLE

LATCH ENABLE

and

inputs (Figure 10). Hysteresis generated
in this manner is independent of output swing and is symmetri­cal around zero. The variation of hysteresis with input voltage is
shown in Figure 6.

H

H

/2.

/2 is

0V

OUTPUT

+V

H

2

INPUT

1

02820-0-005

–V

H

2

0

Figure 5. Comparator Hysteresis Transfer Function

60

50

40

30

20

HYSTERESIS (mV)

10

0

–20 20

–15 –10 –5 0 5 10 15

Figure 6. Comparator Hysteresis Transfer Function

∆ LATCH = LE – LEB (mV)

02820-0-006

Using Latch Enable Input

MINIMUM INPUT SLEW RATE REQUIREMENT

As for all high speed comparators, a minimum slew rate must
be met to ensure that the device does not oscillate when the
input crosses the threshold. This oscillation is due in part to the
high input bandwidth of the comparator and the parasitics of
the package. Analog Devices recommends a slew rate of 5 V/µs
or faster to ensure a clean output transition. If slew rates less
than 5 V/µs are used, then hysteresis should be added to reduce
the oscillation.

Rev. 0 | Page 10 of 16

ADCMP565

V

V

TYPICAL APPLICATION CIRCUITS

V

IN

REF

Figure 7. High Speed Sampling Circuits

+V

REF

V

IN

–V

REF

Figure 8. High Speed Window Comparator

ADCMP565

LATCH
ENABLE
INPUTS

ALL RESISTORS 50Ω

ADCMP565

ADCMP565

LATCH
ENABLE
INPUTS

ALL RESISTORS 50Ω

–2.0V

–2.0V

OUTPUTS

02820-0-007

OUTPUTS

02820-0-008

V

IN

HYSTERESIS

OLTAGE

ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED

Figure 10. Hysteresis Using Latch Enable Input

ADCMP565

450Ω

–2.0V

OUTPUTS

02820-0-010

30Ω 50Ω

V

IN

Figure 11. How to Interface an ECL Output to an

ADCMP565

–5.2V

30Ω

127Ω127Ω

50Ω

02820-0-011

Instrument with a 50 Ω to Ground Input

V

IN

V

REF

Figure 9. Hysteresis Using Positive Feedback

ADCMP565

R1 R2

ALL RESISTORS 50Ω

–2.0V

OUTPUTS

02820-0-009

Rev. 0 | Page 11 of 16

ADCMP565

TYPICAL PERFORMANCE CHARACTERISTICS

(V

= +5.0 V, VEE = −5.2 V, TA = 25°C, unless otherwise noted.)

CC

25

25.0

20

15

10

INPUT BIAS CURRENT (µA)

5

0

–2.5 0.5 3.5

–1.5 –0.5 1.5 2.5

NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0.5V)

Figure 12. Input Bias Current vs. Input Voltage

2.0

1.9

1.8

1.7

1.6

1.5

OFFSET VOLTAGE (mV)

1.4

1.3

1.2
–20 0 20 40 60 80

–40

TEMPERATURE (°C)

Figure 13. Input Offset Voltage vs. Temperature

210

205

200

195

190

185

TIME (ps)

180

175

170

165

160

–30 –20 –10 0 10 20 30 40 50 60 70 80

–40 90

TEMPERATURE (°C)

Figure 14. Rise Time vs. Temperature

02820-0-020

02820-0-022

02820-0-016

24.5

24.0

23.5

23.0

INPUT BIAS CURRENT (µA)

22.5

22.0
–40

–20 0 20 40 60 80

Figure 15. Input Bias Current vs. Temperature

TEMPERATURE (°C)

02820-0-021

60

50

40

30

20

HYSTERESIS (mV)

10

0

–20 20

–15 –10 –5 0 5 10 15

Figure 16. Hysteresis vs. ∆Latch

∆

LATCH = LE – LEB (mV)

02820-0-017

210

205

200

195

190

185

TIME (ps)

180

175

170

165

160

–30 –20 –10 0 10 20 30 40 50 60 70 80

–40 90

Figure 17. Fall Time vs. Temperature

TEMPERATURE (°C)

02820-0-019

Rev. 0 | Page 12 of 16

ADCMP565

315

310

305

300

295

290

PROPAGATION DELAY (ps)

285

280

–30 –20 –10 0 10 20 30 40 50 60 70 80

–40 90

TEMPERATURE (°C)

02820-0-014

Figure 18. Propagation Delay vs. Temperature

35

30

25

20

15

10

PROPAGATION DELAY ERROR (ps)

5

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4

0 1.6

Figure 19. Propagation Delay Error vs. Overdrive Voltage

OVERDRIVE VOLTAGE

02820-0-013

–0.8

FALL

–1.0

RISE

304

303

302

301

300

299

298

297

PROPAGATION DELAY (ps)

296

295

294

–2 3

–1 0 1 2

INPUT COMMON-MODE VOLTAGE (V)

Figure 21. Propagation Delay vs. Common-Mode Voltage

0

–5

–10

–15

–20

–25

–30

PROPOGATION DELAY ERROR (ps)

–35

–40

0.15

2.15 4.15 6.15 8.15
PULSEWIDTH (ns)

Figure 22. Propagation Delay Error vs. Pulsewidth

02820-0-015

02820-0-023

–1.2

–1.4

–1.6

OUTPUT RISE AND FALL (V)

–1.8

–2.0

0.5 1.5

0.7 0.9 1.1 1.3
TIME (ns)

Figure 20. Rise and Fall of Outputs vs. Time

02820-0-018

Rev. 0 | Page 13 of 16

ADCMP565

OUTLINE DIMENSIONS

0.048 (1.21)

0.042 (1.07)

0.048 (1.21)

0.042 (1.07)

3

4

TOP VIEW

(PINSDOWN)

8

0.020
(0.50)

9

0.356 (9.04)

R

0.350 (8.89)

0.395 (10.02)

0.385 (9.78)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.056 (1.42)

0.042 (1.07)

19

18

0.050
(1.27)
BSC

14

13

SQ

SQ

COMPLIANT TO JEDEC STANDARDS MO-047AA

0.180 (4.57)

0.165 (4.19)

0.120 (3.04)

0.090 (2.29)

0.20 (0.51)
MIN

0.021 (0.53)

0.013 (0.33)

0.032 (0.81)

0.026 (0.66)

0.025 (0.64) MIN

Figure 23. 20-Lead Plastic Leaded Chip Carrier [PLCC]

(P-20)

Dimensions shown in inches and (millimeters)

0.330 (8.38)

0.290 (7.37)

0.020 (0.50)
R

BOTTOM

VIEW

(PINSUP)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADCMP565BP −40°C to +85°C 20-Lead PLCC P-20

Rev. 0 | Page 14 of 16

ADCMP565

Notes

Rev. 0 | Page 15 of 16

ADCMP565

Notes

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C02820–0–10/03(0)

Rev. 0 | Page 16 of 16