Datasheet ADCMP564 Datasheet (ANALOG DEVICES)

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Dual, High Speed ECL Comparators

FEATURES

Differential ECL-compatible outputs 700 ps propagation delay input to output 75 ps propagation delay dispersion Input common-mode range: –2.0 V to +3.0 V Robust input protection Differential latch control Internal latch pull-up resistors Power supply rejection greater than 85 dB 700 ps minimum pulse width

1.5 GHz equivalent input rise time bandwidth Typical output rise/fall time of 500 ps ESD protection > 4kV HBM, >200V MM Programmable hysteresis

APPLICATIONS

Automatic test equipment High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Hand-held test instruments Zero crossing detectors Line receivers and signal restoration Clock drivers

GENERAL DESCRIPTION

The ADCMP563/ADCMP564 are high speed comparators fabricated on Analog Devices’ proprietary XFCB process. The devices feature a 700 ps propagation delay with less than 75 ps overdrive dispersion. Dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of high speed comparators. A separate programmable hysteresis pin is available on the ADCMP564.

A differential input stage permits consistent propagation delay wi

th a wide variety of signals in the common-mode range from

−2.0 V to +3.0 V. Outputs are complementary digital signals

ADCMP563/ADCMP564

FUNCTIONAL BLOCK DIAGRAM

HYS*

NONINVERTING

INPUT

ADCMP563/

INVERTING

INPUT

LATCH ENABLE INPUT

ADCMP564

LATCH ENABLE INPUT

*ADCMP564 ONLY

Figure 1.

GND

04650-0-002

GND

–INA +INA

HYS

QA QA

LEA LEA

QA QA

GND

LEA LEA

V –INA +INA

ADCMP563

BRQ

TOP VIEW

(Not to Scale)

GND

LEB

–INB

+INB

Figure 2. ADCMP563 16-Lead QSOP Figure 3. ADCMP564 20-Lead QSOP

QA QA QB QB

16 15 14 13

GND

LEA

PIN1

ADCMP563

BCP

TOP VIEW

(Not to Scale)

–INA +INA +INB –INB

8765

Figure 4. ADCMP563 16-Lead LFCSP

that are fully compatible with ECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to −2 V. A latch input, which is included, permits tracking, track-and-hold, or sample-and-hold modes of operation. The latch input pins contain internal pull-ups that set the latch in tracking mode when left open.

The ADCMP563/ADCMP564 are specified over the industrial

emperature range (−40°C to +85°C).

ADCMP564

BRQ

TOP VIEW

(Not to Scale)

GND

LEB

Q OUTPUT

111151-0-026

04650-0-001

GND

LEB

–INB

+INB

HYSB

04650-0-012

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Considerations.............................................................. 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 8

Timing Information ....................................................................... 10

Application Information................................................................ 11

REVISION HISTORY

5/05—Rev. A to Rev. B

Added 16-Lead LFCSP.......................................................Universal

Changes to Applications .................................................................. 1

Changes to Table 1............................................................................ 3

Changes to Optimizing High Speed Performance Section....... 11

Changes to Comparator Hysteresis Section................................ 12

Changes to Minimum Input Slew Rate Requirement Section.. 12

Changes to Ordering Guide.......................................................... 14

Clock Timing Recovery............................................................. 11

Optimizing High Speed Performance ..................................... 11

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 12

Minimum Input Slew Rate Requirement ................................ 12

Typical Application C i r c uits ......................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

7/04—Rev. 0 to Rev. A

hanges to Specification Table ....................................................... 4

Changes to Figure 14........................................................................ 9

Changes to Figure 21...................................................................... 12

Changes to Figure 23...................................................................... 13

4/04—Revision 0: Initial Version

Rev. B | Page 2 of 16

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SPECIFICATIONS

VCC = +5.0 V, VEE = −5.2 V, TA = −40°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.

Table 1. Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Input Voltage Range −2.0 3.0 V Input Differential Voltage −5 +5 V Input Offset Voltage V

Input Offset Voltage Channel Matching ±2.0 mV Offset Voltage Temperature Coefficient ∆VOS/d Input Bias Current I

Input Bias Current Temperature Coefficient 0.5 nA/°C Input Offset Current ±1.0 μA Input Capacitance C

Input Resistance, Differential Mode 750 kΩ Input Resistance, Common Mode 1800 kΩ Active Gain A

Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +3.0 V 80 dB Hysteresis R

LATCH ENABLE CHARACTERISTICS

Latch Enable Voltage Range −2.0 0 V Latch Enable Differential Input Voltage 0.4 2.0 V Latch Enable Input High Current @ 0.0 V −300 +300 μA Latch Enable Input Low Current @ −2.0 V −300 +300 μA LE Voltage, Open Latch inputs not connected −0.2 0 +0.1 V LE Voltage, Open Latch Setup Time t Latch Hold Time t Latch to Output Delay

Latch Minimum Pulse Width t

Latch inputs not connected −2.8 −2.6 −2.4 V

PLOH

PLOL

DC OUTPUT CHARACTERISTICS

Output Voltage—High Level V Output Voltage—Low Level V Rise Time t Fall Time t

AC PERFORMANCE

Propagation Delay t

V Propagation Delay Temperature Coefficient ∆tPD /d Prop Delay Skew—Rising Transition to Falling

Transition

Within Device Propagation Delay Skew—

Channel-to-Channel Overdrive Dispersion 20 mV ≤ VOD ≤ 100 mV 75 ps 100 mV ≤ VOD ≤ 1.5 V 75 ps Slew Rate Dispersion 0.4 V/ns ≤ SR ≤ 1.33 V/ns 50 ps Pulse Width Dispersion 750ps ≤ PW ≤ 10ns 25 ps Duty Cycle Dispersion 33 MHz, 1 V/ns, 0.5 V 10 ps Common-Mode Voltage Dispersion 1 V swing, −1.5 V ≤ VCM ≤ +2.5 V 10 ps

VCM = 0 V −10.0 ±2.0 +10.0 mV

2.0 μV/°C

@ −IN = −2 V, +IN = +3 V −10.0 ±3 +10.0 μA

0.75 pF

63 dB

= ∞ ±1.0 mV

HYS

VOD = 250 mV 200 ps VOD = 250 mV 200 ps VOD = 250 mV 500 ps

VOD = 250 mV 500 ps

ECL 50 Ω to −2.0 V −1.15 −0.81 V ECL 50 Ω to −2.0 V −1.95 −1.54 V 10% to 90% 530 ps 10% to 90% 450 ps

VOD = 1 V 700 ps

= 20 mV 830 ps

VOD = 1 V 0.25 ps/°C

= 1 V 50 ps

Rev. B | Page 3 of 16

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ADCMP563/ADCMP564

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Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE (Continued)

Equivalent Input Rise Time Bandwidth Maximum Toggle Rate >50% output swing, 50% duty cycle 800 MHz Minimum Pulse Width PW RMS Random Jitter

Unit to Unit Propagation Delay Skew 100 ps

POWER SUPPLY

Positive Supply Current I Negative Supply Current I Positive Supply Voltage V Negative Supply Voltage V Power Dissipation P Dual, with load 150 180 230 mW DC Power Supply Rejection Ratio—V DC Power Supply Rejection Ratio—V

HYSTERESIS (ADCMP564 Only)

Hysteresis R R Hysteresis Pin Bias Voltage Referred to AGND −1 V Hysteresis Pin Series Resistance 3 kΩ

Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/√(tr

20/80 input transition time applied to the comparator and tr is the effective transition time, as digitized by the comparator input.

MIN

0 V to 1 V swing, 2 V/ns 1500 MHz

ΔtPD < 25 ps 700 ps

= 400 mV, 1.3 V/ns, 312 MHz,

1.0 ps

50% duty cycle

VCC

VEE

PSRR PSRR

COMP

@ +5.0 V 2 3.2 5 mA @ −5.2 V 10 19 25 mA Dual 4.75 5.0 5.25 V Dual −4.96 −5.2 −5.45 V Dual, without load 90 120 150 mW

85 dB

VCC

85 dB

VEE

= 23.5 kΩ 20 mV

HYS

= 9.0 kΩ 70 mV

HYS

– tr

COMP

), where tr is the

Rev. B | Page 4 of 16

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltages

Positive Supply Voltage (VCC to GND) −0.5 V to +6.0 V Negative Supply Voltage (VEE to GND) −6.0 V to +0.5 V Ground Voltage Differential −0.5 V to +0.5 V

Input Voltages

Input Common-Mode Voltage −3.0 V to +4.0 V Differential Input Voltage −7.0 V to +7.0 V Input Voltage, Latch Controls VEE to +0.5 V

Output

Output Current 30 mA

Temperature

Operating Temperature, Ambient −40°C to +85°C Operating Temperature, Junction 125°C Storage Temperature Range −65°C to +150°C

tresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CONSIDERATIONS

The ADCMP563 QSOP 16-lead package option has a θJA (junction-to-ambient thermal resistance) of 104°C/W in still air.

The ADCMP563 LFCSP 16-lead package option has a θ (junction-to-ambient thermal resistance) of 70°C/W in still air.

The ADCMP564 QSOP 20-lead package option has a θ (junction-to-ambient thermal resistance) of 80°C/W in still air.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. B | Page 5 of 16

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

QA QA

GND

LEA LEA

V –INA +INA

ADCMP563

BRQ

TOP VIEW

(Not to Scale)

GND

LEB LEB

–INB +INB

Figure 5. ADCMP563 16-Lead QSOP

in Configuration

04650-0-002

ADCMP564

GND

TOP VIEW

(Not to Scale)

BRQ

LEA LEA

–INA +INA

HYS

Figure 6. ADCMP564 20-Lead QSOP

in Configuration

Table 3. Pin Function Descriptions

Pin No.

ADCMP563 16-Lead QSOP

ADCMP563 16-Lead LFCSP

ADCMP564 20-Lead QSOP

Mnemonic

Function

1 GND Analog Ground. 1 15 2 QA

One of Two Complementary Outputs for Channel A. QA is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of the LEA pin for more information.

2 16 3

One of Two Complementary Outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage

at the inverting input (provided the comparator is in compare mode). See

the description of the LEA pin for more information. 3 1 4 GND Analog Ground. 4 2 5 LEA

One of Two Complementary Inputs for Channel A Latch Enable. In compare

mode (logic high), the output tracks change at the input of the comparator.

In latch mode (logic low), the output reflects the input state just prior to the

comparator being placed in the latch mode. LEA

conjunction with LEA. If left unconnected, the comparator defaults to

compare mode. 5 3 6

LEA One of Two Complementary Inputs for Channel A Latch Enable. In compare

mode (logic low), the output tracks change at the input of the comparator.

In latch mode (logic high), the output reflects the input state just prior to the

comparator being placed in the latch mode. LEA must be driven in

conjunction with

compare mode. 6 4 7 V

7 5 8 −INA

Negative Supply Terminal.

Inverting Analog Input of the Differential Input Stage for Channel A. The

Inverting A input must be driven in conjunction with the Noninverting A input. 8 6 9 +INA

Noninverting Analog Input of the Differential Input Stage for Channel A. The

Noninverting A input must be driven in conjunction with the Inverting A input. 10 HYSA 11 HYSB 9 7 12 +INB

Programmable Hysteresis Input.

Noninverting Analog Input of the Differential Input Stage for Channel B. The

Noninverting B input must be driven in conjunction with the Inverting B input. 10 8 13 −INB

Inverting Analog Input of the Differential Input Stage for Channel B. The

Inverting B input must be driven in conjunction with the Noninverting B input. 11 9 14 V

Positive Supply Terminal.

GND

LEB

–INB

+INB

HYSB

04650-0-012

. If left unconnected, the comparator defaults to

LEA

QA QA QB QB

16 15 14 13

GND

LEA

PIN1

ADCMP563

BCP

TOP VIEW

(Not to Scale)

–INA +INA +INB –INB

8765

Figure 7. ADCMP563 16-Lead LFCSP

Pin Configuration

must be driven in

GND

LEB

111151-0-026

Rev. B | Page 6 of 16

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ADCMP563/ADCMP564

www.BDTIC.com/ADI

Pin No.

ADCMP563 16-Lead QSOP

12 10 15

13 11 16 LEB

14 12 17 GND Analog Ground. 15 13 18

16 14 19 QB

20 GND Analog Ground.

ADCMP563 16-Lead LFCSP

ADCMP564 20-Lead QSOP

Mnemonic

LEB

Function

One of Two Complementary Inputs for Channel B Latch Enable. In compare mode (logic low), the output tracks change at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the comparator being placed in the latch mode. LEB must be driven in conjunction with

One of Two Complementary Inputs for Channe mode (logic high), the output tracks change at the input of the comparator. In latch mode (logic low), the output reflects the input state just prior to the comparator being placed in the latch mode. LEB with LEB. If left unconnected, the comparator defaults to compare mode.

One of Two Complementary Outputs for Channel B. QB is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See

the description of the LEB pin for more information. One of Two Complementary Outputs for Channel B. QB i

analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of the LEB pin for more information.

. If left unconnected, the comparator defaults to compare mode.

LEB

l B Latch Enable. In compare

must be driven in conjunction

s logic high if the

Rev. B | Page 7 of 16

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TYPICAL PERFORMANCE CHARACTERISTICS

VCC = 3.3 V, TA = 25°C, unless otherwise noted.

3.0

2.5

2.0

1.5

1.0

0.5

INPUT BIAS CURRENT (μA)

–0.5

–1.0

–2.5 –1.5 –0.5 0.5 1.5 2.5 3.5

NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0V)

Figure 8. Input Bias Current vs. Input Voltage

2.00

1.95

1.90

1.85

1.80

1.75

1.70

1.65

OFFSET VOLTAGE (mV)

1.60

1.55

1.50 –40–200 20406080

TEMPERATURE (°C)

Figure 9. Input Offset Voltage vs. Temperature

550

545

540

535

530

525

TIME (ps)

520

515

510

505

500

–40–30–20–100 102030405060708090

TEMPERATURE (°C)

Figure 10. Rise Time vs. Temperature

04650-0-013

04650-0-014

04650-0-015

2.80

2.78

2.76

2.74

2.72

2.70

2.68

(+IN = 3V, –IN = 0V)

2.66

2.64

+IN INPUT BIAS CURRENT (μA)

2.62

2.60 –40–200 20406080

TEMPERATURE (°C)

Figure 11. Input Bias Current vs. Temperature

–0.8

–1.0

–1.2

–1.4

–1.6

OUTPUT RISE AND FALL (V)

–1.8

–2.0

0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

TIME (ns)

Figure 12. Rise and Fall of Outputs vs. Time

475

470

465

460

455

450

TIME (ps)

445

440

435

430

425

–40–30–20–100 102030405060708090

TEMPERATURE (°C)

Figure 13. Fall Time vs. Temperature

04650-0-016

04650-0-017

04650-0-018

Rev. B | Page 8 of 16

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ADCMP563/ADCMP564

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720

705

715

710

705

700

695

690

PROPAGATION DELAY (ps)

685

680

–40–30–20–100 102030405060708090

TEMPERATURE (°C)

Figure 14. Propagation Delay vs. Temperature

140

120

100

04650-0-019

704

703

702

701

700

699

PROPAGATION DELAY (ps)

698

697

–2–10123

INPUT COMMON-MODE VOLTAGE (V)

Figure 17. Propagation Delay vs. Common-Mode Voltage

04650-0-022

PROPAGATION DELAY ERROR (ps)

0 1.61.41.21.00.80.60.40.2

OVERDRIVE VOLTAGE (V)

Figure 15. Propagation Delay Error vs. Overdrive Voltage

160

140

120

100

PROGRAMMED HYSTERESIS (mV)

50 010203040

(kΩ)

HYS

Figure 16. Comparator Hysteresis vs. R

PROPAGATION DELAY ERROR (ps)

04650-0-020

–5

0.7 1.7 2.7 3.7 4.7 5.7 6.7 7.7 8.7 9.7 PULSE WIDTH (ns)

04650-0-023

Figure 18. Propagation Delay Error vs. Pulse Width

160

140

120

100

PROGRAMMED HYSTERESIS (mV)

04650-0-021

HYS

0 50 100 150

Figure 19. Comparator Hysteresis vs. I

HYS

(μA)

HYS

04650-0-024

Rev. B | Page 9 of 16

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TIMING INFORMATION

LATCH ENABLE

DIFFERENTIAL

INPUT VOLTAGE

50%

± V

REF

Q OUTPUT

PDL

PDH

PLOH

PLOL

50%

Figure 20. System Timing Diagram

Figure 20 shows the compare and latch features of the ADCMP563. Table 4 describes the terms in the diagram.

Table 4. Timing Descriptions

Symbol Timing Description

PDH

Input-to-Output High Delay

Propagation delay measured from the time the i

nput signal crosses the reference (± the

input offset voltage) to the 50% point of an output low-to-high transition.

PDL

Input-to-Output Low Delay

Propagation delay measured from the time the i

nput signal crosses the reference (± the

input offset voltage) to the 50% point of an output high-to-low transition.

PLOH

Latch Enable to Output High Delay

Propagation delay measured from the 50% point of the latch enable sig transition to the 50% point of an output low-to-high transition.

PLOL

Latch Enable to Output Low Delay

Propagation delay measured from the 50% point of the latch enable sig transition to the 50% point of an output high-to-low transition.

Minimum Hold Time

Minimum time after the negative transition of the latch enable must remain unchanged to be acquired and held at the outputs.

Minimum Latch Enable Pulse Width Minimum time the latch enable signal must be high to acquire an input signal change. Minimum Setup Time

Output Rise Time

Output Fall Time

Minimum time before the negative transition of the latch enable signal that an input

hange must be present to be acquired and held at the outputs.

signal c Amount of time required to transition from a low to a high output as measured at the

20% and 80% p Amount of time required to transition from a hig

oints.

h to a low output as measured at the

20% and 80% points.

Voltage Overdrive Difference between the differential input and reference input voltages.

04650-0-003

nal low-to-high

signal that the input signal

Rev. B | Page 10 of 16

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ADCMP563/ADCMP564

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APPLICATION INFORMATION

The ADCMP563/ADCMP564 comparators are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP563/ADCMP564 design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance. Using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board.

It is also important to provide bypass capacitors for the power su

pply in a high speed application. A 1 μF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close as possible from the power supply pins on the ADCMP563/ADCMP564 to ground. These capacitors act as a charge reservoir for the device during high frequency switching.

The LATCH ENABLE input is active low (latched). If the

atching function is not used, the LATCH ENABLE input can be

l left open or grounded (ground is an ECL logic high). The complementary input,

tied to −2.0 V. Leaving the latch inputs unconnected or providing the proper voltages disables the latching function.

Occasionally, one of the two comparator stages within the AD

CMP563/ADCMP564 is not used. The inputs of the unused comparator should not be allowed to float. The high internal gain can cause the output to oscillate (possibly affecting the comparator that is being used), unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the LATCH ENABLE and LATCH ENABLE

The best performance is achieved with the use of proper ECL

erminations. The open emitter outputs of the ADCMP563/

t ADCMP564 are designed to be terminated through 50 Ω resistors to −2.0 V, or any other equivalent ECL termination. If a

−2.0 V supply is not available, an 82 Ω resistor to ground and a 130 Ω resistor to −5.2 V provide a suitable equivalent. If high speed ECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing.

LATCH ENABLE

inputs as described previously.

, can be left open or

CLOCK TIMING RECOVERY

Comparators are often used in digital systems to recover clock timing signals. High speed square waves transmitted over a distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay.

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal performance from the ADCMP563/ADCMP564. The performance limits of high speed circuitry all too often are the result of stray capacitance, improper ground impedance, or other layout issues.

Minimizing resistance from source to the input is an important co

nsideration in maximizing the high speed operation of the ADCMP563/ADCMP564. Source resistance, in combination with equivalent input capacitance, could cause a lagged response at the input, thus delaying the output. The input capacitance of the ADCMP563/ADCMP564, in combination with stray capacitance from an input pin to ground, could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF input capacitance yields a time constant of 15 ns, which is significantly slower than the 750 ps capability of the ADCMP563/ADCMP564. Source impedances should be significantly less than 100 Ω for best performance.

Sockets should be avoided due to stray capacitance and induc-

ance. If proper high speed techniques are used, the devices

t should be free from oscillation when the comparator input signal passes through the switching threshold.

COMPARATOR PROPAGATION DELAY DISPERSION

The ADCMP563/ADCMP564 have been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1.5 V. Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy because the ADCMP563/ADCMP564 are far less sensitive to input variations than most comparator designs.

Rev. B | Page 11 of 16

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Propagation delay dispersion is important in critical timing applications such as ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed ( dr from 100 mV to 1.5 V. This specification applies for both positive and negative overdrive because the ADCMP563 and the ADCMP564 have equal delays for positive and negative going inputs.

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often useful in a noisy environment, or where it is not desirable for the comparator to toggle between states when the input signal is at the switching threshold. The transfer function for a comparator with hysteresis is shown in a

pproaches the threshold from the negative direction, the comparator switches from 0 to 1 when the input crosses +V The new switching threshold becomes −V remains in a 1 state until the threshold −V coming from the positive direction. In this manner, noise centered on 0 V input does not cause the comparator to switch states unless it exceeds the region bounded by ±V

The customary technique for introducing hysteresis into a

omparator uses positive feedback from the output back to the

c input. A limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that can be load dependent and is not symmetrical about the threshold. The external feedback network can also introduce significant parasitics, which reduce high speed performance and can induce oscillation in some cases.

In the ADCMP564, hysteresis is generated through the p

rogrammable hysteresis pin. A resistor from the HYS pin to GND creates a current into the part that is used to generate hysteresis. Hysteresis generated in this manner is independent of output swing and is symmetrical around the trip point. The hysteresis vs. resistance curve is shown in

Figure 21). For the ADCMP563/ADCMP564, over-

ive dispersion is typically 75 ps as the overdrive is changed

1.5V OVERDRIVE

INPUT VOLTAGE

20mV OVERDRIVE

± V

REF

DISPERSION

Q OUTPUT

Figure 21. Propagation Delay Dispersion

03633-0-004

Figure 22. If the input voltage

/2. The comparator

/2 is crossed while

/2.

Figure 23.

/2.

A current may be sourced into the HYS pin. The pin is biased

pproximately 1 V below AGND and has a 3 kΩ series

a resistance. The relationship between the current applied to the HYS pin and the resulting hysteresis is shown in Figure 19.

–V

Figure 22. Comparator Hysteresis Transfer Function

160

140

120

100

PROGRAMMED HYSTERESIS (mV)

50 010203040

Figure 23. Comparator Hysteresis vs. R

OUTPUT

HYS

INPUT

04650-0-005

04650-0-021

(kΩ)

HYS

MINIMUM INPUT SLEW RATE REQUIREMENT

As for all high speed comparators, a minimum slew rate must be met to ensure that the device does not oscillate as the input crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the parasitics of the package. ADI recommends a slew rate of 1 V/μs or faster to ensure a clean output transition. If slew rates less than 1 V/μs are used, hysteresis can be added to prevent the oscillation.

Rev. B | Page 12 of 16

Page 13

ADCMP563/ADCMP564

www.BDTIC.com/ADI

TYPICAL APPLICATION CIRCUITS

REF

ADCMP563/

ADCMP564

LATCH

ENABLE

INPUTS

ALL RESISTORS 50Ω

–2.0V

Figure 24. High Speed Sampling Circuits

REF

–V

REF

LL RESISTORS 50Ω UNLESS OTHERWISE NOTED

ADCMP563/

ADCMP564

ADCMP563/

ADCMP564

LATCH

ENABLE

INPUTS

–2V

Figure 25. High Speed Window Comparator

OUTPUTS

046500-007

04650-0-008

REF

ALL RESISTORS 50Ω, UNLESS OTHERWISE NOTED

ADCMP564

HYS

0Ω TO 80kΩ

OUTPUTS

–2.0V

Figure 26. Adding Hysteresis Using the HYS Control Pin

30Ω 50Ω

ADCMP563/

ADCMP564

–5.2V

30Ω

127Ω127Ω

50Ω

Figure 27. One Method to Interface an ECL Output to an

nt with a 50 Ω to Ground Input

Instrume

04650-0-009

04650-0-011

Rev. B | Page 13 of 16

Page 14

ADCMP563/ADCMP564

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.193 BSC

0.341 BSC

0.065

0.049

0.010

0.004

COPLANARITY

0.004

Figure 28. 16-Lead Shrink Small Outline Package [QSOP]

0.012

0.008

0.154 BSC

0.069

0.053

SEATING PLANE

Q-16)

0.236 BSC

0.010

0.006

PIN 1

0.025 BSC

COMPLIANT TO JEDEC STANDARDS MO-137-AB

Dimensions shown in inches

3.00

BSC SQ

PIN 1

INDICATO

TOP

VIEW

12° MAX

0.90

0.85

0.80

SEATING

PLANE

0.30

0.23

0.18

Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

8° 0°

0.050

0.016

0.010

0.004

COPLANARITY

0.60 MAX

0.45

2.75

BSC SQ

0.50

BSC

0.80 MAX

1.50 REF

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

COMPLIANT

JEDEC STANDARDS MO-220-VEED-2

EXCEPT FOR EXPOSED PAD DIMENSION.

mm × 3 mm Body, Very Thin Quad

(CP-16-3)

Dimensions shown in millimeters

20 11

PIN 1

0.065

0.049

0.025 BSC

0.004 COMPLIANT TO JEDEC STANDARDS MO-137-AD

0.012

0.008

0.069

0.053

SEATING PLANE

0.154 BSC

0.236 BSC

0.010

0.006

Figure 29. 20-Lead Shrink Small Outline Package [QSOP]

Q-20)

Dimensions shown in inches

0.50

0.40

EXPOSED

PAD

(BOT TOM VIEW)

0.30

1.65

1.50 SQ

1.35

0.25 MIN

8° 0°

0.050

0.016

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADCMP563BRQ −40°C to +85°C 16-Lead QSOP RQ-16 ADCMP563BRQZ ADCMP563BCP-R2 −40°C to +85°C 16-Lead LFCSP_VQ, 250 Unit Reel CP-16-3 ADCMP563BCP-RL7 −40°C to +85°C 16-Lead LFCSP_VQ, 1,500 Unit Reel CP-16-3 ADCMP563BCP-WP −40°C to +85°C 16-Lead LFCSP_VQ, 50 Unit Waffle Pack CP-16-3 EVAL-ADCMP563BRQ Evaluation Board ADCMP564BRQ −40°C to +85°C 20-Lead QSOP RQ-20 ADCMP564BRQZ EVAL-ADCMP564BRQ Evaluation Board

Z = Pb-free part.

−40°C to +85°C 16-Lead QSOP RQ-16

−40°C to +85°C 20-Lead QSOP RQ-20

Rev. B | Page 14 of 16

Page 15

ADCMP563/ADCMP564

www.BDTIC.com/ADI

NOTES

Rev. B | Page 15 of 16

Page 16

ADCMP563/ADCMP564

www.BDTIC.com/ADI

NOTES

D04650–0–5/05(B)

Rev. B | Page 16 of 16

Datasheet ADCMP564 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CONSIDERATIONS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TIMING INFORMATION

APPLICATION INFORMATION

CLOCK TIMING RECOVERY

OPTIMIZING HIGH SPEED PERFORMANCE

COMPARATOR PROPAGATION DELAY DISPERSION

COMPARATOR HYSTERESIS

MINIMUM INPUT SLEW RATE REQUIREMENT

TYPICAL APPLICATION CIRCUITS

OUTLINE DIMENSIONS

ORDERING GUIDE