Page 1
2.5 V/3.3 V, Four LVPECL Outputs,
V
FEATURES FEATURES
Operating frequency: 7.0 GHz Operating frequency: 7.0 GHz
Broadband random jitter: 50 fs rms Broadband random jitter: 50 fs rms
On-chip input terminations On-chip input terminations
Power supply (V
APPLICATIONS APPLICATIONS
Low jitter clock distribution Low jitter clock distribution
Clock and data signal restoration Clock and data signal restoration
Level translation Level translation
Wireless communications Wireless communications
Wired communications Wired communications
Medical and industrial imaging Medical and industrial imaging
ATE and high performance instrumentation ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK944 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input can
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A V
pin is available for biasing ac-coupled inputs.
− VEE): 2.5 V to 3.3 V Power supply (VCC − VEE): 2.5 V to 3.3 V
CC
REF
SiGe Clock Fanout Buffer
ADCLK944
FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM
ADCLK944
REF
CLK
CLK
V
REFERENCE
T
Figure 1.
The ADCLK944 features four full-swing emitter-coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias V
operation, bias V
to the positive supply and VEE to ground. For ECL
CC
to ground and VEE to the negative supply.
CC
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to V
tial output swing of 1.6 V.
The ADCLK944 is available in a 16-lead LFCSP and is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
LVPECL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
8770-001
− 2 V for a total differen-
CC
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
Page 2
ADCLK944
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Clock Inputs and Outputs ........................................................... 3
Timing Characteristics ................................................................ 3
Power .............................................................................................. 4
Absolute Maximum Ratings ............................................................ 5
Determining Junction Temperature .......................................... 5
REVISION HISTORY
3/10—Revision 0: Initial Version
ESD Caution...................................................................................5
Thermal Performance ...................................................................5
Pin Configuration and Function Descriptions ..............................6
Typical Performance Characteristics ..............................................7
Theory of Operation .........................................................................9
Clock Inputs ...................................................................................9
Clock Outputs ................................................................................9
PCB Layout Considerations ...................................................... 10
Input Termination Options ....................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
Rev. 0 | Page 2 of 12
Page 3
ADCLK944
SPECIFICATIONS
Typical values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum and maximum values are given for the
full V
− VEE = 3.3 V + 10% to 2.5 V − 5% and TA = −40°C to +85°C variation, unless otherwise noted.
CC
CLOCK INPUTS AND OUTPUTS
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Common-Mode Voltage V
Input Differential Voltage VID 0.4 3.4 V p-p ±1.7 V between input pins
Input Capacitance CIN 0.4 pF
Input Resistance RIN
Single-Ended Mode 50 Ω
Differential Mode 100 Ω
Common Mode 50 kΩ VT open
Input Bias Current 20 μA
DC OUTPUT CHARACTERISTICS
Output Voltage High Level VOH V
Output Voltage Low Level VOL V
Output Voltage, Single-Ended VO 600 960 mV VOH − VOL, output static
Voltage Reference V
Output Voltage (VCC + 1)/2 V −500 μA to +500 μA
Output Resistance 250 Ω
V
ICM
REF
+ 1.35 VCC − 0.1 V
EE
− 1.26 VCC − 0.76 V Load = 50 Ω to (VCC − 2.0 V)
CC
− 1.99 VCC − 1.54 V Load = 50 Ω to (VCC − 2.0 V)
CC
TIMING CHARACTERISTICS
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC PERFORMANCE
Maximum Output Frequency 6.2 7.0 GHz
Output Rise/Fall Time tR 35 50 75 ps 20% to 80%, measured differentially
Propagation Delay tPD 70 100 130 ps VID = 1.6 V p-p
Temperature Coefficient 75 fs/°C
Output-to-Output Skew
1
15 ps
Part-to-Part Skew 35 ps VID = 1.6 V p-p
Additive Time Jitter
Integrated Random Jitter 26 fs rms BW = 12 kHz to 20 MHz, CLK = 1 GHz
Broadband Random Jitter2 50 fs rms VID = 1.6 V p-p, 8 V/ns, V
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise Input slew rate > 1 V/ns (see Figure 11)
fIN = 1 GHz −118 dBc/Hz 100 Hz offset
−135 dBc/Hz 1 kHz offset
−144 dBc/Hz 10 kHz offset
−150 dBc/Hz 100 kHz offset
−150 dBc/Hz >1 MHz offset
1
The output-to-output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2
Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
Differential output voltage swing > 0.8 V
(see Figure 4)
= 2 V
ICM
Rev. 0 | Page 3 of 12
Page 4
ADCLK944
POWER
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage Requirement VCC − VEE 2.375 3.63 V 3.3 V + 10% to 2.5 V − 5%
Power Supply Current Static
Negative Supply Current I
I
Positive Supply Current I
I
Power Supply Rejection
Output Swing Supply Rejection
1
Change in tPD per change in VCC.
2
Change in output swing per change in VCC.
1
2
35 mA VCC − VEE = 2.5 V ± 5%
VEE
37 49 mA VCC − VEE = 3.3 V ± 10%
VEE
139 mA VCC − VEE = 2.5 V ± 5%
VCC
138 165 mA VCC − VEE = 3.3 V ± 10%
VCC
PSR
−3 ps/V
VCC
PSR
28 dB
VCC
Rev. 0 | Page 4 of 12
Page 5
ADCLK944
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage
VCC − VEE 6.0 V
Input Voltage
CLK, CLK
CLK to CLK
Input Termination, VT to CLK, CLK
Input Current, CLK, CLK to VT Pin
VEE − 0.5 V to VCC + 0.5 V
±1.8 V
±2 V
±40 mA
(CML, LVPECL Termination)
Maximum Voltage on Output Pins VCC + 0.5 V
Maximum Output Current 35 mA
Voltage Reference (V
) VCC to VEE
REF
Operating Temperature
Ambient Range −40°C to +85°C
Junction 150°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
DETERMINING JUNCTION TEMPERATURE
To determine the junction temperature on the application
printed circuit board (PCB), use the following equation:
T
= T
J
+ (ΨJT × PD)
CASE
where:
T
is the junction temperature (°C).
J
is the case temperature (°C) measured by the customer at
T
CASE
the top center of the package.
Ψ
is as indicated in Tabl e 5.
JT
is the power dissipation.
P
D
Val u es o f θ
design considerations. θ
imation of T
where T
Val u es o f θ
are provided for package comparison and PCB
JA
can be used for a first-order approx-
JA
using the following equation:
J
= TA + (θJA × PD)
T
J
is the ambient temperature (°C).
A
are provided in Tab l e 5 for package comparison
JB
and PCB design considerations.
ESD CAUTION
THERMAL PERFORMANCE
Table 5.
Parameter Symbol Description Value
Junction-to-Ambient Thermal Resistance
Still Air θJA Per JEDEC JESD51-2
0.0 m/sec Airflow 78 °C/W
Moving Air θ
Per JEDEC JESD51-6
JMA
1.0 m/sec Airflow 68 °C/W
2.5 m/sec Airflow 61 °C/W
Junction-to-Board Thermal Resistance θJB Per JEDEC JESD51-8
Moving Air
1.0 m/sec Airflow 49 °C/W
Junction-to-Case Thermal Resistance (Die-to-Heat Sink) θJC Per MIL-STD-883, Method 1012.1
Still Air
0.0 m/sec Airflow 1.5 °C/W
Junction-to-Top-of-Package Characterization Parameter ΨJT
Still Air Per JEDEC JESD51-2
0.0 m/sec Airflow 2.0 °C/W
1
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine whether they are similar to those assumed in these calculations.
1
Unit
Rev. 0 | Page 5 of 12
Page 6
ADCLK944
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
EE
V
Q0
16
15
CC
Q0
V
13
14
1
CLK
2
V
T
3
V
REF
4
CLK
NOTES
1. EXPOSED PAD MUST BE CONNECTED
TO V
EE
.
ADCLK944
TOP VIEW
(Not to Scale)
6
5
EE
Q3
V
8
7
Q3
V
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK Differential Input (Positive).
2 VT
3 V
4
CLK
REF
Center Tap. This pin provides the center tap of a 100 Ω input resistor for the CLK and CLK
Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK
Differential Input (Negative).
5, 16 VEE Negative Supply Pin.
6, 7
Q3
, Q3
Differential LVPECL Outputs.
8, 13 VCC Positive Supply Pin.
9, 10
11, 12
14, 15
Q2
Q1
Q0
, Q2
, Q1
, Q0
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
EPAD The exposed pad must be connected to VEE.
12
Q1
11
Q1
10
Q2
9
Q2
CC
2
08770-00
inputs.
inputs.
Rev. 0 | Page 6 of 12
Page 7
ADCLK944
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0.0 V, V
ICM
= V
, TA = 25°C, clock outputs terminated at 50 Ω to VCC − 2 V, unless otherwise noted.
REF
1
CH1 300mV M 1.25ns 20. 0GS/s
A CH1 36.0mV
IT 25.0ps/pt
Figure 3. LVPECL Differential Output Waveform at 200 MHz
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
DIFFERENTIAL OUTPUT VOLTAGE SWING (V)
0
0 1000 2000 3000 4000 5000 6000 7000 8000
FREQUENCY (MHz )
3.3V
2.5V
Figure 4. Differential Output Voltage Swing vs. Frequency
1
08770-003
CH1 300mV M 250ps 20.0GS/s
A CH1 36.0mV
IT 5.0ps/pt
08770-006
Figure 6. LVPECL Differential Output Waveform at 1000 MHz
1.55
1.50
1.45
1.40
1.35
DIFFERENTIAL OUTPUT VOLTAGE SWING (V)
1.30
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
08770-004
POWER SUPPLY VOLTAGE (V)
+25°C
+85°C
–40°C
08770-009
Figure 7. Differential Output Voltage Swing vs. Power Supply Voltage
and Temperature, V
= 1.6 V p-p
ID
80
85
90
95
100
105
PROPAGATI ON DELAY (ps)
110
115
0.1 0.3 0.5 0.7 0.9 1.1
DIFFERENTIAL INPUT VOLTAGE SWING (V)
DELAY 3.3V
DELAY 2.5V
Figure 5. Propagation Delay vs. Differential Input Voltage Swing
08770-005
Rev. 0 | Page 7 of 12
140
130
120
110
100
PROPAGATION DELAY (ps)
90
80
1.0 1.5 2.0 2.5 3.0 3.5
2.5V
3.3V
DC COMMON-MODE VOLTAGE (V
ICM
– VEE)
Figure 8. Propagation Delay vs. DC Common-Mode Voltage
0-008
0877
Page 8
ADCLK944
–
160
300
140
I
120
100
80
60
CURRENT (mA)
40
20
0
2.375 2.500 2.625 2.970 3.300 3.630
VCC
I
VEE
POWER SUPPLY VOLTAGE (V)
–40°C
+25°C
+85°C
08770-010
Figure 9. Power Supply Current vs. Power Supply Voltage and Temperature,
− 2 V)
CC
ADCLK944
PHASE NOISE (d Bc/Hz)
All Outputs Loaded (50 Ω to V
90
–100
–110
–120
–130
–140
–150
250
200
s rms)
f
150
100
RANDOM JITT E R (
50
0
02015105
Figure 11. Random Jitter vs. Input Slew Rate, V
INPUT SLEW RATE (V/ns)
Method
ID
08770-012
–160
–170
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY O F FSET (Hz)
CLOCK SOURCE
Figure 10. Absolute Phase Noise Measured at 1 GHz with Agilent E5052B
08770-011
Rev. 0 | Page 8 of 12
Page 9
ADCLK944
A
V
V
V
V
A
A
THEORY OF OPERATION
CLOCK INPUTS
The ADCLK944 accepts a differential clock input and distributes it to all four LVPECL outputs. The maximum specified
frequency is the point at which the output voltage swing is 50%
of the standard LVPECL swing (see Figure 4).
The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input can
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended,
3.3 V operation only), and ac-coupled 1.8 V CMOS, LVDS, and
LVPECL i n p u t s . A V
pin is available for biasing ac-coupled
REF
inputs (see Figure 20 and Figure 21).
Maintain the differential input voltage swing from approximately 400 mV p-p to no more than 3.4 V p-p. See Figure 18
through Figure 21 for various clock input termination schemes.
Output jitter performance is significantly degraded by an input
slew rate below 1 V/ns, as shown in Figure 11. The ADCLK944
is specifically designed to minimize added random jitter over a
wide input slew rate range. Whenever possible, clamp excessively
large input signals with fast Schottky diodes because attenuators
reduce the slew rate. Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good
high frequency characteristics.
CLOCK OUTPUTS
The specified performance necessitates using proper transmission line terminations. The LVPECL outputs of the ADCLK944
are designed to directly drive 800 mV into a 50 Ω cable or into
microstrip/stripline transmission lines terminated with 50 Ω
referenced to V
output stage is shown in Figure 12. The outputs are designed
for best transmission line matching. If high speed signals must
be routed more than a centimeter, either the microstrip or the
stripline technique is required to ensure proper transition times
and to prevent excessive output ringing and pulse-width-dependent
propagation delay dispersion.
− 2 V, as shown in Figure 13. The LVPECL
CC
V
CC
Q
Q
Figure 13 through Figure 16 depict various LVPECL output
termination schemes. When dc-coupled, V
of the receiving
CC
buffer should match VS_DRV.
S_DRV
DCLK944
Z0 = 50Ω
VCC – 2V
Z0 = 50Ω
Figure 13. DC-Coupled, 3.3 V LVPECL
50Ω
50Ω
CC
= VS_DR
LVPECL
08770-014
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below V
of the LVPECL
OL
driver. In this case, VS_DRV on the ADCLK944 should equal
V
of the receiving buffer. Although the resistor combination
CC
shown in Figure 14 results in a dc bias point of VS_DRV − 2 V,
the actual common-mode voltage is VS_DRV − 1.3 V because
there is additional current flowing from the ADCLK944 LVPECL
driver through the pull-down resistor.
S_DRV
VS_DRV
ADCLK944
SINGLE-ENDED
(NOT COUPLED)
50Ω
50Ω
127Ω 127Ω
83Ω 83Ω
V
CC
LVPECL
8770-015
Figure 14. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination
LVPECL Y-termination (see Figure 15) is an elegant termination
scheme that uses the fewest components and offers both oddand even-mode impedance matching. Even-mode impedance
matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers
limited flexibility for varying the drive strength of the emitterfollower LVPECL driver. This can be an important consideration
when driving long trace lengths but is usually not an issue.
VS_DRV VCC = VS_DRV
VS_DRV
DCLK944
Z0 = 50Ω
Z0 = 50Ω
50Ω
50Ω
50Ω
LVPECL
Figure 15. DC-Coupled, 3.3 V LVPECL Y-Termination
DCLK944
0.1nF
0.1nF
100Ω DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
100Ω
V
CC
LVPECL
8770-016
V
EE
08770-013
Figure 12. Simplified Schematic Diagram
of the LVPECL Output Stage
Rev. 0 | Page 9 of 12
200Ω 200Ω
08770-017
Figure 16. AC-Coupled LVPECL with Parallel Transmission Line
Page 10
ADCLK944
PCB LAYOUT CONSIDERATIONS
The ADCLK944 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used
to achieve the specified performance. It is critically important to
use low impedance supply planes for both the negative supply
(V
) and the positive supply (VCC) planes as part of a multilayer
EE
board. Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
The following references to the ground plane assume that the V
power plane is grounded for LVPECL operation. Note that, for
ECL operation, the V
power plane becomes the ground plane.
CC
It is also important to adequately bypass the input and output
supplies. Place a 1 µF electrolytic bypass capacitor within several
inches of each V
power supply pin to the ground plane. In
CC
addition, place multiple high quality 0.001 F bypass capacitors
as close as possible to each V
supply pin, and connect the
CC
capacitors to the ground plane with redundant vias. Select high
frequency bypass capacitors for minimum inductance and ESR.
To improve the effectiveness of the bypass at high frequencies,
minimize parasitic layout inductance. Also, avoid discontinuities
along input and output transmission lines; such discontinuities
can affect jitter performance.
In a 50 Ω environment, input and output matching have a significant impact on performance. The buffer provides internal 50 Ω
termination resistors for both the CLK and
CLK
inputs. Normally,
the return side is connected to the reference pin that is provided.
Bypass the termination potential using ceramic capacitors to
prevent undesired aberrations on the input signal due to parasitic
inductance in the termination return path. If the inputs are dccoupled to a source, take care to ensure that the pins are within
the rated input differential and common-mode voltage ranges.
EE
If the return is floated, the device exhibits a 100 cross-termination, but the source must then control the common-mode
voltage and supply the input bias currents.
ESD/clamp diodes between the input pins prevent the application
from developing excessive offsets to the input transistors. ESD
diodes are not optimized for best ac performance. When a clamp
is required, it is recommended that appropriate external diodes
be used.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK944 package is both an
electrical connection and a thermal enhancement. For the device
to function properly, the paddle must be properly attached to
pins.
the V
EE
When properly mounted, the ADCLK944 also dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK944. The PCB attachment must provide a good thermal
path to a larger heat dissipation area. This requires a grid of vias
from the top layer of the PCB down to the V
power plane (see
EE
Figure 17). The ADCLK944 evaluation board (ADCLK944/PCBZ)
provides an example of how to attach the part to the PCB.
VIAS TO VEE POWER
PLANE
Figure 17. PCB Land for Attaching Exposed Paddle
08770-018
Rev. 0 | Page 10 of 12
Page 11
ADCLK944
V
C
G
A
C
R
INPUT TERMINATION OPTIONS
CC
CONNECT VTTO VCC.
V
T
CLK
CLK
V
REF
50Ω50Ω
Figure 18. Interfacing to CML Inputs
V
REF
V
T
V
– 2V
CC
CLK
CLK
CONNECT VTTO VCC − 2V.
50Ω50Ω
Figure 19. Interfacing to PECL Inputs
V
REF
V
T
REF
50Ω50Ω
.
08770-021
CLK
CLK
08770-019
CONNECT VTTO V
Figure 20. AC Coupling Differential Signal Inputs, Such as LVDS
V
REF
V
T
CLK
CLK
ONNECT VT, V
PLACE A BYPASS CAPACITOR FROM V
08770-020
ROUND.
LTERNATIV E LY, VT, V
ONNECTED TO GETHER, GIVING A CLE ANE
LAY
OUT AND A 180° PHASE S HIFT.
REF
50Ω50Ω
, AND CLK TOGETHER.
, AND CLK CAN BE
REF
TO
T
08770-022
Figure 21. Interfacing to AC-Coupled, Single-Ended Inputs
Rev. 0 | Page 11 of 12
Page 12
ADCLK944
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.80
0.75
0.70
SEATING
PLANE
3.10
3.00 SQ
2.90
0.50
BSC
0.45
0.40
0.35
0.05 MAX
0.02 NOM
0.20 REF
0.30
0.25
0.18
13
12
9
8
BOTTOM VIEWTOP VIEW
COPLANARITY
0.08
1
P
N
I
C
I
A
N
I
16
EXPOSED
PAD
5
FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRI P T I O NS
SECTION O F THIS DATA SHEET.
D
1
1.60
1.50 SQ
1.40
4
0.25 MIN
R
O
T
COMPLIANTTOJEDEC STANDARDS MO-220- W E ED-6.
111808-A
Figure 22. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-18)
Dimensions shown in millimeters
ORDERING GUIDE
1
Model
ADCLK944BCPZ-R2 −40°C to +85°C 16-Lead LFCSP_WQ CP-16-18 Y2K
ADCLK944BCPZ-R7 −40°C to +85°C 16-Lead LFCSP_WQ CP-16-18 Y2K
ADCLK944BCPZ-WP −40°C to +85°C 16-Lead LFCSP_WQ CP-16-18 Y2K
ADCLK944/PCBZ Evaluation Board
1
Z = RoHS Compliant Part.
Temperature Range Package Description Package Option Branding Code
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08770-0-3/10(0)
Rev. 0 | Page 12 of 12
Loading...