Page 1
ADC14071
14-Bit, 7 MSPS, 380 mW A/D Converter
ADC14071 14-Bit, 7 MSPS, 380 mW A/D converter
November 1999
General Description
The ADC14071 is a 14-bit, monotholic analog to digital converter capable of conversion rates up to 8 Megasamples per
second. This CMOS converter uses a differential, piperlined
architecture with digital error correction and an on-chip
track-and-hold circuit to maintain superb dynamic performance with input frequenciesupto20MHz.Tested and guaranteed dynamic performance specifications provide the designer with known performance. TheADC14071operateson
a +5V single supply consuming just 380mW (typical). The
Power Down feature reduces power consumption to 20mW,
typical.
The differential inputs provide a full scale input swing of
±
V
with the possibilityofasingleinput.Fulluse of the dif-
REF
ferential input is recommended for optimum perfomance. For
ease of use, the reference input is single ended. This singleended reference input is converted on-chip to a differential
reference configuration for use by the processing circuitry.
Output data format is 14-bit straight binary.
The ADC14071 may be used to replace many hybrid converters with a resultant saving of space, power and cost.
The ADC14071 comes in a 48-pin TQFP and is specified to
operate over the industrial temperature range of −40˚C to
+85˚C.
Connection Diagram
Features
n Single +5V Operation
n Power Down Mode
n TTL/CMOS Input/Output Compatible
Key Specifications
n Resolution 14 Bits
n Max Conversion Rate 7 Msps (min)
n DNL
n SNR (f
n ENOB (f
n Supply Voltage +5V
n Power Consumption 380 mW (typ)
=
500 kHz) 80 dB (typ)
IN
= 500 kHz) 12.6 Bits (typ)
W
±
0.6 LSB (typ)
±
5
Applications
n Document Scanners
n Imaging
n Instrumentation
n PC-Based Data Acquisition
n Spectrum Analyzers
n Sonar/Radar
n xDSL
n Wireless Local Loop
n Data Acquisition Systems
n DSP Front End
%
DS101101-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS101101 www.national.com
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Ordering Information
ADC14071
Block Diagram
Industrial Temperature Range
(−40˚C ≤ T
≤ +85˚C)
A
NS Package
ADC14071CIVBH VBH48A 48-Pin Thin Quad Flatpak
ADC14071EVAL Evaluation System
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
2V
3V
43 V
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IN
IN
REF IN
+
−
Non-Inverting analog signal input. With a 2.0V reference
voltage the input signal voltage range is from 0V to 2.0V.
Inverting analog signal input. With a 2.0V reference voltage
the input signal voltage range is from 0V to 2.0V. This pin
may be connected to a voltage of
for single-ended operation, but a balanced input signal is
required for best performance.
Positive reference input. This pin should be bypassed to
AGND with a 0.1 µF monolithic capacitor. V
nominal and should be in the range of 1.0V to 2.7V.
DS101101-2
1
⁄2the reference voltage
is 2.0V
REF
Page 3
Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
ADC14071
47 V
1V
REF (MID)
45 V
DIGITAL I/O
11 CLOCK
12 OE
10 PD
REF
REF
+BY
−BY
BY
These pins are high impedance reference bypass pins only.
Connect a 0.1µF capacitor from each of these pins the
AGND. DO NOT connect anything else to these pins.
Digital clock input. The range of frequencies for this input is
25 kHz to 8 MHz (typical) with guaranteed performance at 7
MHz. The input is sampled on the rising edge of this input.
OE is the output enable pin that, when low, enables the
TRI-STATE®data output pins. When this pin is high, the
outputs are in a high impedance state.
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
36 OR
19-23,
25-29,
D0–D13
32-35
ANALOG POWER
5, 6, 7,
13, 41
4, 8, 9,
14, 15,
AGND
42
Out of Range pin. A high at this output pin indicates that the
input voltage is either above the reference voltage or is
below ground. When this pin is high, the digital output pins
will indicate a full scale for input voltages above the
reference voltage, or will indicate a zero scale for input
voltages below zero scale.
Digital data output pins that make up the 14-bit conversion
results. D0 is the LSB, while D13 is the MSB of the straight
binary output word.
Positive analog supply pins. These pins should be
V
A
connected to a clean, quiet +5V voltage source and
bypassed to AGND with 0.1 µF monolithic capacitors located
within 1 cm of these power pins, and by a 10 µF capacitor.
The ground return for the analog supply. AGND and DGND
should be connected together directly beneath the
ADC14071 package. See Section 5 (Layout and Grounding)
for more details.
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Page 4
Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC14071
DIGITAL POWER
Positive digital supply pin. This pin should be connected to
17 V
16 DGND
31 DR V
24, 30,
37
NC
18, 38,
39, 40,
44, 46,
48
D
D
DR GND
NC
the same clean, quiet +5V source as is V
DGND with a 0.1 µF monolithic capacitor in parallel with a
10 µF capacitor, both located within 1 cm of the power pin.
The ground return for the digital supply. AGND and DGND
should be connected together directly beneath the
ADC14071 package. See Section 5 (Layout and Grounding)
for more details.
Positive digital supply pin for the ADC14071’s output drivers.
This pin should be connected to a voltage source of +3 to
+5V and bypassed to DR GND with a 0.1 µF monolithic
capacitor. If the supply for this pin is different from the
supply used for V
a 10 µF tantalum capacitor and never exceed the voltage on
. All bypass capacitors should be located within 1 cm of
V
D
the supply pin.
and VD, it should also be bypassed with
A
The ground return for the digital supply for the ADC14071’s
output drivers. These pins should be connected to the
system digital ground, but not be connected in close
proximity to the ADC14071’s DGND or AGND pins. See
Section 5 (Layout and Grounding) for more details.
All pins marked NC (no connect) should not be connected to
any potential (or to ground). Allow these pins to float.
and bypassed to
A
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Page 5
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
+
=
=
(V
−DRVD,VD−DRV
V
A
Voltage on Any I/O Pin −0.5V to V
Input Current at Pins 1, 45 and
47(Note 3)
Input Current at Any Other Pin (Note
3)
Package Input Current (Note 3)
Power Dissipation at T
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
=
V
V
A
D
) 6.0V
DR V
D
D
=
25˚C See (Note 4)
A
+
+0.5V
±
10 mA
±
25 mA
±
50 mA
1500V
≥0V
200V
Soldering Temperature, Infrared,
10 seconds (Note 6) 300˚C
Storage Temperature −65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Operating Temperature Range −40˚C ≤ T
V
A,VD
DR V
V
REF
D
+4.75V to +5.25V
Digital Inputs −0.3V to V
Analog Inputs −0.3V to V
| ≤100 mV
|V
A−VD
|AGND − DGND| 0V to 100 mV
≤ +85˚C
A
2.7V to V
1.0V to 2.7V
+ 0.3V
D
+ 0.3V
A
ADC14071
D
Converter Electrical Characteristics
=
The following specifications apply for AGND=DGND=DR GND=0V, V
=
V
REF IN
apply for T
+2.0V, V
=
A
(common mode)=1.0V, f
IN
=
T
to T
T
J
MIN
MAX
: all other limits T
CLK
=
A
@
7 MHz
=
=
T
25˚C (Notes 7, 8, 9)
J
50%duty cycle, tr,t
Symbol Parameter Conditions
=
V
A
+5.0V
D
r
=
DC
4ns, C
(Note 10)
Typical
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 14 Bits (min)
INL Integral Non-Linearity (note 12)
DNL Differential Non-Linearity
Positive and Negative Full-Scale
FSE
Error
25˚C 0.9 2.3
TC FSE Full-Scale Error Tempco −5 ppm/˚C
ZSE Zero Offset Error 25˚C 0.1
TC ZSE Zero Offset Error Tempco −0.6 ppm/˚C
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
Reference Voltage Range 2.00
REF
Reference Input Resistance 10M Ohms
R
R
C
Reference Input Capacitance 5 pF
R
+
Input Voltage Range (V
V
IN
C
IN
+
V
IN
−
,V
Input Capacitance V
IN
−
−V
)VIN(common Mode) = V
IN
IN
IN
=
1.0V+0.7 Vrms
/2
REF
(CLK LOW) 14 pF
(CLK HIGH) 5 pF
DYNAMIC CONVERTER CHARACTERISTICS
BW Full Power Bandwidth
ENOB Effective Number of Bits
SINAD Signal-to-Noise and Distortion
SNR Signal -to-Noise Ratio (Note 13)
THD Total Harmonic Distortion
−1 dB 20 MHz
−3 dB 25 MHz
=
f
500 kHz 12.6 12.0 Bits (min)
IN
=
f
3.5 MHz 12.0 Bits
IN
=
f
500 kHz 77 74 dB (min)
IN
=
f
3.5 MHz 74 dB
IN
=
f
500 kHz 80 78 dB (min)
IN
=
f
3.5 MHz 77 dB
IN
=
f
500 kHz −83 −76 dB (min)
IN
=
f
3.5 MHz −79 dB
IN
=
,DRV
L
±
2.2 LSB
±
0.6
3.0V or 5.0V, PD=0V,
D
=
20 pF/pin. Boldface limits
Limits
(Note 11)
+1.0
−0.85
LSB (max)
1.0
2.7
±
±
2.0
1.0
±
2.7
V(max)
V(max)
Units
%
FS
%
FS
V(min)
V(min)
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Page 6
Converter Electrical Characteristics (Continued)
The following specifications apply for AGND=DGND=DR GND=0V, V
V
REF IN
ADC14071
apply for T
=
+2.0V, V
(common mode)=1.0V, f
IN
=
=
T
A
T
J
MIN
to T
MAX
: all other limits T
Symbol Parameter Conditions
DYNAMIC CONVERTER CHARACTERISTICS
SFDR Spurious Free Dynamic Range
IMD Intermodulation Distortion
CLK
=
f
IN
f
IN
f
IN1
f
IN2
@
7 MHz
=
=
T
25˚C (Notes 7, 8, 9)
A
J
=
500 kHz 90 dB
=
3.5 MHz 81 dB
=
95 kHz
=
105 kHz
=
V
A
50%duty cycle, tr,t
D
=
r
+5.0V
=
4ns, C
DC
L
Typical
(Note 10)
3.0V or 5.0V, PD=0V,
D
=
20 pF/pin. Boldface limits
Limits
(Note 11)
=
,DRV
−97 dB
Units
DC and Logic Electrical Characteristics
The following specifications apply for AGND=DGND=DR GND=0V, V
V
REF IN
ply for T
=
+2.0V, V
A
(common mode)=1.0V, f
IN
=
=
T
to T
T
J
MIN
: all other limits T
MAX
Symbol Parameter Conditions
CLOCK OE, PD DIGITAL INPUT CHARACTERISTICS
V
Logical “1” Input Voltage V
IH
V
Logical “0” Input Voltage V
IL
I
Logical “1” Input Current V
IH
I
Logical “0” Input Current V
IL
C
VINInput Capacitance 5 pF
IN
D00 – D13 DIGITAL OUTPUT CHARACTERISTICS
V
Logical “1” Output Voltage
OH
Logical “0” Output Voltage
V
OL
TRI-STATE Output Current
I
OZ
Output Short Circuit Source
+I
SC
Current
Output Short Circuit Sink
−I
SC
Current
POWER SUPPLY CHARACTERISTICS
Analog Supply Current PD=DGND 75.7 81 mA(max)
I
A
I
D+IDR
Digital Supply Current PD=DGND, no output load, dc input 0.3 2 mA(max)
Total Power Consumption
PSRR
Power Supply Rejection
Ratio
=
CLK
=
A
+
=
5.25V 2.0 V(min)
+
=
5.25V 0.8 V(max)
=
5.0V 1 µA
IN
=
0V −1 µA
IN
=
DR V
D
=
DR V
D
=
DR V
D
=
DR V
D
=
V
3V or 5V 100 nA
OUT
=
V
0V −100 nA
OUT
=
DR V
D
=
V
DR V
OUT
@
7 MHz
T
4.75V, I
2.7V, I
4.75V, I
2.7V, I
3V, V
50%duty cycle, tr,t
=
25˚C (Notes 7, 8, 9)
J
=
−360 µA 4.5 V(min)
OUT
=
−360 µA 2.5 V(min)
OUT
=
1.6 mA 0.4 V(max)
OUT
=
1.6 mA 0.4 V(max)
OUT
=
0V −10 mA
OUT
=
3V 12 mA
D
PD=DGND, no output load, dc input 380 425 mW(max)
PD=DR V
, no output load, dc input 20 mW
D
Change in FS Error with 0.5V change in V
250 mV
100 kHz riding on V
PP
=
=
V
A
A
+5.0V
D
r
=
A
DC
4ns, C
=
,DRV
L
3.0V or 5.0V, PD=0V,
D
=
20 pF/pin. Boldface limits ap-
Typical
(Note
10)
Limits
(Note
11)
70 dB
46 dB
Units
AC Electrical Characteristics
The following specifications apply for AGND=DGND=DR GND=0V, V
=
V
REF IN
apply for T
+2.0V, V
=
A
(common mode)=1.0V, f
IN
=
to T
T
T
J
MIN
: all other limits T
MAX
CLK
=
A
@
7 MHz
50%duty cycle, tr,t
=
=
T
25˚C (Notes 7, 8, 9)
J
Symbol Parameter Conditions
f
CLK
Conversion Clock Frequency
Conversion Clock Duty Cycle
www.national.com 6
=
A
=
V
+5.0V
D
=
f
DC
4 ns, C
(Note 10)
=
,DRV
L
Typical
3.0V or 5.0V, PD=0V,
D
=
20 pF/pin. Boldface limits
Limits
(Note 11)
25
8 7
45
55
Units
kHz(min)
MHz(max)
%
(min)
%
(max)
Page 7
AC Electrical Characteristics (Continued)
=
The following specifications apply for AGND=DGND=DR GND=0V, V
=
V
REF IN
apply for T
+2.0V, V
=
A
(common mode)=1.0V, f
IN
=
to T
T
T
J
MIN
: all other limits T
MAX
CLK
=
A
@
7 MHz
50%duty cycle, tr,t
=
=
T
25˚C (Notes 7, 8, 9)
J
Symbol Parameter Conditions
t
t
CH
t
CONV
t
AD
t
t
OD
t
EN
t
DIS
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND=AGND=DGND=DR GND=0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
(10 mA for pins 1, 45 and 47). The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
TQFP, θ
device under normal operation will typically be about 400 mW (380 mW quiescent power +20 mW due to 1 TTL load on each digital output. The values for maximum
power dissipation listed above will be reached only when the ADC14071 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms.
Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 0.3V above V
is limited per (Note 3). However, errors in the A/D conversion can occur if the input goes above (V
is 4.75VDC, the full-scale input voltage must be ≤ 2.75VDCor ≥ −300 mV to ensure accurate conversions.
V
A
Conversion Clock Low Time 63 ns(min)
CL
Conversion Clock High Time 63 ns(min)
Conversion Latency 12
Aperture Delay 3 ns
Aperture Jitter 5 ps(rms)
AJ
Rising Edge of CLOCK to Data Valid
OE Low to Data Valid on D00 – D13 35 ns
OE High to D0 – D13 into TRI-STATE
), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 48-pin
is 76˚C/W, so PDMAX=1,345 mW at 25˚C and 855 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
ja
JA
®
<
AGND or V
IN
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
J
=
V
A
+5.0V
D
=
f
DC
4 ns, C
(Note 10)
DRV
= 3.0V 45 58 ns(max)
D
DRV
= 5.0V 34 53 ns(max)
D
>
VAor VD), the current at that pin should be limited to 25 mA
IN
or to 0.3V below GND will not damage this device, provided current
A
−2.0V) or below GND by more than 300 mV. As an example, if
A
=
,DRV
L
Typical
3.0V or 5.0V, PD=0V,
D
=
20 pF/pin. Boldface limits
Limits
(Note 11)
12 ns
Units
Clock
Cycles
ADC14071
DS101101-8
ESD Protection Scheme for Input and Output Pins
Note 8: To guarantee accuracy, it is required that V
Note 9: With the test condition for V
Note 10: Typical figures are at T
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Integral Non-Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and
negative full-scale.
Note 13: Optimum SNR performance will be obtained by keeping the reference input in the 1.8V to 2.7V range. The LM4041CIM3-ADJ (SOT-23 package) or the
LM4041CIZ-ADJ (TO-92 package bandgap voltage reference is recommended for this application.
REF
=
=
T
A
J
and VDbe connected together and to the same power supply with separate bypass capacitors at each V+pin.
A
=
+−V
(V
REF
25˚C, and represent most likely parametric norms.
−) given as +2.0V, the 14-bit LSB is 244 µV.
REF
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Page 8
AC Electrical Characteristics (Continued)
ADC14071
FIGURE 1. Transfer Characteristic
DS101101-9
FIGURE 2. Description of Errors
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DS101101-10
Page 9
Typical Performance Characteristics V
otherwise stated.
ADC14071
=
=
V
A
D
DR V
=
D
5V. f
CLK
=
7MHz, f
=
500KHz unless
IN
INL
SNR vs Temperature
DS101101-11
DNL
DS101101-12
INL vs Temperature
DNL vs Temperature
DS101101-13
DS101101-15
DS101101-14
THD vs Temperature
DS101101-16
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Page 10
Typical Performance Characteristics V
otherwise stated. (Continued)
ADC14071
SINAD & ENOB vs Temp
=
=
V
A
D
DR V
=
D
5V. f
CLK
=
7MHz, f
SINAD & ENOB vs Clock Duty Cycle
=
500KHz unless
IN
SFDR vs Temperature
IMD Response
DS101101-17
DS101101-19
Power Consumption vs f
Spectral Response
DS101101-18
CLK
DS101101-20
DS101101-21
Specification Definitions
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
APERTURE DELAY is the time from the sampling edge of
the clock to when the input signal is acquired or held for conversion. In other words, it is the time required for the Sample/
Hold circuit to go from the ″sample″ mode to the ″hold″
www.national.com 10
DS101101-22
mode. The Sample/Hold circuit effectively stops capturing
the input signal and goes into the ″hold″ mode this amount of
time after the clock transition.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Page 11
Specification Definitions (Continued)
Distortion or SINAD. ENOB is defined as (SINAD -
1.76)/6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input. The test
is performed with f
of f
. The input frequency at which the output is −3 dB
CLK
relative to the low frequency input signal is the full power
equal to 100 kHz plus integer multiples
IN
bandwidth.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dB.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (
1
⁄2LSB below the first code transition) through
positive full scale (the last code transition). The deviation of
any given code from this straight line is measured from the
center of that code value.
NEGATIVEFULL SCALE ERROR is the measure of how far
the last code transition is from the ideal of
nominal negative full scale. It is the difference between the
input voltage (V
code and the ideal voltage to cause that transition. The ideal
LSB transition (when it should occur) is (V
1
⁄2LSB
+
−
−V
) just causing a transition to the first
IN
IN
1
⁄2LSB above
+
)−(V
IN
−
)
IN
OFFSET ERROR is the difference between the ideal and actual voltages that cause a transition to mid-scale (a code of
8192) when approached from a lower code. The ideal LSB
transition (when it should occur) is (V
IN
+
)−(V
−
)=0
IN
Timing Diagram
PIPELINE DELAY(LATENCY)is the number of clock cycles
between initiation of conversion and the availability of that
same conversion result at the output. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
POSITIVE FULL SCALE ERROR is a measure of how far
the last code transition is from the ideal of 1
nominal positive full scale. It is the difference beween the input voltage (V
full scale and V
called Full Scale Offset Error.
+
−
−V
) just causing a transition to positive
IN
IN
−11⁄2LSB. Full Scalse Error is sometimes
REF
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components
below half the clock frequency, including harmonics but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first nine harmonic components to the rms value of the input signal.
=
1
⁄2LSB below
ADC14071
Output Timing
DS101101-23
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Page 12
Functional Description
Operating on a single +5V supply, the ADC14071 uses a
pipelined architecture and has error correction circuitry to
ADC14071
help ensure maximum performance.
Balanced analog signals are digitized to 14 bits. Each of
these input signals should have a peak-to-peak voltage
equal to the input reference voltage, V
tered around V
to output relationship of the ADC14071. As indicated in
2
, biasing one input to V
its full range signal results ina6dBreduction of the output
range, limiting it to the range of
REF
/2.
Table 1
and
/2 and driving the other input with
REF
1
, and can be cen-
REF
Table 2
indicate the input
⁄4to3⁄4of the minimum output range obtainable if both inputs were driven with complimentary signals.
Section
1.3 SIGNAL INPUTS
explains how to avoid this sig-
nal reduction.
TABLE 1. Input to Output Relationship— Differential
Input
+
V
IN
0V
0.25*V
REF
0.50*V
REF
0.75*V
REF
V
REF
−
V
REF
0.75*V
0.50*V
025*V
IN
REF
REF
REF
Output
00 0000 0000 0000
01 0000 0000 0000
10 0000 0000 0000
11 0000 0000 0000
0 11 1111 1111 1111
TABLE 2. Input to Output Relationship— Single-Ended
Input
+
V
IN
0V
0.25*V
REF
0.50*V
REF
0.75*V
REF
V
REF
−
V
IN
/2 01 0000 0000 0000
REF
V
/2 01 1000 0000 0000
REF
V
/2 10 0000 0000 0000
REF
V
/2 10 1000 0000 0000
REF
V
/2 11 0000 0000 0000
REF
Output
The output word rate is the same as the clock frequency,
which can be between 25kSPS and 8 MSPS (typical). The
analog input voltage is acquired at the rising edge of the
clock and the digital data for that sample is delayed by the
pipeline for 12 clock cycles.
A logic high on the power down (PD) pin reduces the converter power consumption to 20 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC14071:
4.75V ≤ V
V
D
2.7≤ DR VD≤ V
25 kHz ≤ f
1.0V ≤ V
1.1 ANALOG INPUTS
The ADC14071 has two analog signal inputs, V
These two pins form a differential input. There is one reference input pin, V
≤ 5.25V
A
=
V
A
D
≤ 8 MHz
CLK
≤ 2.7V
REF
.
REF
IN
+
and V
Table
IN
1.2 REFERENCE INPUT
TheADC14071 is designed to operate with a 2.0V reference,
but performs well with reference voltages in the range of
1.0V to 2.7V.Reducing the reference voltage below 1.0V will
decrease the signal-to-noise ratio (SNR) of the ADC14071.
Increasing the reference voltage (and the input signal swing)
beyond 2.7V will degrade THD.
It is very important that all grounds associated with the reference voltage and the input signal make connection to the
analog ground plane at a single point to minimize the effects
of noise currents in the ground path.
The reference bypass pins (V
and V
REF (MID)
each of these pins to AGND with 0.1µF capacitors. DO NOT
BY) are for bypass purposes only. Bypass
REF
+
BY, V
LOAD these pins.
1.3 SIGNAL INPUTS
+
The signal inputs are V
defined as
Figure 3
shows the expected input signal range.
IN
=
V
IN
−
and V
. The input signal, VIN,is
IN
+
−
)–(V
(V
IN
IN
Note that the nominal input common mode voltage is 1.0V.
This assumes that the input signals run between the limits of
AGND and 2V with V
creases above 4 V
become V
exceed the voltage described as
/2. The Peaks of the input signals should never
REF
Peak Input Voltage=V
=
2.0V. As the input signal V
REF
, the input common mode range should
P-P
A
to maintain signal integrity and THD and SINAD
performance.
FIGURE 3. Expected Input Signal Range
The ADC14071 performs best with a differential input centered around half the reference voltage, V
peak-to-peak voltage swing at both V
exceed the value of the reference voltage or the output data
IN
will be clipped. The two input signals should be exactly 180˚
out of phase from each other and of the same amplitute to
avoid a reduction in the output amplitude. For angular deviations of up to 10˚ from these two signals being 180 out of
phase, the full scale error in LSB can be described as
E
1.79
=
.
dev
FS
Where dev is the angular difference between the two signals
having a 180˚ relative phase relationship to each other, as
shown in
pedance less than 100Ω.
−
.
Figure 4
. Drive the analog inputs with a source im-
REF
).
− 2.0V
DS101101-24
+
and V
−
BY and V
REF
−
should not
IN
REF
IN
. The
in-
www.national.com 12
Page 13
Applications Information (Continued)
DS101101-31
FIGURE 4. Angular Errors between the Two Input
Signals Will Reduce the Output Level
For single ended operation, one of the analog inputs should
be connected to a voltage equal to the reference voltage,
with the common mode voltage of the driven input equal to
that same voltage. The peak-to-peak input signal should be
twice the reference voltage to minimize SNR and SINAD
loss. For example, set the V
and drive V
The V
analog switch followed by a switched-capacitor amplifier.
+
with signal range of 0V to 2.0V.
IN
+
and the V
IN
−
inputs of the ADC14071 consist of an
IN
to 1.0V, bias V
REF
The capacitance seen at the analog input pins changes with
the clock level, appearing as 14 pF when the clock is low,
and 5 pF when the clock is high. Since a dynamic capacitance is more difficult to drive than is a fixed capacitance,
choose the driving amplifier carefully.The LM6172 is a good
amplifier for driving the ADC14071.
The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 33Ω series resistors at each of the signal
inputs with a 0.0022 µF capacitor across the inputs, as can
be seen in
Figures 6, 7
. These components should be
placed close to the ADC as the input pins of the ADC is the
most sensitive part of the system and this is the last opportunity to filter the input.
2.0 DIGITAL INPUTS
Digital inputs consist of CLOCK, OE and PD.
2.1 CLOCK
The CLOCK signal controls the timing of the sampling process. Drive the clock input with a stable, low phase jitter
clock signal in the range of 25 kHz to 8 MHz and rise and fall
times of less than 4 ns. The trace carrying the clock signal
should be as short as possible. This trace should not cross
any other signal line, analog or digital, not even at 90˚.
The CLOCK signal also drives the internal state machine. If
the clock is interrupted, the charge on internal capacitors can
dissipate to the point where the output data will lose accuracy.
The CLOCK pin should be terminated with a series 100Ω resistor and 200 pF capacitor to ground located within two centimeters of the ADC14071 clock pin, as shown in
−
to 1.0V
IN
Figure 5
Whenever the trace between the clock source and the ADC
clock pin is greater than 2 cm, use a 50Ω series resistor in
the clock line, located within 2 cm of the driving source.
2.2 OE
The OE pin, when low, puts the output pins into a high impedance state. Be very careful when driving a high capacitance bus. The more capacitance the output drivers must
charge for each conversion, the more instantaneous digital
current flows through DR V
charging current spikes can couple into the analog circuitry,
and DR GND. These large
D
degrading dynamic performance. Adequate bypassing and
maintaining separate analog and digital ground planes will
reduce this problem.
Additionally, bus capacitance beyond the specified 20 pF/pin
will cause t
theADC output data. The result could, again, be an apparent
to increase, making it difficult to properly latch
OD
reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC14071, which reduces the energy coupled back into the
converter output pins by limiting the output current.A reasonable value for these resistors is 47Ω.
2.3 PD
The PD pin, when high, holds the ADC14071 in a
power-down mode to conserve power when the converter is
not being used. In this state the power consumption is 20
mW. The output data pins may change randomly when the
PD pin is high. Power consumption during power-down is not
affected by the clock frequency, or by whether there is a
clock signal present. The data in the pipeline is corrupted
while in the power down mode.
3.0 OUTPUTS
The ADC14071 has 15 digital outputs: 14 Data Output pins
and OR (Out of Range).
The output pins are TTL/CMOS compatible and the output
data format is straight binary. Valid data is present at these
outputs while the OE pin is low. While the t
information about output timing, a simple way to capture a
valid output is to latch the data on the
falling edge
version clock (pin 11).
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connecting buffers between the ADC outputs and any other circuitry.
Only one input should be connected to each output pin. Additionally,inserting series resistors of 47Ω to 56Ω at the digital outputs, close to the ADC pins, will isolate the outputs
from trace and other circuitry capacitances and limit the output currents which could otherwise result in performance
degradation, as discussed in Section 2.2. See
The OR pin indicates when the input signal is under- or
over-range. This pin and the MSB, used together, will indi-
.
cate whether the input is out of range low or high.
time provides
OD
of the con-
Figure 5
ADC14071
.
www.national.com13
Page 14
Applications Information (Continued)
ADC14071
FIGURE 5. Simple Application Circuit with Single-Ended to Differential Buffer
DS101101-25
FIGURE 6. Differential Drive Circuit of
Tolerance of the other Resistors is not Critical.
www.national.com 14
Figure 5
. All 100Ω Resistors are 0.1%.
DS101101-26
Page 15
Applications Information (Continued)
FIGURE 7. Driving the Signal Inputs with a Transformer
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pin should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor a centimeter
of each power pin. Leadless chip capacitors are preferred
because they provide low lead inductance.
As is the case with all high-speed converters, the ADC14071
is sensitive to power supply noise. Accordingly the noise on
the analog supply pin should be kept below 10 mV
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be especially careful of this during power up.
The DR V
may be operated from a supply in the range of 2.7V to the V
pin provides power for the output drivers and
D
supply (nominal 5V). This can simplify interfacing to 3.0V devices and systems. Powering the DR V
duce power consumption and noise generation due to output
switching. DO NOT operate the DR V
higher than V
.
D
from 3V will also re-
D
pin at a voltage
D
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Separate analog and
digital ground planes that are connected close to the
ADC14071 are required to achieve specified performance.
The analog and digital grounds may be in the same layer, but
should be separated from each other and should never overlap each other.Separation should be at least
where possible.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
.
P-P
1
⁄8inch (3 mm),
process. To prevent this from happening, the DR GND pins
should not be connected to system ground in close proximity
to any of the ADC14071’s other ground pins.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and from the digital
ground plane, as well as to keep the clock line as short as
possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
D
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is very narrow compared with the
rest of the ground plane. A typical width is about 1/16 inch
(1.5 mm to 2 mm) but will depend upon the total analog
ground current that will flow through it. This narrowing provides a fairly high impedance to the high edge rates of the
digital switching currents, directing them away from the analog pins. The lower slew rate analog ground currents see a
ADC14071
DS101101-27
www.national.com15
Page 16
Applications Information (Continued)
relatively low impedance across this narrow ground connection. This implies that the power supply ground should be
ADC14071
connected to the digital ground plane.
Generally,analog and digital lines should cross each other at
90˚ to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep any clock line
as short as possible and isolated from ALL other lines, including other digital lines. Even the generally accepted 90˚
crossing should be avoided as even a little coupling can
cause problems at high frequencies. This is because other
lines can introduce phase noise (jitter) into the clock line,
which can lead to degradation of SNR. Also, the high speed
clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in
which they are used. Inductors should
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference pin and ground should be connected to a very clean
point in the analog ground plane.
Figure 8
gives an example of a suitable layout.All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog ground plane.All digital circuitry and I/O lines should be placed over the digital ground
plane. Furthermore, all components in the reference circuitry
and the input signal chain that are connected to ground
should be connected together with traces and enter the analog ground plane at a single point.
All ground connections should have a low inductance path to
ground.
not
be placed side by
FIGURE 8. Example of A Suitable Layout
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance with the
ADC14071, the clock source driving the CLK input must be
free of jitter. For best ac performance, isolate the ADC clock
from any digital circuitry with buffers, as with the clock tree
shown in
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce phase
noise (jitter) into the clock signal, which can lead to reduced
SNR performance, and the clock can introduce noise into
other lines. Even lines with 90˚ crossings have capacitive
coupling, so try to avoid even these 90˚ crossings of the
clock line.
www.national.com 16
Figure 9
.
DS101101-28
Page 17
Applications Information (Continued)
DS101101-29
FIGURE 9. Isolating the ADC Clock from other Circuitry
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300 mV beyond the supply rails (more than 300
mV below the ground pins or 300 mV above the supply pins).
Exceeding these limits on even a transient basis may cause
faulty or erratic operation. It is not uncommon for high speed
digital circuits (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot that goes above the power supply or
more than a volt below ground. A resistor of about 50Ω to
100Ω in series with the offending digital input will eliminate
the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up.
Be careful not to overdrive the inputs of the ADC14071 with
a device that is powered from supplies outside the range of
theADC14071 supply. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through DR V
current spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital ground planes will reduce this
problem.
with A Clock Tree
and DR GND. These large charging
D
Additionally, bus capacitance beyond the specified 20 pF/pin
will cause t
theADC output data. The result could, again, be an apparent
to increase, making it difficult to properly latch
OD
reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC14071, which reduces the energy coupled back into the
converter output pins by limiting the output current.A reasonable value for these resistors is 47Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the input alternates between 14 pF and 5 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a
capacitor across the analog inputs (as shown in
Figures 6, 7
will improve performance. The LM6172 has been successfully used to drive the analog inputs of the ADC14071.
Also, it is important that te signals at the two inputs have exactly the same amplitude and be exactly 180˚ out of phase
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the effective phase between these two signals. Remember that an
operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same device operating in the inverting configuration.
Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, V
the range of
1.0V ≤ V
REF
≤ 2.7V.
should be in
REF
Operating outside of these limits could lead to performance
degradation.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR performance.
ADC14071
)
www.national.com17
Page 18
Physical Dimensions inches (millimeters) unless otherwise noted
ADC14071 14-Bit, 7 MSPS, 380 mW A/D converter
48-Lead TQFP Package
Order Number ADC14071CIVBH
NS Package Number VBH48A
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