Page 1
November 2002
ADC12L063
12-Bit, 62 MSPS, 354 mW A/D Converter with Internal
Sample-and-Hold
ADC12L063 12-Bit, 62 MSPS, 354 mW A/D Converter with Internal Sample-and-Hold
General Description
The ADC12L063 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit
digital words at 62 Megasamples per second (MSPS), minimum. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-andhold circuit to minimize die size and power consumption
while providing excellent dynamic performance. Operating
on a single 3.3V power supply, this device consumes just
354 mW at 62 MSPS, including the reference current. The
Power Down feature reduces power consumption to just 50
mW.
The differential inputs provide a full scale input swing equal
±
V
to
of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
with the possibility of a single-ended input. Full use
REF
Features
n Single supply operation
n Low power consumption
n Power down mode
n On-chip reference buffer
Key Specifications
n Resolution 12 Bits
n Conversion Rate 62 MSPS(min)
n Bandwidth 170MHz
n DNL
n INL
n SNR 66 dB(typ)
n SFDR 78 dB(typ)
n Data Latency 6 Clock Cycles
n Supply Voltage +3.3V
n Power Consumption, 62 MHz 354 mW(typ)
±
0.5 LSB(typ)
±
1.0 LSB(typ)
±
300 mV
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Base Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends
Connection Diagram
20026301
© 2002 National Semiconductor Corporation DS200263 www.national.com
Page 2
Ordering Information
ADC12L063
Block Diagram
Industrial (−40˚C ≤ TA≤ +85˚C) Package
ADC12L063CIVY 32 Pin LQFP
ADC12L063CIVYX 32 Pin LQFP Tape and Reel
ADC12L063EVAL Evaluation Board
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20026302
Page 3
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
Non-Inverting analog signal Input. With a 1.0V reference
voltage the input signal level is 1.0 V
Inverting analog signal Input. With a 1.0V reference voltage
the input signal level is 1.0 V
for single-ended operation, but a differential input
to V
CM
P-P
signal is required for best performance.
Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. V
should be between 0.8V and 1.2V.
2V
3V
1V
IN
IN
REF
+
−
.
P-P
. This pin may be connected
is 1.0V nominal and
REF
ADC12L063
31 V
32 V
30 V
DIGITAL I/O
10 CLK
11 OE
RP
RM
RN
These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT connect anything else to these pins.
Digital clock input. The range of frequencies for this input is 1
MHz to 70 MHz (typical) with guaranteed performance at 62
MHz. The input is sampled on the rising edge of this input.
OE is the output enable pin that, when low, enables the
TRI-STATE data output pins. When this pin is high, the
outputs are in a high impedance state.
8PD
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
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Page 4
Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC12L063
14–19,
22–27
D0–D11
Digital data output pins that make up the 12-bit conversion
results. D0 is the LSB, while D11 is the MSB of the offset
binary output word.
ANALOG POWER
Positive analog supply pins. These pins should be connected
5, 6, 29 V
A
to a quiet +3.3V source and bypassed to AGND with 0.1 µF
monolithic capacitors located within 1 cm of these power pins,
and with a 10 µF capacitor.
4, 7, 28 AGND The ground return for the analog supply.
DIGITAL POWER
Positive digital supply pin. This pin should be connected to
the same quiet +3.3V source as is V
13 V
D
DGND with a 0.1 µF monolithic capacitor in parallel with a 10
µF capacitor, both located within 1 cm of the power pin.
Decouple this pin from the V
A
pins.
9, 12 DGND The ground return for the digital supply.
Positive digital supply pin for the ADC12L063’s output drivers.
This pin should be connected to a voltage source of +2.5V to
and bypassed to DR GND with a 0.1 µF monolithic
V
D
21 V
DR
capacitor. If the supply for this pin is different from the supply
used for V
and VD, it should also be bypassed with a 10 µF
A
tantalum capacitor. The voltage at this pin should never
exceed the voltage on V
. All bypass capacitors should be
D
located within 1 cm of the supply pin.
The ground return for the digital supply for the ADC12L063’s
output drivers. This pin should be connected to the system
20 DR GND
digital ground, but not be connected in close proximity to the
ADC12L063’s DGND or AGND pins. See Section 5.0 (Layout
and Grounding) for more details.
and bypassed to
A
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Page 5
ADC12L063
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
Soldering Temperature,
Infrared, 10 sec. (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
A,VD,VDR
|V
| ≤ 100 mV
A–VD
Voltage on Any Input or Output Pin −0.3V to V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
= 25˚C See (Note 4)
A
ESD Susceptibility
or V
A
+0.3V
±
25 mA
±
50 mA
4.2V
D
Operating Ratings (Notes 1, 2)
Operating Temperature −40˚C ≤ T
Supply Voltage (V
Output Driver Supply (V
V
Input 0.8V to 1.2V
REF
CLK, PD, OE
V
Input −0V to (VA− 0.5V)
IN
) +3.0V to +3.60V
A,VD
) +2.5V to V
DR
−0.05V to VD+ 0.05V
|AGND–DGND| ≤100mV
≤ +85˚C
A
Human Body Model (Note 5) 2500V
Machine Model (Note 5) 250V
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD=VDR= +3.3V,
PD = 0V, V
other limits T
REF
A=TJ
= +1.0V, f
= 25˚C (Notes 7, 8, 9)
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits
INL Integral Non Linearity (Note 11)
DNL Differential Non Linearity
GE Gain Error Positive Error −0.8 %FS(max)
Offset Error (V
Under Range Output Code 0 0
Over Range Output Code 4095 4095
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
C
IN
V
REF
Common Mode Input Voltage 1.0 V
VINInput Capacitance (each pin to
GND)
Reference Voltage (Note 13) 1.00
Reference Input Resistance 100 MΩ(min)
= 62 MHz, tr=tf= 2 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T
CLK
Typical
(Note 10)
±
1.0
±
0.5 LSB(max)
Negative Error +0.1
+=VIN−) +0.1
IN
VIN= 1.0 Vdc
+1V
P-P
(CLK LOW) 8 pF
(CLK HIGH) 7 pF
to T
MIN
Limits
(Note 10)
±
2.4 LSB(max)
±
3 %FS(max)
±
0.9 %FS(max)
0.8 V(min)
1.2 V(max)
MAX
Units
(Limits)
: all
D
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Page 6
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD=VDR= +3.3V, PD
REF
= +1.0V, f
A=TJ
= 0V, V
other limits T
ADC12L063
Symbol Parameter Conditions
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
V
V
I
IN(1)
I
IN(0)
C
IN(1)
IN(0)
IN
Logical “1” Input Voltage VD= 3.3V 2.0 V(min)
Logical “0” Input Voltage VD= 3.0V 0.8 V(max)
Logical “1” Input Current V
Logical “0” Input Current V
Digital Input Capacitance 5 pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
V
V
I
OZ
+I
OUT(1)
OUT(0)
SC
Logical “1” Output Voltage I
Logical “0” Output Voltage I
TRI-STATE Output Current
Output Short Circuit Source
Current
−I
SC
Output Short Circuit Sink Current V
POWER SUPPLY CHARACTERISTICS
I
A
I
D
I
DR
Analog Supply Current
Digital Supply Current
Digital Output Supply Current
Total Power Consumption
PSRR1 Power Supply Rejection
PSRR2 Power Supply Rejection
DYNAMIC CONVERTER CHARACTERISTICS
BW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 170 MHz
SNR Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
THD Total Hamonic Distortion
= 62 MHz, tr=tf= 2 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T
CLK
= 25˚C (Notes 7, 8, 9)
Typical
(Note 10)
+
−
,V
IN
IN
OUT
OUT
V
OUT
V
OUT
V
OUT
OUT=VDR
PD Pin = DGND, V
PD Pin = V
= 3.3V 10 µA
IN
+
−
,V
= 0V −10 µA
IN
= −0.5 mA 2.7 V(min)
= 1.6 mA 0.4 V(max)
= 3.3V 100 nA
= 0V −100 nA
= 0V −20 mA(min)
= 1.0V
REF
DR
102
PD Pin = DGND
PD Pin = V
DR,fCLK
=0
PD Pin = DGND, (Note 14)
PD Pin = V
DR,fCLK
PD Pin = DGND, C
PD Pin = V
DR,fCLK
=0
= 0 pF (Note 15)
L
=0
354
Rejection of Full-Scale Error with
= 3.0V vs 3.6V
V
A
SNR Degradation w/10 MHz,
250 mV
f
= 1 MHz, Differential VIN=
IN
riding on V
P-P
A
−53 dB
−0.5 dBFS
fIN= 10 MHz, Differential VIN=
−0.5 dBFS
= 1 MHz, Differential VIN=
f
IN
−0.5 dBFS
= 10 MHz, Differential VIN=
f
IN
−0.5 dBFS
fIN= 1 MHz, Differential VIN=
−0.5 dBFS
= 10 MHz, Differential VIN=
f
IN
−0.5 dBFS
fIN= 1 MHz, Differential VIN=
−0.5 dBFS
= 10 MHz, Differential VIN=
f
IN
−0.5 dBFS
10.6 Bits
10.3 10.0 Bits
−80 dB
−74 −65 dB(max)
to T
MIN
Limits
(Note 10)
20 mA(min)
140 mA(max)
4
5.3
7 mA(max)
2
<
1
0
485 mW
50
58 dB
66 dB
66 63.3 dB(min)
65 dB
65 62 dB
: all
MAX
Units
(Limits)
mA
mA
mA(max)
mA
mW
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Page 7
DC and Logic Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD=VDR= +3.3V, PD
REF
= +1.0V, f
A=TJ
= 0V, V
other limits T
Symbol Parameter Conditions
SFDR Spurious Free Dynamic Range
IMD Intermodulation Distortion
= 62 MHz, tr=tf= 2 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T
CLK
= 25˚C (Notes 7, 8, 9)
Typical
(Note 10)
= 1 MHz, Differential VIN=
f
IN
−0.5 dBFS
= 10 MHz, Differential VIN=
f
IN
−0.5 dBFS
= 9.5 MHz and 10.5 MHz,
f
IN
each = −7 dBFS
MIN
Limits
(Note 10)
to T
: all
MAX
Units
(Limits)
82 dB
78 dB(min)
−75 dBFS
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD,VDR= +3.3V, PD
REF
= +1.0V, f
A=TJ
= 0V, V
other limits T
Symbol Parameter Conditions
1
f
CLK
f
CLK
Maximum Clock Frequency 70 62 MHz(min)
2
Minimum Clock Frequency 1 MHz
Recommended Clock Duty Cycle 50 40 %(min)
t
CH
t
CL
t
CONV
t
OD
t
AD
t
AJ
t
DIS
Clock High Time 6.5 ns(min)
Clock Low Time 6.5 ns(min)
Conversion Latency 6
Data Output Delay after Rising
CLK Edge
Aperture Delay 2 ns
Aperture Jitter 1.2 ps rms
Data outputs into TRI-STATE
Mode
t
EN
Data Outputs Active after
TRI-STATE
t
PD
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
LQFP, θ
this device under normal operation will typically be about 374 mW (354 typical power consumption + 20 mW TTL output loading). The values for maximum power
dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.
Note 7: The inputs are protected as shown below. Input voltages above V
However, errors in the A/D conversion can occur if the input goes above V
voltage must be ≤3.4V to ensure accurate conversions.
Power Down Mode Exit Cycle 20 t
is 79˚C/W, so PDMAX = 1,582 mW at 25˚C and 823 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of
JA
= 62 MHz, tr=tf= 2 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T
CLK
= 25˚C (Notes 7, 8, 9, 12)
Typical
(Note 10)
= 2.5V 12 ns
V
DR
V
= 3.3V 9 13 ns(max)
DR
10 ns
10 ns
<
AGND, or V
IN
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
), and the ambient temperature, (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 32-pin
JA
J
or below GND will not damage this device, provided current is limited per (Note 3).
A
or below GND by more than 100 mV. As an example, if VAis 3.3V, the full-scale input
A
>
VA,VDor VDR), the current at that pin should be limited to
IN
to T
MIN
Limits
(Note 10)
60 %(max)
: all
MAX
Units
(Limits)
Clock
Cycles
CLK
ADC12L063
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Page 8
AC Electrical Characteristics (Continued)
ADC12L063
20026307
Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
Note 9: With the test condition for V
Note 10: Typical figures are at T
Level).
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, V
Note 13: Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ or the LM4051CIM3-1.2
bandgap voltage reference is recommended for this application.
Note 14: I
V
, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0xf0+C1xf1+....C11xf11) where VDRis the output driver power supply
DR
voltage, C
Note 15: Excludes I
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
DR
is total capacitance on the output pin, and fnis the average frequency at which that pin is toggling.
n
. See note 14.
DR
= +1.0V (2V
REF
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’sAOQL (Average Outgoing Quality
A=TJ
differential input), the 12-bit LSB is 488 µV.
P-P
= 0.4V for a falling edge and VIH= 2.4V for a rising edge.
IL
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Page 9
Specification Definitions
APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
COMMON MODE VOLTAGE (V
present at both signal inputs to the ADC.
CONVERSION LATENCY See PIPELINE DELAY.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital
waveform is high to the total time of one period. The specification here refers to the ADC clock input signal.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /
6.02 and says that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Offset Error
INTEGRAL NON LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (
1
⁄2LSB below the first code transition)
through positive full scale (
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC12L063 is guaranteed
not to have any missing codes.
NEGATIVE FULL SCALE ERROR is the difference between
+
−
the input voltage (V
−V
IN
IN
negative full scale to the next code and its ideal value of 0.5
LSB.
OFFSET ERROR is the difference between the ideal differ-
+
ential input voltage (V
–V
IN
voltage required to cause a transition from an output code
2047 to 2048.
) is the d.c. potential
CM
1
⁄2LSB above the last code
) just causing a transition from
−
= 0V) and the actual input
IN
OUTPUT DELAY is the time delay after the rising edge of
the clock before the data update is presented at the output
pins.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1
1
⁄2LSB
below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a mea-
sure of how well the ADC rejects a change in the power
supply voltage. For the ADC12L063, PSRR1 is the ratio of
the change in Full-Scale Error that results from a change in
the dc power supply voltage, expressed in dB. PSRR2 is a
measure of how well an a. c. signal riding upon the power
supply is rejected at the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first nine
harmonic levels at the output to the rms value of the input
frequency at the output. It is calculated as
where f1is the fundamental (input) frequency and f2through
are the first 9 harmonic frequencies.
f
10
ADC12L063
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Timing Diagram
ADC12L063
Transfer Characteristic
Output Timing
20026309
20026310
FIGURE 1. Transfer Characteristic
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ADC12L063
Typical Performance Characteristics V
otherwise stated
DNL vs. V
DNL vs. Temperature INL vs. V
A
20026359
A=VD=VDR
= 3.3V, f
= 62MHz, fIN= 10 MHz unless
CLK
DNL vs. Clock Duty Cycle
A
20026360
20026358
INL vs. Clock Duty Cycle INL vs. Temperature
20026363 20026366
20026362
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Page 12
Typical Performance Characteristics V
otherwise stated (Continued)
A=VD=VDR
= 3.3V, f
= 62MHz, fIN= 10 MHz unless
CLK
ADC12L063
SNR vs. V
A
20026364 20026368
SNR vs. f
SNR vs. Clock Duty Clock Cycle SNR vs. V
CLK
REF
20026371
SNR vs. Temperature THD vs. V
20026372
20026369
A
20026370
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Page 13
ADC12L063
Typical Performance Characteristics V
otherwise stated (Continued)
THD vs. f
THD vs. V
CLK
20026374
REF
A=VD=VDR
= 3.3V, f
= 62MHz, fIN= 10 MHz unless
CLK
THD vs. Clock Duty Cycle
THD vs. Temperature
20026377
SINAD vs. V
20026375
A
20026376 20026380
SINAD vs. f
CLK
20026378
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Page 14
Typical Performance Characteristics V
otherwise stated (Continued)
A=VD=VDR
= 3.3V, f
= 62MHz, fIN= 10 MHz unless
CLK
ADC12L063
SINAD vs. Duty Cycle SINAD vs. V
20026383
SINAD vs. Temperature SFDR vs. V
REF
20026381
A
SFDR vs. f
CLK
20026384
20026386
20026382
SFDR vs. Duty Cycle
20026389
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Page 15
ADC12L063
Typical Performance Characteristics V
otherwise stated (Continued)
SFDR vs. V
REF
20026387
A=VD=VDR
= 3.3V, f
= 62MHz, fIN= 10 MHz unless
CLK
SFDR vs. Temperature
20026390
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Page 16
Functional Description
Operating on a single +3.3V supply, the ADC12L063 uses a
pipelined architecture and has error correction circuitry to
help ensure maximum performance.
ADC12L063
Differential analog input signals are digitized to 12 bits. Each
analog input signal should have a peak-to-peak voltage
equal to the input reference voltage, V
around V
/2. Table 1 and Table 2 indicate the input to the
REF
output relationship of the ADC12L063. As indicated in Table
2, biasing one input to V
/2 and driving the other input with
REF
its full range signal results ina6dBreduction of the output
range, limiting it to the range of
output range obtainable if both inputs were driven with complimentary signals. Section 1.3 explains how to avoid this
signal reduction.
TABLE 1. Input to Output Relationship —
Differential Input
V
V
CM
V
CM
V
−0.5*V
CM
−0.25*V
+0.25*V
+0.5*V
CM
V
V
IN
CM
+
REF
REFVCM
REFVCM
REF
VCM+0.5*V
VCM−0.5*V
−
V
IN
+0.25*V
V
CM
−0.25*V
TABLE 2. Input to Output Relationship —
Single-Ended Input
V
V
CM
V
CM
V
+
V
IN
CM−VREF
−0.5*V
V
CM
+0.5*V
CM+VREF
REF
REF
−
V
IN
V
CM
V
CM
V
CM
V
CM
V
CM
, and be centered
REF
1
⁄4to3⁄4of the minimum
0000 0000 0000
REF
0100 0000 0000
REF
1000 0000 0000
1100 0000 0000
REF
1111 1111 1111
REF
0000 0000 0000
0100 0000 0000
1000 0000 0000
1100 0000 0000
1111 1111 1111
Output
Output
1.2 Reference Pins
The ADC12L063 is designed to operate with a 1.0V reference, but performs well with reference voltages in the range
of 0.8V to 1.2V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12L063. Increasing
the reference voltage (and the input signal swing) beyond
1.2V will degrade THD for a full-scale input. It is very important that all grounds associated with the reference voltage
and the input signal make connection to the analog ground
plane at a single point to minimize the effects of noise
currents in the ground path.
The three Reference Bypass Pins (V
RP,VRM
and VRN) are
made available for bypass purposes only. These pins should
each be bypassed to ground with a 0.1 µF capacitor. DO
NOT LOAD these pins.
1.3 Signal Inputs
The signal inputs are V
+
IN
and V
−
. The input signal, VIN,is
IN
defined as
+
=(V
V
IN
IN
)–(V
−
)
IN
Figure 2 shows the expected input signal range.
Note that the nominal input common mode voltage, V
/2, minimum and the nominal input signals each run
V
REF
between the limits of AGND and 1.0V with V
differential input signal increases above 2 V
= 1.0V. If the
REF
, the minimum
P-P
CM
,is
input common mode voltage should increase proportionally.
The Peaks of the input signals should never exceed the
voltage described as
Peak Input Voltaged = V
A
− 1.0
to maintain dynamic performance.
The output word rate is the same as the clock frequency,
which can be between 1 MSPS and 70 MSPS (typical). The
analog input voltage is acquired at the rising edge of the
clock and the digital data for that sample is delayed by the
pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the converter power consumption to 50 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12L063:
3.0 V ≤ V
V
D=VA
1.5V ≤ VDR≤ V
1 MHz ≤ f
0.8V ≤ V
1.1 Analog Inputs
The ADC12L063 has two analog signal inputs, V
These two pins form a differential input pair. There is one
reference input pin, V
A
CLK
REF
≤ 3.6V
D
≤ 70 MHz
≤ 1.2V
REF
+
and V
IN
IN
.
20026311
FIGURE 2. Expected Input Signal Range
The ADC12L063 performs best with a differential input with
each input centered around V
peak-to-peak voltage swing at both V
(minimum of 0.5V). The
CM
+
IN
and V
−
should not
IN
exceed the value of the reference voltage or the output data
will be clipped. The two input signals should be exactly 180˚
out of phase from each other and of the same amplitude. For
single frequency inputs, angular errors result in a reduction
of the effective full scale input. For a complex waveform,
however, angular errors will result in distortion.
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase, the full scale error in LSB
can be described as approximately
−
.
E
FS
= dev
1.79
Where dev is the angular difference between the two signals
having a 180˚ relative phase relationship to each other (see
Figure 3). Drive the analog inputs with a source impedance
less than 100Ω.
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Page 17
Applications Information (Continued)
20026312
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level or Cause
Distortion
For differential operation, each analog input signal should
have a peak-to-peak voltage equal to the input reference
voltage, V
ended operation, one of the analog inputs should be connected to the d.c. common mode voltage of the driven input.
The peak-to-peak differential input signal should be twice the
reference voltage to maximize SNR and SINAD performance
(Figure 2b). For example, set V
and drive V
very large input signal swings can degrade distortion performance, better performance with a single-ended input can be
obtained by reducing the reference voltage when maintaining a full-range output. Tables 1, 2 indicate the input to
output relationship of the ADC12L063.
The V
IN
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high. Although this difference is small,
a dynamic capacitance is more difficult to drive than is a
fixed capacitance, so choose the driving amplifier carefully.
The LMH6702, LMH6628, LMH6622 and LMH6655 are good
amplifiers for driving the ADC12L063.
The internal switching action at the analog inputs causes
energy to be output from the input pins. As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 33Ω series resistors at each of the signal
inputs with a 10 pF capacitor across the inputs, as can be
seen in Figure 5 and Figure 6. These components should be
placed close to the ADC because the input pins of the ADC
is the most sensitive part of the system and this is the last
opportunity to filter the input. The 10 pF capacitor value is for
undersampling application and should be replaced with a
68 pF capacitor for Nyquist application.
2.0 DIGITAL INPUTS
Digital inputs consist of CLK, OE and PD.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 1 MHz to 70 MHz with rise and fall times of less
than 2 ns. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency is too low, the charge on
internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the
lowest sample rate to 1 MSPS.
, and be centered around VCM. For single
REF
to 1.0V, bias V
+
with a signal range of 0V to 2.0V. Because
IN
+
and the V
−
inputs of the ADC12L063 consist of an
IN
REF
−
IN
to 1.0V
The CLOCK signal also drives an internal state machine. If
the clock is interrupted, or its frequency is too low, the charge
on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade.
The duty cycle of the clock signal can affect the performance
of any A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC12L063 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 35% to 65%.
The clock line should be series terminated in the characteristic impedance of that line at the clock source. If the clock
line is longer than
where tris the clock rise t
is the propagation rate of the
prop
signal along the trace. The CLOCK pin should be a.c. terminated with a series RC such that the resistor value is equal
to the characteristic impedance of the clock line and the
capacitor value is
where "I" is the line length in inches and Zois the characteric
impedance of the clock line. This termination should be
located as close as possible to, but within one centimeter of,
the ADC12L063 clock pin as shown in Figure 4. A typical
propagation rate on FR4 material is about 150ps/inch, or
about 60ps/cm.
2.2 OE
The OE pin, when high, puts the output pins into a high
impedance state. When this pin is low the outputs are in the
active state. The ADC12L063 will continue to convert
whether this pin is high or low, but the output can not be read
while the OE pin is high.
2.3 PD
The PD pin, when high, holds the ADC12L063 in a powerdown mode to conserve power when the converter is not
being used. The power consumption in this state is 50 mW.
The output data pins are undefined in this mode. Power
consumption during power-down is not affected by the clock
frequency, or by whether there is a clock signal present. The
data in the pipeline is corrupted while in the power down
mode.
3.0 OUTPUTS
The ADC12L063 has 12 TTL/CMOS compatible Data Output
pins. The offset binary data is present at these outputs while
the OE and PD pins are low. While the t
time provides
OD
information about output timing, a simple way to capture a
valid output is to latch the data on the rising edge of the
conversion clock (pin 10).
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
and DR GND. These large charging current
DR
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
ADC12L063
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Page 18
Applications Information (Continued)
bypassing and careful attention to the ground plane will
reduce this problem. Additionally, bus capacitance beyond
ADC12L063
the specified 20 pF/pin will cause t
difficult to properly latch the ADC output data. The result
could be an apparent reduction in dynamic performance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connecting buffers between the ADC outputs and any other circuitry
to increase, making it
OD
(74ACQ541, for example). Only one input should be connected to each output pin. Additionally, inserting series resistors of 47Ω to 56Ω at the digital outputs, close to the ADC
pins, will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4.
While the ADC12L063 will operate with V
to 2.5V, t
increases with reduced VDR. Be careful of
OD
external timing when using reduced V
DR
.
DR
voltages down
FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer
20026313
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Page 19
Applications Information (Continued)
FIGURE 5. Differential Drive Circuit of Figure 4
ADC12L063
20026314
FIGURE 6. Driving the Signal Inputs with a Transformer
20026315
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Page 20
Applications Information (Continued)
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF
ADC12L063
capacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the
ADC12L063 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100
.
mV
P-P
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be especially careful of this during turn on and turn off of power.
The V
be operated from a supply in the range of 2.5V to V
(nominal 3.3V). This can simplify interfacing to 3V devices
and systems. DO NOT operate the V
higher than V
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the ADC12L063
between these areas, is required to achieve specified performance.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
pin provides power for the output drivers and may
DR
pin at a voltage
.
D
DR
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close proximity to any of the ADC12L063’s other ground pins.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry
separated from the digital circuitry, and to keep the clock line
as short as possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have significant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
D
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T)
families.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 47Ω to 56Ω
resistors in series with each data output line. Locate these
resistors as close to the ADC output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
FIGURE 7. Example of a Suitable Layout
Generally, analog and digital lines should cross each other at
90˚ to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90˚ crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because
www.national.com 20
20026316
other lines can introduce jitter into the clock line, which can
lead to degradation of SNR. Also, the high speed clock can
introduce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
Page 21
Applications Information (Continued)
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very
clean point in the analog ground plane.
Figure 7 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog ground plane. All digital
circuitry and I/O lines should be placed over the digital
ground plane. Furthermore, all components in the reference
circuitry and the input signal chain that are connected to
ground should be connected together with short traces and
enter the analog ground plane at a single point. All ground
connections should have a low inductance path to ground.
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 8.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines.
Even lines with 90˚ crossings have capacitive coupling, so
try to avoid even these 90˚ crossings of the clock line.
20026317
FIGURE 8. Isolating the ADC Clock from other Circuitry
with a Clock Tree
7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 50Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12L063 with
a device that is powered from supplies outside the range of
the ADC12L063 supply. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
and DR GND. These large charging cur-
DR
rent spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital areas on the pc board will reduce
this problem.
Additionally, bus capacitance beyond the specified 20 pF/pin
will cause t
to increase, making it difficult to properly latch
OD
the ADC output data. The result could, again, be an apparent
reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC12L063, which reduces the energy coupled back into
the converter output pins by limiting the output current. A
reasonable value for these resistors is 47Ω to 56Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the
input alternates between 8 pF and 7 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a
capacitor across the analog inputs (as shown in Figures 5, 6)
will improve performance. The LMH6702, LMH6622 and
LMH6628 have been successfully used to drive the analog
inputs of the ADC12L063.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180
o
out of phase
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the
effective phase between these two signals. Remember that
an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same
device operating in the inverting configuration.
Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, V
should be in
REF
the range of
0.8V ≤ V
REF
≤ 1.2V
Operating outside of these limits could lead to performance
degradation.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance.
ADC12L063
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Page 22
Physical Dimensions inches (millimeters)
unless otherwise noted
32-Lead LQFP Package
Ordering Number ADC12L063CIVY
NS Package Number VBE32A
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1. Life support devices or systems are devices or
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into the body, or (b) support or sustain life, and
ADC12L063 12-Bit, 62 MSPS, 354 mW A/D Converter with Internal Sample-and-Hold
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
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