Page 1
ADC12L030/ADC12L032/ADC12L034/ADC12L038
3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold
June 1999
ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O
A/D Converters with MUX and Sample/Hold
General Description
The ADC12L030 family is 12-bit plus sign successive approximation A/D converters with serial I/O and configurable
input multiplexers. These devices are fully tested with a
single 3.3Vpowersupply. TheADC12L032,ADC12L034 and
ADC12L038 have 2, 4 and 8 channel multiplexers, respectively. Differential multiplexer outputs and A/D inputs are
available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2
pins. The ADC12L030 has a two channel multiplexer withthe
multiplexer outputs and A/D inputs internally connected. On
request, these A/Ds go through a self calibration process
that adjusts linearity, zero and full-scale errors to less than
1
±
⁄2LSB each.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes.A fully differential unipolar analog
input range (0V to +3.3V) can be accommodated with a
single +3.3V supply. In the differential modes, valid outputs
are obtained even when the negative inputs are greater than
the positive because of the 12-bit plus sign two’s compliment
output data format.
The serial I/O is configured to comply with NSC’s
MICROWIRE
references, see the LM4040 or LM4041 data sheets.
™
and Motorola’s SPI standards. For voltage
ADC12L038 Simplified Block Diagram
Features
n 0V to 3.3V analog input range with single 3.3V power
supply
n Serial I/O ( MICROWIRE and SPI Compatible)
n 2, 4, or 8 channel differential or single-ended multiplexer
n Analog input sample/hold function
n Power down mode
n Variable resolution and conversion rate
n Programmable acquisition time
n Variable digital output word length and format
n No zero or full scale adjustment required
n Fully tested and guaranteed with a 2.5V reference
n No Missing Codes over temperature
Key Specifications
n Resolution 12-bit plus sign
n 12-bit plus sign conversion time 8.8 µs (min)
n 12-bit plus sign sampling rate 73 kHz (max)
n Integral linearity error
n Single supply 3.3V
n Power dissipation 15 mW (max)
n Power down 40 µW (typ)
±
1 LSB (max)
±
10
Applications
n Portable Medical instruments
n Portable computing
n Portable Test equipment
%
DS011830-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
COPS
microcontrollers, HPC™and MICROWIRE™are trademarks of National Semiconductor Corporation.
™
Microsoft
is a trademark of Microsoft Corporation.
© 1999 National Semiconductor Corporation DS011830 www.national.com
Page 2
Ordering Information
Industrial Temperature Range NS Package
−40˚C ≤ T
≤ +85˚C Number
A
ADC12L030CIWM M16B
ADC12L032CIWM M20B
ADC12L034CIWM M24B
ADC12L038CIWM M28B
Connection Diagrams
16-Pin Wide Body
SO Packages
Top View
20-Pin Wide Body
SO Packages
24-Pin Wide Body
SO Packages
DS011830-2
DS011830-4
Top View
248-Pin Wide Body
SO Packages
DS011830-3
Top View
www.national.com 2
DS011830-5
Top View
Page 3
Pin Descriptions
CCLK The clock applied to this input controls the su-
SCLK This is the serial data clock input. The clock
DI This is the serial data input pin. The data ap-
DO The data output pin. This pin is an active push/
EOC This pin is an active push/pull output and indi-
CS
cessive approximation conversion time interval
and the acquisition time. The rise and fall times
of the clock edges should not exceed 1 µs.
applied to this input controls the rate at which
the serial data exchange occurs. The rising
edge loads the information on the DI pin into
the multiplexer address and mode select shift
register. This address controls which channel
of the analog input multiplexer (MUX) is selected and the mode of operation for the A/D.
With CS low the falling edge of SCLK shifts the
data resulting from the previous ADC conversion out on DO, with the exception of the first
bit of data. When CS is low continuously, the
first bit of the data is clocked out on the rising
edge of EOC (end of conversion). When CS is
toggled the falling edge of CS always clocks
out the first bit of data. CS should be brought
low when SCLK is low. The rise and fall times
of the clock edges should not exceed 1 µs.
plied to this pin is shifted by the rising edge of
SCLK into the multiplexer address and mode
select register.
Tables 2, 3, 4, 5
show the assignment of the multiplexer address and the
mode select data.
pull output when CS is Low. When CS is High
this output is in TRI-STATE. The A/D conversion result(D0–D12) and converter status data
are clocked out by the falling edge of SCLK on
this pin. The word length and format of this result can vary (see
Table 1
). The word length
and format are controlled by the data shifted
into the multiplexer address and mode select
register (see
Table 5
).
cates the status of the ADC12L030/2/4/8.
When low, it signals that the A/D is busy with a
conversion, auto-calibration, auto-zero or
power down cycle. The rising edge of EOC signals the end of one of these cycles.
This is the chip select pin. When a logic low is
applied to this pin, the rising edge of SCLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE.
With CS low the falling edge of SCLK shifts the
data resulting from the previous ADC conversion out on DO, with the exception of the first
bit of data. When CS is low continuously, the
first bit of the data is clocked out on the rising
edge of EOC (end of conversion). When CS is
toggled the falling edge of CS always clocks
out the first bit of data. CS should be brought
low when SCLK is low. The falling edge of CS
resets a conversion in progress and starts the
sequence for a new conversion. When CS is
brought back low during a conversion, that
conversion is prematurely ended. The data in
the output latches may be corrupted. Therefore, when CS is brought back low during a
conversion in progress the data output at that
time should be ignored. CS may also be left
continuously low. In this case it is imperative
that the correct number of SCLK pulses be applied to the ADC in order to remain synchronous. After theADC supply power is applied, it
expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADC
expects is the same as the digital output word
length. This word length can be modified by
the data shifted in on the DO pin.
Table 5
de-
tails the data required.
DOR
This is the data output ready pin. This pin is an
active push/pull output. It is low when the conversion result is being shifted out and goes
high to signal that all the data has been shifted
out.
CONV
A logic low is required on this pin to program
any mode or change the ADC’s configuration
as listed in the Mode Programming Table
(
Table 5
) such as 12-bit conversion, 8-bit conversion,Auto Cal, Auto Zero etc. When this pin
is high the ADC is placed in the read data only
mode. While in the read data only mode, bringing CS low and pulsing SCLK will only clock
out on DO any data stored in the ADCs output
shift register. The data on DI will be neglected.
A new conversion will not be started and the
ADC will remain in the mode and/or configuration previously programmed. Read data only
cannot be performed while a conversion,
Auto-Cal or Auto-Zero are in progress.
PD This is the power down pin. When PD is high
the A/D is powered down; when PD is low the
A/D is powered up. The A/D takes a maximum
of 700 µs to power up after the command is
given.
CH0–CH7 These are the analog inputs of the MUX. A
channel input is selected by the address information at the DI pin, which is loaded on the rising edge of SCLK into the address register
(see
Tables 2, 3, 4
).
The voltage applied to these inputs should not
exceed V
range on an unselected channel will corrupt
+ or go below GND. Exceeding this
A
the reading of a selected channel.
COM This pin is another analog input pin. It is used
as a pseudo ground when the analog multiplexer is single-ended.
MUXOUT1,
MUXOUT2
A/DIN1,
A/DIN2
These are the multiplexer output
pins.
These are the converter input pins. MUXOUT1
is usually tied to A/DIN1. MUXOUT2 is usually
tied toA/DIN2. If external circuitry is placed between MUXOUT1 and A/DIN1, or MUXOUT2
and A/DIN2 it may be necessary to protect
these pins. The voltage at these pins should
not exceed V
5
).
+ This is the positive analog voltage reference
V
REF
input. In order to maintain accuracy the voltage
range of V
+
or go belowAGND (see
A
=
REF(VREF
V
REF
+−V
REF
Figure
−) is
www.national.com3
Page 4
Pin Descriptions (Continued)
1V
to 3.3 VDCand the voltage at V
DC
not exceed V
mended bypassing.
V
− The negative voltage reference input. In order
REF
to maintain accuracy the voltage at this pin
+. See
A
Figure 6
must not go below GND or exceed V
Figure 6
).
+, VD+ These are the analog and digital power supply
V
A
+
pins. V
A
on the chip. These pins should be tied to the
+
and V
are not connected together
D
same power supply and bypassed separately
(see
Figure 6
V
+ and VD+ is 3.0 VDCto 5.5 VDC.
A
). The operating voltage range of
DGND This is the digital ground pin (see
AGND This is the analog ground pin (see
REF
for recom-
A
Figure 6
Figure 6
+ can-
+. (See
).
).
www.national.com 4
Page 5
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage
+
=
+=VD+) 6.5V
V
(V
Voltage at Inputs and Outputs
Voltage at Analog Inputs
|V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at
A
+
except CH0–CH7 and COM −0.3V to V
CH0–CH7 and COM GND −5V to V
+−VD+| 300 mV
A
=
25˚C (Note 4) 500 mW
T
A
+0.3V
+
±
30 mA
±
120 mA
+5V
Operating Ratings (Notes 1, 2)
Operating Temperature Range T
ADC12L030CIWM,
ADC12L032CIWM,
ADC12L034CIWM,
ADC12L038CIWM −40˚C ≤ T
Supply Voltage
+
=
+=VD+) +3.0V to +5.5V
V
(V
A
+−VD+| ≤ 100 mV
|V
A
+ 0VtoVA+
V
REF
− 0VtoV
V
REF
V
REF(VREF
V
REF
+−V
−) 1V to VA+
REF
Common Mode Voltage Range
ESD Susceptability (Note 5)
Human Body Model 1500V
Soldering Information
N Packages (10 seconds) 260˚C
SO Package (Note 6):
A/DIN1, A/DIN2, MUXOUT1
and MUXOUT2 Voltage Range 0V to V
A/D IN Common Mode Voltage Range
Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
The following specifications apply for V
sion mode, f
1.250V common-mode voltage, and 10(t
to T
T
MIN
Symbol Parameter Conditions Typical
=
f
CK
SK
; all other limits T
MAX
=
5 MHz, R
+
=
+=VD+=+3.3 VDC,V
V
A
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply for T
CK
=
=
T
25˚C. (Notes 7, 8, 9)
A
J
+=+2.500 VDC,V
REF
+ and V
REF
REF
− ≤ 25Ω, fully-differential input with fixed
REF
(Note 10)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 + sign Bits (min)
+ILE Positive Integral Linearity Error After Auto-Cal (Notes 12, 18)
−ILE Negative Integral Linearity Error After Auto-Cal (Notes 12, 18)
±
1/2
±
1/2
DNL Differential Non-Linearity After Auto-Cal
Positive Full-Scale Error After Auto-Cal (Notes 12, 18)
Negative Full-Scale Error After Auto-Cal (Notes 12, 18)
Offset Error After Auto-Cal (Notes 5, 18)
V
(+)=VIN(−)=1.250V
IN
DC Common Mode Error After Auto-Cal (Note 15)
TUE Total Unadjusted Error After Auto-Cal
±
1/2
±
1/2
±
1/2
±
2
±
1 LSB
(Notes 12, 13, 14)
Resolution with No Missing Codes 8-bit + sign mode 8 + sign Bits (min)
+INL Positive Integral Linearity Error 8-bit + sign mode (Note 12)
−INL Negative Integral Linearity Error 8-bit + sign mode (Note 12)
DNL Differential Non-Linearity 8-bit + sign mode
Positive Full-Scale Error 8-bit + sign mode (Note 12)
Negative Full-Scale Error 8-bit + sign mode (Note 12)
Offset Error 8-bit + sign mode,
after Auto-Zero (Note 13)
V
(+)=VIN(−)=+ 1.250V
IN
TUE Total Unadjusted Error 8-bit + sign mode
after Auto-Zero
(Notes 12, 13, 14)
≤ TA≤ T
MIN
≤ +85˚C
A
MAX
REF
−=0VDC, 12-bit + sign conver-
=
=
T
A
J
Limits Units
(Note 11)
±
1 LSB (max)
±
1 LSB (max)
±
1 LSB (max)
±
2 LSB (max)
±
2 LSB (max)
±
2 LSB (max)
±
3.5 LSB (max)
±
1/2 LSB (max)
±
1/2 LSB (max)
±
3/4 LSB (max)
±
1/2 LSB (max)
±
1/2 LSB (max)
±
1/2 LSB (max)
±
3/4 LSB (max)
(Limits)
+
+
A
www.national.com5
Page 6
Converter Electrical Characteristics (Continued)
+
The following specifications apply for V
sion mode, f
1.250V common-mode voltage, and 10(t
to T
T
MIN
=
f
CK
SK
; all other limits T
MAX
=
5 MHz, R
A
Symbol Parameter Conditions Typical
STATIC CONVERTER CHARACTERISTICS
Multiplexer Channel to Channel
Matching
Power Supply Sensitivity V
+ Full-Scale Error
− Full-Scale Error
+ Integral Linearity Error
− Integral Linearity Error
Output Data from (Note 20) +10 LSB (max)
“12-Bit Conversion of Offset” −10 LSB (min)
(see
Table 5
)
Output Data from (Note 20) 4095 LSB (max)
“12-Bit Conversion of Full-Scale” 4093 LSB (min)
(see
Table 5
)
UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plus f
Distortion Ratio f
−3 dB Full Power Bandwidth V
DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plus f
Distortion Ratio f
−3 dB Full Power Bandwidth V
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
C
REF
C
A/D
Reference Input Capacitance 85 pF
A/DIN1 and A/DIN2 Analog Input 75 pF
Capacitance
A/DIN1 and A/DIN2 Analog Input V
Leakage Current V
CH0–CH7 and COM Input Voltage GND − 0.05 V (min)
C
CH
C
MUXOUT
CH0–CH7 and COM Input
Capacitance
MUX Output Capacitance 20 pF
Off Channel Leakage (Note 16) On Channel=3.3V and −0.01 −0.3 µA (min)
CH0–CH7 and COM Pins Off Channel=0V
On Channel Leakage (Note 16) On Channel=3.3V and 0.01 0.3 µA (max)
CH0–CH7 and COM Pins Off Channel=0V
=
+=VD+=+3.3 VDC,V
V
A
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply for T
CK
=
=
T
25˚C. (Notes 7, 8, 9)
J
+
=
Offset Error
=
IN
=
IN
=
f
IN
IN
drops 3 dB
=
IN
=
IN
=
f
IN
IN
drops 3 dB
IN
IN
On Channel=0V and 0.01 0.3 µA (max)
Off Channel=3.3V
On Channel=0V and −0.01 −0.3 µA (min)
Off Channel=3.3V
REF
REF
±
%
10
+3.3V
1 kHz, V
20 kHz, V
40 kHz, V
=
2.5 V
1 kHz, V
20 kHz, V
40 kHz, V
=
±
=
+3.3V or
=
0V
=
IN
=
IN
=
IN
, where S/(N+D)
PP
=
IN
=
IN
=
IN
2.5V, where S/(N+D)
+=+2.500 VDC,V
+ and V
− ≤ 25Ω, fully-differential input with fixed
REF
REF
(Note 10)
±
0.05 LSB
±
0.5
±
0.5
±
0.5
±
0.5 LSB
±
0.5 LSB
2.5 V
2.5 V
2.5 V
PP
PP
PP
69.4 dB
68.3 dB
65.7 dB
31 kHz
±
2.5V 77.0 dB
±
2.5V 73.9 dB
±
2.5V 67.0 dB
40 kHz
±
0.1
10 pF
−=0VDC, 12-bit + sign conver-
=
=
T
A
J
Limits Units
(Note 11)
±
1 LSB (max)
±
1.5 LSB (max)
±
1.5 LSB (max)
±
1.0 µA (max)
V
+ + 0.05 V (max)
A
(Limits)
www.national.com 6
Page 7
Converter Electrical Characteristics (Continued)
+
The following specifications apply for V
sion mode, f
1.250V common-mode voltage, and 10(t
to T
T
MIN
=
f
CK
SK
; all other limits T
MAX
=
5 MHz, R
A
Symbol Parameter Conditions Typical
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
MUXOUT1 and MUXOUT2 V
Leakage Current V
R
ON
MUX On Resistance V
R
Matching Channel to Channel V
ON
Channel to Channel Crosstalk V
MUX Bandwidth 90 kHz
=
+=VD+=+3.3 VDC,V
V
A
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply for T
CK
=
=
T
25˚C. (Notes 7, 8, 9)
J
MUXOUT
MUXOUT
IN
V
MUXOUT
IN
V
MUXOUT
IN
+=+2.500 VDC,V
REF
REF
+ and V
REF
REF
− ≤ 25Ω, fully-differential input with fixed
(Note 10)
=
3.3V or 0.01 0.3 µA (max)
=
0V
=
1.65V and 1300 1900 Ω (max)
=
1.55V
=
1.65V and 5
=
1.55V
=
3.3 V
=
40 kHz −72 dB
PP,fIN
−=0VDC, 12-bit + sign conver-
=
=
T
A
J
Limits Units
(Note 11)
(Limits)
%
DC and Logic Electrical Characteristics
The following specifications apply for V
sion mode, f
1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for T
to T
T
MIN
=
f
CK
SK
; all other limits T
MAX
=
5 MHz, R
+
=
+=VD+=+3.3 VDC,V
V
A
=
25Ω, source impedance for V
S
=
=
T
25˚C. (Notes 7, 8, 9)
A
J
+=+2.500 VDC,V
REF
+ and V
REF
−=0VDC, 12-bit + sign conver-
REF
− ≤ 25Ω, fully-differential input with fixed
REF
=
=
T
A
J
Symbol Parameter Conditions Typical Limits Units
(Note 10) (Note 11) (Limits)
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
+
V
V
I
I
IN(1)
IN(0)
Logical “1” Input Voltage V
IN(1)
Logical “0” Input Voltage V
IN(0)
Logical “1” Input Current V
Logical “0” Input Current V
=
3.6V 2.0 V (min)
+
=
3.0V 0.8 V (max)
=
3.3V 0.005 1.0 µA (max)
IN
=
0V −0.005 −1.0 µA (min)
IN
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
V
V
I
+I
−I
OUT
Logical “1” Output Voltage V
OUT(1)
Logical “0” Output Voltage V
OUT(0)
TRI-STATE®Output Current V
Output Short Circuit Source Current V
SC
Output Short Circuit Sink Current V
SC
=
3.0V, I
+
=
V
3.0V, I
+
=
3.0V, I
=
OUT
=
V
OUT
=
OUT
=
OUT
=
−360 µA 2.4 V (min)
OUT
=
−10µA 2.9 V (min)
OUT
=
1.6 mA 0.4 V (max)
OUT
0V −0.1 −3.0 µA (max)
3.3V 0.1 3.0 µA (max)
0V 14 6.5 mA (min)
+168.0 mA (min)
V
D
+
POWER SUPPLY CHARACTERISTICS
I
+ Digital Supply Current Awake 1.1 1.5 mA (max)
D
I
+ Positive Analog Supply Current Awake 2.2 3.0 mA (max)
A
I
REF
Reference Input Current Awake 70 µA
CS=HIGH, Powered Down, CCLK on
CS=HIGH, Powered Down, CCLK off
CS=HIGH, Powered Down, CCLK on
CS=HIGH, Powered Down, CCLK off
CS=HIGH, Powered Down
600 µA
12 µA
10 µA
0.1 µA
0.1 µA
www.national.com7
Page 8
AC Electrical Characteristics
The following specifications apply for V
sion mode, t
with fixed 1.250V common-mode voltage, and 10(t
=
T
J
=
=
t
3 ns, f
r
f
=
to T
T
MIN
CK
; all other limits T
MAX
+
=
=
5 MHz, R
=
A
A
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply for T
CK
=
T
25˚C. (Note 17)
J
=
f
SK
+=VD+=+3.3 VDC,V
V
+=+2.500 VDC,V
REF
REF
+ and V
−=0VDC, 12-bit + sign conver-
REF
− ≤ 25Ω, fully-differential input
REF
Symbol Parameter Conditions Typical Limits Units
(Note 10) (Note 11) (Limits)
f
CK
Conversion Clock (CCLK) Frequency 10 5 MHz (max)
1 MHz (min)
f
SK
Serial Data Clock SCLK Frequency 10 5 MHz (max)
0 Hz (min)
Conversion Clock Duty Cycle 40
60
Serial Data Clock Duty Cycle 40
60
t
C
Conversion Time 12-Bit + Sign or 12-Bit 44(tCK) 44(tCK) (max)
%
%
%
%
(min)
(max)
(min)
(max)
8.8 µs (max)
8-Bit + Sign or 8-Bit 21(t
) 21(tCK) (max)
CK
4.2 µs (max)
t
A
Acquisition Time 6 Cycles Programmed 6(tCK) 6(tCK) (min)
(Note 19) 7(t
) (max)
CK
1.2 µs (min)
1.4 µs (max)
10 Cycles Programmed 10(t
) 10(tCK) (min)
CK
11(t
) (max)
CK
2.0 µs (min)
2.2 µs (max)
18 Cycles Programmed 18(t
) 18(tCK) (min)
CK
19(t
) (max)
CK
3.6 µs (min)
3.8 µs (max)
34 Cycles Programmed 34(t
) 34(tCK) (min)
CK
35(t
) (max)
CK
6.8 µs (min)
7.0 µs (max)
t
CAL
Self-Calibration Time 4944(tCK) 4944(tCK) (max)
988.8 µs (max)
t
AZ
Auto-Zero Time 76(tCK) 76(tCK) (max)
15.2 µs (max)
t
SYNC
Self-Calibration or Auto-Zero 2(tCK) 2(tCK) (min)
Synchronization Time 3(t
) (max)
CK
from DOR 0.40 µs (min)
0.60 µs (max)
t
DOR
DOR High Time when CS is Low
Continuously
for Read Data and Software Power
9(t
) 9(tSK) (max)
SK
1.8 µs (max)
Up/Down
t
CONV
CONV Valid Data Time 8(tSK) 8(tSK) (max)
1.6 µs (max)
t
HPU
Hardware Power-Up Time, Time from 250 700 µs (max)
PD Falling Edge to EOC Rising Edge
A
www.national.com 8
Page 9
AC Electrical Characteristics (Continued)
+
The following specifications apply for V
sion mode, t
with fixed 1.250V common-mode voltage, and 10(t
=
T
J
=
=
t
r
f
=
to T
T
MIN
MAX
=
3 ns, f
CK
; all other limits T
Symbol Parameter Conditions Typical Limits Units
t
SPU
Software Power-Up Time, Time from
EOC Rising Edge
t
ACC
Access Time Delay from 25 60 ns (max)
CS Falling Edge to DO Data Valid
t
SET-UP
Set-Up Time of CS Falling Edge to 50 ns (min)
Serial Data Clock Rising Edge
t
DELAY
Delay from SCLK Falling 0 5 ns (min)
Edge to CS Falling Edge
t1H,t0HDelay from CS Rising Edge to R
DO TRI-STATE
t
HDI
DI Hold Time from Serial Data 5 15 ns (min)
Clock Rising Edge
t
SDI
DI Set-Up Time from Serial Data 5 10 ns (min)
Clock Rising Edge
t
HDO
DO Hold Time from Serial Data R
Clock Falling Edge 5 ns (min)
t
DDO
Delay from Serial Data Clock 50 90 ns (max)
Falling Edge to DO Data Valid
t
RDO
DO Rise Time, TRI-STATE to High R
DO Rise Time, Low to High 10 40 ns (max)
t
FDO
DO Fall Time, TRI-STATE to Low R
DO Fall Time, High to Low 15 40 ns (max)
t
CD
Delay from CS Falling Edge 50 80 ns (max)
to DOR Falling Edge
t
SD
Delay from Serial Data Clock Falling 45 80 ns (max)
Edge to DOR Rising Edge
C
IN
C
OUT
Note 1: Absolute Maximum Ratingsindicate limits beyond which damageto the device may occur.Operating Ratings indicate conditions for which the deviceis functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
T
Capacitance of Logic Inputs 10 pF
Capacitance of Logic Outputs 20 pF
) at any pin exceeds the power supplies (V
IN
max=150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow:
J
f
SK
=
5 MHz, R
A
D
=
+=VD+=+3.3 VDC,V
V
A
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply for T
=
T
25˚C. (Note 17)
J
CK
=
+=+2.500 VDC,V
REF
REF
+ and V
−=0VDC, 12-bit + sign conver-
REF
− ≤ 25Ω, fully-differential input
REF
(Note 10) (Note 11) (Limits)
500 700 µs (max)Serial Data Clock Falling Edge to
=
=
3k, C
L
=
L
=
L
=
L
=
max − TA)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
(T
J
100 pF 70 100 ns (max)
L
=
3k, C
100 pF 35 65 ns (max)
L
=
3k, C
100 pF 10 40 ns (max)
L
=
3k, C
100 pF 15 40 ns (max)
L
IN
<
GND or V
>
VA+orVD+), the current at that pin should be limited to 20 mA.
IN
max, θJAand the ambient temperature, TA. The maximum
J
A
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Page 10
AC Electrical Characteristics (Continued)
Thermal
Part Number Resistance
θ
ADC12L030CIWM 70˚C/W
ADC12L032CIWM 64˚C/W
ADC12L034CIWM 57˚C/W
ADC12L038CIWM 50˚C/W
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 6: SeeAN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semi-
conductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Twoon-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V
will not damage this device. However, errors in theA/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above V
to ensure accurate conversions.
V
DC
Note 8: Toguarantee accuracy, it is required that the V
pin.
Note 9: With the test condition for V
Note 10: Typicals are at T
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between 1 to 0 and 0 to +1 (see
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 18: TheADC12L030 family’s self-calibration technique ensures linearity and offseterrors as specified, but noise inherent in the self-calibration process will re-
sult in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then t
Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
REF(VREF
=
=
T
25˚C and represent most likely parametric norm.
J
A
Figure 4
+ or below GND by more than 50 mV. As an example, if VA+ is 3.0 VDC, full-scale input voltage must be ≤3.05
A
+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V
A
+−V
−) given as +2.500V the 12-bit LSB is 610 µV and the 8-bit LSB is 9.8 mV.
REF
).
=
0.4V for a falling edge and V
IL
is 6, 10, 18 or 34 clock periods minimum and maximum.
A
JA
+ or 5V below GND
A
DS011830-6
Figure 2
and
Figure 3
).
=
2.4V for a rising edge. TRI-STATE output voltage is forced
IH
+
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Page 11
AC Electrical Characteristics (Continued)
FIGURE 1. Transfer Characteristic
DS011830-7
DS011830-8
FIGURE 2. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
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Page 12
AC Electrical Characteristics (Continued)
FIGURE 3. Simplified Error Curve vs Output Code after Auto-Calibration Cycle
DS011830-9
DS011830-10
FIGURE 4. Offset or Zero Error Voltage
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9)
Linearity Error Change
vs Temperature
DS011830-51
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Full-Scale Error Change
vs Temperature
Full-Scale Error Change
vs Supply Voltage
DS011830-52
DS011830-53
Page 13
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note
9) (Continued)
Zero Error Change
vs Temperature
Digital Supply Current
vs Temperature
Test Circuits
DS011830-54
DS011830-57
Zero Error Change
vs Supply Voltage
DS011830-55
Analog Supply Current
vs Temperature
DS011830-56
DO “TRI-STATE” (t1H,t0H)
DO except “TRI-STATE”
DS011830-15
DS011830-16
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Page 14
Test Circuits (Continued)
Timing Diagrams
Leakage Current
DS011830-17
DO Falling and Rising Edge
DS011830-18
DO “TRI-STATE” Falling and Rising Edge
DS011830-19
DI Data Input Timing
DS011830-20
DO Data Output Timing Using CS
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DS011830-21
Page 15
Timing Diagrams (Continued)
DO Data Output Timing with CS Continuously Low
DS011830-22
ADC12L038 Auto Cal or Auto Zero
Note: DO output data is not valid during this cycle.
DS011830-23
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Page 16
Timing Diagrams (Continued)
ADC12L038 Read Data without Starting a Conversion Using CS
ADC12L038 Read Data without Starting a Conversion with CS Continuously Low
DS011830-24
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DS011830-25
Page 17
Timing Diagrams (Continued)
ADC12L038 Conversion Using CS with 8-Bit Digital Output Format
ADC12L038 Conversion Using CS with 16-Bit Digital Output Format
DS011830-26
DS011830-27
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Page 18
Timing Diagrams (Continued)
ADC12L038 Conversion with CS Continuously Low and 8-Bit Digital Output Format
ADC12L038 Conversion with CS Continuously Low and 16-Bit Digital Output Format
DS011830-28
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DS011830-29
Page 19
Timing Diagrams (Continued)
ADC12L038 Software Power Up/Down Using CS with 16-Bit Digital Output Format
ADC12L038 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format
DS011830-30
DS011830-31
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Page 20
Timing Diagrams (Continued)
ADC12L038 Hardware Power Up/Down
Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will
be stored in the output shift register.
DS011830-32
ADC12L038 Configuration Modification— Example of a Status Read
Note: In order for all 9 bits of status information to be accessible the last conversion programmed before Cycle N needs to have a resolution of 8 bits plus sign,
12 bits, 12 bits plus sign, or greater.
DS011830-33
FIGURE 5. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins
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DS011830-34
Page 21
Timing Diagrams (Continued)
*
Tantalum
**
Monolithic Ceramic or better
DS011830-35
FIGURE 6. Recommended Power Supply Bypassing and Grounding
Tables
TABLE 1. Data Out Formats
DO Formats DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16
with
Sign
17 X X X X Sign MSB 10 987654321LSB
Bits
MSB 13 Sign MSB 10 9 8 7 6 5432 1LSB
First Bits
9 Sign MSB 6 5 4 3 2 1 LSB
Bits
17 LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign XXXX
Bits
LSB 13 LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign
First Bits
9 LSB 1 2 3 4 5 6 MSB Sign
Bits
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Page 22
Tables (Continued)
TABLE 1. Data Out Formats (Continued)
DO Formats DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16
without
Sign
X=High or Low state.
Address with A/DIN1 tied to MUXOUT1 Assignment Channel
DI0 DI1 DI2 DI3 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2
LLLL+− + − CH0 CH1
L L L H + − + − CH2 CH3
L L H L + − + − CH4 CH5
L L H H + − + − CH6 CH7 Differential
L H L L − + − + CH0 CH1
LHLH −+ − + CH2 CH3
L H H L − + − + CH4 CH5
L H H H − + − + CH6 CH7
H L L L + − + − CH0 COM
H L L H + − + − CH2 COM
HLHL + − + − CH4 COM
H L H H + − + − CH6 COM Single-Ended
H H L L + − + − CH1 COM
H H L H + − + − CH3 COM
H H H L + − + − CH5 COM
HHHH + − + − CH7 COM
160000MSB10987654321LSB
Bits
MSB12MSB10987654321LSB
First Bits
8 MSB 6 5 4 3 2 1 LSB
Bits
16LSB12345678910MSB0000
Bits
LSB 12 LSB 1 2 3 4 5 6 7 8 9 10 MSB
First Bits
8 LSB 1 2 3 4 5 6 MSB
Bits
TABLE 2. ADC12L038 Multiplexer Addressing
Analog Channel Addressed A/D Input Multiplexer Mode
MUX and Assignment Polarity Output
and A/DIN2 tied to MUXOUT2 Assignment
TABLE 3. ADC12L034 Multiplexer Addressing
Analog Channel Addressed A/D Input Multiplexer Mode
MUX and Assignment Polarity Output
Address with A/DIN1 tied to MUXOUT1 Assignment Channel
and A/DIN2 tied to MUXOUT2 Assignment
DI0 DI1 DI2 CH0 CH1 CH2 CH3 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2
L L L + − + − CH0 CH1
L L H + − + − CH2 CH3 Differential
L H L − + − + CH0 CH1
L H H − + − + CH2 CH3
H L L + − + − CH0 COM
H L H + − + − CH2 COM Single-Ended
H H L + − + − CH1 COM
H H H + − + − CH3 COM
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Page 23
Tables (Continued)
TABLE 4. ADC12L032 and ADC12L030 Multiplexer Addressing
Analog Channel Addressed A/D Input Multiplexer Mode
MUX and Assignment Polarity Output
Address with A/DIN1 tied to MUXOUT1 Assignment Channel
and A/DIN2 tied to MUXOUT2 Assignment
DI0 DI1 CH0 CH1 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2
L L + − + − CH0 CH1 Differential
L H − + − + CH0 CH1
H L + − + − CH0 COM Single-Ended
H H + − + − CH1 COM
Note 21: ADC12L030 does not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins.
TABLE 5. Mode Programming
ADC12L038 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 Mode Selected
ADC12L034 DI0 DI1 DI2 DI3 DI4 DI5 DI6
(Current)
ADC12L030
and DI0 DI1 DI2 DI3 DI4 DI5
ADC12L032
See
Tables 2, 3, 4
See
Tables 2, 3, 4
See
Tables 2, 3, 4
LLLL 12BitConversion 12 or 13 Bit MSB First
L L L H 12 Bit Conversion 16 or 17 Bit MSB First
L L H L 8 Bit Conversion 8 or 9 Bit MSB First
L L L L L L H H 12 Bit Conversion of Full-Scale 12 or 13 Bit MSB First
See
Tables 2, 3, 4
See
Tables 2, 3, 4
See
Tables 2, 3, 4
L H L L 12 Bit Conversion 12 or 13 Bit LSB First
L H L H 12 Bit Conversion 16 or 17 Bit LSB First
L H H L 8 Bit Conversion 8 or 9 Bit LSB First
L L L L L H H H 12 Bit Conversion of Offset 12 or 13 Bit LSB First
L L L L H L L L Auto Cal No Change
L L L L H L L H Auto Zero No Change
L L L L H L H L Power Up No Change
L L L L H L H H Power Down No Change
L L L L H H L L Read Status Register No Change
L L L L H H L H Data Out without Sign No Change
H L L L H H L H Data Out with Sign No Change
L L L L H H H L Acquisition Time— 6 CCLK
Cycles
L H L L H H H L Acquisition Time — 10 CCLK
Cycles
H L L L H H H L Acquisition Time— 18 CCLK
Cycles
H H L L H H H L Acquisition Time— 34 CCLK
Cycles
L L L LHHHH User Mode No Change
HX X XHHHH Test Mode No Change
(CH1–CH7 become Active
Outputs)
X=Don’t Care
Note 22: The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB first and user mode.
DO Format
(next Conversion
Cycle)
No Change
No Change
No Change
No Change
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Page 24
Tables (Continued)
Status
Bit
Location
Status
Bit
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8
PU PD Cal 8 or 9 12 or 13 16 or 17 Sign Justification Test
TABLE 6. Conversion/Read Data Only Mode Programming
CS CONV PD Mode
LLL See
L H L Read Only (Previous DO Format)
H X L Idle
X X H Power Down
X=Don’t Care
TABLE 7. Status Register
Device Status DO Output Format Status
Table 5
for Mode
No Conversion
Mode
Function
“High”
indicates
a Power
Up
Sequence
is in
progress
“High”
indicates
a Power
Down
Sequence
is in
progress
“High”
indicates
an
Auto-Cal
Sequence
is in
progress
“High”
indicates
an8or9
bit format
Application Hints
1.0 DIGITAL INTERFACE
1.1 Interface Concepts
Figure 7
The example in
after the power is applied to the ADC12L030/2/4/8:
FIGURE 7. Typical Power Supply Power Up Sequence
The first instruction input to the A/D via DI initiates Auto Cal.
The data output on DO at that time is meaningless and is
completely random. To determine whether the Auto Cal has
been completed, a read status instruction is issued to the
A/D. Again the data output at that time has no significance
since the Auto Cal procedure modifies the data in the output
shift register.To retrieve the status information, an additional
read status instruction is issued to the A/D. At this time the
status data is available on DO. If the Cal signal in the status
word is low Auto Cal has been completed. Therefore, the
next instruction issued can start a conversion. The data output at this time is again status information. To keep noise
from corrupting the A/D conversion, the status can not be
read during a conversion. If CS is strobed and is brought low
during a conversion, that conversion is prematurely ended.
www.national.com 24
shows a typical sequence of events
DS011830-36
“High”
indicates
a12or
13 bit
format
“High”
indicates
a16or
17 bit
format
EOC can be used to determine the end of a conversion or
theA/D controller can keep track in software of when it would
be appropriate to communicate to the A/D again. Once it has
been determined that the A/D has completed a conversion
another instruction can be transmitted to the A/D. The data
from this conversion can be accessed when the next instruction is issued to the A/D.
Note, when CS is low continuously it is important to transmit
the exact number of SCLK cycles, as shown in the timing
diagrams. Not doing so will desynchronize theserial communication to the A/D (see Section 1.3).
1.2 Changing Configuration
The configuration of the ADC12L030/2/4/8 on power up defaults to 12-bit plus sign resolution, 12- or 13-bit MSB First,
10 CCLK acquisition time, user mode, no Auto Cal, no Auto
Zero, and power up mode. Changing the acquisition time
and turning the sign bit on and off requires an 8-bit instruction to be issued to the ADC. This instruction will not start a
conversion. The instructions that select a multiplexer address and format the output data do start a conversion.
ure 8
describes an example of changing the configuration of
the ADC12L030/2/4/8.
During I/O sequence 1 the instruction on DI configures the
ADC12L030/2/4/8 to do a conversion with 12-bit +sign resolution. Notice that when the 6 CCLK Acquisition and Data
Out without Sign instructions are issued to the ADC, I/O sequences 2 and 3, a new conversion is not started. The data
“High”
indicates
that the
sign bit is
included.
When
“Low” the
sign bit is
not
included.
When “High”
the conversion
result will be
output MSB
first. When
“Low” the
result will be
output LSB
first.
When
“High”
the
device is
in test
mode.
When
“Low” the
device is
in user
mode.
Fig-
Page 25
Application Hints (Continued)
output during these instructions is from conversion N which
was started during I/O sequence 1. The Configuration Modification timing diagram describes in detail the sequence of
events necessary for a Data Out without Sign, Data Out with
Sign, or 6/10/18/34 CCLK Acquisition time mode selection.
FIGURE 8. Changing the ADC’s Conversion Configuration
Table 5
describes the actual data necessary to be input to
the ADC to accomplish this configuration modification. The
next instruction, shown in
Figure 8
, issued to the A/D starts
conversion N+1 with 8 bits of resolution formatted MSB first.
Again the data output during this I/O cycle is the data from
conversion N.
DS011830-37
The number of SCLKs applied to the A/D during any conversion I/O sequence should vary in accord with the data out
word format chosen during the previous conversion I/O sequence. The various formats and resolutions available are
shown in
Table 1
.In
Figure 8
, since 8-bit without sign MSB
first format was chosen during I/O sequence 4, the number
of SCLKs required during I/O sequence 5 is 8. In the following I/O sequence the format changes to 12-bit without sine
MSB first; therefore the number of SCLKs required during
I/O sequence 6 changes accordingly to 12.
1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that theADC expects. Not doing so will desynchronize the serial communications to the
ADC. When the supply power is first applied to the ADC, it
will expect to see 13 SCLK pulses for each I/O transmission.
The number of SCLK pulses that the ADC expects to see is
the same as the digital output word length. The digital output
word length is controlled by the Data Out (DO) format. The
DO format maybe changed any time a conversion is started
or when the sign bit is turned on or off. The table below details out the number of clock periods required for different
DO formats:
Number of
DO Format SCLKs
Expected
8-Bit MSB or LSB First SIGN OFF 8
SIGN ON 9
12-Bit MSB or LSB First SIGN OFF 12
SIGN ON 13
16-Bit MSB or LSB first SIGN OFF 16
SIGN ON 17
If erroneous SCLK pulses desynchronize the communications, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.
The number of clock pulses required for an I/O exchange
may be different for the case when CS is left low continuously vs. the case when CS is cycled. Take the I/O sequence
detailed in
Figure 7
(Typical Power Supply Sequence) as an
example. The table below lists the number of SCLK pulses
required for each instruction:
Instruction CS Low CS Strobed
Continuously
Auto Cal 13 SCLKs 8 SCLKs
Read Status 13 SCLKs 8 SCLKs
Read Status 13 SCLKs 8 SCLKs
12-Bit + Sign Conv 1 13 SCLKs 8 SCLKs
12-Bit + Sign Conv 2 13 SCLKs 13 SCLKs
1.4 Analog Input Channel Selection
The data input on DI also selects the channel configuration
for a particularA/D conversion (See
ure 8
the only times when the channel configuration could be
Tables2, 3, 4, 5
). In
Fig-
modified would be during I/O sequences 1, 4, 5 and 6. Input
channels are reselected before the start of eachnew conversion. Shown below is the data bit stream required on DI, during I/O sequence number 4 in
Figure 8
, to set CH1 as the
positive input and CH0 as the negative input for the different
versions of ADCs:
Part
Number
ADC12L030 LHLLHLXX
ADC12L032 LHLLHLXX
ADC12L034 LHLLLHLX
ADC12L038 LHLLLLHL
Where X can be a logic high (H) or low (L).
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
DI Data
1.5 Power Up/Down
The ADC may be powered down at any time by taking the
PD pin HIGH or by the instruction input on DI (see
6
, and the Power Up/Down timing diagrams). When the ADC
Tables5,
is powered down in this way the circuitry necessary for an
A/D conversion is deactivated. The circuitry necessary for
digital I/O is kept active. Hardware power up/down is controlled by the state of the PD pin. Software power up/down is
controlled by the instruction issued to the ADC. If a software
power up instruction is issued to the ADC while a hardware
power down is in effect (PD pin high) the device will remain
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Page 26
Application Hints (Continued)
in the power-down state. If a software power down instruction is issued to the ADC while a hardware power up is in effect (PD pin low), the device will power down. When the device is powered down by software, it may be powered up by
either issuing a software power up instruction or by taking
PD pin high and then low. If the power down command is issued during an A/D conversion, that conversion is disrupted.
Therefore, the data output after power up cannot be relied
on.
1.6 User Mode and Test Mode
An instruction may be issued to the ADC to put it into test
mode. Test mode is used by the manufacturer to verify complete functionality of the device. During test mode CH0–CH7
become active outputs. If the device is inadvertently put into
the test mode with CS low continuously, the serial communications may be desynchronized. Synchronization may be regained by cycling the power supply voltage to the device.
Cycling the power supply voltage will also set the device into
user mode. If CS is used in the serial interface, theADC may
be queried to see what mode it is in. This is done by issuing
a “read STATUS register” instruction to the ADC. When bit 9
of the status register is high the ADC is in test mode; when
bit 9 is low theADC is in user mode. As an alternative to cycling the power supply, an instruction sequence may beused
to return the device to user mode. This instruction sequence
must be issued to the ADC using CS.
The followingtable lists the instructions required to return the
device to user mode:
Instruction
TEST MODE HXXXHHHH
RESET LLLLHHHL
TEST MODE LLLLHLHL
INSTRUCTIONS LLLLHLHH
USER MODE LLLLHHHH
Power Up LLLLHLHL
Set DO with H
or without or L L L H H L H
Sign L
Set H H
Acquisition or or L L H H H L
Time L L
Start HHHH HHH
a ororororLororor
Conversion LLLL LLL
X=Don’t Care
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
After returning to user mode with the user mode instruction
the power up, data with or without sign, and acquisition time
instructions need to be resent to ensure that the ADC is in
the required state before a conversion is started.
DI Data
1.7 Reading the Data Without Starting a Conversion
The data from a particular conversion may be accessed
without starting a new conversion by ensuring that the
CONV line is taken high during the I/O sequence. See the
Read Data timing diagrams.
Table6
describes the operation
of the CONV pin.
2.0 DESCRIPTION OF THE ANALOG MULTIPLEXER
For the ADC12L038, the analog input multiplexer can be
configured with 4 differential channels or 8 single ended
channels with the COM input as the zero reference or any
combination thereof (see
the voltages on the V
put voltage span (V
+
to V
. Negative digital output codes result when V
A
+
V
. The actual voltage at V
IN
AGND.
Figure 9
+
REF
). The analog input voltage range is 0
REF
). The difference between
−
and V
pins determines the in-
REF
−
+
or V
IN
IN
cannot go below
−
IN
4 Differential
Channels
DS011830-38
8 Single-Ended Channels
with COM
as Zero Reference
DS011830-39
FIGURE 9.
CH0, CH2, CH4, and CH6 can be assigned to the MUXOUT1 pin in the differential configuration, while CH1, CH3,
CH5, and CH7 can be assigned to the MUXOUT2 pin. In the
differential configuration, the analog inputs are paired as follows: CH0 with CH1, CH2 with CH3, CH4 with CH5 and CH6
with CH7. The A/DIN1 and A/DIN2 pins can be assigned
positive or negative polarity.
With the single-ended multiplexer configuration CH0 through
CH7 can be assigned to the MUXOUT1 pin. The COM pin is
always assigned to the MUXOUT2 pin. A/DIN1 is assigned
as the positive input; A/DIN2 is assigned as the negative input. (See
Figure 10
).
The Multiplexer assignment tables for the ADC12L030,2,4,8
(
Tables2, 3, 4
) summarize the aforementioned functions for
the different versions of A/Ds.
>
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Page 27
Application Hints (Continued)
Differential
Configuration
DS011830-40
A/DIN1 and A/DIN2 can be assigned as the + or − input
A/DIN1 is + input
A/DIN2 is − input
FIGURE 10.
Single-Ended
Configuration
DS011830-41
FIGURE 11. Single-Ended Biasing
2.1 Biasing for Various Multiplexer Configurations
Figure 11
is an example of biasing the device for
single-ended operation. The sign bit is always low.The digital output range is 0 0000 0000 0000 to 0 1111 1111 1111.
One LSB is equal to 610 µV (2.5V/4096 LSBs).
For pseudo-differential signed operation the biasing circuit
shown in
Figure 12
shows a signal AC coupled to the ADC.
This gives a digital output range of −4096 to +4095. With a
1.25V reference, as shown, 1 LSB is equal to 305 µV. Although the ADC is not production tested with a 1.25V reference linearity error typically will not change more than 0.3
LSB. With the ADC set to an acquisition time of 10 clock periods the input biasing resistor needs to be 600Ω or less. Notice though that the input coupling capacitor needs to be
DS011830-46
made fairly large to bring down the high pass corner. Increasing the acquisition time to 34 clock periods (with a
5 MHz CCLK frequency) would allow the 600Ω to increase to
6k, which with a 1 µF coupling capacitor would set the high
pass corner at 26 Hz. The value of R1 will depend on the
value of R2.
An alternative method for biasing pseudo-differential operation is to use the +1.25V from the LM4040 to bias any amplifier circuits driving the ADC as shown in
Figure 13
. The value
of the resistor pull-up biasing the LM4040-2.5 will depend
upon the current required by the op amp biasing circuitry.
Fully differential operation is shown in
Figure 14
. One LSB
for this case is equal to (2.5V/4096)=610 mV.
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Page 28
Application Hints (Continued)
FIGURE 12. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC
DS011830-47
FIGURE 13. Alternative Pseudo-Differential Biasing
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DS011830-48
Page 29
Application Hints (Continued)
FIGURE 14. Fully Differential Biasing
3.0 REFERENCE VOLTAGE
The difference in the voltages applied to the V
−
V
defines the analog input span (the difference between
REF
the voltage applied between two multiplexer inputs or the
voltage applied to one of the multiplexer inputs and analog
ground), over which 4095 positive and 4096 negative codes
exist. The voltage sources driving V
very low output impedance and noise.
REF
+
or V
The ADC12L030/2/4/8 can be used in either ratiometric or
absolute reference applications. In ratiometric systems, the
analog input voltage is proportional to the voltage used for
the ADC’s reference voltage. When this voltage is the system power supply, the V
−
V
is connected to ground. This technique relaxes the
REF
system reference stability requirements because the analog
+
pin is connected to V
REF
input voltage and the ADC reference voltage move together.
This maintains the same output code for given input conditions. For absolute accuracy, where the analog input voltage
varies between very specific voltage limits, a time and temperature stable voltage source can be connected to the reference inputs. Typically, the reference voltage’s magnitude
will require an initial adjustment to null reference voltage induced full-scale errors.
Below are recommended references along with some key
specifications.
Output Temperature
Part Number Voltage Coefficient
Tolerance (max)
LM4041CIM3-Adj
LM4040AIM3-2.5
±
%
0.5
±
%
0.1
±
±
The reference voltage inputs are not fully differential. The
ADC12L030/2/4/8 will not generate correct conversions or
comparisons if V
sions result when V
at all times, between ground and V
mode range, (V
+
(0.6 x V
). Therefore, with V
A
+
is taken below V
REF
REF
+
+V
REF
+
and V
−
)/2, is restricted to (0.1 x V
REF
REF
−
differ by 1V and remain,
REF
+
. The V
A
+
=
3.3V the center of the ref-
A
−
. Correct conver-
REF
−
must have
REF
100ppm/˚C
100ppm/˚C
common
REF
+
and
+
and
A
+
)to
A
DS011830-50
erence ladder should not go below 0.33V or above 1.98V.
Figure 15
tions on V
is a graphic representation of the voltage restric-
+
and V
REF
FIGURE 15. V
REF
−
.
REF
DS011830-43
Operating Range
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Page 30
Application Hints (Continued)
4.0 ANALOG INPUT VOLTAGE RANGE
The ADC12L030/2/4/8’s fully differential ADC generate a
two’s complement output that is found by using the equations shown below:
for (12-bit) resolution the Output Code
for (8-bit) resolution the Output Code
Round off to the nearest integer value between −4096 to
4095 for 12-bit resolution and between −256 to 255 for 8-bit
resolution if the result of the above equation is not a whole
number.
Examples are shown in the table below:
+
−
V
V
REF
REF
+2.5V +1V +1.5V 0V 0,1111,1111,1111
+2.500V 0V +2V 0V 0,1100,1100,1101
+2.500V 0V +2.499V +2.500V 1,1111,1111,1111
+2.500V 0V 0V +2.500V 1,0000,0000,0000
+
V
IN
5.0 INPUT CURRENT
At the start of the acquisition window (t
flows into or out of the analog input pins (A/DIN1 and
A/DIN2) depending on the input voltage polarity. The analog
input pins are CH0–CH7 and COM when A/DIN1 is tied to
MUXOUT1 andA/DIN2 is tied to MUXOUT2. The peak value
of this input current will depend on the actual input voltage
applied, the source impedance and the internal multiplexer
switch on resistance. With MUXOUT1 tied to A/DIN1 and
MUXOUT2 tied to A/DIN2 the internal multiplexer switch on
resistance is typically 1.6 kΩ. The A/DIN1 and A/DIN2 mux
on resistance is typically 750Ω.
6.0 INPUT SOURCE RESISTANCE
For low impedance voltage sources (
charging current will decay, before the end of the S/H’s acquisition time of 2 µs (10 CCLK periods with f
a valuethat will not introduceany conversion errors. For high
source impedances, the S/H’s acquisition time can be increased to 18 or 34 CCLK periods. For less ADC resolution
and/or slower CCLK frequencies the S/H’s acquisition time
may be decreased to 6 CCLK periods. To determine the
number of clock periods (N
with a specific source impedance for the various resolutions
) required for the acquisition time
c
the following equations can be used:
12 Bit + Sign
8 Bit + Sign
=
N
R
+ 2.3] x
[
C
S
=
N
R
+ 2.3] x
[
C
S
Where fCis the conversion clock (CCLK) frequency in MHz
and R
is the external source resistance in kΩ.Asanex-
S
ample, operating with a resolution of 12 Bits+sign,a5MHz
clock frequency and maximum acquistion time of 34 conversion clock periods the ADC’s analog inputs can handle a
source impedanceas high as 6 kΩ. The acquisition time may
=
−
V
IN
) a charging current
A
<
fCx 0.824
fCx 0.57
=
Digital
Output
Code
600Ω), the input
=
5 MHz), to
C
also be extended to compensate for the settling or response
time of external circuitry connected between the MUXOUT
and A/DIN pins.
The acquisition time (t
and ended by a rising edge of CCLK (see Timing Diagrams).
) is started by a falling edge of SCLK
A
If SCLK and CCLK are asynchronous one extra CCLK clock
period may be inserted into the programmed acquisition time
for synchronization. Therefore with asnychronous SCLK and
CCLK the acquisition time will change from conversion to
conversion.
7.0 INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF–0.1 µF) can be connected between the analog input pins, CH0–CH7, and analog ground
to filter any noise caused by inductive pickupassociated with
long input leads. These capacitors will not degrade the conversion accuracy.
8.0 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce the effects of the
noise sources.
9.0 POWER SUPPLIES
Noise spikes on the V
conversion errors; the comparator will respond to the noise.
A
+
+
and V
supply lines can cause
D
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. The
minimum power supply bypassing capacitors recommended
are low inductance tantalum capacitors of 10 µF or greater
paralleled with 0.1 µF monolithic ceramic capacitors.More or
different bypassing may be necessary depending on the
overall system requirements. Separate bypass capacitors
should be used for the V
close as possible to these pins.
A
+
+
and V
supplies and placed as
D
10.0 GROUNDING
The ADC12L030/2/4/8’s performance can be maximized
through proper grounding techniques. These include the use
of separate analog and digital ground planes. The digital
ground plane is placed under all components that handle
digital signals,while the analog ground plane is placed under
all components that handle analog signals. The digital and
analog ground planes are connected together at only one
point, either the power supply ground or at the pins of the
ADC. This greatly reduces the occurence of ground loops
and noise.
Shown in
Figure 16
is the ideal ground plane layout for the
ADC12L038 along with ideal placement of the bypass capacitors. The circuit board layout shown in
Figure 16
uses
three bypass capacitors: 0.01 µF (C1) and 0.1 µF (C2) surface mount capacitors and 10 µF (C3) tantalum capacitor.
11.0 CLOCK SIGNAL LINE ISOLATION
TheADC12L030/2/4/8’s performance is optimized by routing
the analog input/output and reference signal conductors as
far as possible from the conductors that carry the clock signals to the CCLK and SCLK pins. Ground traces parallel to
the clock signal traces can be used on printed circuit boards
to reduce clock signal interference on the analog input/
output pins.
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Page 31
Application Hints (Continued)
FIGURE 16. Ideal Ground Plane for the ADC12L038
12.0 THE CALIBRATION CYCLE
A calibration cycle needs to be started after the power supplies, reference, and clock have been given enough time to
stabilize after initial turn on. During the calibration cycle, correction values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full-scale,
offset, and linearity errors down to the specified limits.
Full-scale error typically changes
ture and linearity error changes even less; thereforeit should
be necessary to go through the calibration cycle only once
after power up if the Power Supply Voltage and the ambient
temperature do not change significantly (see the curves in
the Typical Performance Characteristics).
13.0 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the A/D,
the auto-zero cycle can be used. It may be necessary to do
an auto-zero cycle whenever the ambient temperature or the
power supply voltage change significantly. (See the curves
titled “Zero Error Change vs Ambient Temperature” and
“Zero Error Change vs Supply Voltage” in the Typical Performance Characteristics.)
14.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but the standard DC integral and differential nonlinearity specifications will not accurately predict the A/D converter’s performance with AC input signals. The important
specifications for AC applications reflect the converter’s ability to digitize AC signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
characteristics such as signal-to-noise (S/N), signal-to-noise
+ distortion ratio (S/(N + D)), effective bits, full power bandwidth, aperture time and aperture jitter are quantitative measures of the A/D converter’s capability.
±
0.4 LSB over tempera-
DS011830-44
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform. S/(N + D)
and S/N are calculated from the resulting FFT data, and a
spectral plot may also be obtained.
The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies.This can be
seen inthe S/(N + D)versus frequency curves. These curves
will also give an indication of the full power bandwidth (the
frequency at which the S/(N + D) or S/N drops 3 dB).
Effective number of bits can also be useful in describing the
A/D’s noise performance. An ideal A/D converter will have
some amount of quantization noise, determined by its resolution, which will yield an optimum S/N ratio given by the following equation:
S/N=(6.02xn+1.76) dB
where n is the A/D’s resolution in bits.
The effective bits of a real A/D converter, therefore, can be
found by:
As an example, this device with a±2.5V, 10 kHz sine wave
input signal will typically have a S/N of 78 dB, which is
equivalent to 12.6 effective bits.
15.0 AN RS232 SERIAL INTERFACE
Shown below is a schematic for an RS232 interface to any
IBM and compatible PCs. The DTR, RTS, and CTS RS232
signal lines are buffered via level translators and connected
to the ADC12L038’s DI, SCLK, and DO pins, respectively.
The D flip flop drive the CS control line.
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Page 32
Application Hints (Continued)
+
Note: V
caps. The DS14C335 has an internal DC-DC converter that generates the necessary TIA/EIA-232-E output levels from a 3.3V supply. There are four 0.47 µF
capacitors required for the DC-DC converter that are not shown in the above schematic.
+
,V
A
D
, and V
+
on the ADC12L038 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF
REF
DS011830-45
The assignment of the RS232 port is shown below
B7 B6 B5 B4 B3 B2 B1 B0
COM1 Input Address 3FE X X X CTS X X X X
Output Address 3FC X X X 0 X X RTS DTR
A sample program, written in Microsoft
™
QuickBasic, is
shown on the next page. The program prompts for data
mode select instruction to be sent to the A/D. This can be
found from the Mode Programming table shown earlier. The
data should be entered in “1”s and “0”s as shown in the table
with DI0 first. Next the program prompts for the number of
SCLKs requiredfor the programmed mode select instruction.
For instance, to send all “0”s to the A/D, selects CH0 as the
+input, CH1as the −input, 12-bit conversion, and 13-bit MSB
first data output format (if the sign bit was not turned off by a
previous instruction). This would require 13 SCLK periods
since the output data format is 13 bits. The part powers up
with No Auto Cal, No Auto Zero, 10 CCLK Acquisition Time,
12-bit conversion, data out with sign, 12- or 13-bit MSB First,
power up, and user mode. Auto Cal, Auto Zero, Power UP
and Power Down instructions do not change these default
settings. The following power up sequence should be followed:
1. Run the program
2. Priorto responding to the prompt apply the power to the
ADC12L038
3. Respond to the program prompts
It is recommended that the first instruction issued to the
ADC12L038 be Auto Cal (see Section 1.1).
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Page 33
Application Hints (Continued)
DS011830-63
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Page 34
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADC12L030CIWM
NS Package Number M16B
Order Number ADC12L032CIWM
NS Package Number M20B
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Page 35
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number ADC12L034CIWM
NS Package Number M24B
Order Number ADC12L038CIWM
NS Package Number M28B
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Page 36
A/D Converters with MUX and Sample/Hold
Notes
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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Email: europe.support@nsc.com
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