Page 1
ADC12762
12-Bit, 1.4 MHz, 300 mW A/D Converter
with Input Multiplexer and Sample/Hold
ADC12762 12-Bit, 1.4 MHz, 300 mW A/D Converter with Input Multiplexer and Sample/Hold
June 1999
General Description
Using an innovative multistep conversion technique, the
12-bit ADC12762 CMOS analog-to-digital converter digitizes
signals at a 1.4 MHz sampling rate while consuming a maximum of only 300 mW on a single +5V supply. The
ADC12762 performs a 12-bit conversion in three
lower-resolution “flash” conversions, yielding a fast A/D without the cost and power dissipation associated with true flash
approaches.
The analog input voltage to the ADC12762 is tracked and
held by an internal sampling circuit, allowing high frequency
input signals to be accurately digitized without the need for
an external sample-and-hold circuit. The ADC12762 features
two sample-and-hold/flash comparator sections which allow
the converter to acquire one sample while converting the
previous. This pipelining technique increases conversion
speed without sacrificing performance. The multiplexer output is available to the user in order to perform additional external signal processing before the signal is digitized.
When the converter is not digitizing signals, it can be placed
in the Standby mode; typical power consumption in this
mode is 250 µW.
ADC12762 Block Diagram
Features
n Built-in sample-and-hold
n Single +5V supply
n Single channel or 2 channel multiplexer operation
Key Specifications
n Sampling rate 1.4 MHz (min)
n Conversion time 593 ns (typ)
n SNR, f
n Power dissipation (f
n No missing codes over temperature Guaranteed
=
100 kHz 67.5 dB (min)
IN
=
1.4 MHz) 300 mW (max)
s
Applications
n CCD image scanners
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
n Waveform digitizers
DS012811-1
Ordering Information
Commercial (0˚C ≤ TA≤ +70˚C) Package
ADC12762CCV V44 Plastic Leaded Chip Carrier
ADC12062EVAL Evaluation Board
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012811 www.national.com
Page 2
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
=
Supply Voltage (V
CC
Voltage at Any Input or Output −0.3V to V
Input Current at Any Pin (Note 3) 25 mA
Package Input Current (Note 3) 50 mA
Power Dissipation (Note 4)
ADC12762CCV 875 mW
ESD Susceptibility (Note 5) 2000V
DV
=
) −0.3V to +6V
AV
CC
CC
CC
+ 0.3V
Soldering Information (Note 6)
V Package, Infrared, 15 seconds +300˚C
Storage Temperature Range −65˚C to +150˚C
Maximum Junction Temperature (T
) 150˚C
JMAX
Operating Ratings (Notes 1, 2)
Temperature Range T
ADC12762CCV −0˚C ≤ TA≤ +70˚C
=
) 4.75V to 5.25V
Supply Voltage Range (DV
AV
CC
CC
MIN
≤ TA≤ T
MAX
Converter Characteristics
=
The following specifications apply for DV
1.4 MHz, unless otherwise specified. Boldface limits apply for T
CC
AV
=
+5V, V
CC
REF+(SENSE)
=
+4.096V, V
=
from T
T
A
J
MIN
REF−(SENSE)
to T
MAX
=
AGND, and f
; all other limits T
=
s
=
=
T
+25˚C.
A
J
Symbol Parameter Conditions Typ Limit Units
(Note 7) (Note 8) (Limit)
Resolution 12 Bits
Differential Linearity Error T
Integral Linearity Error T
MIN
MIN
to T
to T
MAX
MAX
±
0.4
±
0.4
±
0.95 LSB (max)
±
2.0 LSB (max)
(Note 9)
R
V
V
V
C
C
REF
REF(+)
REF(−)
IN
ADC
MUX
Offset Error T
Full-Scale Error T
Power Supply Sensitivity
(Note 15)
DV
MIN
MIN
to T
MAX
to T
MAX
=
=
±
%
5V
5
AV
CC
CC
±
0.3
±
0.3
Reference Resistance 940
V
REF+(SENSE)
V
REF−(SENSE)
Input Voltage Range To V
ADC IN Input Leakage AGND to AV
Input Voltage AV
Input Voltage AGND V (min)
, or ADC IN
IN1,VIN2
− 0.3V 0.1 3 µA (max)
CC
ADC IN Input Capacitance 25 pF
MUX On-Channel Leakage AGND to AV
MUX Off-Channel Leakage AGND to AV
− 0.3V 0.1 3 µA (max)
CC
− 0.3V 0.1 3 µA (max)
CC
Multiplexer Input Cap 7 pF
MUX Off Isolation f
=
100 kHz 92 dB
IN
±
4.0 LSB (max)
±
4.0 LSB (max)
±
0.75 LSB (max)
500 Ω (min)
1300 Ω (max)
CC
AV
+0.05V V (max)
CC
V (max)
AGND − 0.05V V (min)
Dynamic Characteristics (Note 10)
=
The following specifications apply for DV
100 kHz, 0 dB from fullscale, and f
; all other limits T
T
MAX
=
A
=
s
=
T
+25˚C.
J
CC
1.4 MHz, unless otherwise specified. Boldface limits apply for T
AV
=
+5V, V
CC
REF+(SENSE)
Symbol Parameter Conditions Typ Limit Units
SINAD
SNR
THD
ENOB
Signal-to-Noise Plus
Distortion Ratio
Signal-to-Noise Ratio
(Note 11)
Total Harmonic Distortion
(Note 12)
Effective Number of Bits
(Note 13)
IMD Intermodulation Distortion f
to T
T
MIN
MAX
to T
T
MIN
MAX
to T
T
MIN
MAX
to t
T
MIN
MAX
=
88.7 kHz, 89.5 kHz −80 dBc
IN
=
+4.096V, V
REF−(SENSE)
=
AGND, R
=
25Ω,f
S
=
from T
T
A
J
MIN
(Note 7) (Note 8) (Limit)
70 67.0 dB (min)
70 67.5 dB (min)
−80 −70 dBc (max)
11.3 10.8 Bits (min)
=
IN
to
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Page 3
DC Electrical Characteristics
=
The following specifications apply for DV
1.4 MHz, unless otherwise specified. Boldface limits apply for T
CC
AV
=
+5V, V
CC
REF+(SENSE)
Symbol Parameter Conditions Typ Limit Units
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
V
OUT(0)
I
OUT
C
OUT
C
IN
DI
CC
AI
CC
I
STANDBY
Logical “1” Input Voltage DV
Logical “0” Input Voltage DV
Logical “1” Input Current 0.1 1.0 µA (max)
Logical “0” Input Current 0.1 1.0 µA (max)
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE®Output
Leakage Current
TRI-STATE Output Capacitance Pins DB0–DB11 5 pF
Digital Input Capacitance 4 pF
DVCCSupply Current 2 10 mA (max)
AVCCSupply Current 32 50 mA (max)
Standby Current (DICC+AICC)PD
=
AV
CC
=
AV
CC
=
AV
DV
CC
=
I
−360 µA 2.4 V (min)
OUT
=
I
−100 µA 4.25 V (min)
OUT
=
DV
AV
CC
=
1.6 mA
I
OUT
Pins DB0–DB11 0.1 3 µA (max)
=
0V 50 µA
=
+4.096V, V
=
from T
T
A
J
MIN
REF−(SENSE)
to T
MAX
=
; all other limits T
AGND, and f
=
A
(Note 7) (Note 8) (Limit)
=
+5.5V 2.0 V (min)
CC
=
+4.5V 0.8 V (max)
CC
=
+4.5V,
CC
=
+4.5V,
CC
0.4 V (max)
=
s
=
T
J
+25˚C.
AC Electrical Characteristics
=
The following specifications apply for DV
1.4 MHz, unless otherwise specified. Boldface limits apply for T
CC
AV
=
+5V, V
CC
REF+(SENSE)
Symbol Parameter Conditions Typ Limit Units
f
s
t
CONV
t
AD
t
S/H
t
EOC
t
ACC
t1H,t
t
INTH
t
INTL
t
UPDATE
t
MS
t
MH
t
CSS
Maximum Sampling Rate
(1/t
THROUGHPUT
)
Conversion Time
(S/H Low to EOC High)
Aperture Delay
(S/H Low to Input Voltage Held)
S/H Pulse Width 10
S/H Low to EOC Low 90
Access Time
(RD Low or OE High to Data Valid)
TRI-STATE Control
0H
(RD High or OE Low to Databus TRI-STATE)
C
R
Delay from RD Low to INT High C
Delay from EOC High to INT Low C
EOC High to New Data Valid 5 15 ns (max)
Multiplexer Address Setup Time
(MUX Address Valid to EOC Low)
Multiplexer Address Hold Time
(EOC Low to MUX Address Invalid)
CS Setup Time
(CS Low to RD Low, S/H Low, or OE High)
=
+4.096V, V
=
from T
T
A
J
MIN
REF−(SENSE)
to T
MAX
=
; all other limits T
AGND, and f
s
=
T
A
J
(Note 7) (Note 8) (Limits)
1.5 MHz (min)
593
560 ns (min)
710 ns (max)
20 ns
5 ns (min)
400 ns (max)
60 ns (min)
126 ns (max)
=
100 pF 10 20 ns (max)
L
=
=
1k, C
L
=
L
=
L
10 pF 25 40 ns (max)
L
100 pF 35 60 ns (max)
100 pF −25
−35 ns (min)
−10 ns (max)
50 ns (min)
50 ns (min)
20 ns (min)
=
=
+25˚C.
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Page 4
AC Electrical Characteristics (Continued)
=
The following specifications apply for DV
1.4 MHz, unless otherwise specified. Boldface limits apply for T
CC
AV
=
+5V, V
CC
REF+(SENSE)
Symbol Parameter Conditions Typ Limit Units
t
CSH
t
WU
Note 1: Absolute Maximum Ratingsindicatelimitsbeyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits, however.For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 2: All voltages are measured with respect to GND (GND=AGND=DGND), unless otherwise specified.
Note 3: When the input voltage (V
to 25 mA or less. The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
(PLCC) package is 55˚C/W. In most cases the maximum derated power dissipation will be reached only during fault conditions.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model ESD rating is 200V.
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at +25˚C and represent most likely parametric norm.
Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints.
Note 10: Dynamic testing of theADC12762 is done using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies. See the graph in the
Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer.
Note 11: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in its calculation.
Note 12: The contributions from the first nine harmonics are used in the calculation of the THD.
Note 13: Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB=(SINAD − 1.76)/
6.02.
Note 14: The digital power supply current takes up to 10 seconds to decay to its final value after PD is pulled low. This prohibits production testing of the standby
current. Some parts may exhibit significantly higher standby currents than the 50 µA typical.
Note 15: Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage.
CS Hold Time
(CS High after RD High, S/H High, or OE Low)
Wake-Up Time
(PD High to First S/H Low)
) at any pin exceeds the power supply rails (V
IN
=
(T
D
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. θJAfor the V
JMAX−TA
IN
=
A
<
GND or V
T
J
=
+4.096V, V
from T
MIN
REF−(SENSE)
to T
MAX
=
; all other limits T
AGND, and f
(Note 7) (Note 8) (Limits)
20 ns (min)
1µs
>
VCC) the absolute value of current at that pin should be limited
IN
, θJAand the ambient temperature TA. The maximum
JMAX
=
s
=
=
T
+25˚C.
A
J
TRI-STATE Test Circuit and Waveforms
DS012811-2
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DS012811-3
Page 5
TRI-STATE Test Circuit and Waveforms (Continued)
DS012811-4
Typical Performance Characteristics
DS012811-5
Offset and Fullscale
Error Change vs
Reference Voltage
Digital Supply Current
vs Temperature
DS012811-6
DS012811-9
Linearity Error Change
vs Reference Voltage
Analog Supply Current
vs Temperature
DS012811-7
DS012811-10
Mux ON Resistance
vs Input Voltage
DS012811-8
Current Consumption in
Standby Mode vs Voltage
on Digital Input Pins
DS012811-11
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Page 6
Typical Performance Characteristics (Continued)
Conversion Time (t
vs Temperature
CONV
)
SINAD vs Input Frequency
(ADC In)
SINAD vs Input Frequency
(Through Mux)
DS012811-12
DS012811-15
EOC Delay Time (t
vs Temperature
EOC
)
SNR vs Input Frequency
(ADC In)
SNR vs Input Frequency
(Through Mux)
DS012811-13
DS012811-16
Spectral Response
DS012811-14
THD vs Input Frequency
(ADC In)
DS012811-17
THD vs Input Frequency
(Through Mux)
DS012811-18
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DS012811-19
DS012811-20
Page 7
Typical Performance Characteristics (Continued)
SNR and THD vs Source
Impedance
Timing Diagrams
DS012811-21
SNR and THD vs
Reference Voltage
DS012811-22
FIGURE 1. Interrupt Interface Timing (MODE=0, OE=1)
DS012811-23
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Page 8
Timing Diagrams (Continued)
FIGURE 2. High Speed Interface Timing (MODE=0, OE=1, CS=0, RD=0)
DS012811-24
FIGURE 3. CS Setup and Hold Timing for S/H, RD, and OE
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DS012811-25
Page 9
Connection Diagrams
Pin Descriptions
AV
CC
DV
CC
AGND,
DGND1,
DGND2
DB0–DB11 These are the TRI-STATE output pins,
V
IN1,VIN2
These are the two positive analog supply
inputs. They should always be connected to the same voltage source, but
are brought out separately to allow for
separate bypass capacitors. Each supply
pin should be bypassed to AGND with a
0.1 µF ceramic capacitor in parallel with
a 10 µF tantalum capacitor.
This is the positive digital supply input. It
should always be connected to the same
voltage as the analog supply, AV
should be bypassed to DGND2 with a
.It
CC
0.1 µF ceramic capacitor in parallel with
a 10 µF tantalum capacitor.
These are the power supply ground pins.
There are separate analog and digital
ground pins for separate bypassing of
the analog and digital supplies. The
ground pins should be connected to a
stable, noise-free system ground. All of
the ground pins should be returned to the
same potential. AGND is the analog
ground for the converter. DGND1 is the
ground pin for the digital control lines.
DGND2 is the ground return for the output databus. See Section 6.0 LAYOUT
AND GROUNDING for more information.
enabled by RD, CS, and OE.
These are the analog input pins to the
multiplexer. For accurate conversions,
no input pin (even one that is not selected) should be driven more than 50
mV below ground or 50 mV above V
CC
DS012811-26
Top View
MUX OUT This is the output of the on-board analog
input multiplexer.
ADC IN This is the direct input to the 12-bit sam-
plingA/D converter. For accurate conversions, this pin should not be driven more
than 50 mV below ground or 50 mV
above V
.
CC
S0 This pin selects the analog input that will
be connected to the ADC12762 during
the conversion. The input is selected
based on the state of S0 when EOC
makes its high-to-low transition. Low selects V
, high selects V
IN1
MODE This pin should be tied to DGND1.
CS
This is the active low Chip Select control
input. When low, this pin enables the RD,
S/H, and OE inputs. This pin can be tied
low.
INT
This is the active low Interrupt output.
When using the Interrupt Interface Mode
(
Figure 1
), this output goes low when a
conversion has been completed and indicates that the conversion result is available in the output latches. This output is
always high when RD is held low (
2
).
EOC
This is the End-of-Conversion control
output. This output is low during a conversion.
RD
This is the active low Read control input.
When RD is low (and CS is low), the INT
output is reset and (if OE is high) data
.
appears on the data bus. This pin can be
tied low.
.
IN2
Figure
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Page 10
Pin Descriptions (Continued)
OE This is the active high Output Enable
S/H
PD
V
REF+(FORCE)
V
REF−(FORCE)
control input. This pin can be thought of
as an inverted version of the RD input
(see
Figure 6
). Data output pins
DB0–DB11 are TRI-STATE when OE is
low. Data appears on DB0–DB11 only
when OE is high and CS and RD are
both low. This pin can be tied high.
This is the Sample/Hold control input.
The analog input signal is held and a
new conversion is initiated by the falling
edge of this control input (when CS is
low).
This is the Power Down control input.
This pin should be held high for normal
operation. When this pin is pulled low,
the device goes into a low power standby
mode.
,
These are the positive and negative voltage reference force inputs, respectively.
See Section 4, REFERENCE INPUTS,
for more information.
V
REF+(SENSE)
V
REF−(SENSE)
,
These are the positive and negative voltage reference sense pins, respectively.
See Section 4, REFERENCE INPUTS,
for more information.
V
/16 This pin should be bypassed to AGND
REF
TEST This pin should be tied to DV
with a 0.1 µF ceramic capacitor.
CC
.
Functional Description
The ADC12762 performs a 12-bit analog-to-digital conversion using a 3 step flash technique. The first flash determines the six most significant bits, the second flash generates four more bits, and the final flash resolves the two least
significant bits.
the converter. It consists of a 2
sistor ladder with two different resolution voltage spans, a
sample/hoId capacitor, a 4-bit flash converter with front end
multiplexer, a digitally corrected DAC, and a capacitive voltage divider. To pipeline the converter, there are two sample/
hold capacitors and 4-bit flash sections, which allows the
converter to acquire the next input sample while converting
the previous one. Only one of the flash converter pairs is
shown in
Figure 4
Figure 4
to reduce complexity.
shows the major functional blocks of
1
⁄2-bit Voltage Estimator, a re-
FIGURE 4. Functional Block Diagram
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DS012811-27
Page 11
Functional Description (Continued)
The resistor string near the center of the block diagram in
Figure 4
generates the 6-bit and 10-bit reference voltages for
the first two conversions. Each of the 16 resistors at the bottom of the string is equal to 1/1024 of the total string resistance. These resistors form the LSB Ladder (The weight of
each resistor on the LSB ladder is actually equivalent to four
12-bit LSBs. It is called the LSB ladder because it has the
highest resolution of all the ladders in the converter) and
have a voltage drop of 1/1024 of the total reference voltage
(V
REF+−VREF−
tors form the MSB Ladder. It is comprised of eight groups of
eight resistors each connected in series (the lowest MSB
ladder resistor is actually the entire LSB ladder). Each MSB
Ladder section has
Within a given MSB ladder section, each of the eight MSB
resistors has
points are found between all of the resistors in both the MSB
and LSB ladders. The Comparator MultipIexer can connect
any of these tap points, in two adjacent groups of eight, to
the sixteen comparators shown at the right of
function provides the necessary reference voltages to the
comparators during the first two flash conversions.
The six comparators, seven-resistor string (Estimator DAC
ladder), and Estimator Decoder at the left of
the Voltage Estimator. The Estimator DAC, connected between V
for the six Voltage Estimator comparators. The comparators
perform a very low resoIution A/D conversion to obtain an
“estimate” of the input voltage. This estimate is used to control the placement of the Comparator Multiplexer, connecting
the appropriate MSB ladder section to the sixteen flash comparators. A total of only 22 comparators (6 in the Voltage Estimator and 16 in the flash converter) is required to quantize
the input to 6 bits, instead of the 64 that would be required
using a traditional 6-bit flash.
Prior to a conversion, the Sample/Hold switch is closed, allowing the voltage on the S/H capacitor to track the input
voItage. Switch 1 is in position 1. A conversion begins by
opening the Sample/Hold switch and latching the output of
the Voltage Estimator. The estimator decoder then selects
two adjacent banks of tap points aIong the MSB ladder.
These sixteen tap points are then connected to the sixteen
flash converters. For exampIe, if the input voltage is between
5/16 and 7/16 of V
decoder instructs the comparator multiplexer to select the
sixteen tap points between 2/8 and 4/8 (4/16 and 8/16) of
V
and connects them to the sixteen flash converters. The
REF
first flash conversion is now performed, producing the first 6
MSBs of data.
At this point, Voltage Estimator errors as large as 1/16 of
V
will be corrected since the flash converters are con-
REF
nected to ladder voltages that extend beyond the range
specified by the Voltage Estimator. For example, if (7/
16)V
REF
parators tied to the tap points below (9/16)V
“1”s (000111). This is decoded by the estimator decoder to
“10”. The 16 comparators will be placed on the MSB ladder
tap points between (
(1/16)V
) across each of them. The remaining resis-
1
⁄8of the total reference voltage across it.
1
⁄64 of the total reference voltage across it. Tap
Figure 4
Figure 4
and V
REF+
<
V
IN
will automatically cancel a Voltage Estimator er-
REF
, generates the reference voltages
REF−
=
REF(VREF
<
(9/16)V
V
REF+−VREF−
, the Voltage Estimator’s com-
REF
3
⁄8)V
and (5⁄8)V
REF
), the estimator
REF
. This overlap of
REF
. This
form
will output
ror of up to 256 LSBs. If the first flash conversion determines
that the input voltage is between (
LSB/2), the Voltage Estimator’s output code will be corrected
3
⁄8)V
REF
and ((4/8)V
REF
by subtracting “1”, resulting in a corrected value of “01” for
the first two MSBs. If the first flash conversion determines
that the input voltage is between (4/8)V
5
(
⁄8)V
, the voltage estimator’s output code is unchanged.
REF
− LSB/2) and
REF
The results of the first flash and the Voltage Estimator’s output are given to the factory-programmed on-chip EEPROM
which returns a correction code corresponding to the error of
the MSB ladder at that tap. This code is converted to a voltage by the Correction DAC. To generate the next four bits,
SW1 is moved to position 2, so the ladder voltage and the
correction voltage are subtracted from the input voltage. The
remainder is applied to the sixteen flash converters and
compared with the 16 tap points from the LSB ladder.
The result of this second conversion is accurate to 10 bits
and describes the input remainder as a voltage between two
tap points (V
two bits, the voltage across the ladder resistor (between V
and VL) on the LSB ladder.To resolve the last
H
and VL) is divided up into 4 equal parts by the capacitive voltage divider, shown in
LSBs below V
used by the digital error correction. SW1 is moved to position
Figure 5
and 6 LSBs above VHto provide overlap
L
. The divider also creates 6
3, and the remainder is compared with these 16 new voltages. The output is combined with the results of the Voltage
Estimator,first flash, and second flash to yield the final 12-bit
result.
By using the same sixteen comparators for all three flash
conversions, the number of comparators needed by the
multi-step converter is significantly reduced when compared
to standard multi-step techniques.
Applications Information
MODES OF OPERATION
The ADC12762 has two interface modes: An interrupt/read
mode and a high speed mode.
the timing diagrams for these interfaces.
In order to clearly show the relationship between S/H, CS,
RD, and OE, the control logic decoding section of the
ADC12762 is shown in
Interrupt Interface
Figure 1
As shown in
, the falling edge of S/H holds the input
voltage and initiates a conversion. At the end of the conversion, the EOC output goes high and the INT output goes low,
indicating that the conversion results are latched and may be
read by pulling RD low.The falling edge of RD resets the INT
line. Note that CS must be low to enable S/H or RD.
High Speed Interface
The Interrupt interface works well at lower speeds, but few
microprocessors could keep up with the 1 µs interrupts that
would be generated if the ADC12762 was running at full
speed. The most efficient interface is shown in
Here the output data is always present on the databus, and
the INT to RD delay is eliminated.
Figure 6
Figure 1
.
and
Figure 2
Figure 2
show
−
H
.
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Page 12
Applications Information (Continued)
FIGURE 5. The Capacitive Voltage Divider
DS012811-28
FIGURE 6. ADC Control Logic
THE ANALOG INPUT
The analog input of the ADC12762 can be modeled as two
small resistances in series with the capacitance of the input
hold capacitor (C
closed during the Sample period, and open during Hold. The
), as shown in
IN
source has to charge C
sample period. Note that the source impedance of the input
voltage (R
charge C
will not settle to within 0.5 LSBs of V
) has a direct effect on the time it takes to
SOURCE
.IfR
IN
SOURCE
version begins, and the conversion results will be incorrect.
Figure 7
. The S/H switch is
to the input voltage within the
IN
is too large, the voltage across C
before the con-
SOURCE
IN
From a dynamic performance viewpoint, the combination of
R
SOURCE,RMUX,RSW
mizing R
SOURCE
input stage of the converter.
Typical values for the components shown in
=
R
100Ω,R
MUX
time to n bits is:
t
SETTLE
=
, and CINform a low pass filter. Mini-
will increase the frequency response of the
=
100Ω, and C
SW
(R
SOURCE+RMUX+RSW
IN
Figure 7
=
25 pF. The settling
*n*
)*C
IN
are:
ln (2).
The bandwidth of the input circuit is:
=
*
1/(2
3.14*(R
SOURCE+RMUX+RSW
f
−3dB
www.national.com 12
)*CIN)
DS012811-29
The ADC12762 is operated in a pipelined sequence, with
one hold capacitor acquiring the next sample while a conversion is being performed on the voltage stored on the other
hold capacitor. This gives the source over t
charge the hold capacitor to its final value. At 1.4 MHz, the
CONV
seconds to
settling time must be less than 714 ns. Using the settling
time equation and component values given, the maximum
source impedance that will allow the input to settle to
(n=13) at full speed is ∼3kΩ.To ensure
1
⁄2LSB settling over
temperature and device-to-device variation, R
should be a maximum of 500Ω when the converter is oper-
1
⁄2LSB
SOURCE
ated at full speed.
If the signal source has a high output impedance, its output
should be buffered with an operational amplifier capable of
driving a switched 25 pF/100Ω load. Any ringing or instabilities at the op amp’s output during the sampling period can
result in conversion errors. The LM6361 high speed op amp
is a good choice for this application due to its speed and its
ability to drive large capacitive loads.
Figure 8
shows the
LM6361 driving the ADC IN input of an ADC12762. The
100 pF capacitor at the input of the converter absorbs some
of the high frequency transients generated by the S/H
Page 13
Applications Information (Continued)
switching, reducing the op amp transient response requirements. The 100 pF capacitor should only be used with high
speed op amps that are unconditionally stable driving capacitive loads.
Another benefit of using a high speed buffer is improved
THD performance when using the multiplexer of the
FIGURE 7. Simplified ADC12762 Input Stage
ADC12762. The MUX on-resistance is somewhat non-linear
over input voltage, causing the RC time constant formed by
C
This results in increasing THD with increasing frequency. In-
, and RSWto vary depending on the input voltage.
IN,RMUX
serting the buffer between the MUX OUT and the ADC IN
terminals as shown in
R
, significantly reducing the THD of the multiplexed
MUX
system.
Figure 8
will eliminate the loading on
DS012811-30
FIGURE 8. Buffering the Input with an LM6361 High Speed Op Amp
Correct converter operation will be obtained for input voltages greater than AGND − 50 mV and less than AV
mV. Avoid driving the signal source more than 300 mV
higher than AV
analog input pin is forced beyond these voltages, the current
, or more than 300 mV below AGND. If an
CC
+50
CC
flowing through that pin should be limited to 25 mA or less to
avoid permanent damage to the IC. The sum of all the over-
DS012811-31
drive currents into all pins must be less than 50 mA. When
the input signal is expected to extend more than 300 mV beyond the power supply limits for any reason (unknown/
uncontrollable input voltage range, power-on transients, fault
conditions, etc.) some form of input protection, such as that
shown in
Figure 9
, should be used.
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Page 14
Applications Information (Continued)
FIGURE 9. Input Protection
ANALOG MULTIPLEXER
The ADC12762 has an input multiplexer that is controlled by
the logic level on pin S0 when EOC goes low, as shown in
Figure 1
and
Figure 2
respect to the S/H input can be determined by these two
equations:
t
MS (wrt S/H)
t
MH (wrt S/H)
Note that t
the data on S0 must become valid within 10 ns after S/H
MS (wrt S/H)
goes low in order to meet the setup time requirements. S0
must be valid for a length of
(t
MH+tEOC (max)
Table 1
shows how the input channels are assigned:
The output of the multiplexer is available to the user via the
MUX OUT pin. This output allows the user to perform additional signal processing, such as filtering or gain, before the
. Multiplexer setup and hold times with
=
t
MS−tEOC (min)
=
t
MH+tEOC (max)
=
50−60=−10 ns
=
50 + 125=175 ns
is a negative number; this indicates that
)−(tMS−t
EOC (min)
)=185 ns.
TABLE 1. ADC12762 Input
Multiplexer Programming
S0 Channel
0V
1V
IN1
IN2
DS012811-32
signal is returned to the ADC IN input and digitized. If no additional signal processing is required, the MUX OUT pin
should be tied directly to the ADC IN pin.
See Section 9.0 (APPLICATIONS) for a simple circuit that
will alternate between the two inputs while converting at full
speed.
REFERENCE INPUTS
In addition to the fully differential V
inputs used on most National Semiconductor ADCs, the
REF+
and V
REF−
reference
ADC12762 has two sense outputs for precision control of the
ladder voltage. These sense inputs compensate for errors
due to IR drops between the reference source and the ladder
itself. The resistance of the reference ladder may be 750Ω.
The parasitic resistance (R
wires, PCB traces, etc. can easily be 0.5Ω to 1.0Ω or more.
) of the package leads, bond
P
This may not be significant at 8-bit or 10-bit resolutions, but
at 12 bits it can introduce voltage drops causing offset and
gain errors as large as 6 LSBs.
The ADC12762 provides a means to eliminate this error by
bringing out two additional pins that sense the exact voltage
at the top and bottom of the ladder. With the addition of two
op amps, the voltages on these internal nodes can be forced
to the exact value desired, as shown in
Figure 10
.
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Page 15
Applications Information (Continued)
FIGURE 10. Reference Ladder Force and Sense Inputs
Since the current flowing through the SENSE lines is essentially zero, there is negligible voltage drop across R
1kΩresistor, so the voltage at the inverting input of the op
and the
S
amp accurately represents the voltage at the top (or bottom)
of the ladder. The op amp drives the FORCE input and
forces the voltage at the ends of the ladder to equal the voltage at the op amps’s non-inverting input, plus or minus its input offset voltage. For this reason op amps with low V
such as the LMC6081, should be used for this application.
OS
When used in this configuration, the ADC12762 has less
than 4 LSBs of offset and gain error without any user adjustments.
The 0.1 µF and 10 µF capacitors on the force inputs provide
high frequency decoupling of the reference ladder.The 500Ω
force resistors isolate the op amps from this large capacitive
load. The 0.01 µF/1 kΩ network provides zero phase shift at
high frequencies to ensure stability.Note that the positive op
amp supply voltage must be at least 2.5V above the reference voltage and that a negative op amp supply is needed to
supply the sub-zero voltage to the V
V
output should be bypassed to analog ground with a
REF/16
0.1 µF ceramic capacitor.
REF− (FORCE)
pin. The
The reference inputs are fully differential and define the zero
to full-scale range of the input signal. They can be configured
to span up to 5V (V
connected to different voltages (within the 0V to 5V limits)
when other input spans are required. The ADC12762 is
tested at V
ducing the reference voltage span to less than 4V increases
REF− (SENSE)
REF−
=
=
0V, V
0V, V
=
5V), or they can be
REF+
REF+ (SENSE)
the sensitivity (reduces the LSB size) of the converter; however noise performance degrades when lower reference
voltages are used. A plot of dynamic performance vs refer-
,
ence voltage is given in the Typical Performance Characteristics section.
If the converter will be used in an application where DC accuracy is secondary to dynamic performance, then a simpler
reference circuit may suffice. The circuit shown in
will introduce several LSBs of offset and gain error, but INL,
DNL, and all dynamic specifications will be unaffected.
All bypass capacitors should be located as close to the
ADC12762 as possible to minimize noise on the reference
ladder. The V
ground with a 0.1 µF ceramic capacitor.
output should be bypassed to analog
REF/16
The LM4040 shunt voltage reference is available with a
4.096V output voltage. With initial accuracies as low as
±
0.1%, it makes an excellent reference for the ADC12762.
DS012811-33
=
4.096V. Re-
Figure 11
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Page 16
Applications Information (Continued)
FIGURE 11. Using the V
POWER SUPPLY CONSIDERATIONS
The ADC12762 is designed to operate from a single +5V
power supply. There are two analog supply pins (AV
one digital supply pin (DV
ternal bypass capacitors for the analog and digital portions of
). These pins allow separate ex-
CC
CC
) and
the circuit. To guarantee proper operation of the converter,
all three supply pins should be connected to the same voltage source. In systems with separate analog and digital supplies, the converter should be powered from the analog supply.
The ground pins are AGND (analog ground), DGND1 (digital
input ground), and DGND2 (digital output ground). These
pins allow for three separate ground planes for these sections of the chip. Isolating the analog section from the two
digital sections reduces digital interference in the analog circuitry, improving the dynamic performance of the converter.
Separating the digital outputs from the digital inputs (particularly the S/H input) reduces the possibility of ground bounce
from the 12 data lines causing jitter on the S/H input. The
analog ground plane should be connected to the Digital2
ground plane at the ground return for the power supply.The
Digital1 ground plane should be tied to the Digital2 ground
plane at the DGND1 and DGND2 pins.
Both AV
plane with 0.1 µF ceramic capacitors. One of the two AV
pins should also be bypassed with a 10 µF tantalum capaci-
www.national.com 16
pins should be bypassed to the AGND ground
CC
CC
DS012811-34
Force Pins Only
REF
tor. DV
with a 0.1 µF capacitor in parallel with a 10 µF tantalum ca-
should be bypassed to the DGND2 ground pIane
CC
pacitor.
LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC12762, it is necessary to use appropriate circuit board
layout techniques. Separate analog and digital ground
planes are required to meet datasheetAC and DC limits. The
analog ground plane should be low-impedance and free of
noise from other parts of the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a filter capacitor) connected across the converter’s input should
be connected to a very clean analog ground return point.
Grounding the component at the wrong point will result in increased noise and reduced conversion accuracy.
Figure 12
gives an example of a suitable layout, including
power supply routing, ground plane separation, and bypass
capacitor placement. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed on the
analog ground plane. All digital circuitry and I/O lines (ex-
Page 17
Applications Information (Continued)
cluding the S/H input) should use the digital2 ground plane
as ground. The digital1 ground plane should only be used for
the S/H signal generation.
DS012811-35
FIGURE 12. PC Board Layout
DYNAMIC PERFORMANCE
The ADC12762 is AC tested and its dynamic performance is
guaranteed. In order to meet these specifications, the clock
source driving the S/H input must be free of jitter. For the
best AC performance, a crystal oscillator is recommended.
For operation at or near the ADC12762’s 1.4 MHz maximum
sampling rate, a 1.4 MHz squarewave will provide a good
signal for the S/H input. As long as the duty cycle is near
50%, the waveform will be low for about 360 ns, which is
within the 400 ns limit. When operating the ADC12762 at a
sample rate of 1.25 MHz or below, the pulse width of the S/H
signal must be smaller than half the sample period.
DS012811-36
FIGURE 13. Crystal Clock Source
Figure 13
is an example of a low jitter S/H pulse generator
that can be used with the ADC12762 and allow operation at
sampling rates from DC to 1.4 MHz. A standard 4-pin DIP
crystal oscillator provides a stable 1.4 MHz squarewave.
Since most DIP oscillators have TTL outputs, a 4.7k pullup
resistor is used to raise the output high voltage to CMOS input levels. The output is fed to the trigger input (falling edge)
of an MM74HC4538 one-shot. The 1k resistor and 12 pF capacitor set the pulse length to approximately 100 ns. The
S/H pulse stream for the converter appears on the Q output
of the HC4538. This is the S/H clock generator used on the
ADC12062EVAL evaluation board. For lower power, a
CMOS inverter-based crystal oscillator can be used in place
of the DIP crystal oscillator. See Application Note AN-340 in
the National Semiconductor CMOS Logic Databook for more
information on CMOS crystal oscillators.
COMMON APPLICATION PITFALLS
Driving inputs (analog or digital) outside power supply
rails. The Absolute Maximum Ratings state that all inputs
must be between GND − 300 mV and V
rule is most often broken when the power supply to the con-
+ 300 mV. This
CC
verter is turned off, but other devices connected to it (op
amps, microprocessors) still have power. Note that if there is
no power to the converter, DGND=AGND=DV
=
0V, so all inputs should be within
±
300 mV of AGND and
=
AV
CC
DGND.
Driving a high capacitance digital data bus. The more ca-
pacitance the data bus has to charge for each conversion,
the more instantaneous digital current required from DV
and DGND. These large current spikes can couple back to
the analog section, decreasing the SNR of the converter.
While adequate supply bypassing and separate analog and
digital ground planes will reduce this problem, buffering the
digital data outputs (with a pair of MM74HC541s, for example) may be necessary if the converter must drive a
heavily loaded databus.
CC
CC
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Page 18
Applications Information (Continued)
9.0 APPLICATIONS
2’s Complement Output
DS012811-37
Ping-Ponging between V
IN1
and V
IN2
DS012811-38
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Page 19
Applications Information (Continued)
AC Coupling Bipolar Inputs
DS012811-39
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Page 20
Physical Dimensions inches (millimeters) unless otherwise noted
Plastic Leaded Chip Carrier (V)
Order Number ADC12762CCV
NS Package Number V44A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
ADC12762 12-Bit, 1.4 MHz, 300 mW A/D Converter with Input Multiplexer and Sample/Hold
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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