Datasheet ADC12138CIWM, ADC12138CIMSA, ADC12132CIMSA, ADC12130CIWM Datasheet (NSC)

ADC12130/ADC12132/ADC12138
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold

March 2000

ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with

MUX and Sample/Hold

General Description

The ADC12130, ADC12132 and ADC12138 are 12-bit plus
sign successiveapproximationA/D converters with serial I/O
and configurable input multiplexer. The ADC12132 and
ADC12138 have a 2 and an 8 channel multiplexer, respec­tively.The differential multiplexer outputs andA/D inputs are
available on the MUXOUT1, MUXOUT2,A/DIN1 and A/DIN2
pins. TheADC12130 has a two channel multiplexer with the
multiplexer outputs and A/D inputs internally connected. The
ADC12130 family is tested with a 5 MHz clock. On request,
these A/Ds go through a self calibration process that adjusts
linearity, zero and full-scale errors to typically less than
LSB each.

The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes. A fully differential unipolar analog
input range (0V to +5V) can be accommodated with a single
+5V supply. In the differential modes, valid outputs are ob­tained even when the negative inputs are greater than the
positive because of the 12-bit plus sign output data format.

The serial I/O is configured to comply with the NSC MI­CROWIRE
LM4041.

™

. For voltage references, see the LM4040 or

±

Features

n Serial I/O (MICROWIRE, SPI and QSPI Compatible)
n 2 or 8 channel differential or single-ended multiplexer
n Analog input sample/hold function
n Power down mode
n Programmable acquisition time
n Variable digital output word length and format
n No zero or full scale adjustment required
n 0V to 5V analog input range with single 5V power

supply

1

Key Specifications

n Resolution: 12-bit plus sign
n 12-bit plus sign conversion time: 8.8 µs (max)
n 12-bit plus sign throughput time: 14 µs (max)
n Integral linearity error:
n Single supply: 3.3V or 5V
n Power consumption

— 3.3V 15 mW (max)
— 3.3V power down 40 µW (typ)
— 5V 33 mW (max)
— 5V power down 100 µW (typ)

±

2 LSB (max)

±

10%

Applications

n Pen-based computers
n Digitizers
n Global positioning systems

ADC12138 Simplified Block Diagram

DS012079-1

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

™

COPS

microcontrollers, HPC™and MICROWIRE™are trademarks of National Semiconductor Corporation.

© 2000 National Semiconductor Corporation DS012079 www.national.com

Ordering Information

Industrial Temperature Range

ADC12130CIN N16E, Dual-In-Line
ADC12130CIWM M16B, Wide Body SO
ADC12132CIMSA MSA20, SSOP
ADC12138CIN N28B, Dual-In-Line
ADC12138CIWM M28B
ADC12138CIMSA MSA28, SSOP

Connection Diagrams

ADC12130/ADC12132/ADC12138

16-Pin Dual-In-Line and

Wide Body SO Packages

Top View

−40˚C ≤ T

DS012079-2

≤ +85˚C

A

NS Package Number

20-Pin SSOP Package

DS012079-47

Top View

28-Pin Dual-In-Line, SSOP and

Wide Body SO Packages

DS012079-3

Top View

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Pin Descriptions

CCLK The clock applied to this input controls the su-

cessive approximation conversion time interval
and the acquisition time. The rise and falltimes
of the clock edges should not exceed 1 µs.

SCLK This is the serial data clock input. The clock

applied to this input controls the rate at which
the serial data exchange occurs. The rising
edge loads the information on the DI pin into
the multiplexer address and mode select shift
register. This address controls which channel
of the analog input multiplexer (MUX) is se­lected and the mode of operation for the A/D.
With CS low, the falling edge of SCLK shifts
the data resulting from the previous ADC con­version out on DO, with the exception of the
first bit of data. When CS is low continuously,
the first bit of the data is clocked out on the ris­ing edge of EOC (end of conversion). When
CS is toggled, the falling edge of CS always
clocks out the first bit of data. CS should be
brought low when SCLK is low. The rise and
fall times of the clock edges should not exceed
1 µs.

DI This is the serial data input pin. The data ap-

plied to this pin is shifted by the rising edge of
SCLK into the multiplexer address and mode
select register.
the assignment of the multiplexer address and
the mode select data.

DO The data output pin. This pin is an active push/

pull output when CS is low. When CS is high,
this output is TRI-STATE. The A/D conversion
result (DB0–DB12) and converter status data
are clocked out by the falling edge of SCLK on
this pin. The word length and format of this re­sult can vary (see
and format are controlled by the data shifted
into the multiplexer address and mode select
register (see

EOC This pin is an active push/pull output and indi-

cates the status of the ADC12130/2/8. When
low, it signals that the A/D is busy with a con­version, auto-calibration, auto-zero or power
down cycle. The rising edge of EOC signals
the end of one of these cycles.

CS

This is the chip select pin. When a logic low is
applied to this pin, the rising edge of SCLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE.
With CS low, the falling edge of SCLK shifts
the data resulting from the previous ADC con­version out on DO, with the exception of the
first bit of data. When CS is low continuously,
the first bit of the data is clocked out on the ris­ing edge of EOC (end of conversion). When
CS is toggled, the falling edge of CS always
clocks out the first bit of data. CS should be
brought low when SCLK is low. The falling
edge of CS resets a conversion in progress
and starts the sequence for a new conversion.
When CS is brought back low during a conver­sion, that conversion is prematurely termi­nated. The data in the output latches may be
corrupted. Therefore, whenCS is brought back

Table 2

Table 4

through

Table 1

). The word length

).

Table 4

show

low during a conversion in progress the data
output at that time should be ignored. CS may
also be left continuously low. In this case it is
imperative that the correct number of SCLK
pulses be applied to the ADC in order to re­main synchronous. After the ADC supply
power is applied it expects to see 13 clock
pulses for each I/O sequence. The number of
clock pulses the ADC expects is the same as
the digital output word length. This word length
can be modified by the data shifted in on the

DOR

DO pin.
This is the data output ready pin. This pin is an

Table 4

details the data required.

active push/pull output. It is low when the con­version result is being shifted out and goes
high to signal that all the data has been shifted
out.

CONV

A logic low is required on this pin to program
any mode or change the ADC’s configuration
as listed in the Mode Programming Table
(

Table 4

) such as 12-bit conversion, Auto Cal,
Auto Zero etc. When this pin is high theADC is
placed in the read dataonly mode. While in the
read data only mode, bringing CS low and
pulsing SCLK will only clock out on DO any
data stored in the ADCs output shift register.
The data on DI will be neglected. A new con­version will not be started and the ADC will re­main in the mode and/or configuration previ­ously programmed. Read data only cannot be
performed while a conversion, Auto-Cal or
Auto-Zero are in progress.

PD This is the power down pin. When PD is high

the A/D is powered down; when PD is low the
A/D is powered up. The A/D takes a maximum
of 700 µs to power up after the command is
given.

CH0–CH7 These are the analog inputs of the MUX. A

channel input is selected by the address infor­mation at the DI pin, which is loaded on the ris­ing edge of SCLK into the address register
(see

Table 2

and

Table 3

).

The voltage applied to these inputs should not
exceed V

+ or go below GND. Exceeding this

A

range on an unselected channel will corrupt
the reading of a selected channel.

COM This pin is another analog input pin. It is used

as a pseudo ground when the analog multi­plexer is single-ended.

MUXOUT1,
MUXOUT2

A/DIN1,
A/DIN2

These are the multiplexer output
pins.

These are the converter input pins. MUXOUT1
is usually tied to A/DIN1. MUXOUT2 is usually
tied to A/DIN2. If external circuitry is placedbe­tween MUXOUT1 and A/DIN1, or MUXOUT2
and A/DIN2 it may be necessary to protect
these pins. The voltage at these pins should
not exceed V

5

).

V

+ This is the positive analog voltage reference

REF

+

or go belowAGND (see

A

Figure

input. In order to maintain accuracy, the volt­age range of V

REF(VREF=VREF

+−V

REF

−) is

ADC12130/ADC12132/ADC12138

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Pin Descriptions (Continued)

1V

to 5.0 VDCand the voltage at V

DC

cannot exceed V
mended bypassing.

V

− The negative voltage reference input. In order

REF

to maintain accuracy, the voltage at this pin
must not go below GND or exceed V

Figure 6

).

ADC12130/ADC12132/ADC12138

+. See

A

Figure 6

REF

for recom-

+. (See

A

+, VD+ These are the analog and digital power supply

V

A

pins. V

+

on the chip. These pins should be tied to the

A

+

and V

+

are not connected together

D

same power supply and bypassed separately
(see

Figure 6

V

+ and VD+ is 3.0 VDCto 5.5 VDC.

A

DGND This is the digital ground pin (see
AGND This is the analog ground pin (see

). The operating voltage range of

Figure 6

Figure 6

).

).

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ADC12130/ADC12132/ADC12138

Absolute Maximum Ratings (Notes 1, 2)

Storage Temperature −65˚C to +150˚C

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Positive Supply Voltage

+

(V

=VA+=VD+) 6.5V

Voltage at Inputs and Outputs

+

except CH0–CH7 and COM −0.3V to V

+0.3V

Voltage at Analog Inputs

+

±

30 mA

±

120 mA

+5V

CH0–CH7 and COM GND −5V to V

+−VD+| 300 mV

|V

A

Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at

= 25˚C (Note 4) 500 mW

T

A

ESD Susceptability (Note 5)

Human Body Model 1500V

Soldering Information

N Packages (10 seconds) 260˚C

Operating Ratings (Notes 1, 2)

Operating Temperature Range T

ADC12130CIN, ADC12130CIWM,
ADC12132CIMSA,
ADC12138CIMSA,
ADC12138CIN, ADC12138CIWM −40˚C ≤ T

+

Supply Voltage (V

+−VD+| ≤ 100 mV

|V

A

+ 0VtoVA+

V

REF

− 0VtoV

V

REF

V

REF(VREF

V

REF

+−V

Common Mode Voltage Range

=VA+=VD+) +3.0V to +5.5V

−) 1V to VA+

REF

A/DIN1, A/DIN2, MUXOUT1

and MUXOUT2 Voltage Range 0V to V

A/D IN Common Mode Voltage

Range

≤ TA≤ T

MIN

A

0.1 VA+ to 0.6 VA+

SO Package (Note 6):

Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C

0V to VA+

Converter Electrical Characteristics

The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = 3.3V, V
common-mode voltage), V
25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=T

to T

; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)

MAX

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V

REF

+ = 2.5V and fully-differential input with fixed 1.250V

REF

Symbol Parameter Conditions Typical

STATIC CONVERTER CHARACTERISTICS

Resolution 12 + sign Bits (min)

+ILE Positive Integral Linearity Error After Auto-Cal (Notes 12, 18)

−ILE Negative Integral Linearity Error After Auto-Cal (Notes 12, 18)
DNL Differential Non-Linearity After Auto-Cal

Positive Full-Scale Error After Auto-Cal (Notes 12, 18)
Negative Full-Scale Error After Auto-Cal (Notes 12, 18)
Offset Error After Auto-Cal (Notes 5, 18)

V

(+)=VIN(−) = 2.048V

IN

DC Common Mode Error After Auto-Cal (Note 15)

TUE Total Unadjusted Error After Auto-Cal

(Notes 12, 13, 14)

+ = +4.096V, and fully differential input with fixed 2.048V

REF

−

and V

REF

Limits Units

(Note 10)

±

1/2

±

1/2

±

1/2

±

1/2

±

1/2

±

2 LSB (max)

±

1 LSB

(Note 11)

±

2 LSB (max)

±

2 LSB (max)

±

1.5 LSB (max)

±

3.0 LSB (max)

±

3.0 LSB (max)

±

2 LSB (max)

MAX

≤ +85˚C

REF

+

REF

MIN

(Limits)

+

+

A

≤

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Converter Electrical Characteristics

The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = 3.3V, V
common-mode voltage), V

≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T

MIN

to T

; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9) (Continued)

MAX

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V

REF

+ = +2.5V and fully-differential input with fixed 1.250V

REF

Symbol Parameter Conditions Typical

STATIC CONVERTER CHARACTERISTICS (Continued)

Multiplexer Channel to Channel
Matching
Power Supply Sensitivity V

ADC12130/ADC12132/ADC12138

+

= +5V±10%

V

= +4.096V

REF

Offset Error

+ Full-Scale Error

− Full-Scale Error

+ Integral Linearity Error

− Integral Linearity Error

UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS

S/(N+D) Signal-to-Noise Plus f

Distortion Ratio f

−3 dB Full Power Bandwidth V

= 1 kHz, VIN=5VPP,V

IN

= 20 kHz, VIN=5VPP,V

IN

f

= 40 kHz, VIN=5VPP,V

IN

=5VPP, where S/(N+D) drops 3 dB 31 kHz

IN

DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS

S/(N+D) Signal-to-Noise Plus f

Distortion Ratio f

−3 dB Full Power Bandwidth V

= 1 kHz, VIN=±5V, V

IN

= 20 kHz, VIN=±5V, V

IN

f

= 40 kHz, VIN=±5V, V

IN

=±5V, where S/(N+D) drops 3 dB 40 kHz

IN

+ = +4.096V, and fully differential input with fixed 2.048V

REF

Limits Units

(Note 10)

±

0.05 LSB

±

0.5 LSB

±

0.5 LSB

±

0.5 LSB

±

0.5 LSB

±

0.5 LSB

+

= 5.0V 69.4 dB

REF

+

= 5.0V 68.3 dB

REF

+ = 5.0V 65.7 dB

REF

+

= 5.0V 77.0 dB

REF

+

= 5.0V 73.9 dB

REF

+

= 5.0V 67.0 dB

REF

(Note 11)

REF

− and V

+

REF

(Limits)

Electrical Characteristics

The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = +3.3V, V
common-mode voltage), V

≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T

MIN

to T

; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)

MAX

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V

REF

+ = 2.5V and fully-differential input with fixed 1.250V

REF

Symbol Parameter Conditions Typical Limits Units

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS

C

REF

C

A/D

Reference Input Capacitance 85 pF
A/DIN1 and A/DIN2 Analog Input 75 pF
Capacitance
A/DIN1 and A/DIN2 Analog Input V

Leakage Current V

= +5.0V or

IN

=0V

IN

CH0–CH7 and COM Input Voltage GND − 0.05 V

C

CH

CH0–CH7 and COM Input
Capacitance

C

MUXOUT

MUX Output Capacitance 20 pF
Off Channel Leakage (Note 16) On Channel = 5V and −0.01 µA
CH0–CH7 and COM Pins Off Channel = 0V

On Channel = 0V and 0.01 µA
Off Channel = 5V

+ = +4.096V, and fully differential input with fixed 2.048V

REF

− and V

REF

(Note 10) (Note 11) (Limits)

±

0.1 µA

V

+ + 0.05

A

10 pF

REF

+

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Electrical Characteristics (Continued)

The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = +3.3V, V
common-mode voltage), V

≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T

MIN

to T

; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)

MAX

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V

REF

+ = 2.5V and fully-differential input with fixed 1.250V

REF

Symbol Parameter Conditions Typical Limits Units

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS

On Channel Leakage (Note 16) On Channel = 5V and 0.01 µA
CH0–CH7 and COM Pins Off Channel = 0V

On Channel = 0V and −0.01 µA
Off Channel = 5V

R

ON

MUXOUT1 and MUXOUT2 V
Leakage Current V
MUX On Resistance VIN= 2.5V and 850 1900 Ω (max)

R

Matching Channel to Channel VIN= 2.5V and 5 %

ON

Channel to Channel Crosstalk V

MUXOUT
MUXOUT

V

MUXOUT

V

MUXOUT

=5VPP,fIN= 40 kHz −72 dB

IN

MUX Bandwidth 90 kHz

+ = +4.096V, and fully differential input with fixed 2.048V

REF

− and V

REF

REF

(Note 10) (Note 11) (Limits)

= 5.0V or 0.01 µA
=0V

= 2.4V

= 2.4V

ADC12130/ADC12132/ADC12138

+

DC and Logic Electrical Characteristics

The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V
common-mode voltage), V
≤ 25Ω,f

T

to T

MIN

CK=fSK

= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=

; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)

MAX

+

=VA+=VD+ = +3.3V, V

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V

REF

+ = +2.5V and fully-differential input with fixed 1.250V

REF

Symbol Parameter Conditions Typical

CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS

V

IN(1)

Logical “1” Input

VA+=VD+=V++10% 2.0 2.0 V (min)

Voltage

V

IN(0)

Logical “0” Input

VA+=VD+=V+−10% 0.8 0.8 V (max)

Voltage

I

IN(1)

Logical “1” Input

VIN=V

+

Current

I

IN(0)

Logical “0” Input

VIN= 0V −0.005 −1.0 −1.0 µA (min)

Current

DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS

V

V

I

+I

OUT

OUT(1)

OUT(0)

SC

Logical “1” VA+=VD+=V+− 10%,
Output Voltage I

= −360 µA 2.4 2.4 V (min)

OUT

V

+=VD+=V+− 10%, 2.9 4.25 V (min)

A

I

= −10 µA

OUT

Logical “0” VA+=VD+=V+− 10%
Output Voltage I
TRI-STATE V
Output Current V
Output Short

= 1.6 mA 0.4 0.4 V (max)

OUT

= 0V −0.1 −3.0 −3.0 µA (max)

OUT
OUT

V

OUT

+

=V

= 0V −14 mA
Circuit Source
Current

+ = +4.096V, and fully-differential input with fixed 2.048V

REF

(Note

10)

0.005 1.0 1.0 µA (max)

−0.1 3.0 3.0

− and V

REF

+

=VA+= V+=VA+ = Units

V

+ = 3.3V VD+=5V

V

D

Limits Limits

(Note 11) (Note 11)

+

REF

(Limits)

www.national.com7

DC and Logic Electrical Characteristics (Continued)

The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = +3.3V, V
common-mode voltage), V

≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T

MIN

to T

; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)

MAX

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V

REF

+ = +2.5V and fully-differential input with fixed 1.250V

REF

Symbol Parameter Conditions Typical

DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS

−I

SC

ADC12130/ADC12132/ADC12138

Output Short
Circuit Sink

V

OUT=VD

+16 mA

Current

POWER SUPPLY CHARACTERISTICS

I

+ Digital Supply 1.5 2.5 mA (max)

D

Current CS = HIGH, Powered Down, CCLK on

CS = HIGH, Powered Down, CCLK off

I

+ Positive Analog 3.0 4.0 mA (max)

A

Supply Current CS = HIGH, Powered Down, CCLK on

CS = HIGH, Powered Down, CCLK off

I

REF

Reference Input

Current CS = HIGH, Powered Down, CCLK on

CS = HIGH, Powered Down, CCLK off

+ = +4.096V, and fully-differential input with fixed 2.048V

REF

− and V

REF

+

=VA+= V+=VA+ = Units

(Note

10)

V

+ = 3.3V VD+=5V

V

D

Limits Limits

(Note 11) (Note 11)

600 µA

20 µA

10 µA

0.1 µA

70 µA

0.1 µA

+

REF

(Limits)

AC Electrical Characteristics

The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V
common-mode voltage), V
≤ 25Ω,f

T

to T

MIN

CK=fSK

= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=

; all other limits TA=TJ= 25˚C. (Note 17)

MAX

+

=VA+=VD+ = +3.3V, V

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V

REF

+ = +2.5V and fully-differential input with fixed 1.250V

REF

Symbol Parameter Conditions Typical Limits Units

f

CK

Conversion Clock 10 5 MHz (max)
(CCLK) Frequency 1 MHz (min)

f

SK

Serial Data Clock 10 5 MHz (max)
SCLK Frequency 0 Hz (min)
Conversion Clock 40 % (min)
Duty Cycle 60 % (max)
Serial Data Clock 40 % (min)
Duty Cycle 60 % (max)

t

C

Conversion Time 12-Bit + Sign or 12-Bit 44(tCK) 44(tCK) (max)

+ = +4.096V, and fully-differential input with fixed 2.048V

REF

− and V

REF

(Note

10)

(Note

11)

8.8 µs (max)

REF

(Limits)

+

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AC Electrical Characteristics (Continued)

The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = +3.3V, V
common-mode voltage), V

≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T

MIN

to T

; all other limits TA=TJ= 25˚C. (Note 17)

MAX

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V

REF

+ = +2.5V and fully-differential input with fixed 1.250V

REF

Symbol Parameter Conditions Typical Limits Units

t

A

Acquisition Time 6 Cycles Programmed 6(tCK) 6(tCK) (min)
(Note 19) 7(t

t

CAL

t

AZ

t

SYNC

Self-Calibration Time 4944(tCK) 4944(tCK) (max)

Auto-Zero Time 76(tCK) 76(tCK) (max)

Self-Calibration or 2(tCK) 2(tCK) (min)
Auto-Zero Synchronization 3(t
Time from DOR 0.40 µs (min)

t

DOR

DOR High Time when CS is Low 9(tSK) 9(tSK) (max)
Continuously for Read Data and Software

Power Up/Down

t

CONV

CONV Valid Data Time 8(tSK) 8(tSK) (max)

+ = +4.096V, and fully-differential input with fixed 2.048V

REF

(Note

10)

(Note

11)

CK

1.2 µs (min)

1.4 µs (max)

10 Cycles Programmed 10(t

) 10(tCK) (min)

CK

11(t

CK

2.0 µs (min)

2.2 µs (max)

18 Cycles Programmed 18(t

) 18(tCK) (min)

CK

19(t

CK

3.6 µs (min)

3.8 µs (max)

34 Cycles Programmed 34(t

) 34(tCK) (min)

CK

35(t

CK

6.8 µs (min)

7.0 µs (max)

988.8 µs (max)

15.2 µs (max)

CK

0.60 µs (max)

1.8 µs (max)

1.6 µs (max)

− and V

REF

REF

(Limits)

) (max)

) (max)

) (max)

) (max)

) (max)

ADC12130/ADC12132/ADC12138

+

AC Electrical Characteristics

The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V
common-mode voltage), V
≤ 25Ω,f

T

to T

MIN

CK=fSK

= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=

; all other limits TA=TJ= 25˚C. (Note 17) (Continued)

MAX

+

=VA+=VD+ = +3.3V, V

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V

REF

+ = +2.5V and fully-differential input with fixed 1.250V

REF

Symbol Parameter Conditions Typical Limits Units

t

HPU

Hardware Power-Up Time, Time from 500 700 µs (max)
PD Falling Edge to EOC Rising Edge

t

SPU

Software Power-Up Time, Time from
Serial Data Clock Falling Edge to 500 700 µs (max)
EOC Rising Edge

t

ACC

Access Time Delay from 25 60 ns (max)
CS Falling Edge to DO Data Valid

+ = +4.096V, and fully-differential input with fixed 2.048V

REF

− and V

REF

(Note 10) (Note 11) (Limits)

www.national.com9

REF

+

AC Electrical Characteristics (Continued)

The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = +3.3V, V
common-mode voltage), V

≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T

MIN

to T

; all other limits TA=TJ= 25˚C. (Note 17) (Continued)

MAX

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V

REF

+ = +2.5V and fully-differential input with fixed 1.250V

REF

Symbol Parameter Conditions Typical Limits Units

t

SET-UP

Set-Up Time of CS Falling Edge to 50 ns (min)
Serial Data Clock Rising Edge

t

DELAY

ADC12130/ADC12132/ADC12138

t1H,t

0H

t

HDI

Delay from SCLK Falling 0 5 ns (min)
Edge to CS Falling Edge
Delay from CS Rising Edge to RL= 3k, CL= 100 pF 70 100 ns (max)
DO TRI-STATE

®

DI Hold Time from Serial Data 5 15 ns (min)
Clock Rising Edge

t

SDI

DI Set-Up Time from Serial Data 5 10 ns (min)
Clock Rising Edge

t

HDO

DO Hold Time from Serial Data RL= 3k, CL= 100 pF 35 65 ns (max)
Clock Falling Edge 5 ns (min)

t

DDO

Delay from Serial Data Clock 50 90 ns (max)
Falling Edge to DO Data Valid

t

RDO

DO Rise Time, TRI-STATE to High RL= 3k, CL= 100 pF 10 40 ns (max)
DO Rise Time, Low to High 10 40 ns (max)

t

FDO

DO Fall Time, TRI-STATE to Low RL= 3k, CL= 100 pF 15 40 ns (max)
DO Fall Time, High to Low 15 40 ns (max)

t

CD

Delay from CS Falling Edge 45 80 ns (max)
to DOR Falling Edge

t

SD

Delay from Serial Data Clock Falling 45 80 ns (max)
Edge to DOR Rising Edge

C

IN

C

OUT

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is func­tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci­fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V

The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

allowable power dissipation at any temperature is P

max = 150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow:

T

J

Capacitance of Logic Inputs 10 pF
Capacitance of Logic Outputs 20 pF

) at any pin exceeds the power supplies (V

IN

=(TJmax − TA)/θJAor the number given in theAbsolute Maximum Ratings, whichever is lower. For this device,

D

+ = +4.096V, and fully-differential input with fixed 2.048V

REF

REF

(Note 10) (Note 11) (Limits)

IN

<

GND or V

>

VA+orVD+), the current at that pin should be limited to 30 mA.

IN

max, θJAand the ambient temperature, TA. The maximum

J

− and V

REF

+

Thermal

Part Number Resistance

θ

JA

ADC12130CIN 53˚C/W
ADC12130CIWM 70˚C/W
ADC12132CIMSA 134˚C/W
ADC12138CIN 40˚C/W
ADC12138CIWM 50˚C/W
ADC12138CIMSA 125˚C/W

Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semi-

conductor Linear Data Book for other methods of soldering surface mount devices.

www.national.com 10

AC Electrical Characteristics (Continued)

Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND

will not damage this device. However,errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above V

to ensure accurate conversions.

V

DC

Note 8: To guarantee accuracy, it is required that the V
pin.

Note 9: With the test condition for V
Note 10: Typicals are at T

REF(VREF

= 25˚C and represent most likely parametric norm.

J=TA

Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive

full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions be-

tween −1 to 0 and 0 to +1 (see

Figure 4

).

Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, V

to 1.4V.
Note 18: The ADC12130 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will re-

sult in a maximum repeatability uncertainty of 0.2 LSB.

Note 19: If SCLK and CCLK are driven from the same clock source, then t
Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output

data from these modes are not an indication of the accuracy of a conversion result.

+ or below GND by more than 50 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55

A

DS012079-4

+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V

A

+−V

−) given as +4.096V, the 12-bit LSB is 1.0 mV. For V

REF

= 0.4V for a falling edgeand VOL= 2.4V for a rising edge.TRI-STATEoutput voltage isforced

OL

is 6, 10, 18 or 34 clock periods minimum and maximum.

A

= 2.5V, the 12-bit LSB is 610 µV.

REF

Figure 2

and

Figure 3

).

ADC12130/ADC12132/ADC12138

+

FIGURE 1. Transfer Characteristic

DS012079-5

www.national.com11

AC Electrical Characteristics (Continued)

ADC12130/ADC12132/ADC12138

FIGURE 2. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles

DS012079-6

FIGURE 3. Simplified Error Curve vs Output Code after Auto-Calibration Cycle

FIGURE 4. Offset or Zero Error Voltage

www.national.com 12

DS012079-7

DS012079-8

Typical Performance Characteristics The following curves apply for 12-bit + sign mode after

auto-calibration unless otherwise specified.

ADC12130/ADC12132/ADC12138

Linearity Error Change
vs Clock Frequency

Linearity Error Change
vs Supply Voltage

DS012079-53

Linearity Error Change
vs Temperature

Full-Scale Error Change
vs Clock Frequency

DS012079-54

Linearity Error Change
vs Reference Voltage

DS012079-55

Full-Scale Error Change
vs Temperature

Full-Scale Error Change
vs Reference Voltage

DS012079-56

DS012079-59

Full-Scale Error Change
vs Supply Voltage

DS012079-57

DS012079-60

DS012079-58

Zero Error Change
vs Clock Frequency

DS012079-61

www.national.com13

Typical Performance Characteristics The following curves apply for 12-bit + sign mode after

auto-calibration unless otherwise specified. (Continued)

Zero Error Change
vs Temperature

ADC12130/ADC12132/ADC12138

DS012079-62

Analog Supply Current
vs Temperature

Zero Error Change
vs Reference Voltage

Digital Supply Current
vs Clock Frequency

DS012079-63

Zero Error Change
vs Supply Voltage

DS012079-64

Digital Supply Current
vs Temperature

Linearity Error Change
vs Temperature

Zero Error Change
vs Temperature

DS012079-65

DS012079-68

Full-Scale Error Change
vs Temperature

Zero Error Change
vs Supply Voltage

DS012079-66

DS012079-69

DS012079-67

Full-Scale Error Change
vs Supply Voltage

DS012079-70

Analog Supply Current
vs Temperature

DS012079-71

www.national.com 14

DS012079-72

DS012079-73

Typical Performance Characteristics The following curves apply for 12-bit + sign mode after

auto-calibration unless otherwise specified. (Continued)

Digital Supply Current
vs Temperature

DS012079-74

Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign

mode after auto-calibration unless otherwise specified.

ADC12130/ADC12132/ADC12138

Bipolar Spectral Response

with 1 kHz Sine Wave Input

DS012079-75

Bipolar Spectral Response

with 30 kHz Sine Wave Input

Bipolar Spectral Response

with 10 kHz Sine Wave Input

DS012079-76

Bipolar Spectral Response

with 40 kHz Sine Wave Input

Bipolar Spectral Response

with 20 kHz Sine Wave Input

DS012079-77

Bipolar Spectral Response

with 50 kHz Sine Wave Input

DS012079-78

DS012079-79

DS012079-80

www.national.com15

Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign

mode after auto-calibration unless otherwise specified. (Continued)

Bipolar Spurious Free

Dynamic Range

ADC12130/ADC12132/ADC12138

DS012079-81

Unipolar Signal-to-Noise

+ Distortion Ratio

vs Input Signal Level

Unipolar Signal-to-Noise Ratio

vs Input Frequency

DS012079-82

Unipolar Spectral Response

with 1 kHz Sine Wave Input

Unipolar Signal-to-Noise

+ Distortion Ratio

vs Input Frequency

DS012079-83

Unipolar Spectral Response

with 10 kHz Sine Wave Input

DS012079-84

Unipolar Spectral Response

with 20 kHz Sine Wave Input

DS012079-87

DS012079-85

Unipolar Spectral Response

with 30 kHz Sine Wave Input

DS012079-88

DS012079-86

Unipolar Spectral Response

with 40 kHz Sine Wave Input

DS012079-89

www.national.com 16

Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign

mode after auto-calibration unless otherwise specified. (Continued)

Unipolar Spectral Response

with 50 kHz Sine Wave Input

DS012079-90

Test Circuits

ADC12130/ADC12132/ADC12138

DO “TRI-STATE” (t1H,t0H)

DO except “TRI-STATE”

DS012079-13

DS012079-14

Leakage Current

DS012079-15

Timing Diagrams

DO Falling and Rising Edge

DO “TRI-STATE” Falling and Rising Edge

DS012079-16

DS012079-17

www.national.com17

Timing Diagrams (Continued)

ADC12130/ADC12132/ADC12138

DI Data Input Timing

DS012079-18

DO Data Output Timing Using CS

DO Data Output Timing with CS Continuously Low

DS012079-19

DS012079-20

www.national.com 18

Timing Diagrams (Continued)

Note: DO output data is not valid during this cycle.

ADC12130/ADC12132/ADC12138

ADC12138 Auto Cal or Auto Zero

DS012079-21

ADC12138 Read Data without Starting a Conversion Using CS

DS012079-22

www.national.com19

Timing Diagrams (Continued)

ADC12138 Read Data without Starting a Conversion with CS Continuously Low

ADC12130/ADC12132/ADC12138

DS012079-23

ADC12138 Conversion Using CS with 16-Bit Digital Output Format

DS012079-24

www.national.com 20

Timing Diagrams (Continued)

ADC12138 Conversion with CS Continuously Low and 16-Bit Digital Output Format

ADC12130/ADC12132/ADC12138

ADC12138 Software Power Up/Down Using CS with 16-Bit Digital Output Format

DS012079-25

DS012079-26

www.national.com21

Timing Diagrams (Continued)

ADC12138 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format

ADC12130/ADC12132/ADC12138

DS012079-27

ADC12138 Hardware Power Up/Down

DS012079-28

Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will
be stored in the output shift register.

www.national.com 22

Timing Diagrams (Continued)

ADC12138 Configuration Modification—Example of a Status Read

ADC12130/ADC12132/ADC12138

DS012079-29

DS012079-30

FIGURE 5. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins

www.national.com23

Timing Diagrams (Continued)

ADC12130/ADC12132/ADC12138

*

Tantalum

*

Monolithic Ceramic or better

*

DS012079-31

FIGURE 6. Recommended Power Supply Bypassing and Grounding

www.national.com 24

Tables

TABLE 1. Data Out Formats

DO Formats DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16

17XXXXSign MSB 10 9 8 7 654321LSB

Bits

MSB

First

with

Sign

LSB
First

MSB
First

without

Sign

LSB
First

X = High or Low state.

13 Sign MSB 10 9 8 76543 2 1LSB

Bits

17LSB123 45678910MSBSign XXXX

Bits

13LSB123 45678910MSBSign

Bits

160000MSB109876 54321LSB

Bits

12MSB10987 654321LSB

Bits

16LSB12345678910MSB0000

Bits

12LSB12345678910MSB

Bits

ADC12130/ADC12132/ADC12138

TABLE 2. ADC12138 Multiplexer Addressing

Analog Channel Addressed A/D Input Multiplexer Mode

MUX and Assignment Polarity Output

Address with A/DIN1 tied to MUXOUT1 Assignment Channel

and A/DIN2 tied to MUXOUT2 Assignment

DI0 DI1 DI2 DI3 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2

LLLL+− + − CH0 CH1
L L L H + − + − CH2 CH3
L L H L + − + − CH4 CH5
L L H H + − + − CH6 CH7 Differential
L H L L − + − + CH0 CH1
LHLH −+ − + CH2 CH3
L H H L − + − + CH4 CH5
L H H H − + − + CH6 CH7
H L L L + − + − CH0 COM
H L L H + − + − CH2 COM
HLHL + − + − CH4 COM
H L H H + − + − CH6 COM Single-Ended
H H L L + − + − CH1 COM
H H L H + − + − CH3 COM
H H H L + − + − CH5 COM
HHHH + − + − CH7 COM

www.national.com25

Tables (Continued)

TABLE 3. ADC12130 and ADC12132 Multiplexer Addressing

Analog Channel Addressed A/D Input Multiplexer Mode

MUX and Assignment Polarity Output

Address with A/DIN1 tied to MUXOUT1 Assignment Channel

and A/DIN2 tied to MUXOUT2 Assignment

DI0 DI1 CH0 CH1 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2

L L + − + − CH0 CH1 Differential
L H − + − + CH0 CH1

H L + − + − CH0 COM Single-Ended

ADC12130/ADC12132/ADC12138

H H + − + − CH1 COM

Note: ADC12130 do not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins.

TABLE 4. Mode Programming

ADC12138 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 Mode Selected
ADC12130

and DI0 DI1 DI2 DI3 DI4 DI5

ADC12132

See

Table 2orTable

LLLL 12BitConversion 12 or 13 Bit MSB First

(Current)

DO Format

(next Conversion

Cycle)

3

See

Table 2orTable

L L L H 12 Bit Conversion 16 or 17 Bit MSB First

3

See

Table 2orTable

L H L L 12 Bit Conversion 12 or 13 Bit LSB First

3

See

Table 2orTable

LHLH 12BitConversion 16 or 17 Bit LSB First

3

L L L L H L L L Auto Cal No Change
L L L L H L L H Auto Zero No Change
LLLLHLHL Power Up No Change
LLLLHLHH Power Down No Change
LLLLHHLL Read Status Register No Change
LLLLHHLH Data Out without Sign No Change

H L L L H H L H Data Out with Sign No Change

LLLLHHHLAcquisition Time—6 CCLK Cycles No Change

L H L L H H H L Acquisition Time—10 CCLK Cycles No Change
H L L L H H H L Acquisition Time—18 CCLK Cycles No Change
H H L L H H H L Acquisition Time—34 CCLK Cycles No Change

LLLLHHHH User Mode No Change
HXXXHHHH Test Mode No Change

(CH1–CH7 become Active Outputs)

Note: The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB First, and user mode.
X = Don’t Care

TABLE 5. Conversion/Read Data Only Mode Programming

CS CONV PD Mode

LLL See

L H L Read Only (Previous DO Format). No Conversion.
H X L Idle
X X H Power Down

X = Don’t Care

www.national.com 26

Table 4

for Mode

Tables (Continued)

TABLE 6. Status Register

Status Bit DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8

Location

Status Bit PU PD Cal 12 or 13 16 or 17 Sign Justification Test

Mode

Device Status DO Output Format Status

Function

“High”
indicates
a Power
Up
Sequence
is in
progress

“High”
indicates
a Power
Down
Sequence
is in
progress

“High”
indicates
an
Auto-Cal
Sequence
is in
progress

Not used “High”

indicates
a12or
13 bit
format

“High”
indicates
a16or
17 bit
format

“High”
indicates
that the
sign bit is
included.
When
“Low” the
sign bit is
not
included.

When
“High” the
conversion
result will
be output
MSB first.
When “Low”
the result
will be
output LSB
first.

When
“High”
the
device is
in test
mode.
When
“Low” the
device is
in user
mode.

Application Hints

1.0 DIGITAL INTERFACE

1.1 Interface Concepts

The example in
after the power is applied to the ADC12130/2/8:

FIGURE 7. Typical Power Supply Power Up Sequence

The first instruction input to the A/D via DI initiatesAuto Cal.
The data output on DO at that time is meaningless and is
completely random. To determine whether the Auto Cal has
been completed, a read status instruction is issued to the
A/D. Again the data output at that time has no significance
since theAuto Cal procedure modifies the data in the output
shift register. To retrieve the status information, an additional
read status instruction is issued to the A/D. At this time the
status data is available on DO. If the Cal signal in the status
word, is low Auto Cal has been completed. Therefore, the
next instruction issued can start a conversion. The data out­put at this time is again status information. To keep noise
from corrupting the A/D conversion, status can not be read
during a conversion. If CS is strobed and is brought low dur­ing a conversion, that conversion is prematurely ended.
EOC can be used to determine the end of a conversion or
theA/D controller cankeep track insoftware of when it would
be appropriate to comnmunicate to the A/D again. Once it
has been determined that the A/D has completed a conver­sion, another instruction can be transmitted to the A/D. The
data from this conversion can be accessed when the next in­struction is issued to the A/D.

Note, when CS is low continuously it is important to transmit
the exact number of SCLK cycles, as shown in the timing
diagrams. The Data Out Format sets the number of SCLK
cycles required in the next I/O cycle. A12-bit no sign format
will require 12 SCLKs to be transmitted; a 12-bit plus sign

Figure 7

shows a typical sequence of events

DS012079-32

format will require 13 SCLKs to be transmitted, etc. Not do­ing so will desynchronize the serial communication to the
A/D. (See Section 1.3.)

1.2 Changing Configuration

The configuration of the ADC12130/2/8 on power up defaults
to 12-bit plus sign resolution, 12- or 13-bit MSB First, 10
CCLK acquisition time, user mode, no Auto Cal, no Auto
Zero, and power up mode. Changing the acquisition time
and turning the sign bit on and off requires an 8-bit instruc­tion to be issued to the ADC. This instruction will not start a
conversion. The instructions that select a multiplexer ad­dress and format the output data do start a conversion.

ure 8

describes an example of changing the configuration of

the ADC12130/2/8.
During I/O sequence 1, the instruction on DI configures the

ADC12130/2/8 to do a conversion with 12-bit +sign resolu­tion. Notice that when the 6 CCLK Acquisition and Data Out
without Sign instructions are issued to the ADC, I/O se­quences 2 and 3, a new conversion is not started. The data
output during these instructions is from conversion N which
was started during I/O sequence 1. The Configuration Modi­fication timing diagram describes in detail the sequence of
events necessary for a Data Out without Sign, Data Out with
Sign, or 6/10/18/34 CCLK Acquisition time mode selection.

Table 4

the ADC to accomplish this configuration modification. The
next instruction, shown in
conversion N+1 with 16-bit format with 12 bits of resolution
formatted MSB first. Again the data output during this I/O
cycle is the data from conversion N.

The number of SCLKs applied to theA/D during any conver­sion I/O sequence should vary in accord with the data out
word format chosen during the previous conversion I/O se­quence. The various formats and resolutions available are
shown in
first format was chosen during I/O sequence 4, the number
of SCLKs required during I/O sequence 5is 16. In the follow­ing I/O sequence the format changes to 12-bit without sign
MSB first; therefore the number of SCLKs required during
I/O sequence 6 changes accordingly to 12.

describes the actual data necessary to be input to

Table 1

.In

Figure 8

Figure 8

, issued to the A/D starts

, since 16-bit without sign MSB

Fig-

ADC12130/ADC12132/ADC12138

www.national.com27

Application Hints (Continued)

1.3 CS Low Continuously Considerations

When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that the ADC expects. Not do­ing so will desynchronize the serial communications to the
ADC. When the supply power is first applied to the ADC, it
will expect to see 13 SCLK pulses for each I/O transmission.
The number of SCLK pulses that the ADC expects to see is
the same as the digital output word length. The digital output
word length is controlled by the Data Out (DO) format. The
DO format maybe changed any time a conversion is started
or when the sign bit is turned on or off. The table below de­tails out the number of clock periods required for different

ADC12130/ADC12132/ADC12138

DO formats:

DO Format SCLKs

12-Bit MSB or LSB First SIGN OFF 12

SIGN ON 13

16-Bit MSB or LSB first SIGN OFF 16

SIGN ON 17

If erroneous SCLK pulses desynchronize the communica­tions, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.

The number of clock pulses required for an I/O exchange
may be different for the case when CS is left low continu­ously vs the case when CS is cycled. Take the I/O sequence
detailed in
example. The table below lists the number of SCLK pulses
required for each instruction:

Auto Cal 13 SCLKs 8 SCLKs
Read Status 13 SCLKs 8 SCLKs
Read Status 13 SCLKs 8 SCLKs
12-Bit + Sign Conv 1 13 SCLKs 8 SCLKs
12-Bit + Sign Conv 2 13 SCLKs 13 SCLKs

Figure 7

Instruction CS Low CS Strobed

(Typical Power Supply Sequence) as an

Continuously

Number of

Expected

1.4 Analog Input Channel Selection

The data input on DI also selects the channel configuration
for a particular A/D conversion (see

Table 4

). In

Figure 8

figuration could be modified would be during I/O sequences
1, 4, 5 and 6. Input channels are reselected before the start
of each new conversion. Shown below is the data bit stream
required on DI, during I/O sequence number 4 in
set CH1 as the positive input and CH0 as the negative input
for the different versions of ADCs:

Part

Number

ADC12130 LHLLHLXX

and

ADC12132
ADC12138 LHLLLLHL

Where X can be a logic high (H) or low (L).

1.5 Power Up/Down

The ADC may be powered down at any time by taking the
PD pin HIGH or by the instruction input on DI (see
and

Table 5

When the ADC is powered down in this way, the circuitry
necessary for anA/D conversion is deactivated. The circuitry
necessary for digital I/O is kept active. Hardware power up/
down is controlled by the state of the PD pin. Software
power-up/down is controlled by the instruction issued to the
ADC. If a software power up instruction is issued to the ADC
while a hardware power down is in effect (PD pin high) the
device will remain in the power-down state. If a software
power down instruction is issued to the ADC while a hard­ware power up is in effect (PD pin low), the device will power
down. When the device is powered down by software, it may
be powered upby either issuing a softwarepower up instruc­tion or by taking PD pin high and then low. If the power down
command is issued during an A/D conversion, that conver­sion is disrupted. Therefore, the data output after power up
cannot be relied upon.

, and the Power Up/Down timing diagrams).

the only times when the channel con-

DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

Table 2,Table 3

DI Data

Figure 8

Table 4

and

,to

FIGURE 8. Changing the ADC’s Conversion Configuration

1.6 User Mode and Test Mode

An instruction may be issued to the ADC to put it into test
mode. Test mode is used by the manufacturer to verify com­plete functionality of the device. During test mode CH0–CH7
become active outputs. If the device is inadvertently put into

www.national.com 28

DS012079-33

the test mode with CS continuously low, the serial communi­cations may be desynchronized. Synchronization may be re­gained by cycling the power supply voltage to the device.
Cycling the power supply voltage will also set the device into
user mode. If CS is used in the serial interface, the ADCmay

Application Hints (Continued)

be queried to see what mode it is in. This is done by issuing
a “read STATUS register” instruction to the ADC. When bit 9
of the status register is high, the ADC is in test mode; when
bit 9 is low the ADC, is in user mode. As an alternative to cy­cling the powersupply,an instruction sequence may be used
to return the device to user mode. This instruction sequence
must be issuedto the ADC using CS.The following tablelists
the instructions required to return the device to user mode:

Instruction DI Data

DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

TEST MODE H X X X HHHH

Reset

Test Mode

Instructions

USER

MODE

Power Up LLLLHLHL

Set DO with H

or without or L L L H H L H

Sign L

Set H H

Acquisition or or L L H H H L

Time L L
Start HHHH HHH

a ororororLororor

Conversion LLLL LLL

X = Don’t Care

After returning to user mode with the user mode instruction
the power up, data with or without sign, and acquisition time
instructions need to be resent to ensure that the ADC is in
the required state before a conversion is started.

LLLLHHHL
LLLLHLHL
LLLLHLHH
LLLLHHHH

DS012079-34

DS012079-35

FIGURE 9.

CH0, CH2, CH4, and CH6 can be assigned to the MUX­OUT1 pin in the differential configuration, while CH1, CH3,
CH5, and CH7 can be assigned to the MUXOUT2 pin. In the
differential configuration, the analog inputs are paired as fol­lows: CH0 with CH1, CH2 with CH3,CH4 with CH5 and CH6
with CH7. The A/DIN1 and A/DIN2 pins can be assigned
positive or negative polarity.

With the single-ended multiplexer configuration CH0 through
CH7 can be assigned to the MUXOUT1 pin. The COM pin is
always assigned to the MUXOUT2 pin. A/DIN1 is assigned
as the positve input; A/DIN2 is assigned as the negative in­put. (See

Figure 10

).

Differential

Configuration

ADC12130/ADC12132/ADC12138

1.7 Reading the Data Without Starting a Conversion

The data from a particular conversion may be accessed
without starting a new conversion by ensuring that the
CONV line is taken high during the I/O sequence. See the
Read Data timing diagrams.

Table 5

describes the operation

of the CONV pin.

2.0 DESCRIPTION OF THE ANALOG MULTIPLEXER

For theADC12138, the analog input multiplexer can be con­figured with 4 differential channels or 8 single ended chan­nels with the COM input as the zero reference or any combi­nation thereof (see
voltages on the V
voltage span (V

+

V

. Negative digital output codes result when V

A

The actual voltage at V

Figure 9

REF

). The analog input voltage range is 0 to

REF

). The difference between the

+

and V

IN

−

−

pins determines the input

REF

+

or V

cannot go below AGND.

IN

−

IN

>

V

IN

DS012079-36

A/DIN1 and A/DIN2 can be assigned as the + or − input

Single-Ended

Configuration

+

.

DS012079-37

A/DIN1 is + input
A/DIN2 is − input

FIGURE 10.

www.national.com29

Application Hints (Continued)

The Multiplexer assignment tables for the ADC12130/2/8
(

Table 2

tions for the different versions of A/Ds.

2.1 Biasing for Various Multiplexer Configurations

Figure 11

single-ended operation. The sign bit is always low. The digi­tal output range is 0 0000 0000 0000 to 0 1111 1111 1111.
One LSB is equal to 1 mV (4.1V/4096 LSBs).

ADC12130/ADC12132/ADC12138

and

Table 3

) summarize the aforementioned func-

is an example of biasing the device for

FIGURE 11. Single-Ended Biasing

For pseudo-differential signed operation, the biasing circuit
shown in

Figure 12

shows a signal AC coupled to the ADC.

This gives a digital output range of −4096 to +4095. With a

2.5V reference, as shown, 1 LSB is equal to 610 µV. Al­though, the ADC is not production tested with a 2.5V refer­ence, when V

A

+

and V

+

are +5.0V linearity error typically

D

will not change more than 0.1 LSB (see the curves in the
Typical Electrical Characteristics Section). With theADC set

DS012079-38

to an acquisition time of 10 clock periods, the input biasing
resistor needs to be 600Ω or less. Notice though that the in­put coupling capacitor needs to be made fairly large to bring
down the high pass corner.Increasing the acquisition time to
34 clock periods (with a 5 MHz CCLK frequency) would al­low the 600Ω to increase to 6k, which with a 1 µF coupling
capacitor would set the high pass corner at 26 Hz. Increas­ing R, to 6k would allow R

to be 2k.

2

www.national.com 30

Application Hints (Continued)

FIGURE 12. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC

An alternative method for biasing pseudo-differential opera­tion is to use the +2.5V from the LM4040 to bias any ampli­fier circuits drivingtheADC as shown in
of the resistor pull-up biasing the LM4040-2.5 will depend
upon the current required by the op amp biasing circuitry.

In the circuit of

Figure 13

some voltage range is lost since
the amplifier will not be able to swing to +5V and GND with
a single +5V supply. Using an adjustable version of the

Figure 13

. The value

DS012079-39

LM4041 to set the full scale voltage at exactly 2.048V and a
lower grade LM4040D-2.5 to bias up everything to 2.5V as
shown in

Figure 14

will allow the use of all the ADC’s digital
output range of −4096 to +4095 while leaving plenty of head
room for the amplifier.

Fully differential operation is shown in

Figure 15

. One LSB

for this case is equal to (4.1V/4096) = 1 mV.

ADC12130/ADC12132/ADC12138

FIGURE 13. Alternative Pseudo-Differential Biasing

DS012079-40

www.national.com31

Application Hints (Continued)

ADC12130/ADC12132/ADC12138

FIGURE 14. Pseudo-Differential Biasing without the Loss of Digital Output Range

DS012079-41

FIGURE 15. Fully Differential Biasing

3.0 REFERENCE VOLTAGE

The difference in the voltages applied to the V

−

V

defines the analog input span (the difference between

REF

REF

+

and

the voltage applied between two multiplexer inputs or the
voltage applied to one of the multiplexer inputs and analog
ground), over which 4095 positive and 4096 negative codes
exist. The voltage sources drivingV

www.national.com 32

REF

+

or V

REF

−

must have

DS012079-42

very low output impedance and noise. The circuit in

16

is an example of a very stable reference appropriate for

use with the device.

Figure

Application Hints (Continued)

DS012079-43

*

Tantalum

FIGURE 16. Low Drift Extremely

Stable Reference Circuit

TheADC12130/2/8 can be used in eitherratiometric or abso­lute reference applications. In ratiometric systems, the ana­log input voltage is proportional to the voltage used for the
ADC’s reference voltage. When this voltage is the system
power supply, the V
is connected to ground. This technique relaxes the system
reference stability requirements because the analog input
voltage and the ADC reference voltage move together. This
maintains the same output code for given input conditions.
For absolute accuracy, where theanalog input voltage varies
between very specific voltage limits, a time and temperature
stable voltage source can be connected to the reference in­puts. Typically, the referencevoltage’s magnitude willrequire
an initial adjustment to null reference voltage induced
full-scale errors.

Below are recommended references along with some key
specifications.

Part Number Voltage Coefficient

LM4041CI-Adj
LM4040AI-4.1
Circuit of

Figure 16

The reference voltage inputs are not fully differential. The
ADC12130/2/8 will not generate correct conversions or com­parisons if V
result when V
times, between ground and V
range, (V

+

V

). Therefore, with V

A

REF

REF

+

REF

+V

ladder should not go below 0.5V or above 3.0V.
a graphic representation of the voltage restrictions on V
and V

REF

−

.

+

pin is connected to V

REF

Output Temperature

Tolerance

±
±

Adjustable

+

is taken below V

+

and V

REF

−

differ by 1V and remain, at all

REF

+

. The V

−

A

)/2 is restricted to (0.1 x V

+

= 5V the center of the reference

A

A

0.5%

0.1%

REF

±
±

−

. Correct conversions

common mode

REF

+

and V

REF

100ppm/˚C
100ppm/˚C

±

2ppm/˚C

+

) to (0.6 x

A

Figure 17

REF

ADC12130/ADC12132/ADC12138

−

FIGURE 17. V

Operating Range

REF

4.0 ANALOG INPUT VOLTAGE RANGE

The ADC12130/2/8’s fully differential ADC generate a two’s
complement output that is found by using the equation
shown below:

for (12-bit) resolution the Output Code =

Round off to the nearest integer value between −4096 to
4095 if the result of the above equation is not a whole num­ber.

Examples are shown in the table below:

+

V

REF

+2.5V +1V +1.5V 0V 0,1111,1111,1111
+4.096V 0V +3V 0V 0,1011,1011,1000
+4.096V 0V +2.499V +2.500V 1,1111,1111,1111
+4.096V 0V 0V +4.096V 1,0000,0000,0000

−

V

REF

+

V

IN

−

V

IN

5.0 INPUT CURRENT

is

+

At the start of the acquisition window (t
flows into or out of the analog input pins (A/DIN1 and

) a charging current

A

A/DIN2) depending on the input voltage polarity. The analog
input pins are CH0–CH7 and COM when A/DIN1 is tied to
MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value
of this input current will depend on the actual input voltage
applied, the source impedance and the internal multiplexer
switch on resistance. With MUXOUT1 tied to A/DIN1 and
MUXOUT2 tied to A/DIN2 the internal multiplexer switch on
resistance is typically 1.6 kΩ. The A/DIN1 and A/DIN2 mux
on resistance is typically 750Ω.

DS012079-44

Digital

Output

Code

6.0 INPUT SOURCE RESISTANCE

For low impedance voltage sources (

<

600Ω), the input
charging current will decay, before the end of the S/H’s ac­quisition time of 2 µs (10 CCLK periods with f

= 5 MHz), to

CK

a value thatwill not introduceany conversion errors.For high
source impedances, the S/H’s acquisition time can be in-

www.national.com33

Application Hints (Continued)

creased to 18 or 34 CCLK periods. For less ADC accuracy
and/or slower CCLK frequencies the S/H’s acquisition time
may be decreased to 6 CCLK periods. To determine the
number of clock periods (N
with a specific source impedance for the various resolutions
the following equations can be used:

12 Bit + Sign

N

C

Where fCKis the conversion clock (CCLK) frequency in MHz
and R

is the external source resistance in kΩ.Asanex-

S

ample, operating with a resolution of 12 Bits+sign, a 5 MHz
clock frequency and maximum acquistion time of 34 conver­sion clock periods the ADC’s analog inputs can handle a

ADC12130/ADC12132/ADC12138

source impedance ashigh as 6kΩ. The acquisitiontime may
also be extended to compensate for the settling or response
time of external circuitry connected between the MUXOUT
and A/DIN pins.

The acquisition time t
and ended by a rising edge of CCLK (see timing diagrams).
If SCLK and CCLK are asynchronous one extra CCLK clock
period may be inserted intothe programmed acquisition time
for synchronization. Therefore with asnychronous SCLK and
CCLKs the acquisition time will change from conversion to
conversion.

7.0 INPUT BYPASS CAPACITANCE

External capacitors (0.01 µF–0.1 µF) can be connected be­tween the analog input pins, CH0–CH7, and analog ground
to filter any noise caused by inductive pickupassociated with
long input leads. These capacitors will not degrade the con­version accuracy.

) required for the acquisition time

c

=[

R

+ 2.3] x

S

is started by a falling edge of SCLK

A

fCKx 0.824

9.0 POWER SUPPLIES

Noise spikes on the V

+

A

and V

+

supply lines can cause

D

conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. The
minimum power supply bypassing capacitors recommended
are low inductance tantalum capacitors of 10 µF or greater
paralleled with 0.1µF monolithic ceramic capacitors. More or
different bypassing may be necessary depending on the
overall system requirements. Separate bypass capacitors
should be used for the V

A

+

and V

+

supplies and placed as

D

close as possible to these pins.

10.0 GROUNDING

The ADC12130/2/8’s performance can be maximized
through proper grounding techniques. These include the use
of separate analog and digital ground planes. The digital
ground plane is placed under all components that handle
digital signals, whilethe analog groundplane is placedunder
all components that handle analog signals. The digital and
analog ground planes are connected together at only one
point, either the power supply ground or at the pins of the
ADC. This greatly reduces the occurence of ground loops
and noise.

Shown in

Figure 18

is the ideal ground plane layout for the
ADC12138 along with ideal placement of the bypass capaci­tors. The circuit board layout shown in

Figure 18

uses three
bypass capacitors: 0.01 µF (C1) and 0.1 µF (C2) surface
mount capacitors and 10 µF (C3) tantalum capacitor.

8.0 NOISE

The leads to each ofthe analog multiplexer input pinsshould
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion er­rors. Input filtering can be used to reduce the effects of the
noise sources.

FIGURE 18. Ideal Ground Plane

www.national.com 34

DS012079-45

Application Hints (Continued)

11.0 CLOCK SIGNAL LINE ISOLATION

The ADC12130/2/8’s performance is optimized by routing
the analog input/output and reference signal conductors as
far as possible from the conductors that carry the clock sig­nals to the CCLK and SCLK pins. Ground traces parallel to
the clock signal traces can be used on printed circuit boards
to reduce clock signal interference on the analog input/
output pins.

12.0 THE CALIBRATION CYCLE

A calibration cycle needs to be started after the power sup­plies, reference, and clock have been given enough time to
stabilize after initial turn-on. During the calibration cycle, cor­rection values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full-scale,
offset, and linearity errors down to the specified limits.
Full-scale error typically changes
ture and linearity error changes even less; thereforeit should
be necessary to go through the calibration cycle only once
after power up if the Power Supply Voltage and the ambient
temperature do not change significantly (see the curves in
the Typical Performance Characteristics).

13.0 THE AUTO-ZERO CYCLE

To correct for any change in the zero (offset) error of the A/D,
the auto-zero cycle can be used. It may be necessary to do
an auto-zero cycle whenever the ambient temperature or the
power supply voltage change significantly. (See the curves
titled “Zero Error Change vs Ambient Temperature” and
“Zero Error Change vs Supply Voltage”in the Typical Perfor­mance Characteristics.)

14.0 DYNAMIC PERFORMANCE

Many applications require the A/D converter to digitize AC
signals, but the standard DC integral and differential nonlin­earity specifications will not accurately predict the A/D con­verter’s performance with AC input signals. The important
specifications forAC applications reflect the converter’s abil­ity to digitize AC signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic

±

0.4 LSB over tempera-

ADC12130/ADC12132/ADC12138

characteristics such as signal-to-noise (S/N), signal-to-noise
+ distortion ratio (S/(N + D)), effective bits, full power band­width, aperture time and aperture jitter are quantitative mea­sures of the A/D converter’s capability.

An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal wave­form is applied to the A/D converter’s input, and the trans­form is then performed on the digitized waveform. S/(N + D)
and S/N are calculated from the resulting FFT data, and a
spectral plot may also be obtained. Typical values for S/N
are shown in the table of Electrical Characteristics, and
spectral plots of S/(N + D) are included in the typical perfor­mance curves.

The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurringat higher signal frequencies. This canbe
seen in theS/(N + D) versus frequency curves. Thesecurves
will also give an indication of the full power bandwidth (the
frequency at which the S/(N + D) or S/N drops 3 dB).

Effective number of bits can also be useful in describing the
A/D’s noise performance. An ideal A/D converter will have
some amount of quantization noise, determined by its reso­lution, which will yield an optimum S/N ratio given by the fol­lowing equation:

S/N = (6.02xn+1.76) dB
where n is the A/D’s resolution in bits.
The effective bits of a real A/D converter, therefore, can be

found by:

As an example, this device with a differential signed 5V,
10 kHz sine wave input signal will typically have a S/N of
78 dB, which is equivalent to 12.6 effective bits.

15.0 AN RS232 SERIAL INTERFACE

Shown on the following page is a schematic for an RS232 in­terface to any IBM and compatible PCs. The DTR, RTS, and
CTS RS232 signal lines are buffered via level translators
and connected to the ADC12138’s DI, SCLK, and DO pins,
respectively. The D flip/flop is used to generate the CS
signal.

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Application Hints (Continued)

ADC12130/ADC12132/ADC12138

DS012079-46

Note: V
caps.

+

+

,V

, and V

A

D

+

on the ADC12138 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF

REF

The assignment of the RS232 port is shown below

B7 B6 B5 B4 B3 B2 B1 B0

COM1 Input Address 3FE X X X CTS X X X X

Output Address 3FC X X X 0 X X RTS DTR

Asample program, written in Microsoft QuickBasic, is shown
on the next page. The program prompts for data mode select
instruction to be sent to the A/D. This can be found from the
Mode Programming table shown earlier. The data should be
entered in “1”s and “0”s as shown in the table with DI0 first.
Next the program prompts for the numberof SCLKs required
for the programmed mode select instruction. For instance, to
send all “0”s to the A/D, selects CH0 as the +input, CH1 as
the −input, 12-bit conversion, and 13-bit MSB first data out­put format (if the sign bit was not turned off by a previous in­struction). This would require 13 SCLKperiods since theout­put data format is 13 bits. The part powers up with No Auto

sion, data out with sign, power up, 12- or 13-bit MSB First,
and user mode. Auto Cal, Auto Zero, Power Up and Power
Down instructions do not change these default settings.
Since there is no CS signal to synchronize the serial inter­face the following power up sequence should be followed:

1. Run the program

2. Prior to responding to the prompt apply the power to the
ADC12138

3. Respond to the program prompts

It is recommended that the first instruction issued to the
ADC12138 be Auto Cal (see Section 1.1).

Cal, No Auto Zero, 10 CCLK Acquisition Time,12-bit conver-

Code Listing:

’variables DOL=Data Out word length, DI=Data string for A/D DI input,
’ DO=A/D result string
’SET CS# HIGH
OUT <&>H3FC, (<&>H2 OR INP (<&>H3FC) ’set RTS
HIGH
OUT <&>H3FC, (<&>HFE AND INP(<&>H3FC) ’SET DTR LOW
OUT <&>H3FC, (<&>HFD AND INP (<&>H3FC) ’SET RTS LOW
OUT <&>H3FC, (<&>HEF AND INP(<&>H3FC)) ’set B4 low
10
LINE INPUT <&ldquo>DI data for ADC12138 (see Mode Table on data sheet)<&rdquo>; DI$
INPUT <&ldquo>ADC12138 output word length (12,13,16 or 17)<&rdquo>; DOL
20
’SET CS# HIGH
OUT <&>H3FC, (<&>H2 OR INP (<&>H3FC) ’set RTS
HIGH
OUT <&>H3FC, (<&>HFE AND INP(<&>H3FC) ’SET DTR LOW
OUT <&>H3FC, (<&>HFD AND INP (<&>H3FC) ’SET RTS LOW

www.national.com 36

Application Hints (Continued)

’SET CS# LOW
OUT <&>H3FC, (<&>H2 OR INP (<&>H3FC) ’set RTS
HIGH
OUT <&>H3FC, (<&>H1 OR INP(<&>H3FC) ’SET DTR
HIGH
OUT <&>H3FC, (<&>HFD AND INP (<&>H3FC) ’SET RTS LOW
DO$=<&ldquo> <&rdquo> ’reset DO
variable

OUT <&>H3FC, (<&>H1 OR INP(<&>H3FC) ’SET DTR

HIGH

OUT <&>H3FC, (<&>HFD AND INP(<&>H3FC)) ’SCLK low

FOR N = 1 TO 8

Temp$ = MID$(DI$, N, 1)
IF Temp$=<&ldquo>0<&rdquo> THEN

OUT <&>H3FC, (<&>H1 OR INP(<&>H3FC))
ELSE OUT <&>H3FC, (<&>HFE AND INP(<&>H3FC))
END IF ’out DI
OUT <&>H3FC, (<&>H2 OR INP(<&>H3FC)) ’SCLK high
IF (INP(<&>H3FE) AND 16) = 16 THEN

DO$ = DO$ + <&ldquo>0<&rdquo>

ELSE

DO$ = DO$ + <&ldquo>1<&rdquo>
END IF ’Input DO
OUT <&>H3FC, (<&>H1 OR INP(<&>H3FC) ’SET DTR

HIGH

OUT <&>H3FC, (<&>HFD AND INP(<&>H3FC)) ’SCLK low

NEXT N
IF DOL > 8 THEN

FOR N=9 TO DOL
OUT <&>H3FC, (<&>H1 OR INP(<&>H3FC) ’SET DTR

HIGH

OUT <&>H3FC, (<&>HFD AND INP(<&>H3FC)) ’SCLK low
OUT <&>H3FC, (<&>H2 OR INP(<&>H3FC)) ’SCLK high
IF (INP(<&>H3FE) AND <&>H1O) = <&>H1O THEN

DO$ = DO$ + <&ldquo>0<&rdquo>
ELSE

DO$ = DO$ + <&ldquo>1<&rdquo>
END IF
NEXT N

END IF
OUT <&>H3FC, (<&>HFA AND INP(<&>H3FC)) ’SCLK low
and DI high
FOR N = 1 TO 500
NEXT N
PRINT DO$
INPUT <&ldquo>Enter <&ldquo>C<&rdquo> to convert else <&ldquo>RETURN<&rdquo> to alter DI
data<&rdquo>; s$
IF s$ = <&ldquo>C<&rdquo> OR s$ = <&ldquo>c<&rdquo> THEN
GOTO 20
ELSE
GOTO 10
END IF
END

ADC12130/ADC12132/ADC12138

www.national.com37

Physical Dimensions inches (millimeters) unless otherwise noted

ADC12130/ADC12132/ADC12138

Order Number ADC12130CIWM

NS Package Number M16B

Order Number ADC12138CIWM

NS Package Number M28B

www.national.com 38

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

ADC12130/ADC12132/ADC12138

Order Number ADC12132CIMSA

NS Package Number MSA20

Order Number ADC12138CIMSA

NS Package Number MSA28

www.national.com39

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

ADC12130/ADC12132/ADC12138

Order Number ADC12130CIN

NS Package Number N16E

Order Number ADC12138CIN

NS Package Number N28B

www.national.com 40

Notes

ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with

MUX and Sample/Hold

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accordance with instructions for use provided in the

2. A critical component is any component of a life
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can be reasonably expected to cause the failure of
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labeling, can be reasonably expected to result in a
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