Page 1
ADC12062
12-Bit, 1 MHz, 75 mW A/D Converter
with Input Multiplexer and Sample/Hold
December 1994
ADC12062 12-Bit, 1 MHz, 75 mW A/D Converter
with Input Multiplexer and Sample/Hold
General Description
Using an innovative multistep conversion technique, the
12-bit ADC12062 CMOS analog-to-digital converter digitizes
signals at a 1 MHz sampling rate while consuming a maximum of only 75 mW on a single
a
5V supply. The
ADC12062 performs a 12-bit conversion in three lower-resolution ‘‘flash’’ conversions, yielding a fast A/D without the
cost and power dissipation associated with true flash approaches.
The analog input voltage to the ADC12062 is tracked and
held by an internal sampling circuit, allowing high frequency
input signals to be accurately digitized without the need for
an external sample-and-hold circuit. The multiplexer output
is available to the user in order to perform additional external signal processing before the signal is digitized.
When the converter is not digitizing signals, it can be placed
in the Standby mode; typical power consumption in this
mode is 100 mW.
Block Diagram
Features
Y
Built-in sample-and-hold
Y
Singlea5V supply
Y
Single channel or 2 channel multiplexer operation
Y
Low Power Standby mode
Key Specifications
Y
Sampling rate 1 MHz (min)
Y
Conversion time 740 ns (typ)
Y
Signal-to-Noise Ratio, f
Y
Power dissipation (f
Y
No missing codes over temperature Guaranteed
e
100 kHz 69.5 dB (min)
IN
e
1 MHz) 75 mW (max)
s
Applications
Y
Digital signal processor front ends
Y
Instrumentation
Y
Disk drives
Y
Mobile telecommunications
Y
Waveform digitizers
TL/H/11490– 1
Ordering Information
s
Industrial (b40§CsT
ADC12062BIV V44 Plastic Leaded Chip Carrier
ADC12062BIVF VGZ44A Plastic Quad Flat Package
ADC12062CIV V44 Plastic Leaded Chip Carrier
ADC12062CIVF VGZ44A Plastic Quad Flat Package
ADC12062EVAL Evaluation Board
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
TL/H/11490
a
85§) Package
A
Page 2
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
DV
CC
Voltage at Any Input or Output
e
AVCC)
b
0.3V to V
b
0.3V toa6V
a
CC
0.3V
e
Input Current at Any Pin (Note 3) 25 mA
Package Input Current (Note 3) 50 mA
Power Dissipation (Note 4) 875 mW
ESD Susceptibility (Note 5) 2000V
Converter Characteristics The following specifications apply for DV
a
4.096V, V
T
MIN
to T
MAX
REFb(SENSE)
; all other limits T
e
AGND, and f
A
e
1 MHz, unless otherwise specified. Boldface limits apply for T
s
e
ea
T
25§C.
J
Symbol Parameter Conditions
Resolution 12 Bits
Differential Linearity Error T
Integral Linearity Error T
(Note 9)
Offset Error T
Full Scale Error T
Power Supply Sensitivity DV
(Note 15)
R
REF
V
REF(a)VREFa(SENSE)
V
REF(b)VREFb(SENSE)
V
IN
Reference Resistance
Input Voltage Range To V
Input Voltage AV
Input Voltage AGND V (min)
A
T
MIN
MIN
T
A
T
MIN
MIN
T
A
T
MIN
MIN
T
A
T
MIN
e
ea
ea
ea
CC
IN1,VIN2
25§C
to T
MAX
to T
MAX
25§C (CIV Suffix)
to T
MAX
to T
MAX
25§C (CIV Suffix)
to T
MAX
to T
MAX
25§C (CIV Suffix)
to T
MAX
e
AV
ADC IN Input Leakage AGND to AV
C
ADC
ADC IN Input Capacitance 25 pF
MUX On-Channel Leakage AGND to AV
MUX Off-Channel Leakage AGND to AV
C
MUX
Multiplexer Input Cap 7 pF
MUX Off Isolation f
e
100 kHz 92 dB
IN
Soldering Information (Note 6)
V Package, Infrared, 15 seconds
VF Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
Storage Temperature Range
Maximum Junction Temperature (T
Operating Ratings (Notes 1, 2)
Temperature Range T
ADC12062BIV, ADC12062CIV,
ADC12062BIVF, ADC12062CIVF
Supply Voltage Range (DV
(Note 7) (Note 8) (Limit)
g
(BIV Suffix)
(CIV Suffix)
(BIV Suffix)
(CIV Suffix)
(BIV Suffix)
(CIV Suffix)
e
5Vg10%
CC
, or ADC IN AV
b
0.3V 0.1 3 mA (max)
CC
b
0.3V 0.1 3 mA (max)
CC
b
0.3V 0.1 3 mA (max)
CC
g
g
g
g
g
g
a
300§C
a
215§C
a
s
A
T
A
s
A
e
TJfrom
s
a
220§C
T
85§C
CC
b
65§Ctoa150§C
) 150§C
JMAX
MIN
b
40§CsT
e
AVCC) 4.5V to 5.5V
CC
e
ea
AV
CC
5V, V
REFa(SENSE)
Typ Limit Units
0.4
0.4
0.4
0.3
0.3
0.2
0.2
750
g
0.8 LSB (max)
g
0.95 LSB (max)
g
1.0 LSB (max)
g
1.0 LSB (max)
g
1.5 LSB (max)
g
1.25 LSB (max)
g
1.25 LSB (max)
g
2.0 LSB (max)
g
1.0 LSB (max)
g
1.0 LSB (max)
g
1.5 LSB (max)
g
1.0 LSB (max)
500 X (min)
1000 X (max)
CC
a
0.05V V (max)
CC
b
AGND
0.05V V (min)
V (max)
MAX
e
2
Page 3
Dynamic Characteristics (Note 10) The following specifications apply for DV
V
REFa(SENSE)
otherwise specified. Boldface limits apply for T
Symbol Parameter Conditions
SINAD Signal-to-Noise Plus T
SNR Signal-to-Noise Ratio T
THD Total Harmonic Distortion T
ENOB Effective Number of Bits T
IMD Intermodulation Distortion f
ea
4.096V, V
REFb(SENSE)
e
Distortion Ratio
(Note 11)
(Note 12) T
(Note 13)
AGND, R
S
e
TJfrom T
A
to T
MIN
to T
MIN
ea
25§C
A
to T
MIN
to T
MIN
e
102.3 kHz, 102.7 kHz
IN
e
MAX
MAX
MAX
MAX
25X,f
e
100 kHz, 0 dB from fullscale, and f
IN
to T
MIN
; all other limits T
MAX
Typ Limit Units
(Note 7) (Note 8) (Limit)
71 68.0 dB (min)
72 69.5 dB (min)
b
82
11.5 11.0 Bits (min)
b
80 dBc
e
CC
e
T
A
J
b
74 dBc (max)
b
70 dBc (max)
AV
CC
e
1 MHz, unless
s
ea
25§C.
ea
5V,
DC Electrical Characteristics The following specifications apply for DV
V
REFa(SENSE)
for T
A
Symbol Parameter Conditions
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
V
OUT(0)
I
OUT
C
OUT
C
IN
DI
CC
AI
CC
I
STANDBY
e
TJfrom T
ea
4.096V, V
to T
MIN
REFb(SENSE)
MAX
e
AGND, and f
; all other limits T
e
1 MHz, unless otherwise specified. Boldface limits apply
s
e
ea
T
A
25§C.
J
Typ Limit Units
(Note 7) (Note 8) (Limit)
e
Logical ‘‘1’’ Input Voltage DV
Logical ‘‘0’’ Input Voltage DV
CC
CC
ea
AV
e
AV
5.5V 2.0 V (min)
CC
ea
4.5V 0.8 V (max)
CC
Logical ‘‘1’’ Input Current 0.1 1.0 mA (max)
Logical ‘‘0’’ Input Current 0.1 1.0 mA (max)
e
Logical ‘‘1’’ Output Voltage DV
Logical ‘‘0’’ Output Voltage DV
I
I
I
OUT
OUT
OUT
CC
CC
eb
eb
e
TRI-STATEÉOutput Pins DB0 – DB11
Leakage Current
ea
AV
360 mA 2.4 V (min)
CC
4.5V,
100 mA 4.25 V (min)
e
ea
AV
1.6 mA
CC
4.5V,
0.1 3 mA (max)
TRI-STATE Output Capacitance Pins DB0–DB11 5 pF
Digital Input Capacitance 4 pF
DVCCSupply Current 2 3 mA (max)
AVCCSupply Current 10 12 mA (max)
Standby Current (DI
a
AICC)PD
CC
e
0V 20 mA
e
AV
CC
CC
0.4 V (max)
ea
5V,
3
Page 4
AC Electrical Characteristics The following specifications apply for DV
V
REFa(SENSE)
for T
A
Symbol Parameter Conditions
f
s
t
CONV
t
AD
t
S/H
t
EOC
t
ACC
t1H,t
0H
t
INTH
t
INTL
t
UPDATE
t
MS
t
MH
t
CSS
t
CSH
t
WU
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions.
Note 2: All voltages are measured with respect to GND (GND
Note 3: When the input voltage (V
limited to 25 mA or less. The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
(PLCC) package is 55
conditions.
e
TJfrom T
ea
4.096V, V
to T
MIN
REFb(SENSE)
MAX
e
AGND, and f
; all other limits T
e
1 MHz, unless otherwise specified. Boldface limits apply
s
e
ea
T
A
25§C.
J
Typ Limit Units
(Note 7) (Note 8) (Limits)
Maximum Sampling Rate
(1/t
THROUGHPUT
)
Conversion Time 740 600 ns (min)
(S/H
Low to EOC High) 980 ns (max)
Aperture Delay
(S/H
Low to Input Voltage Held)
20 ns
S/H Pulse Width 5 ns (min)
S/H Low to EOC Low
Access Time C
(RD
Low or OE High to Data Valid)
TRI-STATE Control
High or OE Low to Databus TRI-STATE)
(RD
Delay from RD Low to INT High C
Delay from EOC High to INT Low C
e
100 pF
L
e
R
L
e
L
e
L
e
1k, C
10 pF 25 40 ns (max)
L
100 pF 35 60 ns (max)
100 pF
95
10 20 ns (max)
b
25
EOC High to New Data Valid 5 15 ns (max)
Multiplexer Address Setup Time
(MUX Address Valid to EOC Low)
Multiplexer Address Hold Time
(EOC Low to MUX Address Invalid)
CS Setup Time
(CS Low to RD Low, S/H Low, or OE High)
CS Hold Time
(CS
High after RD High, S/H High, or OE Low)
Wake-Up Time
(PD
High to First S/H Low)
e
) at any pin exceeds the power supply rails (V
IN
e
C/W. iJAfor the VF (PQFP) package is 62§C/W. In most cases the maximum derated power dissipation will be reached only during fault
§
D
AGNDeDGND), unless otherwise specified.
b
(T
TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. iJAfor the V
JMAX
IN
k
GND or V
l
VCC) the absolute value of current at that pin should be
IN
JMAX
1 ms
, iJAand the ambient temperature TA. The maximum
e
CC
1 MHz (min)
550 ns (max)
60 ns (min)
125 ns (max)
b
b
50 ns (min)
50 ns (min)
20 ns (min)
20 ns (min)
ea
AV
CC
35 ns (min)
10 ns (max)
5V,
4
Page 5
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor. Machine model ESD rating is 200V.
Note 6: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at
Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Integral Linearity Error is the maximum deviation from a straight line between the
Note 10: Dynamic testing of the ADC12062 is done using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies. See the graph in the
Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer.
Note 11: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in its calculation.
Note 12: The contributions from the first nine harmonics are used in the calculation of the THD.
Note 13: Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB
1.76)/6.02.
Note 14: The digital power supply current takes up to 10 seconds to decay to its final value after PD is pulled low. This prohibits production testing of the standby
current. Some parts may exhibit significantly higher standby currents than the 20 mA typical.
Note 15: Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage.
a
25§C and represent most likely parametric norm.
measured
offset and full scale endpoints.
e
(SINAD
TRI-STATE Test Circuit and Waveforms
TL/H/11490– 2
TL/H/11490– 3
b
TL/H/11490– 4
TL/H/11490– 5
5
Page 6
Typical Performance Characteristics
Offset and Fullscale
Error Change vs
Reference Voltage
Linearity Error Change
vs Reference Voltage
Mux ON Resistance vs
Input Voltage
Digital Supply Current
vs Temperature
Conversion Time (t
vs Temperature
SINAD vs Input Frequency
(ADC IN)
CONV
Analog Supply Current
vs Temperature
)
EOC Delay Time (t
vs Temperature
SNR vs Input Frequency
(ADC IN)
EOC
)
Current Consumption in
Standby Mode vs Voltage
on Digital Input Pins
Spectral Response
THD vs Input Frequency
(ADC IN)
TL/H/11490– 27
6
Page 7
Typical Performance Characteristics (Continued)
SINAD vs Input Frequency
(Through Mux)
Timing Diagrams
SNR vs Input Frequency
(Through Mux)
SNR and THD vs Source
Impedance
THD vs Input Frequency
(Through Mux)
SNR and THD vs
Reference Voltage
TL/H/11490– 28
FIGURE 1. Interrupt Interface Timing (MODEe1, OEe1)
7
TL/H/11490– 9
Page 8
Timing Diagrams (Continued)
FIGURE 2. High Speed Interface Timing (MODEe1, OEe1, CSe0, RDe0)
FIGURE 3. CS Setup and Hold Timing for S/H,RD, and OE
Connection Diagrams
TL/H/11490– 10
TL/H/11490– 11
Top View
TL/H/11490– 13
Top View
TL/H/11490– 29
8
Page 9
Pin Descriptions
AV
CC
DV
CC
AGND, These are the power supply ground pins.
DGND1, There are separate analog and digital
DGND2 ground pins for separate bypassing of the
DB0–DB11 These are the TRI-STATE output pins, en-
V
IN1,VIN2
MUX OUT This is the output of the on-board analog
ADC IN This is the direct input to the 12-bit sam-
S0 This pin selects the analog input that will
These are the two positive analog supply
inputs. They should always be connected
to the same voltage source, but are
brought out separately to allow for separate bypass capacitors. Each supply pin
should be bypassed to AGND with a
0.1 mF ceramic capacitor in parallel with a
10 mF tantalum capacitor.
This is the positive digital supply input. It
should always be connected to the same
voltage as the analog supply, AV
should be bypassed to DGND2 with a
CC
.It
0.1 mF ceramic capacitor in parallel with a
10 mF tantalum capacitor.
analog and digital supplies. The ground
pins should be connected to a stable,
noise-free system ground. All of the
ground pins should be returned to the
same potential. AGND is the analog
ground for the converter. DGND1 is the
ground pin for the digital control lines.
DGND2 is the ground return for the output
databus. See Section 6.0 LAYOUT AND
GROUNDING for more information.
abled by RD
,CS, and OE.
These are the analog input pins to the multiplexer. For accurate conversions, no input pin (even one that is not selected)
should be driven more than 50 mV below
ground or 50 mV above V
CC
.
input multiplexer.
pling A/D converter. For accurate conversions, this pin should not be driven more
than 50 mV below AGND or 50 mV above
AV
.
CC
be connected to the ADC12062 during the
conversion. The input is selected based on
the state of S0 when EOC makes its highto-low transition. Low selects V
selects V
IN2
.
IN1
, high
MODE This pin should be tied to DV
CC
.
CS This is the active low Chip Select control
input. When low, this pin enables the RD
S/H
, and OE inputs. This pin can be tied
low.
INT
This is the active low Interrupt output.
When using the Interrupt Interface Mode
(Figure 1),
this output goes low when a
conversion has been completed and indicates that the conversion result is available in the output latches. This output is
always high when RD
is held low
(Figure
2).
EOC This is the End-of-Conversion control out-
put. This output is low during a conversion.
RD
This is the active low Read control input.
When RD
is low (and CS is low), the INT
output is reset and (if OE is high) data appears on the data bus. This pin can be tied
low.
OE This is the active high Output Enable con-
trol input. This pin can be thought of as an
inverted version of the RD
ure 6
). Data output pins DB0 –DB11 are
input (see
Fig-
TRI-STATE when OE is low. Data appears
on DB0 –DB11 only when OE is high and
CS
and RD are both low. This pin can be
tied high.
S/H
This is the Sample/Hold control input. The
analog input signal is held and a new conversion is initiated by the falling edge of
this control input (when CS
is low).
PD This is the Power Down control input. This
pin should be held high for normal operation. When this pin is pulled low, the device
goes into a low power standby mode.
V
REFa(FORCE)
V
REFb(FORCE)
, These are the positive and negative volt-
age reference force inputs, respectively.
See Section 4, REFERENCE INPUTS, for
more information.
V
REFa(SENSE)
V
REFb(SENSE)
, These are the positive and negative volt-
age reference sense pins, respectively.
See Section 4, REFERENCE INPUTS, for
more information.
V
/16 This pin should be bypassed to AGND with
REF
TEST This pin should be tied to DV
a 0.1 mF ceramic capacitor.
CC
.
,
9
Page 10
Functional Description
The ADC12062 performs a 12-bit analog-to-digital conversion using a 3 step flash technique. The first flash determines the six most significant bits, the second flash generates four more bits, and the final flash resolves the two least
significant bits.
of the converter. It consists of a 2(/2-bit Voltage Estimator, a
resistor ladder with two different resolution voltage spans, a
sample/hold capacitor, a 4-bit flash converter with front end
multiplexer, a digitally corrected DAC, and a capacitive voltage divider.
The resistor string near the center of the block diagram in
Figure 4
for the first two conversions. Each of the 16 resistors at the
bottom of the string is equal to (/1024 of the total string resistance. These resistors form the LSB Ladder* and have a
voltage drop of (/1024 of the total reference voltage (V
b
V
REF
form the MSB Ladder. It is comprised of eight groups of
eight resistors each connected in series (the lowest MSB
ladder resistor is actually the entire LSB ladder). Each MSB
Ladder section has (/8 of the total reference voltage across
it. Within a given MSB ladder section, each of the eight MSB
resistors has (/64 of the total reference voltage across it. Tap
points are found between all of the resistors in both the
MSB and LSB ladders. The Comparator MultipIexer can
connect any of these tap points, in two adjacent groups of
eight, to the sixteen comparators shown at the right of
Figure 4.
voltages to the comparators during the first two flash conversions.
The six comparators, seven-resistor string (Estimator DAC
ladder), and Estimator Decoder at the left of
*Note: The weight of each resistor on the LSB ladder is actually equivalent
Figure 4
shows the major functional blocks
generates the 6-bit and 10-bit reference voltages
) across each of them. The remaining resistors
b
REF
This function provides the necessary reference
Figure 4
form
to four 12-bit LSBs. It is called the LSB ladder because it has the
highest resolution of all the ladders in the converter.
the Voltage Estimator. The Estimator DAC, connected between V
ages for the six Voltage Estimator comparators. The com-
REF
a
and V
, generates the reference volt-
b
REF
parators perform a very low resoIution A/D conversion to
obtain an ‘‘estimate’’ of the input voltage. This estimate is
used to control the placement of the Comparator Multiplexer, connecting the appropriate MSB ladder section to the
sixteen flash comparators. A total of only 22 comparators (6
in the Voltage Estimator and 16 in the flash converter) is
required to quantize the input to 6 bits, instead of the 64 that
would be required using a traditional 6-bit flash.
Prior to a conversion, the Sample/Hold switch is closed,
allowing the voltage on the S/H capacitor to track the input
voItage. Switch 1 is in position 1. A conversion begins by
opening the Sample/Hold switch and latching the output of
the Voltage Estimator. The estimator decoder then selects
a
two adjacent banks of tap points aIong the MSB ladder.
These sixteen tap points are then connected to the sixteen
flash converters. For exampIe, if the input voltage is between ±/16 and -/16 of V
estimator decoder instructs the comparator multiplexer to
REF(VREF
e
V
select the sixteen tap points between )/8 and %/8 (%/16 and
`/16)ofV
The first flash conversion is now performed, producing the
and connects them to the sixteen comparators.
REF
first 6 MSBs of data.
At this point, Voltage Estimator errors as large as (/16 of
V
will be corrected since the comparators are connect-
REF
ed to ladder voltages that extend beyond the range specified by the Voltage Estimator. For example, if (-/16)V
k
k
V
('/16)V
IN
tied to the tap points below ('/16)V
, the Voltage Estimator’s comparators
REF
(000111). This is decoded by the estimator decoder to ‘‘10’’.
The 16 comparators will be placed on the MSB ladder
b
a
REF
will output ‘‘1’’s
REF
V
), the
b
REF
REF
FIGURE 4. Functional Block Diagram
10
TL/H/11490– 14
Page 11
Functional Description (Continued)
tap points between (*/8)V
((/16)V
ror of up to 256 LSBs. If the first flash conversion determines that the input voltage is between (*/8)V
((%/8)V
will be corrected by subtracting ‘‘1’’, resulting in a corrected
will automatically cancel a Voltage Estimator er-
REF
b
LSB/2), the Voltage Estimator’s output code
REF
REF
and (±/8)V
value of ‘‘01’’ for the first two MSBs. If the first flash conversion determines that the input voltage is between (%/8)V
b
LSB/2) and (±/8)V
code is unchanged.
, the voltage estimator’s output
REF
The results of the first flash and the Voltage Estimator’s
output are given to the factory-programmed on-chip
EEPROM which returns a correction code corresponding to
the error of the MSB ladder at that tap. This code is converted to a voltage by the Correction DAC. To generate the next
four bits, SW1 is moved to position 2, so the ladder voltage
and the correction voltage are subtracted from the input
voltage. The remainder is applied to the sixteen flash converters and compared with the 16 tap points from the LSB
ladder.
The result of this second conversion is accurate to 10 bits
and describes the input remainder as a voltage between two
tap points (V
last two bits, the voltage across the ladder resistor (between
V
and VL) is divided up into 4 equal parts by the capacitive
H
voltage divider, shown in
6 LSBs below V
used by the digital error correction. SW1 is moved to posi-
and VL) on the LSB ladder. To resolve the
H
Figure 5.
and 6 LSBs above VHto provide overlap
L
tion 3, and the remainder is compared with these 16 new
voltages. The output is combined with the results of the
. This overlap of
REF
and
REF
REF
The divider also creates
Voltage Estimator, first flash, and second flash to yield the
final 12-bit result.
By using the same sixteen comparators for all three flash
conversions, the number of comparators needed by the
multi-step converter is significantly reduced when compared
to standard multi-step techniques.
Applications Information
1.0 MODES OF OPERATION
The ADC12062 has two interface modes: An interrupt/read
mode and a high speed mode.
timing diagrams for these interfaces.
In order to clearly show the relationship between S/H
RD
, and OE, the control logic decoding section of the
ADC12062 is shown in
Interrupt Interface
As shown in
Figure 1,
the falling edge of S/H holds the input
voltage and initiates a conversion. At the end of the conversion, the EOC output goes high and the INT
low, indicating that the conversion results are latched and
may be read by pulling RD
sets the INT
line. Note that CS must be low to enable S/H
or RD.
High Speed Interface
This is the fastest interface, shown in
output data is always present on the databus, and the INT
RD
delay is eliminated.
Figure 6
Figures 1
.
and2show the
output goes
low. The falling edge of RD re-
Figure 2.
,CS,
Here the
to
FIGURE 5. The Capacitive Voltage Divider
11
TL/H/11490– 15
Page 12
Applications Information (Continued)
FIGURE 6. ADC Control Logic
2.0 THE ANALOG INPUT
The analog input of the ADC12062 can be modeled as two
small resistances in series with the capacitance of the input
hold capacitor (C
is closed during the Sample period, and open during Hold.
The source has to charge C
sample period. Note that the source impedance of the input
voltage (R
charge C
IN
will not settle to within 0.5 LSBs of V
conversion begins, and the conversion results will be incor-
), as shown in
IN
) has a direct effect on the time it takes to
SOURCE
.IfR
SOURCE
Figure 7
to the input voltage within the
IN
is too large, the voltage across C
SOURCE
. The S/H switch
before the
rect. From a dynamic performance viewpoint, the combination of R
SOURCE,RMUX,RSW
filter. Minimizing R
sponse of the input stage of the converter.
Typical values for the components shown in
e
R
MUX
tling time to n bits is:
t
SETTLE
100X,R
e
(R
SOURCE
SOURCE
SW
, and CINform a low pass
will increase the frequency re-
e
100X, and C
a
R
MUX
e
25 pF. The set-
IN
a
RSW) * CIN* n * ln (2).
Figure 7
are:
The bandwidth of the input circuit is:
f
b
3dB
e
1/(2 * 3.14 * (R
SOURCE
a
a
R
RSW) * CIN)
MUX
TL/H/11490– 16
For maximum performance, the impedance of the source
driving the ADC12062 should be made as small as possible.
A source impedance of 100X or less is recommended. A
plot of dynamic performance vs. source impedance is given
in the Typical Performance Characteristics section.
If the signal source has a high output impedance, its output
should be buffered with an operational amplifier capable of
driving a switched 25 pF/100X load. Any ringing or instabilities at the op amp’s output during the sampling period can
IN
result in conversion errors. The LM6361 high speed op amp
is a good choice for this application due to its speed and its
ability to drive large capacitive loads.
LM6361 driving the ADC IN input of an ADC12062. The
100 pF capacitor at the input of the converter absorbs some
of the high frequency transients generated by the S/H
switching, reducing the op amp transient response requirements. The 100 pF capacitor should only be used with high
speed op amps that are unconditionally stable driving capacitive loads.
Figure 8
shows the
FIGURE 7. Simplified ADC12062 Input Stage
12
TL/H/11490– 17
Page 13
Applications Information (Continued)
FIGURE 8. Buffering the Input with an LM6361 High Speed Op Amp
Another benefit of using a high speed buffer is improved
THD performance when using the multiplexer of the
ADC12062. The MUX on-resistance is somewhat non-linear
over input voltage, causing the RC time constant formed by
C
This results in increasing THD with increasing frequency.
, and RSWto vary depending on the input voltage.
IN,RMUX
Inserting the buffer between the MUX OUT and the ADC IN
terminals as shown in
R
, significantly reducing the THD of the multiplexed sys-
MUX
tem.
Correct converter operation will be obtained for input voltages greater than AGND
Figure 8
will eliminate the loading on
b
50 mV and less than AV
CC
a
TL/H/11490– 18
50 mV. Avoid driving the signal source more than 300 mV
higher than AV
analog input pin is forced beyond these voltages, the cur-
, or more than 300 mV below AGND. If an
CC
rent flowing through that pin should be limited to 25 mA or
less to avoid permanent damage to the IC. The sum of all
the overdrive currents into all pins must be less than 50 mA.
When the input signal is expected to extend more than
300 mV beyond the power supply limits for any reason (unknown/uncontrollable input voltage range, power-on transients, fault conditions, etc.) some form of input protection,
such as that shown in
Figure 9,
should be used.
FIGURE 9. Input Protection
13
TL/H/11490– 19
Page 14
Applications Information (Continued)
3.0 ANALOG MULTIPLEXER
The ADC12062 has an input multiplexer that is controlled by
the logic level on pin S0 when EOC goes low, as shown in
Figures 1
spect to the S/H
equations:
t
MS (wrt S/H)
Note that t
that the data on S0 must become valid within 10 ns after
S/H
S0 must be valid for a length of
Table I shows how the input channels are assigned:
The output of the multiplexer is available to the user via the
MUX OUT pin. This output allows the user to perform additional signal processing, such as filtering or gain, before the
and2.Multiplexer setup and hold times with re-
input can be determined by these two
e
t
MH (wrt S/H)
t
MS
e
t
MH
MS (wrt S/H)
b
t
EOC (min)
a
t
EOC (max)
is a negative number; this indicates
e50b60eb
e50a
125e175 ns
goes low in order to meet the setup time requirements.
a
(t
t
MH
EOC (max)
)b(t
MS
b
t
EOC (min)
)e185 ns.
TABLE I. ADC12062 Input
Multiplexer Programming
S0 Channel
0V
1V
IN1
IN2
10 ns
signal is returned to the ADC IN input and digitized. If no
additional signal processing is required, the MUX OUT pin
should be tied directly to the ADC IN pin.
See Section 9.0 (APPLICATIONS) for a simple circuit that
will alternate between the two inputs while converting at full
speed.
4.0 REFERENCE INPUTS
In addition to the fully differential V
ence inputs used on most National Semiconductor ADCs,
REF
a
and V
REF
b
refer-
the ADC12062 has two sense outputs for precision control
of the ladder voltage. These sense inputs compensate for
errors due to IR drops between the reference source and
the ladder itself. The resistance of the reference ladder is
typically 750X. The parasitic resistance (R
leads, bond wires, PCB traces, etc. can easily be 0.5X to
) of the package
P
1.0X or more. This may not be significant at 8-bit or 10-bit
resolutions, but at 12 bits it can introduce voltage drops
causing offset and gain errors as large as 6 LSBs.
The ADC12062 provides a means to eliminate this error by
bringing out two additional pins that sense the exact voltage
at the top and bottom of the ladder. With the addition of two
op amps, the voltages on these internal nodes can be
forced to the exact value desired, as shown in
Figure 10.
FIGURE 10. Reference Ladder Force and Sense Inputs
14
TL/H/11490– 20
Page 15
Applications Information (Continued)
Since the current flowing through the SENSE lines is essentially zero, there is negligible voltage drop across R
1kXresistor, so the voltage at the inverting input of the op
amp accurately represents the voltage at the top (or bottom) of the ladder. The op amp drives the FORCE input and
forces the voltage at the ends of the ladder to equal the
voltage at the op amps’s non-inverting input, plus or minus
its input offset voltage. For this reason op amps with low
V
, such as the LM627 or LM607, should be used for this
OS
application. When used in this configuration, the ADC12062
typically has less than 0.5 LSB of offset and gain error without any user adjustments.
The 0.1 mF and 10 mF capacitors on the force inputs provide high frequency decoupling of the reference ladder. The
500X force resistors isolate the op amps from this large
capacitive load. The 0.01 mF/1 kX network provides zero
phase shift at high frequencies to ensure stability. Note that
the op amp supplies in this example must be
g
15V to meet the input/output voltage range requirements
of the LM627 and supply the sub-zero voltage to the
V
REFb(FORCE)
passed to analog ground with a 0.1 mF ceramic capacitor.
pin. The V
output should be by-
REF/16
and the
S
g
10V to
The reference inputs are fully differential and define the
zero to full-scale range of the input signal. They can be
configured to span up to 5V (V
or they can be connected to different voltages (within the
0V to 5V limits) when other input spans are required. The
ADC12062 is tested at V
e
(SENSE)
less than 4V increases the sensitivity (reduces the LSB size)
4.096V. Reducing the reference voltage span to
REFb(SENSE)
REF
e
0V, V
b
e
REF
0V, V
e
5V),
a
REF
of the converter; however noise performance degrades
when lower reference voltages are used. A plot of dynamic
performance vs reference voltage is given in the Typical
Performance Characteristics section.
If the converter will be used in an application where DC
accuracy is secondary to dynamic performance, then a simpler reference circuit may suffice. The circuit shown in
ure 11
will introduce several LSBs of offset and gain error,
Fig-
but INL, DNL, and all dynamic specifications will be unaffected.
All bypass capacitors should be located as close to the
ADC12062 as possible to minimize noise on the reference
ladder. The V
ground with a 0.1 mF ceramic capacitor.
output should be bypassed to analog
REF/16
The LM4040 shunt voltage reference is available with a
4.096V output voltage. With initial accuracies as low as
g
0.1%, it makes an excellent reference for the ADC12062.
a
FIGURE 11. Using the V
15
Force Pins Only
REF
TL/H/11490– 21
Page 16
Applications Information (Continued)
5.0 POWER SUPPLY CONSIDERATIONS
The ADC12062 is designed to operate from a single
power supply. There are two analog supply pins (AV
one digital supply pin (DV
external bypass capacitors for the analog and digital por-
). These pins allow separate
CC
tions of the circuit. To guarantee proper operation of the
converter, all three supply pins should be connected to the
same voltage source. In systems with separate analog and
digital supplies, the converter should be powered from the
analog supply.
The ground pins are AGND (analog ground), DGND1 (digital
input ground), and DGND2 (digital output ground). These
pins allow for three separate ground planes for these sections of the chip. Isolating the analog section from the two
digital sections reduces digital interference in the analog circuitry, improving the dynamic performance of the converter.
Separating the digital outputs from the digital inputs (particularly the S/H
input) reduces the possibility of ground bounce
from the 12 data lines causing jitter on the S/H
analog ground plane should be connected to the Digital2
ground plane at the ground return for the power supply. The
Digital1 ground plane should be tied to the Digital2 ground
plane at the DGND1 and DGND2 pins.
Both AV
plane with 0.1 mF ceramic capacitors. One of the two AV
pins should be bypassed to the AGND ground
CC
pins should also be bypassed with a 10 mF tantalum capacitor. DV
with a 0.1 mF capacitor in parallel with a 10 mF tantalum
should be bypassed to the DGND2 ground pIane
CC
capacitor.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC12062, it is necessary to use appropriate circuit board
layout techniques. Separate analog and digital ground
planes are required to meet datasheet AC and DC limits.
The analog ground plane should be low-impedance and free
of noise from other parts of the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a
filter capacitor) connected across the converter’s input
should be connected to a very clean analog ground return
point. Grounding the component at the wrong point will result in increased noise and reduced conversion accuracy.
Figure 12
gives an example of a suitable layout, including
power supply routing, ground plane separation, and bypass
capacitor placement. All analog circuitry (input amplifiers,
filters, reference components, etc.) should be placed on the
analog ground plane. All digital circuitry and I/O lines (excluding the S/H
input) should use the digital2 ground plane
as ground. The digital1 ground plane should only be used
for the S/H
signal generation.
a
) and
CC
input. The
5V
CC
FIGURE 12. PC Board Layout
TL/H/11490– 22
7.0 DYNAMIC PERFORMANCE
The ADC12062 is AC tested and its dynamic performance is
guaranteed. In order to meet these specifications, the clock
source driving the S/H
input must be free of jitter. For the
best AC performance, a crystal oscillator is recommended.
For operation at or near the ADC12062’s 1 MHz maximum
sampling rate, a 1 MHz squarewave will provide a good signal for the S/H
input. As long as the duty cycle is near 50%,
the waveform will be low for about 500 ns, which is within
the 550 ns limit. When operating the ADC12062 at a sample
rate of 910 kHz or below, the pulse width of the S/H
signal
must be smaller than half the sample period.
FIGURE 13. Crystal Clock Source
TL/H/11490– 23
Figure 13
is an example of a low jitter S/H pulse generator
that can be used with the ADC12062 and allow operation at
sampling rates from DC to 1 MHz. A standard 4-pin DIP
crystal oscillator provides a stable 1 MHz squarewave.
Since most DIP oscillators have TTL outputs, a 4.7k pullup
resistor is used to raise the output high voltage to CMOS
input levels. The output is fed to the trigger input (falling
16
Page 17
Applications Information (Continued)
edge) of an MM74HC4538 one-shot. The 1k resistor and 12
pF capacitor set the pulse length to approximately 100 ns.
The S/H
pulse stream for the converter appears on the Q
output of the HC4538. This is the S/H
on the ADC12062EVAL evaluation board. For lower power,
a CMOS inverter-based crystal oscillator can be used in
place of the DIP crystal oscillator. See Application Note
AN-340 in the National Semiconductor CMOS Logic Databook for more information on CMOS crystal oscillators.
8.0 COMMON APPLICATION PITFALLS
Driving inputs (analog or digital) outside power supply
rails. The Absolute Maximum Ratings state that all inputs
must be between GND
b
300 mV and V
rule is most often broken when the power supply to the
9.0 APPLICATIONS
clock generator used
a
300 mV. This
CC
2’s Complement Output
converter is turned off, but other devices connected to it (op
amps, microprocessors) still have power. Note that if there
is no power to the converter, DGND
e
AV
AGND and DGND.
0V, so all inputs should be withing300 mV of
CC
e
AGNDeDV
CC
Driving a high capacitance digital data bus. The more
capacitance the data bus has to charge for each conversion, the more instantaneous digital current required from
DV
and DGND. These large current spikes can couple
CC
back to the analog section, decreasing the SNR of the converter. While adequate supply bypassing and separate analog and digital ground planes will reduce this problem, buffering the digital data outputs (with a pair of MM74HC541s,
for example) may be necessary if the converter must drive a
heavily loaded databus.
e
Ping-Ponging between V
17
IN1
and V
TL/H/11490– 24
IN2
TL/H/11490– 25
Page 18
Applications Information (Continued)
AC Coupling Bipolar Inputs
TL/H/11490– 26
18
Page 19
Physical Dimensions inches (millimeters)
Plastic Leaded Chip Carrier (V)
Order Number ADC12062BIV, ADC12062CIV
NS Package Number V44A
19
Page 20
Physical Dimensions inches (millimeters) (Continued)
with Input Multiplexer and Sample/Hold
Plastic Quad Flat Package (VF)
Order Number ADC12062BIVF, ADC12062CIVF
ADC12062 12-Bit, 1 MHz, 75 mW A/D Converter
NS Package Number VGZ44A
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