Page 1
TL/H/5676
ADC1205/ADC1225 12-Bit Plus Sign mP Compatible A/D Converters
June 1994
ADC1205/ADC1225 12-Bit Plus Sign
mP Compatible A/D Converters
General Description
The ADC1205 and ADC1225 are CMOS, 12-bit plus sign
successive approximation A/D converters. The 24-pin
ADC1205 outputs the 13-bit data result in two 8-bit bytes,
formatted high-byte first with sign extended. The 28-pin
ADC1225 outputs a 13-bit word in parallel for direct interface to a 16-bit data bus.
Negative numbers are represented in 2’s complement data
format. All digital signals are fully TTL and MOS compatible.
A unipolar input (0V to 5V) can be accommodated with a
single 5V supply, while a bipolar input (
b
5V toa5V) re-
quires the addition of a 5V negative supply.
The ADC1205C and ADC1225C have a maximum non-linearity of 0.0224% of Full Scale.
Key Specifications
Y
ResolutionÐ12 bits plus sign
Y
Linearity ErrorÐg1 LSB
Y
Conversion TimeÐ100 ms
Features
Y
Compatible with all mPs
Y
True differential analog voltage inputs
Y
0V to 5V analog voltage range with single 5V supply
Y
TTL/MOS input/output compatible
Y
Low powerÐ25 mW max
Y
Standard 24-pin or 28-pin DIP
Connection and Functional Diagrams
Dual-In-Line Package
TL/H/5676– 1
Top View
Dual-In-Line Package
TL/H/5676– 2
Top View
TL/H/5676– 3
See Ordering Information
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Page 2
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (DV
CC
and AVCC) 6.5V
Negative Supply Voltage (V
b
)
b
15V to GND
Logic Control Inputs
b
0.3V toa15V
Voltage at Analog Inputs
[
V
IN(a),VIN(b)
]
(V
b
)b0.3V to V
CC
a
0.3V
Voltage at All Outputs, V
REF,VOS
b
0.3V to (V
CC
a
0.3)V
Input Current per Pin
g
5mA
Input Current per Package
g
20mA
Storage Temperature Range
b
65§Ctoa150§C
Package Dissipation at T
A
e
25§C 875 mW
Lead Temp. (Soldering, 10 seconds) 300
§
C
ESD Susceptibility (Note 12) 800V
Operating Conditions (Notes1&2)
Temperature Range T
MIN
s
T
A
s
T
MAX
ADC1205CCJ, ADC1225CCD
b
40§CsT
A
s
a
85§C
ADC1205CCJ-1, ADC1225CCD-1 0
§
CsT
A
s
70§C
Supply Voltage (DV
CC
and AVCC) 4.5 VDCto 6.0 V
DC
Negative Supply Voltage (Vb)
b
15V to GND
Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e
5V, V
REF
e
5V, f
CLK
e
1.0 MHz, V
b
eb
5V for bipolar input range, or
V
b
e
GND for unipolar input range unless otherwise specified. Bipolar input range is defined asb5.05VsV
IN(a)
s
5.05V;
b
5.05VsV
IN(b)
s
5.05V andlV
IN(a)
b
V
IN(b)
l
s
5.05V. Unipolar input range is defined asb0.05VsV
IN(a)
s
5.05V;
b
0.05VsV
IN(b)
s
5.05V andlV
IN(a)
b
V
IN(b)
l
s
5.05V. Boldface limits apply from T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25§C (Notes 3, 4, 5, 6, 7).
Parameter Conditions
ADC1205CCJ, ADC1225CCD ADC1205CCJ-1, ADC1225CCD-1
Units
Limit
Typ
Tested Design
Typ
Tested Design
(Note 8)
Limit Limit
(Note 8)
Limit Limit
(Note 9) (Note 10) (Note 9) (Note 10)
CONVERTER CHARACTERISTICS
Linearity Error Unipolar Input
ADC1205CCJ, ADC1225CCD Range
g
1 LSB
ADC1205CCJ-1, ADC1225CCD-1 (Note 11)
g
1
g
1 LSB
Unadjusted Zero Error Unipolar Input
g
2
g
2
g
2 LSB
Range
Unadjusted Positive and Negative Unipolar Input
g
30
g
30
g
30 LSB
Full-Scale Error Range
Negative Full-Scale Error Unipolar Input
g
(/2
g
(/2 LSB
Range, Full
Scale Adj. to
Zero
Linearity Error Bipolar Input
ADC1205CCJ, ADC1225CCD Range
g
2 LSB
ADC1205CCJ-1, ADC1225CCD-1 (Note 11)
g
2
g
2 LSB
Unadjusted Zero Error Bipolar Input
g
2
g
2
g
2 LSB
Range
Unadjusted Positive and Negative Bipolar Input
g
30
g
30
g
30 LSB
Full-Scale Error Range
Negative Full-Scale Error Bipolar Input
g
2
g
2
g
2 LSB
Range, Full
Scale Adj. to
Zero
Maximum Gain Temperature 6 15 6 15 ppm/§C
Coefficient
Maximum Offset Temperature 0.5 1.5 0.5 1.5 ppm/§C
Coefficient
Minimum V
REF
Input Resistance 4.0 2 4.0 2 2 kX
Maximum V
REF
Input Resistance 4.0 8 4.0 8 8 kX
2
Page 3
Electrical Characteristics (Continued)
The following specifications apply for DV
CC
e
AV
CC
e
5V, V
REF
e
5V, f
CLK
e
1.0 MHz, V
b
eb
5V for bipolar input range, or
V
b
e
GND for unipolar input range unless otherwise specified. Bipolar input range is defined asb5.05VsV
IN(a)
s
5.05V;
b
5.05VsV
IN(b)
s
5.05V andlV
IN(a)
b
V
IN(b)
l
s
5.05V. Unipolar input range is defined asb0.05VsV
IN(a)
s
5.05V;
b
0.05VsV
IN(b)
s
5.05V andlV
IN(a)
b
V
IN(b)
l
s
5.05V. Boldface limits apply from T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25§C (Notes 3, 4, 5, 6, 7).
Parameter Conditions
ADC1205CCJ, ADC1225CCD ADC1205CCJ-1, ADC1225CCD-1
Units
Limit
Typ
Tested Design
Typ
Tested Design
(Note 8)
Limit Limit
(Note 8)
Limit Limit
(Note 9) (Note 10) (Note 9) (Note 10)
CONVERTER CHARACTERISTICS (Continued)
Minimum Analog Input Unipolar Input GND-0.05 GND-0.05 GND-0.05 V
Voltage Range
Bipolar Input
b
V
CC
b
0.05
b
V
C
b
0.05bV
CC
b
0.05 V
Range
Maximum Analog Input Unipolar Input V
CC
a
0.05 V
CC
a
0.05 V
CC
a
0.05 V
Voltage Range
Bipolar Input V
CC
a
0.05 V
CC
a
0.05 V
CC
a
0.05 V
Range
DC Common-Mode Error
g
(/8
g
(/2
g
(/8
g
(/2
g
(/2 LSB
Power Supply Sensitivity AV
CC
e
DV
CC
e
5Vg5%,
V
b
eb
5Vg5%
Zero Error
g
*/4
g
*/4
g
*/4 LSB
Positive and Negative
g
*/4
g
*/4
g
*/4 LSB
Full-Scale Error
Linearity Error
g
(/4
g
(/4
g
(/4 LSB
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
, Logical ‘‘1’’ Input V
CC
e
5.25V, 2.0 2.0 2.0 V
Voltage (Min) All Inputs except
CLK IN
V
IN(0)
, Logical ‘‘0’’ Input V
CC
e
4.75V, 0.8 0.8 0.8 V
Voltage (Max) All Inputs except
CLK IN
I
IN(1)
, Logical ‘‘1’’ Input V
IN
e
5V 0.005 1 0.005 1 mA
Current (Max)
I
IN(0)
, Logical ‘‘0’’ Input V
IN
e
0V
b
0.005
b
1
b
0.005
b
1 mA
Current (Max)
V
T
a
(Min), Minimum Positive- CLK IN 3.1 2.7 3.1 2.7 2.7 V
Going Threshold Voltage
V
T
a
(Max), Maximum Positive- CLK IN 3.1 3.5 3.1 3.5 3.5 V
Going Threshold Voltage
V
T
b
(Min), Minimum Negative- CLK IN 1.8 1.4 1.8 1.4 1.4 V
Going Threshold Voltage
V
T
b
(Max), Maximum Negative- CLK IN 1.8 2.1 1.8 2.1 2.1 V
Going Threshold Voltage
VH(Min), Minimum Hysteresis CLK IN 1.3 0.6 1.3 0.6 0.6 V
[
V
T
a
(Min)bV
T
b
(Max)
]
VH(Max), Maximum Hysteresis CLK IN 1.3 2.1 1.3 2.1 2.1 V
[
V
T
a
(Max)bV
T
b
(Min)
]
3
Page 4
Electrical Characteristics (Continued)
The following specifications apply for DV
CC
e
AV
CC
e
5V, V
REF
e
5V, f
CLK
e
1.0 MHz, V
b
eb
5V for bipolar input range, or
V
b
e
GND for unipolar input range unless otherwise specified. Bipolar input range is defined asb5.05VsV
IN(a)
s
5.05V;
b
5.05VsV
IN(b)
s
5.05V andlV
IN(a)
b
V
IN(b)
l
s
5.05V. Unipolar input range is defined asb0.05VsV
IN(a)
s
5.05V;
b
0.05VsV
IN(b)
s
5.05V andlV
IN(a)
b
V
IN(b)
l
s
5.05V. Boldface limits apply from T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25§C (Notes 3, 4, 5, 6, 7).
Parameter Conditions
ADC1205CCJ, ADC1225CCD ADC1205CCJ-1, ADC1225CCD-1
Units
Limit
Typ
Tested Design
Typ
Tested Design
(Note 8)
Limit Limit
(Note 8)
Limit Limit
(Note 9) (Note 10) (Note 9) (Note 10)
DIGITAL AND DC CHARACTERISTICS (Continued)
V
OUT(1)
, Logical ‘‘1’’ Output V
CC
e
4.75V
Voltage (Min) I
OUT
eb
360 mA 2.4 2.4 2.4 V
I
OUT
eb
10 mA 4.5 4.5 4.5 V
V
OUT(0)
, Logical ‘‘0’’ Output V
CC
e
4.75V 0.4 0.4 0.4 V
Voltage (Max) I
OUT
e
1.6 mA
I
OUT
, TRI-STATE Output Leakage V
OUT
e
0V
b
0.01
b
3
b
0.01
b
0.3
b
3 mA
Current (Max) V
OUT
e
5V 0.01 3 0.01 0.3 3 mA
I
SOURCE
, Output Source Current V
OUT
e
0V
b
12
b
6.0
b
12
b
7.0
b
6.0 mA
(Min)
I
SINK
, Output Sink Current (Min) V
OUT
e
5V 16 8.0 16 9.0 8.0 mA
DICC,DVCCSupply Current (Max) f
CLK
e
1 MHz, CSe11 3 1 2.5 3 mA
AICC,AVCCSupply Current (Max) f
CLK
e
1 MHz, CSe11 3 1 2.5 3 mA
Ib,VbSupply Current (Max) f
CLK
e
1 MHz, CSe110 100 10 100 100 mA
AC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e
5.0V, t
r
e
t
f
e
20 ns and T
A
e
25§C unless otherwise specified.
Typ
Tested Design
Limit
Parameter Conditions
(Note 8)
Limit Limit
Units
(Note 9) (Note 10)
f
CLK
, Clock Frequency MIN 1.0 0.3 MHz
MAX 1.0 1.5 MHz
Clock Duty Cycle MIN 40 %
MAX 60 %
TC, Conversion Time MIN 108 1/f
CLK
MAX 109 1/f
CLK
MIN f
CLK
e
1.0 MHz 108 ms
MAX f
CLK
e
1.0 MHz 109 ms
t
W(WR)L
,WRPulse Width MAX 220 350 ns
t
ACC
, Access Time (Delay from C
L
e
100 pF 210 340 ns
Falling Edge of RD
to
Output Data Valid) (Max)
t1H,t0H, TRI-STATE Control (Delay R
L
e
2k, C
L
e
100 pF 170 290 ns
from Rising Edge of RD
to
Hi-Z State) (Max)
t
PD(READYOUT)
,RDor WR to 250 400 ns
READYOUT Delay (Max)
t
PD(INT),
RD or WR to Reset of INT 250 400 ns
(Max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings.
Note 2: All voltages are measured with respect to ground, unless otherwise specified.
Note 3: A parasitic zener diode exists internally from AV
CC
and DVCCto ground. This parasitic zener has a typical breakdown voltage of 7 VDC.
4
Page 5
AC Electrical Characteristics (Continued)
Note 4: Two on-chip diodes are tied to each analog input as shown below.
TL/H/5676– 4
Errors in the A/D conversion can occur if these diodes are forward biased more than 50 mV. This means that if AVCCand DVCCare minimum (4.75 VDC) and Vbis
minimum (
b
4.75VDC), full-scale must bes4.8VDC.
Note 5: A diode exists between analog V
CC
and digital VC.
TL/H/5676– 20
To guarantee accuracy, it is required that the AVCCand DVCCbe connected together to a power supply with separate bypass filters at each VCCpin.
Note 6: A diode exists between analog ground and digital ground.
TL/H/5676– 21
To guarantee accuracy, it is required that the analog ground and digital ground be connected together externally.
Note 7: Accuracy is guaranteed at f
CLK
e
1.0 MHz. At higher clock frequencies accuracy may degrade.
Note 8: Typicals are at 25
§
C and represent most likely parametric norm.
Note 9: Tested and guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 11: Linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line which passes through positive full scale and zero,
after adjusting zero error. (See
Figures 1b
and1c).
Note 12: Human body model; 100 pF discharged through a 1.5 kX resistor.
TL/H/5676– 8
FIGURE 1a. Transfer Characteristic
5
Page 6
TL/H/5676– 22
FIGURE 1b. Simplified Error Curve vs. Output Code Without Zero and Fullscale Adjustment
TL/H/5676– 23
FIGURE 1c. Simplified Error Curve vs. Output Code after Zero/Fullscale Adjustment
TL/H/5676– 7
FIGURE 2. TRI-STATE Test Circuits and Waveforms
6
Page 7
Timing Diagrams
TL/H/5676– 15
FIGURE 3. Timing Diagram
TL/H/5676– 13
FIGURE 4. Ready Out
TL/H/5676– 14
FIGURE 5. Data Out
7
Page 8
TL/H/5676– 5
FIGURE 6. Functional Block Diagram
8
Page 9
Functional Description
1.0 THE A/D CONVERSION
1.1 STARTING A CONVERSION
When using the ADC1225 or ADC1205 with a microprocessor, starting an A-to-D conversion is like writing to an external memory location. The WR
and CS lines are used to start
the conversion. The simplified logic (
Figure 6
) shows that
the falling edge of WR
with CS low clocks the D-type flipflop and initiates the conversion sequence. A new conversion can therefore be restarted before the end of the previous sequence. INT
going low indicates the conversion’s
end.
1.2 THE CONVERSION PROCESS (Numbers designated
by[]refer to portions of
Figure 6
.)
The SARS LOGIC[2]controls the A-to-D conversion process. When ‘sars’ goes high the clock (clk) is gated to the
TIMING GENERATOR[9]. One of the outputs of the TIMING GENERATOR, T
z
, provides the clock for the Succes-
sive Approximation Register, SAR LOGIC[5]. The T
z
clock
rate is (/8 of the CLK IN frequency.
Inputs to the 12-BIT DAC[11]and control of the SAMPLED
DATA COMPARATOR[10]sign logic are provided by the
SAR LOGIC. The first step in the conversion process is to
set the sign to positive (logic ‘0’) and the input of the DAC to
000 (HEX notation). If the differential input, V
IN(a)
b
V
IN(b)
,
is positive the sign bit will remain low. If it is negative the
sign bit will be set high. Differential inputs of only a few
hundred microvolts are enough to provide full logic swings
at the output of the SAMPLED DATA COMPARATOR.
The sign bit indicates the polarity of the differential input. If it
is set high, the negative input must have been greater than
the positive input. By reversing the polarity of the differential
input, V
IN(a)
and V
IN(b)
are interchanged and the DAC
sees the negative input as positive. The input polarity reversal is done digitally by changing the timing on the input sampling switches of the SAMPLED DATA COMPARATOR.
Thus, with almost no additional circuitry, the A/D is extended from a unipolar 12-bit to a bipolar 12-bit (12-bit plus sign)
device.
After determining the input polarity, the conversion proceeds with the successive approximation process. The SAR
LOGIC successively tries each bit of the 12-BIT DAC. The
most significant bit (MSB), B11, has a weight of (/2 of V
REF
.
The next bit, B10, has a weight of (/4 V
REF
. Each successive
bit is reduced in weight by a factor of 2 which gives the least
significant bit (LSB) a weight of 1/4096 V
REF
.
When the MSB is tried, the comparator compares the DAC
output, V
REF
/2, to the analog input. If the analog input is
greater than V
REF
/2 the comparator tells the SAR LOGIC to
set the MSB. If the analog input is less than V
REF
/2 the
comparator tells the SAR LOGIC to reset the MSB. On the
next bit-test the DAC output will either be */4 V
REF
or (/4
V
REF
depending on whether the MSB was set or not. Following this sequence through for each successive bit will
approximate the analog input to within 1-bit (one part in
4096).
On completion of the LSB bit-test the conversion-complete
flip-flop (CC) is set, signifying that the conversion is finished.
The end-of-conversion (EOC) and interrupt (INT
) lines are
not changed at this time. Some internal housekeeping tasks
must be completed before the outside world is notified that
the conversion is finished.
Setting CC enables the UPDATE LOGIC[12]. This logic
controls the transfer of data from the SAR LOGIC to the
OUTPUT LATCH[6]and resets the internal logic in preparation for a new conversion. This means that when EOC
goes high, a new conversion can be immediately started
since the internal logic has already been reset. In the same
way, data is transferred to the OUTPUT LATCH prior to issuing an interrupt. This assures that data can be read immediately after INT
goes low.
2.0 READING THE A/D
The ADC 1225 makes all thirteen bits of the conversion
result available in parallel. Taking CS
and RD low enables
the TRI-STATE
É
output buffers. The conversion result is
represented in 2’s complement format.
The ADC1205 makes the conversion result available in two
eight-bit bytes. The output format is 2’s complement with
extended sign. Data is right justified and presented high
byte first. With CS
low and STATUS high, the high byte
(DB12–DB8) will be enabled on the output buffers the first
time RD
goes low. When RD goes low a second time, the
low byte (DB7– DB0) will be enabled. On each read operation, the ‘byst’ flip-flop is toggled so that on successive
reads alternate bytes will be available on the outputs. The
‘byst’ flip-flop is always reset to the high byte at the end of a
conversion. Table 1 below shows the data bit locations on
the ADC1205.
The ADC1205’s STATUS
pin makes it possible to read the
conversion status and the state of the ‘byst’ flip-flop. With
RD
, STATUS and CS low, this information appears on the
data bus. The ‘byst’ status appears on pin 18 (DB2/DB10).
A low output on pin 18 indicates that the next data read will
be the high byte. A high output indicates that the next data
read will be the low byte. A high status bit on pin 22 (DB6/
DB12) indicates that the conversion is in progress. A high
output appears on pin 17 (DB1/DB9) when the conversion
is completed and the data has been transferred to the output latch. A high output on pin 16 (DB0/DB8) indicates that
the conversion has been completed and the data is ready to
read. This status bit is reset when a new conversion is initiated, data is read, or status is read. When reading status or a
conversion result, STATUS
should always change states at
least 600 ns before RD
goes low. If the conversion status
information is not needed, the STATUS
pin should be hard-
wired to V
a
. Table 2 summarizes the meanings of the four
status bits.
TABLE I. Data Bit Locations, ADC1205
HIGH BYTE DB12 DB12 DB12 DB12 DB11 DB10 DB9 DB8
LOW BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
TABLE II. Status Bit Locations and Meanings
Status
Status
Condition to
Bit
Bit
Meaning Clear Status
Location Bit
DB6 SARS ‘‘High’’ indicates that
the conversion is in
progress
DB2 BYST ‘‘Low’’ indicates that Status write
the next data read is or toggle it
the high byte. with data
‘‘High’’ indicates that read
the next data read is
the low byte
9
Page 10
Functional Description (Continued)
TABLE II. Status Bit Locations and Meanings
(Continued)
Status Status Condition to
Bit Bit Meaning Clear Status
Location Bit
DB1 EOC ‘‘High’’ indicates that
the conversion is
completed and data is
transferred to the
output latch.
DB0 INT ‘‘High’’ indicates that Data read or
it is the end of the status read
conversion and the or status
data is ready to read write
3.0 INTERFACE
3.1 RESET OF INTERRUPT
INT
goes low at the end of the conversion and indicates that
data is transferred to the output latch. By reading data, INT
will be reset to high on the leading edge of the first read (RD
going low). INT is also reset on the leading (falling) edge of
WR
when starting a conversion.
3.2 READY OUT
To simplify the hardware connection to high speed microprocessors, a READY OUT line is provided. This allows the
A-to-D to insert a wait state in the mP’s read cycle. The
equivalent circuit and the timing diagram for READY OUT is
shown in
Figures 7
and8.
TL/H/5676– 9
FIGURE 7. READY OUT Equivalent Circuit
TL/H/5676– 10
FIGURE 8. READY OUT Timing Diagram
3.3 RESETTING THE A/D
All the internal logic can be reset, which will abort any conversion in process and reset the status bits. The reset function is achieved by performing a status write (CS
,WRand
STATUS
are low).
3.4 ADDITIONAL TIMING AND INTERFACE OPTIONS
ADC1225
1. WR
and RD can be tied together with CS low continuously or strobed. The previous conversion’s data will be
available when the WR
and RD are low as shown below.
One drawback is that, since the conversion is started on the
falling edge and the data read on the rising edge of WR
/RD,
the first data access will have erroneous information depending on the power-up state of the internal output latches.
If the WR
/RD strobe is longer than the conversion time,
INTR
will never go low to signal the end of a conversion.
The conversion will be completed and the output latches will
be updated. In this case the READY OUT signal can be
used to sense the end of the conversion since it will go low
when the output latches are being updated.
TL/H/5676– 24
FIGURE 9
10
Page 11
Functional Description (Continued)
TL/H/5676– 25
FIGURE 10
TL/H/5676– 26
FIGURE 11
TL/H/5676– 27
FIGURE 12
11
Page 12
Functional Description (Continued)
TL/H/5676– 28
TL/H/5676– 29
FIGURE 13
When using this method of conversion only one strobe is
necessary and the rising edge of WR
/RD can be used to
read the current conversion results. These methods reduce
the throughput time of the conversion since the RD
and WR
cycles are combined.
2. With the standard timing WR pulse width longer than the
conversion time a conversion is completed but the INTR
will
never go low to signal the end of a conversion. The output
latches will be updated and valid information will be available when the RD
cycle is accomplished.
3. Tying CS
and RD low continuously and strobing WR to
initiate a conversion will also yield valid data. The INTR
will
never go low to signal the end of a conversion and the
digital outputs will always be enabled, so using INTR
to
strobe the WR
line for a continuous conversion cannot be
done with this part.
A simple stand-alone circuit can be accomplished by driving
WR
with the inverse of the READY OUT signal using a sim-
ple inverter as shown below.
TL/H/5676– 30
FIGURE 14
12
Page 13
Functional Description (Continued)
ADC1205
Case 1 would be the only one that would appy to the
ADC1205 since two RD
strobes are necessary to retrieve
the 13 bits of information on the 8 bit data bus. Simultaneously strobing WR
and RD low will enable the most significant byte on DB0 – DB7 and start a conversion. Pulsing
WR
/RD low before the end of this conversion will enable
the least significant byte of data on the outputs and restart a
conversion.
4.0 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog inputs (the difference
between V
IN(a)
and V
IN(b)
, over which 4096 positive output codes and 4096 negative output codes exist. The
A-to-D can be used in either ratiometric or absolute reference applications. V
REF
must be connected to a voltage
source capable of driving the reference input resistance
(typically 4 kX).
In a ratiometric system, the analog input voltage is proportional to the voltage used for the A/D reference. When this
voltage is the system power supply, the V
REF
pin can be
tied to V
CC
. This technique relaxes the stability requirement
of the system reference as the analog input and A/D reference move together maintaining the same output code for a
given input condition.
For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the reference voltage will require an initial adjustment to null out full-scale errors.
5.0 THE ANALOG INPUTS
5.1 DIFFERENTIAL VOLTAGE INPUTS AND COMMON
MODE REJECTION
The differential inputs of the ADC1225 and ADC1205 actually reduce the effects of common-mode input noise, i.e.,
signals common to both V
IN(a)
and V
IN(b)
inputs (60 Hz is
most typical). The time interval between sampling the ‘‘
a
’’
and ‘‘
b
‘‘ input is 4 clock periods. Therefore, a change in the
common-mode voltage during this short time interval may
cause conversion errors. For a sinusoidal common-mode
signal the error would be:
V
ERROR(MAX)
e
V
PEAK
(2q fCM)
4
f
CLK
where fCMis the frequency of the common-mode signal,
V
PEAK
is its peak voltage value and f
CLK
is the converter’s
clock frequency. In most cases V
ERROR
will not be significant. For a 60 Hz common-mode signal to generate a (/4
LSB error (300 mV) with the converter running at 1 MHz its
peak value would have to be 200mV.
5.2 INPUT CURRENT
Due to the sampling nature of the analog inputs, short duration spikes of current enter the ‘‘
a
’’ input and exit the ‘‘b’’
input at the leading clock edges during the actual conversion. These currents decay rapidly and do not cause errors
as the internal comparator is strobed at the end of a clock
period.
5.3 INPUT BYPASS CAPACITORS
Bypass capacitors at the inputs will average the current
spikes mentioned in 5.2 and cause a DC current to flow
through the output resistance of the analog signal source.
This charge pumping action is worse for continuous conversions with the V
IN(a)
input voltage at full-scale. For continuous conversions with a 1 MHz clock frequency and the
V
IN(a)
input at 5V, the average input current is approximately 5 mA. For this reason bypass capacitors should not be
used at the analog inputs for high resistance sources
(R
SOURCE
100 X).
If input bypass capacitors are necessary for noise filtering
and high source resistance is desirable to minimize capacitor
size, the detrimental effects of the voltage drop across this
input resistance, due to the average value of the input current, can be minimized with a full-scale adjustment while the
given source resistance and input bypass capacitor are both
in place. This is effective because the average value of the
input current is a linear function of the differential input voltage.
5.4 INPUT SOURCE RESISTANCE
Large values of source resistance where an input bypass
capacitor is not used, will not cause errors as the input currents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series resistor (R
s
100 X) for a passive RC section or add an op amp
RC active low pass filter. For low source resistance applications, (R
SOURCE
s
100 X) a 0.001 mF bypass capacitor at
the inputs will prevent pickup due to series lead inductance
of a long wire. A 100 X series resistor can be used to isolate
this capacitor – both the R and C are placed outside the
feedback loop – from the output of an op amp, if used.
5.5 NOISE
The leads to the analog inputs should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to these inputs can cause
errors. Input filtering can be used to reduce the effects of
these sources, but careful note should be taken of sections
5.3 and 5.4 if this route is taken.
6.0 POWER SUPPLIES
Noise spikes on the V
CC
supply line can cause conversion
errors as the comparator will respond to this noise. Low
inductance tantalum capacitors of 1 mF or greater are recommended for supply bypassing. Separate bypass caps
should be placed close to the DV
CC
and AVCCpins. If an
unregulated voltage source is available in the system, a separate LM340LAZ-5.0 voltage regulator for the A-to-D’s V
CC
(and other analog circuitry) will greatly reduce digital noise
on the supply line.
7.0 ERRORS AND REFERENCE VOLTAGE
ADJUSTMENTS
7.1 ZERO ADJUST
The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be measured by grounding the V
IN(b)
input and applying a small
magnitude positive voltage to the V
IN(a)
input. Zero error is
the difference between the actual DC input voltage necessary to just cause an output digital code transition from all
zeroes to 0,0000,0000,0001 and the ideal (/2 LSB value ((/2
LSB
e
0.61 mV for V
REF
e
5VDC). Zero error can be adjust-
ed as shown in
Figure 15
.V
IN(a)
is forced to 0.61 mV, and
V
IN(b)
is forced to 0V. The potentiometer is adjusted until
the digital output code changes from all zeroes to
0,000,0000,0001.
13
Page 14
Functional Description (Continued)
A simpler, although slightly less accurate, approach is to
ground V
IN(a)
and V
IN(b)
, and adjust for all zeros at the
output. Error will be well under (/2 LSB if the adjustment is
done so that the potentiometer is ‘‘centered’’ within the
0,000,000 range. A positive voltage at the V
OS
input will
reduce the output code. The adjustment range is
a
4to
b
30 LSB.
TL/H/5676– 11
FIGURE 15. Zero Adjust Circuit
7.2 POSITIVE AND NEGATIVE FULL-SCALE
ADJUSTMENT
Unipolar Inputs
Apply a differential input voltage which is 1.5 LSB below the
desired analog full-scale voltage (V
F
) and adjust the magni-
tude of the V
REF
input so that the output code is just chang-
ing from 0,1111,1111,1110 to 0,1111,1111,1111.
Bipolar Inputs
Do the same procedure outlined above for the unipolar case
and then change the differential input voltage so that the
digital output code is just changing from 1,0000,0000,0001
to 1,0000,0000,0000. Record the differential input voltage,
V
X
. the ideal differential input voltage for that transition
should be;
#
b
V
F
a
V
F
8192
J
Calculate the difference between Vx and the ideal voltage;
D
e
V
X
b#b
V
F
a
V
F
8192
J
Then apply a differential input voltage of;
#
V
X
b
D
2
J
and adjust the magnitude of V
REF
so the digital output
code is just changing from 1,0000,0000,0001 to
1,0000,0000,0000. That will obtain the positive and negative
full-scale transition with symmetrical minimum error.
Typical Applications
*Input must have some
current return path to
signal ground
TL/H/5676– 12
14
Page 15
Typical Applications (Continued)
Protecting the Input
TL/H/5676– 16
Diodes are 1N914
Operating with Ratiometric Transducers
*VIN(b)e0.15 V
CC
15% of V
CC
s
V
XDR
s
85% of V
CC
TL/H/5676– 17
15
Page 16
Typical Applications (Continued)
Bipolar Input Temperature Converter
TL/H/5676– 18
a
150 tob55§C with 0.04§C resolution
Note: * resistors are 1% metal film types
Strain Gauge Converter with .025% Resolution and Single Power Supply
TL/H/5676– 19
Note: 1)* resistors are 1% metal film types
2) LF412 power
a
10V and ground
16
Page 17
Ordering Information
Temperature Range 0§Cto70§C
b
40§Ctoa85§C
Non-Linearity 0.024% ADC1205CCJ-1 ADC1225CCD-1 ADC1205CCJ ADC1225CCD
Package Outline J24A D28D J24A D28D
Physical Dimensions inches (millimeters)
Ceramic Dual-In Line Package (J)
Order Number ADC1205CCJ-1 or ADC1205CCJ
NS Package Number J24A
17
Page 18
ADC1205/ADC1225 12-Bit Plus Sign mP Compatible A/D Converters
Physical Dimensions inches (millimeters) (Continued)
Ceramic Dual-In-Line Package (D)
Order Number ADC1225CCD-1 or ADC1225CCD
NS Package Number D28D
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