Page 1
ADC1173
8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter
ADC1173 8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter
February 1999
General Description
The ADC1173 is a low power, 15 MSPS analog-to-digital
converter that digitizes signals to 8 bits while consuming just
33 mW ofpower(typ). The ADC1173 uses a unique architecture that achieves 7.6 Effective Bits. Output formatting is
straight binary coding.
The excellent DC and AC characteristics of this device, together with its low power consumption and +3V single supply
operation, make it ideally suited for many video, imaging and
communications applications, including use in portable
equipment. Furthermore, the ADC1173 is resistant to latchup
and the outputs are short-circuit proof. The top and bottom of
theADC1173’s reference ladder is available for connections,
enabling a wide range of input possibilities.
TheADC1173 is offered in SOIC (EIAJ) and TSSOP. It is designed to operate over the commercial temperature range of
-20˚C to +75˚C.
Features
n Internal Sample-and-Hold Function
n Single +3V Operation
n Internal Reference Bias Resistors
n Industry Standard Pinout
n TRI-STATE
®
Outputs
Ordering Information
ADC1173CIJM SOIC (EIAJ)
ADC1173CIJMX SOIC (EIAJ) (tape & reel)
ADC1173CIMTC TSSOP
ADC1173CIMTCX TSSOP (tape & reel)
Key Specifications
n Resolution 8 Bits
n Maximum Sampling Frequency 15 MSPS (min)
n THD −56 dB (typ)
n DNL
n ENOB at 3.58 MHz Input 7.6 Bits (typ)
n Guaranteed No Missing Codes
n Differential Phase 0.5 Degree (max)
n Differential Gain 1.5%(typ)
n Power Consumption 33mW (typ)
(excluding reference current)
±
0.8 LSB (max)
Applications
n Video Digitization
n Digital Still Cameras
n Set Top Boxes
n Camcorders
n Personal Computer Video
n Digital Television
n CCD Imaging
n Electro-Optics
Pin Configuration
DS100890-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100890 www.national.com
Page 2
Block Diagram
Pin Descriptions and Equivalent Circuits
DS100890-2
Pin
Symbol Equivalent Circuit
No.
19 V
16 V
17 V
23 V
RTS
Description
IN
Analog signal input. Conversion range is VRBto
.
V
RT
Reference Top Bias with internal pull-up resistor.
Short this pin to V
ladder.
to self bias the reference
RT
Analog Input that is the high (top) side of the
reference ladder of the ADC. Nominal range is 1.0V
. Voltage on VRTand VRBinputs define the
RT
to AV
DD
conversion range. Bypass well. See Section 2.0
V
IN
for more information.
Analog Input that is the low (bottom) side of the
reference ladder of the ADC. Nominal range is 0V
RB
to 2.0V. Voltage on V
conversion range. Bypass well. See Section 2.0
V
IN
for more information.
and VRBinputs define the
RT
www.national.com 2
Page 3
Pin Descriptions and Equivalent Circuits (Continued)
Pin
Symbol Equivalent Circuit
No.
22 V
RBS
1OE
12 CLK
Description
Reference Bottom Bias with internal pull down
resistor. Short to V
ladder.
to self bias the reference
RB
CMOS/TTL compatible Digital input that, when low,
enables the digital outputs of the ADC1173. When
high, the outputs are in a high impedance state.
CMOS/TTL compatible digital clock Input. VINis
sampled on the falling edge of CLK input.
3 thru
10
D0-D7
11, 13 DV
2, 24 DV
14,
15, 18
AV
20, 21 AV
Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are
enabled by bringing the OE pin low.
Positive digital supply pin. Connect to a clean, quiet
voltage source of +3V. AV
DD
a common source and be separately bypassed with
a 10µF capacitor and a 0.1µF ceramic chip
and DVDDshould have
DD
capacitor. See Section 3.0 for more information.
The ground return for the digital supply. AVSSand
should be connected together close to the
SS
DV
SS
ADC1173.
Positive analog supply pin. Connected to a clean,
quiet voltage source of +3V. AV
DD
have a common source and be separately bypassed
with a 10 µF capacitor and a 0.1 µF ceramic chip
and DVDDshould
DD
capacitor. See Section 3.0 for more information.
The ground return for the analog supply. AVSSand
should be connected together close to the
SS
DV
SS
ADC1173 package.
www.national.com3
Page 4
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
AV
,DV
DD
DD
Voltage on Any Pin −0.3V to 6.5V
V
RT,VRB
CLK, OE Voltage −0.05 to (AVDD+ 0.05V)
Digital Output Voltage DV
Input Current (Note 3)
Package Input Current
(Note 3)
Package Dissipation at 25˚C (Note 4)
AVDDto V
to DV
SS
±
25mA
±
50mA
6.5V
SS
DD
ESD Susceptibility (Note 5)
Human Body Model 2000V
Machine Model 200V
Soldering Temp., Infared, 10
sec. (Note 6) 300˚C
Storage Temperature −65˚C to +150˚C
Operating Ratings(Notes 1, 2)
Temperature Range −20˚C ≤ T
AV
,DV
DD
|AV
V
V
V
DD
-DVSS| 0V to 100 mV
SS
RT
RB
Voltage Range VRBto V
IN
≤ +75˚C
A
+2.7V to +3.6V
1.0V to AV
0V to 2.0V
Converter Electrical Characteristics
The following specifications apply for AVDD=DV
at 50%duty cycle. Boldface limits apply for T
=
DD
=
T
A
MIN
+3.0V
to T
,OE=0V, V
DC
; all other limits T
MAX
Symbol Parameter Conditions
DC Accuracy
INL Integral Non Linearity
DNL Differential Non Linearity
Missing Codes 0 (max)
E
OT
E
OB
Top Offset −12 mV
Bottom Offset +1.0 mV
Video Accuracy
DP Differential Phase Error f
DG Differential Gain Error f
=
3.58 MHz sine wave 0.5 Degree
in
=
3.58 MHz sine wave 1.5
in
Analog Input and Reference Characteristics
V
IN
C
IN
R
IN
Input Range 2.0
VINInput Capacitance V
=
1.5V + 0.7Vrms
IN
Input Resistance
BW Analog Input Bandwidth 120 MHz
R
RT
R
REF
R
RB
I
REF
V
RT
V
RB
V
RTS
V
RBS
Top Reference Resistor 360 Ω
Reference Ladder
Resistance
to V
V
RT
RB
Bottom Reference Resistor 90 Ω
=
V
V
RT
RTS,VRB
=
V
RBS
Reference Ladder Current
Reference Top Self Bias
Voltage
Reference Bottom Self Bias
Voltage
Self Bias Voltage Delta
=
V
V
RT
VRTconnected to V
VRBconnected to V
connected to V
V
RT
V
connected to V
RB
connected to V
V
RT
connected to V
V
RB
connected to V
V
RT
connected to V
V
RB
RTS,VRB
=
AV
SS
RTS
RBS
RTS
RBS
,
RTS
RBS
,
RTS
SS
RT
=
+2.0V, V
A
(CLK
LOW)
(CLK
HIGH)
=
=
=
0V, C
RB
25˚C (Notes 7, 8)
Typical
(Note 9)
±
±
L
0.5
0.4
20 pF, f
Limits Units
4
11
>
1MΩ
300 200 Ω(min)
4.2
4.8 mA
1.56
0.36
1.2
1.38 V
=
15MHz
CLK
±
1.3 LSB( max)
±
0.85 LSB( max)
%
V
RB
V
RT
V(min)
V(max)
pF
400 Ω(max)
mA
1.45
1.65
V(min)
V(max)
0.32 V(min)
0.40 V(max)
1.1
1.3
µAmin
µAmax
DD
RT
www.national.com 4
Page 5
Converter Electrical Characteristics (Continued)
The following specifications apply for AVDD=DV
at 50%duty cycle. Boldface limits apply for T
=
DD
=
T
A
MIN
+3.0V
to T
,OE=0V, V
DC
; all other limits T
MAX
Symbol Parameter Conditions
Analog Input and Reference Characteristics
-
V
RT
V
RB
Reference Voltage Delta 2
Power Supply Characteristics
=
IA
ID
IAV
IDV
DD
DD
Analog Supply Current DV
Digital Supply Curretn DV
+
DD
Total Operating Current
DD
Power Consumption DV
DD
DD
DV
DDAVDD
DV
DD
(Note 10)
DD
=
AV
3.6V 6.8 mA
DD
=
=
AV
3.6V 2.3 mA
DD
=
3.6V, 9.1 11 mA
=
=
AV
3.6V, CLK Low
DD
=
=
AV
3.6V 33 40 mW
DD
CLK, OE Digital Input Characteristics
=
V
IH
V
IL
I
IH
I
IL
C
IN
Logical High Input Voltage DV
Logical Low Input Voltage DV
Logical High Input Current V
Logic Low Input Current V
DD
DD
=
IH
=
IL
Logic Input Capacitance 5 pF
AV
=
AV
DV
DD
0V, DV
=
3.6V 2.2 V (min)
DD
=
3.6V 0.8 V (max)
DD
=
=
AV
3.6V 5 µA
DD
=
=
AV
DD
DD
Digital Output Characteristics
V
V
I
I
OZH
OZL
=
DV
2.7V, I
OH
OL
High Level Output Voltage
Low Level Output Voltage DV
,
Tri-State®Leakage Current
DV
DV
V
DD
DD
DD
DD
OL
=
2.7V, I
=
2.7V, I
=
3.6V, OE=DV
=
0V or V
=
−360µA 2.4 V(min)
OH
=
−1.1mA 2.1 1.9 V(min)
OH
=
1.6mA 0.32 0.6 V(max)
OL
DD
=
DV
OH
DD
AC Electrical Characteristics
f
C1
f
C2
t
OD
t
OD
Maximum Conversion Rate 20 15 MHz(min)
Minimum Conversion Rate 1 MHz
−0 Output Delay CLK high to low data valid 28 ns(max)
−1 Output Delay CLK low to high data valid 24 ns(max)
Pipline Delay (Latency) 2.5
t
DS
t
AJ
t
OH
t
EN
t
DIS
ENOB Effective Number of Bits
SINAD Signal-to- Noise & Distortion
SNR Signal-to-Noise Ratio
SFDR
THD Total Harmonic Distortion
Sampling (Aperture) Delay CLK low to acquissition of data 3 ns
Aperture Jitter 30 ps rms
Output Hold Time CLK high to data invalid 15 ns
OE Low to Data Valid Loaded as in
OE High to High Z State Loaded as in
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
Spurious Free Dynamic
Range
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
Figure 2
Figure 2
1.31 MHz
3.58 MHz
7.5 MHz
1.31 MHz
3.58 MHz
7.5 MHz
1.31 MHz
3.58 MHz
7.5 MHz
1.31 MHz
3.58 MHz
7.5 MHz
1.31 MHz
3.58 MHz
7.5 MHz
RT
=
+2.0V, V
A
=
0V, C
RB
=
25˚C (Notes 7, 8)
Typical
(Note 9)
=
20 pF, f
L
CLK
Limits Units
=
1.0 V(min)
V
A
5.8 mA
3.6V −5 µA
,
±
20 µA
22 ns
12 ns
7.7
7.6
7.0 Bits (min)
7.4
49
47.7
43 dB(min)
46.5
49
48.7
44 dB(min)
48.0
65
55
51
−62
−54
−51
15MHz
V(max)
Clock
Cycles
dB
dB
www.national.com5
Page 6
Converter Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND=AV
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AV
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperatures (T
junction-to-ambient thermal resistance θ
TSSOP, θ
this part is 98˚C/W for the EIAJ SOIC). Note that the power dissipation of this device under normal operation will typically be about 49 mW (33 mW quiescent power
+ 13 mW reference ladder power+3mWdueto1TTLloan on each digital output. The values for maximum power dissipation listed above will be reached only when
the ADC1173 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
is 92˚C/W, so PDMAX=1,358 mW at 25˚C and 815 mW at the maximum operating ambient temperature of 75˚C. (Typical thermal resistance, θJA,of
JA
, and the ambient temperature, TA, and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 24-pin
JA
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pf discharged through ZERO Ω.
Note 6: See AN450, ″Surface Mounting Methods and Their Effect on Product Reliability″, or the section entitled ″Surface Mount″ found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this device. However, errors
in the A/D conversion can occur if the input goes above V
be ≤2.75V
to ensure accurate conversions.
DC
Note 8: To guarantee accuracy, it is required that AV
Note 9: Typical figures are at T
Level).
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
J
Note 10: At least two clock cycles must be presented to the ADC1173 after power up. See Section 4.0 for details.
=
=
DV
SS
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
J
or below GND by more than 50 mV. As an example, if AVDDis 2.7VDC, the full-scale input voltage must
DD
and DVDDbe well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
DD
0V, unless otherwise specified.
SS
SS
DS100890-10
or DVSS, or greater than AVDDor DVDD), the current at that pin should
www.national.com 6
Page 7
Typical Performance Characteristics
INL vs Temperature
SNR vs f
IN
SINAD/ENOB vs f
DNL vs Temperature
DS100890-20
DS100890-21
THD vs Temperature
DS100890-33
IN
SFDR vs f
IN
DS100890-23
SNR vs Temperature
DS100890-22
SINAD/ENOB vs Temp
DS100890-24
Differential Gain vs Temperature
DS100890-31
Differential Phase vs Temperature
DS100890-27
Spectral Response
DS100890-29
DS100890-28
IDDD+IADDvs f
DS100890-26
CLK
DS100890-32
www.national.com7
Page 8
Typical Performance Characteristics (Continued)
t
vs Temperature
OD
DS100890-25
Specification Definitions
ANALOG INPUT BANDWIDTH is a measure of the fre-
quency at which the reconstructed output fundamental drops
3 dB below its low frequency value for a full scale input. The
test is performed with f
tiples of f
dB relative to the low frequency input signal is the full power
. The input frequency at which the output is −3
CLK
bandwidth.
APERTURE JITTER is the time uncertainty of the sampling
point (t
), or the range of variation in the sampling delay.
DS
BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to the first
code and the negative reference voltage. Bottom offset is
defined as E
sition input voltage. Note that this is different from the normal
OB
Zero Scale Error.
DIFFERENTIAL GAIN ERROR is the percentage difference
between the output amplitudes of a high frequency reconstructed sine wave at two different dc levels.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave at two
different dc levels.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD -
1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from zero
1
scale (
⁄2LSB below the first code transition) through positive
full scale (
1
⁄2LSB above the last code transition). The deviation of any given code from this straight line is measured
from the center of that code value. The end poinnt test
method is used.
OUTPUT DELAY is the time delay after the rising edge of
the input clock before the data update is present at the output pins.
OUTPUT HOLD TIME is the length of time that the output
data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and the availability of that
conversion result at the output. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay.
equal to 100 KHz plus integer mul-
IN
=
, where VZTis the first code tran-
V
ZT-VRB
SAMPLING (APERTURE) DELAYis that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input signal and goes into the ″hold″ mode t
low.
SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms
value of the input signal to the rms value of the other spectral
components below one-half the sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) Is the ratio of the rms value of the input signal to the
rms value of all of the other spectral components below half
the clock frequency, including harmonics but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOP OFFSET is the difference between the positive reference voltage and the input voltage that just causes the output code to transition to full scale and is defined as E
V
FT−VRT
age. Note that this is different from the normal Full Scale Error.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the
rms total of the first six harmonic components, to the rms
value of the input signal.
after the clock goes
DS
. Where VFTis the full scale transition input volt-
OT
=
www.national.com 8
Page 9
Timing Diagram
DS100890-11
FIGURE 1. ADC1173 Timing Diagram
FIGURE 2. tEN,t
Test Circuit
DIS
DS100890-12
www.national.com9
Page 10
Functional Description
The ADC1173 uses a new, unique architecture to achieve
7.4 effective bits at and maintains superior dynamic performance up to
The analog signal at V
by V
Input voltages below V
sist of all zeroes. Input voltages above V
output word to consist of all ones. V
to the analog supply voltage, AV
0 to 2.0 Volts. V
positive than V
If V
RT
are connected together, the nominal values of VRTand V
are 1.56V and 0.36V, respectively. If VRTand V
nected together and V
V
RT
1
⁄2the clock frequency.
that is within the voltage range set
and VRBare digitized to eight bits at up to 20 MSPS.
RT
and V
RTS
is 1.38V.
IN
will cause the output word to con-
RB
RT
, while VRBhas a range of
should always be at least 1.0 Volt more
RT
.
RB
DD
will cause the
RT
has a range of 1.0 Volt
are connected together and VRBand V
is grounded, the nominal value of
RB
RTS
RBS
are con-
Data is acquired at the falling edge of the clock and the digital equivalent of the data is available at the digital outputs 2.5
clock cycles plus t
as the clock signal is present at pin 12. The Output Enable
later.TheADC1173 will convert as long
OD
pin OE, when low, enables the output pins. The digital outputs are in the high impedance state when the OE pin is
high.
Applications Information
1.0 The Analog Input
The analog input of the ADC1173 is a switch followed by an
integrator. The input capacitance changes with the clock
level, appearing as 4 pF when the clock is low, and 11 pF
when the clock is high. Since a dynamic capacitance is more
difficult to drive than a fixed capacitance, choose an amplifier
that can drive this type of load. The CLC409, CLC440,
LM6152, LM6154, LM6181 and LM6182 have been found to
be excellent devices for driving the ADC1173. Do not drive
the input beyond the supply rails.
Figure 3
LM6181. This circuit has both gain andoffset adjustments. If
shows an example of an input circuit using the
you desire to eliminate these adjustments, you should reduce the signal swing to avoid clipping at the ADC1173 output that can result from normal tolerances of all system components. With no adjustments, the nominal value for the
amplifier feedback resistor is 510Ω and the 5.1k resistor at
the inverting input should be changed to 860Ω and returned
to +3V rather than to the Offset Adjust potentiometer.
2.0 Reference Inputs
The reference inputs V
ence Bottom) are the top and bottom of the reference ladder.
(Reference Top) and VRB(Refer-
RT
Input signals between these two voltages will be digitized to
8 bits. External voltages applied to the reference input pins
should be within the range specified in the Operating Ratings
RB
table (1.0V to AV
Any device used to drive the reference pins should be able to
source sufficient current into the V
current from the V
The reference ladder can be self-biased by connecting V
to V
and connecting VRBto V
RTS
tom reference voltages of approximately 1.56V and 0.36V,
respectively, with V
Figure 3
.IfVRTand V
analog ground, a top reference voltage of approximately
for VRTand 0V to (AVDD- 1.0V) for VRB).
DD
pin and sink sufficient
pin.
RB
= 3.0V. This connection is shown in
CC
RTS
RT
to provide top and bot-
RBS
are tied together, but VRBis tied to
RT
1.38V is generated. The top and bottom of the laddershould
be bypassed with 10µF tantalum capacitors located close to
the reference pins.
The reference self-bias circuit of
Figure 3
is very simple and
performance is adequate for many applications. Superior
performance can generally be achieved by driving the reference pins with a low impedance source.
By forcing a little current into or out of the top and bottom of
the ladder, as shown in
Figure 4
, the top and bottom reference voltages can be trimmed. The resistive divider at the
amplifier inputs can be replaced with potentiometers. The
LMC662 amplifier shown was chosen for its low offset voltage and low cost. Note that a negative power supply is
needed for these amplifiers as their outputs may be required
to go slightly negative to force the required reference
voltages.
www.national.com 10
Page 11
Applications Information (Continued)
DS100890-13
FIGURE 3. Simple, Low Component Count, Self -Bias Reference application. Because of resistor tolerances, the
reference voltages can vary by as much as 6%. Choose an amplifier that can drive a dynamic capacitance (see text).
www.national.com11
Page 12
Applications Information (Continued)
DS100890-14
FIGURE 4. Better defining the ADC Reference Voltage. Self-bias is still used, but the reference voltages are trimmed
by providing a small trim current with the operational amplifiers.
www.national.com 12
Page 13
Applications Information (Continued)
DS100890-15
FIGURE 5. Driving the reference to force desired values requires driving with a low impedance source, provided by
the transistors. Note that pins 16 and 22 are not connected.
If reference voltages are desired that are more than a few
tens of millivolts from the self-bias values, the circuit of
ure 5
will allow forcing the reference voltages to whatever
Fig-
levels are desired. This circuit provides the best performance
because of the low source impedance of the transistors.
Note that the V
can be anywhere between VRB+ 1.0V and the analog
V
RT
supply voltage, and V
and 1.0V below V
accurate conversions, the total reference voltage range (V
-VRB) should be a minimum of 1.0V and a maximum of
about V
. Best performance can be realized with V
A
=
and V
RB
0.36V.
RTS
and V
RT
pins are left floating.
RBS
can be anywhere between ground
RB
. To minimize noise effects and ensure
RT
=
1.56
RT
3.0 Power Supply Considerations
Many A/D converters draw sufficienttransient current to corrupt their own power supplies if not adequately bypassed. A
10µF tantalum or aluminum electrolytic capacitor should be
placed within an of inch (2.5 centimeters) of the A/D power
pins, with a 0.1 µF ceramic chip capacitor placed as close as
possible to the converter’s power supply pins. Leadless chip
capacitors are preferred because they have low lead inductance.
While a single voltage source should be used for the analog
and digital supplies of the ADC1173, these supply pins
should be well isolated from each other to prevent any digital
noise from being coupled to the analog power pins. A 47
Ohm resistor is recommend between the analog and digital
supply lines, with a ceramic capacitor close to the analog
supply pin. Avoid inductive components in the analog supply
line.
The converter digital supply should not be the supply that is
used for other digital circuitry on the board. It should be the
same supply used for the A/D analog supply.
As is the case with all high speed converters, the ADC1173
should be assumed to have little power supply rejection, especially when self-biasing is used by connecting V
V
together.
RTS
RT
No pin should ever have a voltage on it that is in excess of
the supply voltages or below ground, not even on a trasient
www.national.com13
and
Page 14
Applications Information (Continued)
basis. This can be a problem upon application of power to a
circuit. Be sure that the supplies to circuits driving the CLK,
OE, analog input and reference pins do not come up any
faster than does the voltage at the ADC1173 power pins.
4.0 The ADC1173 Clock
Although the ADC1173is tested and its performance is guaranteed with a 15MHz clock, it typically will function with clock
frequencies from 1MHz to 20MHz.
If continuous conversions are not required, power consumption can be reduced somewhat by stopping the clock at a
logic low when the ADC1173is not being used. This reduces
the current drain in the ADC1173’s digital circuitry from a
typical value of 2.3mA to about 100µA.
Note that powering up the ADC1173 with the clock stopped
may not save power, as it will result in an increased current
flow (by as much as 170%) in the reference ladder. In some
cases, this may increase the ladder current above the specified limit. Toggling the clock twice at 1MHz or higher and returning it to the low state will eliminate the excess ladder current.
An alternative power-saving technique is to power up the
ADC1173with the clock active, then halt the clock in the low
state after two clock cycles. Stopping the clock in the high
state is not recommended as a power-saving technique.
5.0 Layout and Grounding
Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Separate analog and
digital ground planes that are connected beneath the
ADC1173are required to meet data sheet limits. The analog
and digital grounds may be in the same layer, but should be
separated from each other. The analog and digital ground
planes should never overlap each other.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and
remedy.The solution is to keep the analog circuity well separated from the digital circuitry and from the digital ground
plane.
Digital circuits create substantial supply and ground transients. The logic noise thus generated could have significant
impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise
characteristics, such as the 74HC(T) and 74AC(T)Q families.
Worst noise generators are logic families that draw the largest supply current transients during clock or signal edges,
like the 74F and the 74AC(T) families. In general, slower
logic families, such as 74LS and 74HC(T), will produce less
high frequency noise than do high speed logic families, such
as the 74F and 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is very narrow (about 3/16 inch)
compared with the rest of the ground plane. This narrowing
beneath the converter provides a fairly high impedance to
the high frequency components of the digital switching currents, directing them away from the analog pins. The relatively lower frequency analog ground currents do not see a
significant impedance across this narrow ground connection.
Generally,analog and digital lines should cross each other at
90 degrees to avoid getting digital noise into the analog path.
In video (high frequency) systems, however, avoid crossing
analog and digital lines altogether. Clock lines should be isolated from ALL other lines, analog and digital. Even the generally accepted 90 degree crossing should be avoided as
even a little coupling can cause problems at high frequencies. Best performance at high frequencies and at high resolution is obtained with a straight signal path.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, not even with just a small part of their bodies being beside each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input and ground should be connected
to a very clean point in the analog ground return.
DS100890-16
FIGURE 6. Layout example showing separate analog
and digital ground planes connected below the
Figure 6
gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be placed over the digital
ground plane.
6.0 Dynamic Performance
The ADC1173 is ac tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
ac performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock
tree. See
Figure 7
ADC1173.
.
www.national.com 14
Page 15
Applications Information (Continued)
FIGURE 7. Isolating the ADC clock from Digital Circuitry.
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce jitter into the clock signal.
7.0 Common Application Pitfalls
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 50mV below the ground pins or 50mV above the
supply pins. Exceeding these limits on even a transient basis
can cause faulty or erratic operation. It is not uncommon for
high speed digital circuits (e.g., 74F and 74AC devices) to
exhibit undershoot that goes more than a volt below ground.
A resistor of 50Ω in series with the offending digital input will
usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC1173. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current is
required from DV
rent spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with
an 74ACQ541, for example) may be necessary if the data
bus to be driven is heavily loaded. Dynamic performance
can also be improved by adding 47Ω series resistors at each
digital output, reducing the energy coupled back into the
converter output pins.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.0, the capacitance seen at the input alternates between 4 pF and 11 pF with the clock. This
and DGND. These large charging cur-
DD
DS100890-17
dynamic capacitance is more difficult to drive than is a fixed
capacitance, and should be considered when choosing a
driving device. The CLC409, CLC440, LM6152, LM6154,
LM6181 and LM6182 have been found to be excellent devices for driving the ADC1173 analog input.
Driving the V
not source or sink the current required by the ladder. As
pin or the VRBpin with devices that can
RT
mentioned in section 2.0, care should be taken to see that
any driving devices can source sufficient current into the V
pin and sink sufficient current from the VRBpin. If these pins
are not driven with devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic performance.
Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. Simple gates with RC
timing is generally inadequate as a clock source.
Input test signal contains harmonic distortion that interferes with the measurement of dynamic signal to noise
ratio. Harmonic and other interfering signals can be re-
moved by inserting a filter at the signal input. Suitable filters
are shown in
Figure 8
and
Figure 9
. The circuit of
Figure 8
has cutoff of about 5.5 MHz and is suitable for input frequencies of 1 MHz to 5 MHz. The circuit of
Figure 9
has a cutoff
of about 11 MHz and is suitable for input frequencies of 5
MHz to 10 MHz. These filters should be driven by a generator of 75 Ohm source impedance and terminated with a 75
ohm resistor.
RT
DS100890-18
FIGURE 8. 5.5 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input.
DS100890-19
FIGURE 9. 11 MHz Low Pass filter to eliminate harmonics at the signal input.
Use at input frequencies of 5 MHz to 10 MHz
www.national.com15
Page 16
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Package JM
Ordering Number ADC1173CIJM
NS Package Number M24D
www.national.com 16
Page 17
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
ADC1173 8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter
24-Lead Package TC
Ordering Number ADC1173CIMTC
NS Package Number MTC24
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National Semiconductor
Europe
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: sea.support@nsc.com
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Loading...