Page 1
June 1999
ADC10662/ADC10664
10-Bit 360 ns A/D Converter with Input Multiplexer and
Sample/Hold
ADC10662/ADC10664 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold
General Description
Using an innovative, patented multistep*conversion technique, the 10-bit ADC10662 and ADC10664 are 2- and
4-input CMOS analog-to-digital converters offering
sub-microsecond conversion times yet dissipating a maximum of only 235 mW. The ADC10662 and ADC10664 perform a 10-bit conversion in two lower-resolution “flashes”,
thus yielding a fast A/D without the cost, power dissipation,
and other problems associated with true flash approaches.
In addition to standard static performance specifications
(Linearity,Full-Scale Error, etc.) dynamic performance (THD,
S/N) is guaranteed.
The analog input voltage to the ADC10662 andADC10664 is
sampled and held by an internal sampling circuit. Input signals at frequencies from dc to over 250 kHz can therefore be
digitized accurately without the need for an external
sample-and-hold circuit.
The ADC10662 and ADC10664 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 360 ns.
For ease of interface to microprocessors, the ADC10662 and
ADC10664 have been designed to appear as a memory location or I/O port without the need for external interface
logic.
Ordering Information
ADC10662
Industrial
(−40˚C ≤ T
ADC10662CIWM M24B Small Outline
≤ +85˚C)
A
Package
Features
n Built-in sample-and-hold
n Single +5V supply
n 2- or 4-input multiplexer options
n No external clock required
Key Specifications
n Conversion time to 10 bits: 360 ns typical, 466 ns
max over temperature
n Sampling Rate: 1.5 MHz (min)
n Low power dissipation: 235 mW (max)
n Total harmonic distortion (50 kHz): −60 dB (max)
n No missing codes over temperature
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
ADC10664
Industrial
(−40˚C ≤ T
ADC10664CIWM M28B Small Outline
≤ +85˚C)
A
Package
*
U.S. Patent Number 4918449
®
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011192 www.national.com
Page 2
Simplified Block Diagram
*ADC10664 Only
Connection Diagrams
Top View
DS011192-9
DS011192-10
DS011192-11
Top View
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Page 3
Pin Descriptions
DVCC,
AV
CC
INT
S/H This is the Sample/Hold control input. When
RD
CS
S0, S1 These pins select the analog input that will be
V
REF−
V
REF+
These are the digital and analog positive supply voltage inputs. They should always be connected to the same voltage source, but are
brought out separately to allow for separate
bypass capacitors. Each supply pin should be
bypassed with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor to
ground.
This is the active low interrupt output. INT
goes low at the end of each conversion, and
returns to a high state following the rising edge
of RD .
this pin is forced low (and CS is low), it causes
the analog input signal to be sampled and initiates a new conversion.
This is the active low Read control input.
When this RD and CS are low, any data
present in the output registers will be placed
on the data bus.
This is the active low Chip Select control input.
When low, this pin enables the RD and S /H
pins.
connected to the A/D during the conversion.
The input is selected based on the state of S0
and S1 when S /H makes its High-to-Low transition (See the Timing Diagrams). The
ADC10664 includes both S0 and S1. The
ADC10662 includes just S0.
,
These are the reference voltage inputs. They
may be placed at any voltage between GND
and V
, but V
CC
V
. An input voltage equal to V
REF−
duces an output code of 0, and an input voltage equal to (V
put code of 1023.
must be greater than
REF+
− 1 LSB) produces an out-
REF+
REF−
pro-
V
V
IN0,VIN1
IN2,VIN3
,
These are the analog input pins. The
ADC10662 has two inputs (V
the ADC10664 has four inputs (V
V
and V
IN2
should be less than 500Ω for best accuracy
). The impedance of the source
IN3
and V
IN0
and conversion speed. For accurate conversions, no input pin (even one that is not selected) should be driven more than 50 mV
GND, AGND,
DGND
above V
These are the power supply ground pins. The
ADC10662 and ADC10664 have separate
or 50 mV below ground.
CC
analog and digital ground pins (AGND and
DGND) for separate bypassing of the analog
and digital supplies. The ground pins should
be connected to a stable, noise-free system
ground. Both pins should be returned to the
same potential.
DB0–DB9 These are the TRI-STATE output pins.
SPEED
ADJ
By connecting a resistor between this pin and
ground, the conversion time can be reduced.
The specifications listed in the table of Electri-
cal Characteristics apply for a speed adjust re-
sistor (R
kΩ (Mode 2). See the Typical Performance
) equal to 14.0 kΩ (Mode 1) or 8.26
SA
Curves and the table of Electrical Characteris-
tics.
) and
IN1
IN0,VIN1
,
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Page 4
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+
=
Supply Voltage (V
Voltage at Any Input or Output −0.3V to V
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4) 875 mW
ESD Susceptability (Note 5) 2000V
Soldering Information (Note 6)
N Package (10 Sec) 260˚C
Converter Characteristics
The following specifications apply for V
through a 14.0 kΩ resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface limits apply for T
=
=
T
to T
T
J
Min
Max
=
AV
DV
CC
CC
; all other limits T
) −0.3V to +6V
+
=
=
T
A
+5V, V
=
+25˚C.
J
REF(+)
+
+ 0.3V
=
+5V, V
SO Package:
Vapor Phase (60 Sec) 215˚C
Infrared (15 Sec) 220˚C
Storage Temperature Range −65˚C to +150˚C
Junction Temperature 150˚C
Operating Ratings (Notes 1, 2)
Temperature Range T
ADC10662CIN, ADC10662CIWM,
ADC10664CIN,
ADC10664CIWM −40˚C ≤ T
Supply Voltage Range 4.5V to 5.5V
=
GND, and Speed Adjust pin connected to ground
REF(−)
MIN
≤ TA≤ T
≤ +85˚C
A
Symbol Parameter Conditions Typical Limit Units
(Note 7) (Note 8) (Limit)
Resolution 10 Bits
Integral Linearity Error
Offset Error
Full-Scale Error
Total Unadjusted Error
±
0.5
±
0.5
±
1.0/±1.5 LSB
±
1 LSB (max)
±
1 LSB (max)
±
1.5/±2.0 LSB
Missing Codes 0 (max)
Power Supply Sensitivity V
THD Total Harmonic Distortion (Note 10) f
SNR Signal-to-Noise Ratio (Note 10) f
ENOB Effective Number of Bits (Note 10) f
R
REF
Reference Resistance 650 400 Ω (min)
=
5V
+
=
V
5V
=
1 kHz, 4.85 V
IN
=
f
50 kHz, 4.85 V
IN
=
f
100 kHz, 4.85 V
IN
=
f
240 kHz, 4.85 V
IN
=
1 kHz, 4.85 V
IN
=
f
50 kHz, 4.85 V
IN
=
f
100 kHz, 4.85 V
IN
=
1 kHz, 4.85 V
IN
=
f
50 kHz, 4.85 V
IN
±
5%,V
±
10%,V
REF
REF
=
4.5V
=
4.5V
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
±
1/16 LSB
1
±
⁄
8
LSB
−68 dB
−66 −60 dB (max)
−62 dB
−58 dB
61 dB
60 58 dB (min)
60 dB
9.6 Bits
9.5 9 Bits (min)
+
900 Ω (max)
V
V
V
V
V
V
REF(+)
REF(−)
REF(+)
REF(−)
IN
IN
V
Input Voltage V++ 0.05 V (max)
REF(+)
V
Input Voltage GND −
REF(−)
V
Input Voltage V
REF(+)
V
Input Voltage V
REF(−)
0.05
REF(−)
REF(+)
V (min)
V (min)
V (max)
Input Voltage V++ 0.05 V (max)
Input Voltage GND −
V (min)
0.05
OFF Channel Input Leakage Current CS=V
ON Channel Input Leakage Current CS=V
+
+
,V
,V
+
=
V
IN
+
=
V
IN
0.01 3 µA (max)
±
1 −3 µA (max)
MAX
A
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Page 5
DC Electrical Characteristics
The following specifications apply for V
through a 14.0 kΩ resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface limits apply for
=
=
to T
T
T
A
T
J
MIN
Symbol Parameter Conditions
V
V
I
I
V
V
I
DI
AI
IN(1)
IN(0)
OUT
IN(1)
IN(0)
OUT(1)
OUT(0)
CC
CC
Logical “1” Input Voltage V
Logical “0” Input Voltage V
Logical “1” Input Current V
Logical “0” Input Current V
Logical “1” Output Voltage V
Logical “0” Output Voltage V
TRI-STATE®Output Current V
DVCCSupply Current CS=S/H=RD=0 1.0 2 mA (max)
AVCCSupply Current CS=S/H=RD=0 30 45 mA (max)
; all other limits T
MAX
+
=
+5V, V
A
=
5V V
REF(+)
=
=
T
+25˚C.
J
+
=
5.5V 2.0 V (min)
+
=
4.5V 0.8 V (max)
=
5V 0.005 3.0 µA (max)
IN(1)
0V −0.005 −3.0 µA (max)
IN(0)
+
=
4.5V, I
+
=
V
4.5V, I
+
=
4.5V, I
=
5V 0.1 50 µA (max)
OUT
=
V
0V −0.1 −50 µA (max)
OUT
=
GND, and Speed Adjust pin connected to ground
REF(−)
Typical
(Note 7)
=
−360 µA 2.4 V (min)
OUT
=
−10 µA 4.25 V (min)
OUT
=
1.6 mA 0.4 V (max)
OUT
Limit
(Note 8)
(Limits)
Units
AC Electrical Characteristics
The following specifications apply for V
nected to ground through a 14.0 kΩ resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface
limits apply for T
Symbol Parameter Conditions
=
=
T
A
T
J
MIN
to T
+
MAX
=
+5V, t
=
=
t
r
f
; all other limits T
20 ns, V
=
A
=
5V, V
REF(+)
=
T
+25˚C.
J
=
GND, and Speed Adjust pin con-
REF(−)
Typical
(Note 7)
Limit
(Note 8)
Units
(Limits)
Mode 1 Conversion Time
t
CONV
t
CRD
t
ACC1
t
ACC2
t
SH
t
1H,t0H
t
INTH
t
P
t
MS
t
MH
C
VIN
C
OUT
C
IN
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.OperatingRatings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits, however.For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditons.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
the maximum derated power dissipation will be reached only during fault conditions. For these devices, T
tables below:
from Rising Edge of S /H
to Falling Edge of INT
Mode 2 Conversion Time 470 610 ns (max)
=
1k, C
=
100 pF
L
=
100 pF
L
(Figure 1 )
=
10 pF
L
; (Note 9) 150 ns (max)
Access Time (Delay from Falling
Mode 1; C
Edge of RD to Output Valid)
Access Time (Delay from Falling
Mode 2; C
Edge of RD to Output Valid)
Minimum Sample Time Mode 1
TRI-STATE Control (Delay
from Rising Edge of RD
R
L
to High-Z State)
Delay from Rising Edge of RD
to Rising Edge of INT
=
C
100 pF
L
Delay from End of Conversion
to Next Conversion
Multiplexer Control Setup Time 10 75 ns (max)
Multiplexer Hold Time 10 40 ns (max)
Analog Input Capacitance 35 pF (max)
Logic Output Capacitance 5 pF (max)
Logic Input Capacitance 5 pF (max)
) at any pin exceeds the power supply rails (V
IN
=
(T
D
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
JMAX−TA
IN
<
GND or V
>
V+) the absolute value of current at that pin should be limited
IN
JMAX
JMAX
360 466 ns (max)
30 50 ns (max)
475 616 ns (max)
30 60 ns (max)
25 50 ns (max)
50 ns (max)
, θJAand the ambient temperature, TA. The maximum
for a board-mounted device can be found from the
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Page 6
AC Electrical Characteristics (Continued)
Part θJA(˚C/W)
ADC10662CIWM 82
ADC10664CIWM 78
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals represent most likely parametric norm.
Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if t
Note 10: THD, SNR, and ENOB are tested in Mode 1. Measuring these quantities in Mode 2 yields similar values.
is shorter than the value specified. See curves of Accuracy vs tSH.
SH
Typical Performance Characteristics
Zero (Offset) Error
vs Reference Voltage
Digital Supply Current
vs Temperature
Conversion Time vs
Speed-Up Resistor
DS011192-14
DS011192-17
Linearity Error
vs Reference Voltage
Conversion Time
vs Temperature
Conversion Time vs
Speed-Up Resistor
DS011192-15
DS011192-18
Analog Supply Current
vs Temperature
DS011192-16
Conversion Time
vs Temperature
DS011192-19
Spectral Response with
100 kHz Sine Wave Input
DS011192-20
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DS011192-21
DS011192-22
Page 7
Typical Performance Characteristics (Continued)
Spectral Response with
100 kHz Sine Wave Input
DS011192-23
Linearity Change vs
Speed-Up Resistor
Signal-to-Noise + THD Ratio
vs Signal Frequency
Linearity Error Change
vs Sample Time
DS011192-26
TRI-STATE Test Circuits and Waveforms
DS011192-24
Linearity Change
vs Speed-Up Resistor
DS011192-25
DS011192-27
DS011192-3
DS011192-5
DS011192-4
DS011192-6
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Page 8
Timing Diagrams
FIGURE 1. Mode 1. The conversion time (t
) is set by the internal timer.
CONV
DS011192-7
FIGURE 2. Mode 2 (RD Mode). The conversion time (t
sampling time and is determined by the internal timer.
Functional Description
The ADC10662 and ADC10664 digitize an analog input signal to 10 bits accuracy by performing two lower-resolution
“flash” conversions. The first flash conversion provides the
six most significant bits (MSBs) of data, and the second flash
conversion provides the four least significant bits LSBs).
Figure 3
is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the bottom of the string of resistors are 16 resistors, each of which
has a value 1/1024 the resistance of the whole resistor
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DS011192-8
) includes the
CRD
string. These lower 16 resistors (the LSB Ladder) therefore
have a voltage drop of 16/1024, or 1/64 of the total reference
voltage (V
resistor string is made up of eight groups of eight resistors
REF+−VREF−
connected in series. These comprise the MSB Ladder. Each
section of the MSB Ladder has
) across them. The remainder of the
1
⁄8of the total reference voltage across it, and each of the LSB resistors has 1/64 of the
total reference voltage across it. Tap points across these resistors can be connected, in groups of sixteen, to the sixteen
comparators at the right of the diagram.
Page 9
Functional Description (Continued)
On the left side of the diagram is a string of seven resistors
connected between V
pare the input voltage with the tap voltages on this resistor
string to provide a low-resolution “estimate” of the input voltage. This estimate is then used to control the multiplexer that
connects the MSB Ladder to the sixteen comparators on the
right. Note that the comparators on the left needn’t be very
accurate; they simply provide an estimate of the input voltage. Only the sixteen comparators on the right and the six on
the left are necessary to perform the initial six-bit flash conversion, instead of the 64 comparators that would be required using conventional half-flash methods.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB Ladder tap points will be connected to the sixteen comparators
on the right. For example, assume that the estimator determines that V
timator decoder will instruct the comparator MUX to connect
is between 11/16 and 13/16 of V
IN
the 16 comparators to the taps on the MSB ladder between
10/16 and 14/16 of V
form the first flash conversion. Note that since the compara-
and V
REF+
. The 16 comparators will then per-
REF
. Six comparators com-
REF−
REF
. The es-
tors are connected to ladder voltages that extend beyond the
range indicated by the estimator circuit, errors in the estimator as large as 1/16 of the reference voltage (64 LSBs) will
be corrected. This first flash conversion produces the six
most significant bits of data — four bits in the flash itself, and
2 bits in the estimator.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 10-bit
result is latched.
Note that the sixteen comparators used in the first flash conversion are reused for the second flash. Thus, the multistep
conversion technique used in theADC10662 andADC10664
needs only a small fraction of the number of comparators
that would be required for a traditional flash converter, and
far fewer than would be used in a conventional half-flash approach. This allows the ADC10662 and ADC10664 to perform high-speed conversions without excessive power drain.
FIGURE 3. Block Diagram of the Multistep Converter Architecture
Applications Information
1.0 MODES OF OPERATION
The ADC10662 and ADC10664 have two basic digital interface modes.
the two modes. The ADC10662 and ADC10664 have input
multiplexers that are controlled by the logic levels on pins S
and S1when S /H goes low.
how the input channnels are assigned.
Figure 1
and
Figure 2
are timing diagrams for
Table1
is a truth table showing
DS011192-12
Mode 1
In this mode, the S /H pin controls the start of conversion.
S/H is pulled low for a minimum of 150 ns. This causes the
comparators in the “coarse” flash converter to become active. When S /H goes high, the result of the coarse conver-
0
sion is latched and the “fine” conversion begins. After 360 ns
(typical), INT goes low, indicating that the conversion results
are latched and can be read by pulling RD low. Note that CS
must be low to enable S /H or RD. CS is internally “ANDed”
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Page 10
Applications Information (Continued)
with S /H and RD; the input voltage is sampled when CS and
S /H are low, and data is read when CS and RD are low.INT
is reset high on the rising edge of RD.
TABLE 1. Input Multiplexer Programming
S
1
00V
01V
10V
11V
TABLE 2. Input Multiplexer Programming
S
0
0V
1V
Mode 2
In Mode 2, also called “RD mode”, the S /H and RD pins are
tied together. A conversion is initiated by pulling both pins
low. The A/D converter samples the input voltage and
causes the coarse comparators to become active. An internal timer then terminates the coarse conversion and begins
the fine conversion. 470 ns (typical) after S /H and RD are
pulled low, INT goes low, indicating that the conversion is
completed. Approximately 20 ns later the data appearing on
the TRI-STATE output pins will be valid. Note that data will
appear on these pins throughout the conversion, but until
INT goes low the data at the output pins will be the result of
the previous conversion.
2.0 REFERENCE CONSIDERATIONS
The ADC10662 and ADC10664 each have two reference inputs. These inputs, V
and define the zero to full-scale range of the input signal.
The reference inputs can be connected to span the entire
supply voltage range (V
metric applications, or they can be connected to different
voltages (as long as they are between ground and V
when other input spans are required. Reducing the overall
V
span to less than 5V increases the sensitivity of the
REF
converter (e.g., if V
however, that linearity and offset errors become larger when
lower reference voltages are used. See the Typical Performance Curves for more information. For this reason, reference voltages less than 2V are not recommended.
ADC10664
S
0
Channel
IN0
IN1
IN2
IN3
ADC10662
Channel
IN0
IN1
and V
REF+
REF−
=
2V,then 1 LSB=1.953 mV). Note,
REF
, are fully differential
REF−
=
0V, V
REF+
=
V
CC
) for ratio-
CC
In most applications, V
ground, but it is often useful to have an input span that is off-
will simply be connected to
REF−
set from ground. This situation is easily accommodated by
the reference configuration used in the ADC10662 and
ADC10664. V
ground as long as the voltage source connected to this pin is
capable of sinking the converter’s reference current (12.5
@
mA Max
other than ground, bypass it with multiple capacitors.
can be connected to a voltage other than
REF−
=
V
5V). If V
REF
is connected to a voltage
REF−
Since the resistance between the two reference inputs can
be as low as 400Ω, the voltage source driving the reference
inputs should have low output impedance. Any noise on either reference input is a potential cause of conversion errors,
so each of these pins must be supplied with a clean, low
noise voltage source. Each reference pin should be bypassed with a 10 µF tantalum and a 0.1 µF ceramic.
3.0 THE ANALOG INPUT
The ADC10662 and ADC10664 sample the analog input
voltage once every conversion cycle. When this happens,
the input is briefly connected to an impedance approximately
equal to 600Ω in series with 35 pF. Short-duration current
spikes can therefore be observed at the analog input during
normal operation. These spikes are normal and do not degrade the converter’s performance.
Large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy. Therefore, only signal sources with output impedances less than
500Ω should be used if rated accuracy is to be achieved at
the minimum sample time (250 ns maximum). If the sampling time is increased, the source impedance can be larger.
If a signal source has a high output impedance, its output
should be buffered with an operational amplifier. The operational amplifier’s output should be well-behaved when driving
a switched 35 pF/600Ω load. Any ringing or voltage shifts at
the op amp’s output during the sampling period can result in
conversion errors.
Correct conversion results will be obtained for input voltages
greater than GND − 50 mV and less than V
allow the signal source to drive the analog input pin more
than 300 mV higher than AV
mV lower than GND. If an analog input pin is forced beyond
and DVCC, or more than 300
CC
these voltages, the current flowing through the pin should be
limited to 5 mA or less to avoid permanent damage to the IC.
The sum of all the overdrive currents into all pins must be
less than 20 mA. When the input signal is expected to extend
)
more than 300 mV beyond the power supply limits, some
sourt of protection scheme should be used.A simple network
using diodes and resistors is shown in
Figure 4
+
+ 50 mV. Do not
.
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Page 11
Applications Information (Continued)
DS011192-13
FIGURE 4. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. If V
is not grounded, it should also be bypassed to analog ground using multiple capacitors (see 5.0 “Power Supply
Considerations”). AGND and DGND should be at the same potential. V
4.0 INHERENT SAMPLE-AND-HOLD
Because the ADC10662 and ADC10664 sample the input
signal once during each conversion, they are capable of
measuring relatively fast input signals without the help of an
external sample-hold. In a non-sampling
successive-approximation A/D converter, regardless of
±
speed, the input signal must be stable to better than
1/2
LSB during each conversion cycle or significant errors will
result. Consequently, even for many relatively slow input signals, the signals must be externally sampled and held constant during each conversion if a SAR with no internal
sample-and-hold is used.
Because they incorporate a direct sample/hold control input,
the ADC10662 and ADC10664 are suitable for use in
DSP-based systems. The S /H input allows synchronization
of the A/D converter to the DSP system’s sampling rate and
to other ADC10662s, andADC10664s.
The ADC10662 and ADC10664 can perform accurate conversions of input signals with frequency components from
DC to over 250 kHz.
5.0 POWER SUPPLY CONSIDERATIONS
The ADC10662 and ADC10664 are designed to operate
from a +5V (nominal) power supply. There are two supply
pins, AV
bypass capacitors for the analog and digital portions of the
and DVCC. These pins allow separate external
CC
circuit. To guarantee accurate conversions, the two supply
pins should be connected to the same voltage source, and
each should be bypassed with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor. Depending on the
circuit board layout and other system considerations, more
bypassing may be necessary.
The ADC10662 and ADC10664 have separate analog and
digital ground pins for separate bypassing of the analog and
digital supplies. Their ground pins should be connected to
the same potential, and all grounds should be “clean” and
free of noise.
In systems with multiple power supplies, careful attention to
power supply sequencing may be necessary to avoid overdriving inputs. The A/D converter’s power supply pins should
be at the proper voltage before digital or analog signals are
applied to any of the other pins.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC10662 and ADC10664, it is necessary to use appropriate circuit board layout techniques. The analog ground return path should be low-impedance and free of noise from
other parts of the system. Noise from digital circuitry can be
especially troublesome, so digital grounds should always be
separate from analog grounds. For best performance, separate ground planes should be provided for the digital and
analog parts of the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input.Any external component (e.g., a filter capacitor) connected across the converter’s input should
be connected to a very clean ground return point. Grounding
the component at the wrong point will result in reduced conversion accuracy.
7.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but conventional DC integral and differential nonlinearity specifications don’t accurately predict theA/D converter’s performance with AC input signals. The important specifications for AC applications reflect the converter’s ability to
digitize AC signals without significant spectral errors and
without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise ratio (SNR) and total harmonic distortion (THD), are quantitative measures of this capability.
is shown with an input protection network.
IN0
REF−
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Applications Information (Continued)
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform. The resulting spectral plot might look like the ones shown in the
typical performance curves. The large peak is the fundamental frequency, and the noise and distortion components (if
any are present) are visible above and below the fundamental frequency. Harmonic distortion components appear at
whole multiples of the input frequency. Their amplitudes are
combined as the square root of the sum of the squares and
compared to the fundamental amplitude to yield the THD
specification. Guaranteed limits for THD are given in the
table of Electrical Characteristics.
Signal-to-noise ratio is the ratio of the amplitude at the fundamental frequency to the rms value at all other frequencies,
excluding any harmonic distortion components. Guaranteed
limits are given in the Electrical Characteristics table. An alternative definition of signal-to-noise ratio includes the distortion components along with the random noise to yield a
signal-to-noise-plus-distortion ration, or S/(N + D).
The THD and noise performance of the A/D converter will
change with the frequency of the input signal, with more distortion and noise occurring at higher signal frequencies. One
way of describing the A/D’s performance as a function of signal frequency is to make a plot of “effective bits” versus frequency. An ideal A/D converter with no linearity errors or
self-generated noise will have a signal-to-noise ratio equal to
(6.02n + 1.76) dB, where n is the resolution in bits of the A/D
converter. A real A/D converter will have some amount of
noise and distortion, and the effective bits can be found by:
where S/(N + D) is the ratio of signal to noise and distortion,
which can vary with frequency.
As an example, an ADC10662 with a 4.85 V
sine wave input signal will typically have a
, 100 kHz
P-P
signal-to-noise-plus-distortion ratio of 59.2 dB, which is
equivalent to 9.54 effective bits. As the input frequency increases, noise and distortion gradually increase, yielding a
plot of effective bits or S/(N + D) as shown in the typical performance curves.
8.0 SPEED ADJUST
The speed adjust pin is connected to an on-chip current
source that determines the converter’s internal timing. By
connecting a resistor between the speed adjust pin and
ground as shown in
Figure 4
, the internal programming current is increased, which reduces the conversion time. The
ADC10662 andADC10664 are specified and guaranteed for
operation with R
(Mode 2). Smaller resistors will result in faster conversion
times, but linearity will begin to degrade as R
smaller (see curves).
=
14.0 kΩ (Mode 1) or R
SA
SA
SA
=
8.26k
becomes
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Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADC10662CIWM
NS Package Number M24B
Order Number ADC10664CIWM
NS Package Number M28B
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
ADC10662/ADC10664 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National Semiconductor
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Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
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