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ADC1061
10-Bit High-Speed µP-Compatible A/D Converter with
Track/Hold Function
General Description
Using a modified half-flash conversion technique, the 10-bit
ADC1061 CMOS analog-to-digital converter offers very fast
conversion timesyet dissipates a maximum of only 235 mW.
The ADC1061 performs a 10-bit conversion in two
lower-resolution “flashes”, thus yielding a fast A/D without
the cost, power dissipation, and other problems associated
with true flash approaches.
The analog input voltage to theADC1061is tracked andheld
by an internal sampling circuit. Input signals at frequencies
from DC to greater than 160 kHz can therefore be digitized
accurately without the need for an external sample-and-hold
circuit.
For ease of interface to microprocessors, the ADC1061 has
been designed to appear as a memory location or I/O port
without the need for external interface logic.
Features
n 1.8 µs maximum conversion time to 10 bits
n Low power dissipation: 235 mW (maximum)
n Built-in track-and-hold
n No external clock required
n Single +5V supply
n No missing codes over temperature
Applications
n Waveform digitizers
n Disk drives
n Digital signal processor front ends
n Mobile telecommunications
Simplified Block and Connection Diagrams
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DS010559-2
June 1999
ADC1061 10-Bit High-Speed µP-Compatible A/D Converter with Track/Hold Function
© 1999 National Semiconductor Corporation DS010559 www.national.com
Page 2
Simplified Block and Connection Diagrams (Continued)
Ordering Information
Industrial (−40˚C ≤ TA≤ 85˚C) Package
ADC1061CIN N20A
ADC1061CIWM M20B
Pin Descriptions
Symbol Function
DV
CC
,
AV
CC
(1, 6)
These are the digital and analog positive supply voltage inputs. They should always be connected to the
same voltage source, but are brought out separately to allow for separate bypass capacitors. Each
supply pin should be bypassed with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum
capacitor.
INT (2)
This is the active low interrupt output. INT goes low at the end of each conversion, and returns to a high
state following the rising edge of RD .
S/H(3) This is the Sample/Hold control input. When this pin is forced low, it causes the analog input signal to be
sampled and initiates a new conversion.
RD (4)
This is the active low Read control input. When this pin is low, any data present in the ADC1061’s output
registers will be placed on the data bus. In Mode 2, the Read signal must be low until INT goes low. Until
INT goes low, the data at the output pins will be incorrect.
CS (5) This is the active low Chip Select control input. This pin enables the S /H and RD inputs.
V
REF−
,
V
REF+
(7, 9)
These are the reference voltage inputs. They may be placed at any voltage between GND − 50 mV and
V
CC
+ 50 mV, but V
REF+
must be greater than V
REF−
. An input voltage equal to V
REF−
produces an
output code of 0, and an input voltage equal to V
REF+
− 1LSB produces an output code of 1023.
V
IN
(8) This is the analog input pin. The impedance of the source should be less than 500Ω for best accuracy
and conversion speed. To avoid damage to the ADC1061, V
IN
should not be allowed to extend beyond
the power supply voltages by more than 300 mV unless the drive current is limited. For accurate
conversions, V
IN
should not extend more than 50 mV beyond the supply voltages.
GND (10) This is the power supply ground pin. The ground pin should be connected to a “clean” ground reference
point.
DB0–DB9
(11-20)
These are the TRI-STATE output pins.
Dual-In-Line Package
DS010559-1
Top View
Order Number
ADC1061CIN or ADC1061CIWM
See NS Package J20A,
M20B or N20A
www.national.com 2
Page 3
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
+
=
AV
CC
=
DV
CC
) −0.3V to +6V
Voltage at any Input or Output −0.3V to V
+
+0.3V
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4) 875 mW
ESD Susceptibility (Note 5) 1500V
Soldering Information (Note 6)
N Package (10 seconds) 260˚C
J Package (10 seconds) 300˚C
SO Package (Note 6)
Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C
Junction Temperature, T
J
+150˚C
Storage Temperature Range −65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Temperature Range T
MIN
≤ TA≤ T
MAX
ADC1061CIN, ADC1061CIWM −40˚C ≤ TA≤ +85˚C
Supply Voltage Range 4.5V to 5.5V
Converter Characteristics
The following specifications apply for V
+
=
+5V, V
REF(+)
=
5V, and V
REF(−)
=
GND unless otherwise specified. Boldface lim-
its apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions Typical Limit Units
(Note 7) (Note 8) (Limit)
Resolution 10 Bits
Total Unadjusted Error
±
1.0
±
2.0 LSB (Max)
Integral Linearity Error
±
0.3
±
1.5 LSB (Max)
Differential Linearity Error
±
1.0 LSB (Max)
Offset Error
±
0.1
±
1.0 LSB (Max)
Fullscale Error
±
0.5
±
1.0 LSB (Max)
R
REF
Reference Resistance 0.65 0.4 kΩ (Min)
R
REF
Reference Resistance 0.65 0.9 kΩ (Max)
V
REF(+)
V
REF(+)
Input Voltage V++ 0.05 V (Max)
V
REF(−)
V
REF(−)
Input Voltage GND − 0.05 V (Min)
V
REF(+)
V
REF(+)
Input Voltage V
REF(−)
V (Min)
V
REF(−)
V
REF(−)
Input Voltage V
REF(−)
V (Max)
V
IN
Input Voltage V++ 0.05 V (Max)
V
IN
Input Voltage GND − 0.05 V (Min)
Analog Input Leakage Current CS=V
+
,V
IN
=
V
+
0.01 3 µA (Max)
CS=V
+
,V
IN
=
GND
0.01 −3 µA (Max)
Power Supply Sensitivity V
+
=
5V
±
5
%
±
0.125
±
0.5 LSB
V
REF
=
4.75V
DC Electrical Characteristics
The following specifications apply for V
+
=
+5V, V
REF(+)
=
5V, and V
REF(−)
=
GND unless otherwise specified. Boldface lim-
its apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions Typical Limit Units
(Note 7) (Note 8) (Limits)
V
IN(1)
Logical “1” Input Voltage V
+
=
5.25V 2.0 V (Min)
V
IN(0)
Logical “0” Input Voltage V
+
=
4.75V 0.8 V (Max)
I
IN(1)
Logical “1” Input Current V
IN(1)
=
5V 0.005 1.0 µA (Max)
I
IN(0)
Logical “0” Input Current V
IN(0)
=
0V −0.005 −1.0 µA (Max)
V
OUT(1)
Logical “1” Output Voltage V
+
=
4.75V I
OUT
=
−360 µA 2.4 V (Min)
V
+
=
4.75V I
OUT
=
−10 µA 4.5 V (Min)
V
OUT(0)
Logical “0” Output Voltage V
+
=
4.75V I
OUT
=
1.6 mA 0.4 V (Max)
I
OUT
TRI-STATE®Output Current V
OUT
=
5V 0.1 50 µA (Max)
V
OUT
=
0V −0.1 −50 µA (Max)
DI
CC
DVCCSupply Current CS=WR=RD=0 0.1 2 mA (Max)
AI
CC
AVCCSupply Current CS=WR=RD=0 30 45 mA (Max)
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AC Electrical Characteristics
The following specifications apply for V
+
=
+5V, t
r
=
t
f
=
20 ns, V
REF(+)
=
5V, and V
REF(−)
=
GND unless otherwise specified.
Boldface limits apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions Typical Limit Units
(Note 7) (Note 8) (Limits)
t
CONV
Conversion Time from Rising Edge Mode 1 1.2 1.8 µs (Max)
of S /H to Falling Edge of INT
t
CRD
Conversion Time for MODE 2 Mode 2 1.8 2.4 µs (Max)
(RD Mode)
t
ACC1
Access Time (Delay from Falling Mode 1; C
L
=
100 pF 20 50 ns (Max)
Edge of RD to Output Valid)
t
ACC2
Access Time (Delay from Falling Mode 2; C
L
=
100 pF t
CRD
+50 ns (Max)
Edge of RD to Output Valid)
t
SH
Minimum Sample Time (
Figure 1
); (Note 9) 250 ns (Max)
t
1H,t0H
TRI-STATE Control (Delay from Rising R
L
=
1k, C
L
=
10 pF 20 50 ns (Max)
Edge of RD to High-Z State)
t
INTH
Delay from Rising Edge of RD 10 50 ns (Max)
to Rising Edge of INT
t
ID
Delay from INT to Output Valid C
L
=
100 pF 20 50 ns (Max)
t
P
Delay from End of Conversion 10 20 ns (Max)
to Next Conversion
SR Slew Rate for Correct 2.5 V/µs
Track-and-Hold Operation
C
VIN
Analog Input Capacitance 35 pF
C
OUT
Logic Output Capacitance 5 pF
C
IN
Logic Input Capacitance 5 pF
Note 1: AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamageto the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
V−or V
IN
>
V+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
, θJAand the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is P
D
=
(T
JMAX−TA
)/θJAor the number given in theAbsolute Maximum Ratings, whichever is lower. For this device,
T
JMAX
=
150˚C, and the typical thermal resistance (θ
JA
) when board mounted is 47˚C/W for the plastic (N) package, 85˚C/W for the ceramic (J) package, and 65˚C/W
for the small outline (WM) package.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: SeeAN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at 25˚C and represent most likely parametric norm.
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if t
SH
is shorter than the value specified.
TRI-STATE Test Circuits and Waveforms
DS010559-3
DS010559-4
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TRI-STATE Test Circuits and Waveforms (Continued)
Timing Diagrams
DS010559-5
DS010559-6
DS010559-7
FIGURE 1. Mode 1. The conversion time (t
CONV
) is determined by the internal timer.
DS010559-8
FIGURE 2. Mode 2 (RD Mode). The conversion time (t
CRD
) includes
the sampling time, and is determined by the internal timer.
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Typical Performance Characteristics
Functional Description
The ADC1061 digitizes an analog input signal to 10 bits accuracy by performing two lower-resolution “flash” conversions. The first flash conversion provides the six most significant bits (MSBs) of data, and the second flash conversion
provides the four least significant bits (LSBs).
Figure 3
is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the bottom of the string of resistors are 16 resistors, each of which
has a value 1/1024th the resistance of the whole resistor
string. These lower 16 resistors (the LSB Ladder) therefore
have a voltage drop of 16/1024, or 1/64th of the total reference voltage (V
REF+
− VREF−) across them. The remainder
of the resistor string is made upof eight groups of eight resistors connected in series. These comprise the MSB Ladder.
Each section of the MSB Ladder has 1/8th of the total reference voltage across it, and each of the MSB resistors has
1/64th of the total reference voltage across it. Tap points
across all of these resistors can be connected, in groups, to
the sixteen comparators at the right of the diagram.
On the left side of the diagram is a string of seven resistors
connected between V
REF+−VREF−
. Six comparators compare the input voltage with the tap voltages on the resistor
string to provide an estimate of the input voltage. This esti-
mate is then used to controlthe multiplexer that connects the
MSB Ladder to the sixteen comparators on the right. Note
that the comparators on the left needn’t be very accurate;
they simply provide an estimate of the input voltage. Onlythe
sixteen comparators on the right and the six on the left are
necessary to perform the initial six-bit flash conversion, instead of the 64 comparators that would be required using
conventional half-flash methods.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB Ladder tap points will be connected to the sixteen comparators
on the right. For example, assume that the estimator determines that V
IN
is between 11/16and 13/16 of VREF. The estimator decoder will instruct the comparator mux to connect
the 16 comparators to the taps on the MSB Ladder between
10/16 and 14/16 of VREF.The 16 comparators will then perform the first flash conversion. Note that since the comparators are connected to Ladder voltages that extend beyond
the range indicated by the estimator circuit, errors in the estimator as large as 1/16 of the reference voltage (64 LSBs)
will be corrected. This first flash conversion produces the six
most significant bits of data.
Zero (Offset) Error
vs Reference Voltage
DS010559-9
Linearity Error vs
Reference Voltage
DS010559-10
Mode 1 Conversion Time
vs Temperature
DS010559-11
Mode 2 Conversion Time
vs Temperature
DS010559-12
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Page 7
Functional Description (Continued)
The remaining four LSBs may now be determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second flash
conversion is then decoded, and the full 10-bit result is
latched.
Note that the sixteen comparators used in the first flash conversion are reused for the second flash. Thus, the half-flash
conversion techniques used in the ADC1061 needs only a
small fraction of the number of comparators that would berequired for a traditional flash converter, and far fewer than
would be used in a conventional half-flash approach. This allows the ADC1061 to perform high-speed conversions without excessive power drain.
Applications Information
1.0 Modes of Operation
The ADC1061 has two basic digital interface modes. These
are illustrated in
Figure 1
and
Figure 2
.
MODE 1
In this mode, the S /H pin controls the start of conversion.
S /H is pulled low for a minimum of 250 ns. This causes the
comparators in the “coarse” flash converter to become ac-
tive. When S /H goes high, the result of the coarse conversion is latched and the “fine” conversion begins. After approximately 1.2 µs (1.8 µs maximum), INT goes low,
indicating that the conversion results are latched and can be
read by pulling RD low. Note that CS must be low to enable
S /H or RD . CS is internally “ANDed” with the sample and
read control signals; the input voltage is sampled when CS
and S /H are low, and is read when CS and RD are low.
MODE 2
In Mode 2, also called “RD mode”, the S /H and RD pins are
tied together. A conversion is initiated by pulling both pins
low.TheADC1061samples the input voltage and causes the
coarse comparators to become active. An internal timer then
terminates the coarse conversion and begins the fine conversion.
About 1.8 µs (2.4 µs maximum) after S /H and RD are pulled
low,INT goes low, indicating that the conversionis complete.
Approximately 20 ns later the data appearing on the
TRI-STATE output pins will be valid. Note that data will appear on these pins throughout the conversion, but will be
valid only after INT goes low.
DS010559-13
FIGURE 3. Block Diagram of the Modified Half-Flash Converter Architecture
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1.0 Modes of Operation (Continued)
2.0 Reference Considerations
The ADC1061 has two reference inputs. These inputs,
V
REF+
and V
REF−
, are fully differential and define the zero to
full-scale range of the input signal. The reference inputs can
be connected to span the entire supply voltage range (V
REF−
=
0V, V
REF+
=
V
CC
) for ratiometric applications, or they can
be connected to different voltages (as long as they are between ground and V
CC
) when other input spans are required.
Reducing the overall V
REF
span to less than 5V increases
the sensitivity of the converter (e.g., if V
REF
=
2V,then 1LSB
=
1.953 mV). Note, however, that linearity and offset errors
become larger when lower reference voltages are used. See
the Typical Performance Curves for more information. Reference voltages less than 2V are not recommended.
In most applications, V
REF−
will simply be connected to
ground, but it is often useful to have an input span that is offset from ground. This situation is easily accommodated by
the reference configuration used in the ADC1061. V
REF−
can
be connected to a voltage other than ground as long as the
reference for this pin is capable of sinking current. If V
REF−
is
connected to a voltage other than ground, bypass it withmultiple capacitors.
Since the resistance between the two reference inputs can
be as low as 400Ω, the voltage source driving the reference
inputs should have low output impedance. Any noise on either reference input is a potential cause of conversion errors,
so each of these pins must be supplied with a clean, low
noise voltage source. Each reference pin should normally be
bypassed with a 10 µF tantalum and a 0.1 µF ceramic capacitor. More bypassing may be necessary in some systems.
The choice of reference voltage source will depend on the
requirements of the system. In ratiometric data acquisition
systems with a power supply-referenced sensor, the reference inputs are normally connected to V
CC
and GND, and
no reference other than the power supply is necessary. In
absolute measurement systems requiring 10-bit accuracy, a
reference with better than 0.1%accuracy will be necessary.
3.0 The Analog Input
The ADC1061 samples the analog input voltage once every
conversion cycle. When this happens, the input is briefly
connected to an impedance approximately equal to 600Ω in
series with 35 pF. Short-duration current spikes can therefore be observed at the analog input during normal operation. These spikes are normal and do not degrade the convertor’s performance.
Note that large source impedances can slow the charging of
the sampling capacitors and degrade conversion accuracy.
Therefore, only signal sources with output impedances less
than 500Ω should be used if rated accuracy is to be
achieved at the minimum sample time. If the sampling timeis
increased, the source impedance can be larger. If a signal
source has a high output impedance, its output should be
buffered with an operational amplifier. The operational amplifier’s output should be well-behaved when driving a switched
35 pF/600Ω load. Any ringing or voltage shifts at the op
amp’s output during the sampling period can result in conversion errors.
Correct conversion results will be obtained for input voltages
greater than GND − 50 mV and less than V
+
+ 50 mV.Donot
allow the signal source to drive the analog input pin more
than 300 mV higher thanAV
CC
and DVCC, or more than 300
mV lower than GND. If the analog input pin is forced beyond
these voltages, the current flowing through the pin should be
limited to 5 mA or less to avoid permanent damage to the
ADC1061.
4.0 Inherent Sample-and-Hold
Because the ADC1061 samples the input signal once during
each conversion, it is capable of measuring relatively fast input signals without the help of an external sample-hold. In a
conventional successive-approximation A/D converter, regardless of speed, the input signal must be stable
to better than
±
1
⁄2LSB during each conversion cycle or significant errors will result. Consequently, even for many relatively slow input signals, the signals must be externally
sampled and held constant during each conversion.
DS010559-14
FIGURE 4. Typical connection. Note the multiple bypass capacitors on the reference
and power supply pins. If V
REF
− is not grounded, it should also be bypassed to
ground using multiple capacitors (see 5.0 “Power Supply Considerations”).
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4.0 Inherent Sample-and-Hold
(Continued)
The ADC1061 can perform accurate conversions of input
signals at frequencies from DC to greater than 160 kHz without the need for external sampling circuitry.
5.0 Power Supply Considerations
The ADC1061 is designed to operate from a +5V (nominal)
power supply. There are two supply pins, AV
CC
and DVCC.
These pins allow separate external bypass capacitors for the
analog and digital portions of the circuit. To guarantee accurate conversions, the two supply pins should be connected
to the same voltage source, and each should be bypassed
with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. Depending on the circuit board layout and
other system considerations, more bypassing may benecessary.
It is important to ensure that none of the ADC1061’s input or
output pins are ever driven to a voltage more than 300 mV
above AV
CC
and DVCC, or more than 300 mV below GND. If
these voltage limits are exceeded, the overdrive current into
or out of any pin on the ADC1061 must be limited to less
than 5 mA, and no more than 20 mA of overdrive current (all
overdriven pins combined) should flow. In systems with mul-
tiple power supplies, this may require careful attention to
power supply sequencing. The ADC1061’s power supply
pins should be at the proper voltage before signals are applied to any of the other pins.
6.0 Layout and Grounding
In order to ensure fast, accurate conversions from the
ADC1061, it is necessary to use appropriate circuit board
layout techniques. The analog ground return path should be
low-impedance and free of noise from other parts of the system. Noise from digital circuitry can be especially troublesome, so digital grounds should always be separate from
analog grounds. For best performance, separate ground
planes should be provided for the digital and analog parts of
the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a filter capacitor) connected across the converter’s input should
be connected to a very clean ground return point. Grounding
the component at the wrong point will result in reduced conversion accuracy.
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Page 10
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADC1061CIWM
NS Package Number M20B
Order Number ADC1061CIN
NS Package Number N20A
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
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Français Tel: +49(0) 1 80-532 93 58
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Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: sea.support@nsc.com
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
www.national.com
ADC1061 10-Bit High-Speed µP-Compatible A/D Converter with Track/Hold Function
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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