Page 1
January 2000
ADC10221
10-Bit, 15 MSPS, 98 mW A/D Converter with Internal
Sample and Hold
ADC10221 10-Bit, 15 MSPS, 98 mW A/D Converter with Internal Sample and Hold
General Description
The ADC10221 is the first in a family of low power, high performance CMOS analog-to-digital converters. It can digitize
signals to 10 bits resolution at sampling rates up to 20 MSPS
(15 MSPS guaranteed) while consuming a typical 98 mW
from a single 5V supply. Reference force and sense pins allow the user to connect an external reference buffer amplifier
to ensure optimal accuracy. The ADC10221 is guaranteed to
have no missing codes over the full operating temperature
range. The unique two stage architecture achieves 9.2 Effective Bits with a 10MHz input signal and a 20MHz clock frequency. Output formatting is straight binary coding.
To ease interfacing to 3V systems, the digital I/O power pins
of the ADC10221 can be tied to a 3V power source, making
the outputs 3V compatible. When not converting, power consumption can be reduced by pulling the PD (Power Down)
pin high, placing the converter into a low power standby
state, where it typically consumes less than 4 mW. The
ADC10221’s speed, resolution and single supply operation
make it well suited for a variety of applications in video, imaging, communications, multimedia and high speed data acquisition. Low power, single supply operation ideally suit the
ADC10221 for high speed portable applications, and its
speed and resolution are ideal for charge coupled device
(CCD) input systems.
The ADC10221 comes in a space saving 32-pin TQFP and
operates over the industrial (−40˚C ≤ T
ture range.
≤ +85˚C) tempera-
A
Features
n Internal Sample-and-Hold
n Single +5V Operation
n Low Power Standby Mode
n Guaranteed No Missing Codes
n TTL/CMOS or 3V Logic Input/Output Compatible
Key Specifications
n Resolution 10 Bits
n Conversion Rate 20 MSPS (typ)
15 MSPS (min)
n ENOB 10 MHz Input,
20 MHz Clock 9.2 Bits (typ)
n DNL 0.35 LSB (typ)
n Power Consumption 98 mW (typ)
n Low Power Standby Mode
<
4 mW (typ)
Applications
n Digital Video
n Document Scanners
n Medical Imaging
n Electro-Optics
n Plain Paper Copiers
n CCD Imaging
Connection Diagram
DS101038-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101038 www.national.com
Page 2
Ordering Information
ADC10221
Block Diagram
Commercial
(−40˚C ≤ T
ADC10221CIVT TQFP
≤ +85˚C)
A
NS Package
DS101038-2
www.national.com 2
Page 3
Pin Descriptions and Equivalent Circuits
ADC10221
Pin
No.
Symbol Equivalent Circuit Description
Analog I/O
30 V
31 V
32 V
2V
1V
IN
REF
REF
REF
REF−
+
+
−
9 CLK
Analog Input signal to be converted. Conversion
range is V
REF
+
StoV
REF
−
S.
Analog input that goes to the high side of the
F
S
reference ladder of the ADC. This voltage should
+
force V
S to be in the range of 2.3V to 4.0V.
REF
Analog output used to sense the voltage at the top
of the ADC reference ladder.
Analog input that goes to the low side of the
F
S
reference ladder of the ADC. This voltage should
force V
S to be in the range of 1.3V to 3.0V.
REF−
Analog output used to sense the voltage at the
bottom of the ADC reference ladder.
Converter digital clock input. VINis sampled on the
falling edge of CLK input.
8PD
26 OE
14
thru
19
and
D0 -D9
22
thru
25
3, 7,
28
5, 10 V
V
A
D
Power Down input. When this pin is high, the
converter is in the Power Down mode and the data
output pins are in a high impedance state.
Output Enable pin. When this pin and the PD pin
are low, the output data pins are active. When this
pin or the PD pin is high, the output data pins are in
a high impedance state.
Digital Output pins providing the 10 bit conversion
results. D0 is the LSB, D9 is the MSB. Valid data is
present just after the falling edge of the CLK input.
Positive analog supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.
and VDshould have a common supply and be
V
A
separately bypassed with 10µF to 50µF capacitors
in parallel with 0.1µF capacitors.
Positive digital supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.
and VDshould have a common supply and be
V
A
separately bypassed with 10µF to 50µF capacitors
in parallel with 0.1µF capacitors.
www.national.com3
Page 4
Pin Descriptions and Equivalent Circuits (Continued)
ADC10221
Pin
No.
Analog I/O
12, 21 V
4, 27,
29
6, 11 DGND
13, 20 DGND I/O The ground return of the digital output drivers.
Symbol Equivalent Circuit Description
Positive supply pins for the digital output drivers.
I/O
D
AGND
These pins should be connected to a clean, quiet
voltage source of +3V to +5V and be separately
bypassed with 10µF capacitors.
The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC10221 package.
The ground return for the digital supply. AGND and
DGND should be connected together close to the
ADC10221 pacjage.
www.national.com 4
Page 5
ADC10221
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
Soldering Temp., Infrared, 10 sec. (Note 6) 300˚C
Storage Temperature −65˚C to +150˚C
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage (V=V
Voltage on Any I/O Pin −0.3V to (V
=
) 6.5V
V
A
D
or VD) +0.3V)
A
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
=
25˚C See (Note 4)
A
ESD Susceptibility (Note 5)
Human Body Model 1500V
±
25mA
±
50mA
Operating Ratings(Notes 1, 2)
Operating Temperature −40˚C ≤ T
V
Supply Voltage +4.5V to +5.5V
A,VD
V
I/O Supply Voltage +2.7V to 5.5V
D
V
Voltage Range 1.3V to (VA-1.0V)
IN
V
+ Voltage Range 2.3V to (VA-1.0V)
REF
V
− Voltage Range 1.3V to 3.0V
REF
PD, CLK, OE Voltage
−0.3V to + 5.5V
≤ +85˚C
A
Machine Model 200V
Converter Electrical Characteristics
The following specifications apply for V
=
C
20pF, f
L
CLK
=
15 MHz, R
=
S
=
+5.0V
A
25Ω. Boldface limits apply for T
Symbol Parameter Conditions
Static Converter Characteristics
INL Integral Non-Linearity
DNL Differential-Non Linearity
Resolution with No Missing
Codes
Zero Scale Offset Error −6 mV(max)
Full-Scale Error −6 mV(max)
Dynamic Converter Characteristics
=
f
IN
ENOB Effective Number of Bits
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
SNR Signal-to-Noise Ratio
THD Total Harmonic Distortion
SFDR
Spurious Free Dynamic
Range
DG Differential Gain Error f
DP Differential Phase Error f
Overrange Output Code V
Underrange Output Code V
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
IN
=
IN
>
IN
<
IN
BW Full Power Bandwidth 150 MHz
PSRR
Power Supply Rejection
Ratio
Change in Full Scale with 4.5V to
5.5V Supply Change
Reference and Analog Input Characteristics
V
IN
C
IN
I
IN
Analog Input Range
Analog VINInput
Capacitance
Input Leakage Current 10 µA
DC,VD
=
5.0V
DC,VD
=
A
I/O=5.0VDC,V
to T
T
MIN
MAX
+=+3.5VDC,V
REF
: all other limits T
Typical
(Note 8)
±
0.45
±
0.35
1.0 MHz
4.43 MHz
10 MHz, f
CLK
=
20 MHz
1.0 MHz
4.43 MHz
10 MHz, f
CLK
=
20 MHz
1.0 MHz
4.43 MHz
10 MHz, f
CLK
=
20 MHz
1.0 MHz
4.43 MHz
10 MHz, f
CLK
=
20 MHz
1.0 MHz
4.43 MHz
10 MHz, f
4.43 MHz, f
4.43 MHz, f
V
REF
V
REF
=
20 MHz
CLK
=
17.72 MHz 0.5
CLK
=
17.72 MHz 0.5 deg
CLK
+ 1023
− 0
9.5
9.5
9.2
59
59
57
60
60
58
−71
−70
−66
74
72
68
56 dB
5pF
−=+1.5VDC,
REF
=
25˚C(Note 7)
A
Limits
(Note 9)
±
1.0 LSB(max)
±
0.85 LSB(max)
Units
10 Bits
9.0
56
58
−59
Bits(min)
dB(min)
dB(min)
dB(min)
60
1.3
4.0
V(min)
V(max)
Bits
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
%
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Page 6
Converter Electrical Characteristics (Continued)
The following specifications apply for V
=
C
20pF, f
L
ADC10221
CLK
=
15 MHz, R
=
S
=
+5.0V
A
25Ω. Boldface limits apply for T
Symbol Parameter Conditions
Reference and Analog Input Characteristics
R
REF
V
+ Positive Reference Voltage 3.5 4.0 V(max)
REF
−
V
REF
(V
REF
(V
REF
Reference Ladder
Resistance
Negative Reference
Voltage
+) −
Total Reference Voltage 2.0
−)
DC,VD
=
5.0V
DC and Logic Electrical Characteristics
The following specifications apply for V
=
C
20 pF, f
L
CLK
=
15 MHz, R
=
S
=
+5.0V
A
25Ω. Boldface limits apply for T
Symbol Parameter Conditions
CLK, OE, PD, Digital Input Characteristics
V
IH
V
IL
I
IH
I
IL
Logical ″1″ Input Voltage V
Logical ″0″ Input Voltage V
Logical ″1″ Input Current V
Logical ″0″ Input Current V
=
5.5V 2.0 V(min)
D
=
4.5V 1.0 V(max)
D
=
V
IH
=
DGND −10 µA
IL
D00 - D13 Digital Output Characteristics
V
OH
V
OL
I
OZ
I
OS
Logical ″1″ Output
Voltage
Logical ″0″ Output
Voltage
TRI-STATE Output
Current
Output Short Circuit
Current
VDI/O=+ 4.5V, I
I/O=+ 2.7V, I
V
D
VDI/O=+ 4.5V, I
I/O=+ 2.7V, I
V
D
=
V
OUT
=
V
OUT
VDI/O=3V
V
I/O=5V
D
Power Supply Characteristics
I
A
I
+
D
I/O
I
D
P
D
Analog Supply Current
Digital Supply Current
Power Consumption 98 110 mW (max)
PD=LOW, Ref not included
PD=HIGH, Ref not included
PD=LOW, Ref not included
PD=HIGH, Ref not included
DC,VD
D
DGND
V
D
=
+5.0V
OUT
OUT
OUT
OUT
DC,VD
A
DC,VD
=
−0.5 mA
=
−0.5 mA
=
1.6 mA
=
1.6 mA
A
I/O=5.0VDC,V
=
to T
T
MIN
I/O=5.0VDC,V
=
T
MIN
to T
MAX
MAX
+=+3.5VDC,V
REF
: all other limits T
Typical
(Note 8)
1000
REF
=
25˚C(Note 7)
A
Limits
(Note 9)
850
1150
−=+1.5VDC,
1.5 1.3 V(min)
1.0
2.7
+=+3.5VDC,V
REF
: all other limits T
Typical
(Note 8)
(Note 9)
Limits
−=+1.5VDC,
REF
=
25˚C (Note 7)
A
10 µA
4.0
2.4
0.4
0.4
−10
10
±
12 mA
±
25 mA
14.5
16
0.5
5
6
0.2
Units
Ω(min)
Ω(max)
V(min)
V(max)
Units
V(min)
V(min)
V(max)
V(max)
µA
µA
mA(max)
mA(max)
AC Electrical Characteristics
The following specifications apply for V
=
=
t
t
rc
fc
=
25˚C(Note 7)
5 ns, R
S
=
25Ω.C
(data bus loading)=20 pF, Boldface limits apply for T
L
Symbol Parameter Conditions
f
f
t
t
CLK1
CLK2
CH
CL
Maximum Clock Frequency 20 15 MHz(min)
Minimum Clock Frequency 1 MHz(max)
Clock High Time 23 ns(min
Clock Low Time 23 ns(min)
Duty Cycle 50
Pipeliine Delay (Latency) 2.0 Clock Cycles
t
rc,tfc
www.national.com 6
Clock Input Rise and Fall Time 5 ns(max)
=
+5.0V
A
I/O=5.0VDC,V
DC,VD
+=+3.5VDC,V
REF
Typical
(Note 8)
REF
=
T
A
−=+1.5VDC,f
to T
MIN
MAX
Limits
(Note 9)
45
55
=
15 MHz,
CLK
: all other limits T
Units
(Limits)
%
(min)
%
(max)
A
Page 7
AC Electrical Characteristics (Continued)
The following specifications apply for V
=
=
t
t
rc
fc
=
25˚C(Note 7)
5 ns, R
S
=
25Ω.C
(data bus loading)=20 pF, Boldface limits apply for T
L
Symbol Parameter Conditions
t
r,tf
t
OD
t
OH
t
DIS
t
EN
t
VALID
t
AJ
Output Rise and Fall Times 10 ns
Fall of CLK to data valid 20 25 ns(max)
Output Data Hold Time 12 ns
Rising edge of OE to valid data
Falling edge of OE to valid data 1K to V
Data valid time 40 ns
Aperture Jitter
Full Scale Step Response t
Overrange Recovery Time
t
WU
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND=AGND=DGND=0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies ( V
50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
TQFP, θ
device under normal operation will typically be about 110 mW (98 mW quiescent power+2mWreference ladder power +10 mW due to 10 TTL load on each digital
output). The values for maximum power dissipation listed above will be reached only when the ADC10221 is operated in a severe fault condition (e.g. when input or
output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pF discharged through ZERO Ω.
Note 6: See AN450, ″Surface Mounting Methods and Their Effect on Product Reliability″, or the section entitled ″Surface Mount″ found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 500mV beyond the supply rails will not damage this device. However, errors in
the A/D conversion can occur if the input goes above V
is 69˚C/W, so PDMAX = 1,811 mW at 25˚C and 942 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
JA
PD low to 1/2 LSB accurate
conversion (Wake-Up time)
), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 32-pin
JA
=
+5.0V
A
I/O=5.0VDC,V
DC,VD
From output High,
2K to Ground
From output Low,
2K to V
=
r
V
IN
(V
REF
(V
REF
+=+3.5VDC,V
REF
(Note 8)
Typical
REF
=
T
A
−=+1.5VDC,f
to T
MIN
MAX
Limits
(Note 9)
: all other limits T
25 ns
I/O
D
CC
18 ns
25 ns
<
30 ps
10ns 1 conversion
step from
+ +100 mV) to
1 conversion
−)
700 ns
<
AGND or V
IN
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
J
or below AGND by more than 300 mV.
A
>
VAor VD), the current at that pin should be limited to 25 mA. The
IN
CLK
=
15 MHz,
Units
(Limits)
A
ADC10221
DS101038-12
DS101038-11
=
Note 8: Typical figures are at T
Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: When the input signal is between V
the output code will be 000h, or all 0s.
=
T
25˚C, and represent most likely parametric norms.
A
J
+ and (VA+ 300mV), the output code will be 3FFh, or all 1s. When the input signal is between −300 mV and V
REF
DS101038-24
www.national.com7
REF
−,
Page 8
Typical Performance Characteristics V
specified.
ADC10221
Typical INL
INL vs f
CLK
=
=
D
I/O=5V, f
V
D
V
A
=
20MHz, unless otherwise
CLK
INL vs V
A
INL vs Clock Duty Cycle
DNL vs V
A
DS101038-29
DS101038-25
DS101038-38
DS101038-26
Typical DNL
DS101038-39
DNL vs Clock Duty Cycle
DS101038-40
DNL vs f
CLK
SINAD & ENOB vs
Temperature and f
DS101038-27
DS101038-28
IN
DS101038-30
SINAD & ENOB vs V
A
DS101038-31
www.national.com 8
f
CLK
and f
IN
SINAD & ENOB vs
IA+IDvs. Temperature
DS101038-37
DS101038-32
Page 9
Typical Performance Characteristics V
specified. (Continued)
Spectral Response at 20 MSPs
DS101038-35
Specification Definitions
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
APERTURE DELAY See Sampling Delay.
DIFFERENTIAL GAIN ERROR is the percentage difference
between the output amplitudes of a given amplitude small
signal, high frequency sine wave input at two different dc input levels.
DIFFERENTIAL PHASE ERROR is the difference in the output phase of a small signal sine wave input at two different
dc input levels.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio (S/N+D or SINAD). ENOB is defined as (SINAD −1.76) / 6.02.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its 1 MHz value for a full scale input. The test is performed with f
f
. The input frequency at which the output is −3 dB rela-
CLK
tive to the1 MHz input signal is the full power bandwidth.
FULL SCALE (FS) INPUT RANGE of the ADC is the input
range of voltages over which the ADC will digitize that input.
For V
REF
(V
−)=2.00V.
REF
FULL SCALE OFFSET ERROR is a measure of how far the
last code transition is from the ideal 1
and is defined as V
the voltage at which the transitions from code 1022 to 1023
occurs.
FULL SCALE STEP RESPONSE is defined as the time required after V
V
−, and settles sufficiently for the converter to recover
REF
and make a conversion with its rated accuracy.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a line drawn from negative full scale (
positive full scale (1
The deviation of any given code from this straight line is
measured from the center of that code value.
equal to 100 kHz plus integral multiples of
IN
+=3.50V and V
1023
goes from V
IN
1
⁄2LSB below the first code transition) through
1
⁄2LSB above the last code transition).
−=1.50V, FS=(V
REF
−1.5 LSB − V
−toV
REF
1
⁄2LSB below V
+ , where V
REF
+, or V
REF
REF
REF
1023
+) −
REF
+to
+
is
=
=
D
I/O=5V, f
V
D
V
A
=
20MHz, unless otherwise
CLK
OUTPUT DELAY is the time delay after the fall of the input
clock before the data update is present at the output pins.
OUTPUT HOLD TIME is the length of time that the output
data is valid after the fall of the input clock.
OVER RANGE RECOVERY TIME is the time required after
goes from AGND to V
V
IN
+orVINgoes from VAto V
REF
for the converter to recover and make a conversion with its
rated accuracy.
PIPELINE DELAY(LATENCY) is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available by the Pipeline Delay plus the Output Delay after
that sample is taken. New data is available at every clock
cycle, but the data lags the conversion by the pipeline delay.
PSRR (POWER SUPPLY REJECTION RATIO) is the ratio
of the change in dc power supply voltage to the resulting
change in Full Scale Error, expressed in dB.
SAMPLING (APERTURE) DELAY or APERTURE TIME is
that time required after the fall of the clock input for the sampling switch to open. The sample is effectively taken this
amount of time after the fall of the clock input.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the RMS value of the
input signal to the RMS value of all of the other spectral components below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB or dBc, between the RMS values of
the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that
is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic components, to the rms value of the input signal.
ZERO SCALE OFFSET ERROR is the difference between
the ideal input voltage (
1
⁄2LSB) and the actual input voltage
that just causes a transition from an output code of zero to
an output code of one.
REF
ADC10221
−
www.national.com9
Page 10
Timing Diagram
ADC10221
FIGURE 1. ADC10221 Timing Diagram
DS101038-17
FIGURE 2. AC Test Circuit
Functional Description
The ADC10221 maintains excellent dynamic performance
for input signals up to half the clock frequency. The use of an
internal sample-and-hold amplifier (SHA) enables sustained
dynamic performance for signals of input frequency beyond
the clock rate, lowers the converter’s input capacitance and
reduces the number of external components required.
The analog signal at V
by V
+ S and V
REF
25 MSPS. Input voltages below V
put word to consist of all zeroes. Input voltages above V
S will cause the output word to consist of all ones. V
that is within the voltage range set
IN
− S are digitized to ten bits at up to
REF
− S will cause the out-
REF
REF
REF
+S
DS101038-15
DS101038-16
FIGURE 3. tEN,t
has a range of 2.3 to 4.0 Volts,while V
1.3 to 3.0 Volts. V
more positive than V
+ S should always be at least 1.0 Volt
REF
−S.
REF
Test Circuit
DIS
− S has a range of
REF
Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital outputs
2.0 clock cycles plus t
later.The ADC10221 will convert as
OD
long as the clock signal is present at pin 9 and the PD pin is
low.The Output Enable pin (OE), when low,enables the output pins. The digital outputs are in the high impedance state
+
when the OE pin is low or the PD pin is high.
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Page 11
Applications Information
1.0 THE ANALOG INPUT
The analog input of the ADC10221 is a switch (transmission
gate) followed by a switched capacitor amplifier. The capacitance seen at the input changes with the clock level, appearing as about 3 pF when the clock is low, and about 5 pF
when the clock is high. This small change in capacitance can
be reasonably assumed to be a fixed capacitance. Care
should be taken to avoid driving the input beyond the supply
rails, even momentarily, as during power-up.
The CLC409 has been found to be a good device todrive the
ADC10221 because of its low voltage capability, wide bandwidth, low distortion and minimal Differential Gain and Differential Phase. The CLC409 performs best with a feedback resistor of about 100 ohms.
Care should be taken to keep digital noise out of the analog
input circuitry to maintain highest noise performance.
2.0 REFERENCE INPUTS
Note: Throughout this data sheet reference is made to
V
+ and to V
REF
across the reference ladder and are, nominally,V
V
− S, respectively.
REF
−. These refer to the internal voltage
REF
REF
+ S and
Figure 4
shows a simple reference biasing scheme with
minimal components. While this circuit might suffice for
some applications, it does suffer from thermal drift because
the external 750Ω resistor at pins 1 and 2 will have a different temperature coefficient than the on-chip resistors. Also,
the on-chip resistors, while well matched to each other, will
have a large tolerance compared with any external resistors,
causing the value of V
The circuit of
Figure 4
Figure 5
in that both ends of the reference ladder are defined
- to be quite variable.
REF
is an improvement over the circuit of
with reference voltages. This reduces problems of high reference variability and thermal drift, but requires two reference
sources.
In addition to the usual V
REF
+ and V
− reference inputs,
REF
theADC10221 has two sense outputs for precision control of
the ladder voltages. These sense outputs (V
V
− S) compensate for errors due to IR drops between the
REF
REF
+ S and
source of the reference voltages and the ends of the reference ladder itself.
With the addition of two op-amps, the voltages at the top and
bottom of the reference ladder can be forced to the exact
value desired, as shown in
Figure 6
.
ADC10221
FIGURE 4. Simple, low component cournt reference biasing
DS101038-18
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Page 12
Applications Information (Continued)
ADC10221
FIGURE 5. Better low component count reference biasing
The V
+ F and V
REF
− F pins should each be bypassed to
REF
AGND with 10 µF tantalum or electrolytic and 0.1 µF ceramic
capacitors. The circuit of
Figure 6
may be used if it is desired
to obtain precise reference voltages. The LMC6082 in this
circuit was chosen for its low offset voltage, low voltage capability and low cost.
Since the current flowing through the sense lines (those lines
associated with V
+ S and V
REF
− S) is essentially zero,
REF
there is negligible voltage drop across any resistance in series with these sense pins and the voltage at the inverting input of the op-amp accurately represents the voltage at the
top (or bottom) of the ladder. The op-amp drives the force input, forcing the voltage at the ends of the ladder to equal the
voltage at the op-amp’s non-inverting input, plus any offset
voltage. For this reason, op-amps with low V
, such as the
OS
LMC6081 and LMC6082, should be used for this application.
DS101038-19
Voltagesat the reference sense pins (V
+ S and V
REF
REF
−S)
should be within the range specified in the Operating Ratings
table (2.3V to 4.0V for V
+ and 1.3V to 3.0V for V
REF
REF
−).
Any device used to drive the reference pins should be able to
source sufficient current into the V
cient current from the V
− F pin when the ladder is at its
REF
+ F pin and sink suffi-
REF
minimum value of 850 Ohms.
The reference voltage at the top of the ladder (V
REF
+) may
take on values as low as 1.0V above the voltage at the bottom of the ladder (V
The voltage at the bottom of the ladder (V
−) and as high as (VA- 1.0V) Volts.
REF
−) may take on
REF
values as low as 1.3 Volts and as high as 3.0V. However, to
minimize noise effects and ensure accurate conversions, the
total reference voltage range (V
REF
+-V
−) should be a
REF
minimum of 2.0V and a maximum of 2.7V.
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Page 13
Applications Information (Continued)
ADC10221
FIGURE 6. Setting precision reference voltages
3.0 POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A 10
µF to 50 µF tantalum or aluminum electrolytic capacitor
should be placed within an inch (2.5 centimeters) of the A/D
power pins, with a 0.1 µF ceramic chip capacitor placed as
close as possible to each of the converter’s power supply
pins. Leadless chip capacitors are preferred because they
have low lead inductance.
While a single voltage source should be used for the analog
and digital supplies of the ADC10221, these supply pins
should be well isolated from each other to prevent any digital
noise from being coupled to the analog power pins. A choke
or ferrite bead is recommended between the analog and
digital supply lines, with a ceramic capacitor close to the
analog supply pin.
The converter digital supply should not be the supply that is
used for other digital circuitry on the board. It should be the
same supply used for the ADC10221 analog supply.
As is the case with all high speed converters, theADC10221
should be assumed to have little high frequency power supply rejection. A clean analog power source should be used.
No pin should ever have a voltage on it that is in excess of
the supply voltages or below ground, not even on a transient
basis. This can be a problem upon application of power to a
DS101038-20
circuit. Be sure that the supplies to circuits driving the CLK,
PD, OE, analog input and reference pins do notcome up any
faster than does the voltage at the ADC10221 power pins.
4.0 THE ADC10221 CLOCK
Although the ADC10221 is tested and its performance is
guaranteed with a 15 MHz clock, it typically will function with
clock frequencies from 1 MHz to 20 MHz. Performance is
best if the clock rise and fall times are 5 ns or less and if the
clock line is terminated with a series RC of about 100 Ohms
and 47 pF near the clock input pin, as shown in
5.0 LAYOUT AND GROUNDING
Proper routing of all signals and proper ground techniques
are essential to ensure accurate conversion. Separate analog and digital ground planes are required to meet data sheet
limits. The analog ground plane should be low impedance
and free of noise form other parts of the system.
Each bypass capacitor should be located as close to the appropriate converter pin as possible and connected to the pin
and the appropriate ground plane with short traces.The analog input should be isolated from noisy signal traces to avoid
coupling of spurious signals into the input.Any external com-
Figure 6
.
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Page 14
Applications Information (Continued)
ponent (e.g., a filter capacitor) connected between the converter’s input and ground should be connected to a very
ADC10221
clean point in the analog ground return.
Figure 7
power supply routing, ground plane separation, and bypass
capacitor placement. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed on or
over the analog ground plane. All digital circuitry and I/O
lines should be over the digital ground plane.
gives an example of a suitable layout, including
Digital and analog signal lines should never run parallel to
each other in close proximity with each other. They should
only cross each other when absolutely necessary, and then
only at 90˚ angles. Violating this rule can result in digital
noise getting into the input, which degrades accuracy and
dynamic performance (THD, SNR, SINAD).
FIGURE 7. An acceptable layout pattern
DS101038-21
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Page 15
Applications Information (Continued)
6.0 DYNAMIC PERFORMANCE
The ADC10221 is ac tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
ac performance, isolating theADC clock from any digital circuitry should be done with adequate buffers, as with a clock
tree. See
Meeting dynamic specifications is also dependent upon
keeping digital noise out of the input, as mentioned in Sections 1.0 and 5.0.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300mV beyond the supply pins. Exceeding these
limits on even a transient basis can cause faulty or erratic
operation. It is not uncommon for high speed digital circuits
Figure 8
DS101038-22
FIGURE 8. Isolating the ADC clock from digital
circuitry
(e.g., 74F and 74AC devices) to exhibit undershoot that goes
more than a volt below ground. A resistor of 50 to 100Ω in
series with the offending digital input will usually eliminate
the problem.
Care should be taken not to overdrive the inputs of the
ADC10221 (or any device) with a device that is powered
from supplies outside the range of the ADC10221 supply.
Such practice may lead to conversion inaccuracies and even
to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers has to charge for
each conversion, the more instantaneous digital current is
required from V
and DGND. These large charging current
D
spikes can couple into the analog section, degrading dynamic performance. Adequate bypassing and maintaining
separate analog and digital ground planes will reduce this
problem on the board. Buffering the digital data outputs (with
an 74F541, for example) may be necessary if the data bus to
be driven is heavily loaded. Dynamic performance can also
be improved by adding series resistors of 47Ω at each digital
output.
Driving the V
+ F pin or the V
REF
− F pin with devices
REF
that can not source or sink the current required by the
ladder. As mentioned in section 2.0, be careful to see that
any driving devices can source sufficient current into the
V
+ F pin and sink sufficient current from the V
REF
REF
− F pin.
If these pins are not driven with devices than can handle the
required current, they will not be held stable and the converter output will exhibit excessive noise.
Using a clock source with excessive jitter.This will cause
the sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. Simple gates with RC
timing is generally inadequate.
Using the same voltage source for V
logic. As mentioned in Section 3.0, V
power source used by V
, but should be decoupled from VA.
A
and other digital
D
should use the same
D
ADC10221
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Page 16
Physical Dimensions inches (millimeters) unless otherwise noted
32-Lead TQFP Package
Ordering Number ADC10221CIVT
NS Package Number VBE32A
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ADC10221 10-Bit, 15 MSPS, 98 mW A/D Converter with Internal Sample and Hold
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