Page 1
November 1999
ADC10154/ADC10158
10-Bit Plus Sign 4 µs ADCs with 4- or 8-Channel MUX,
Track/Hold and Reference
ADC10154/ADC10158 10-Bit Plus Sign 4 µs ADCs with 4- or 8-Channel MUX, Track/Hold and
Reference
General Description
The ADC10154 and ADC10158 are CMOS 10-bit plus sign
successive approximationA/D converters with versatile analog input multiplexers, track/hold function and a 2.5V
band-gap reference. The 4-channel or 8-channel multiplexers can be software configured for single-ended, differential
or pseudo-differential modes of operation.
The input track/hold is implemented using a capacitive array
and sampled-data comparator.
Resolution can be programmed to be 8-bit, 8-bit plus sign,
10-bit or 10-bit plus sign. Lower-resolution conversions can
be performed faster.
The variable resolution output data word is read in two bytes,
and can be formatted left justified or right justified, high byte
first.
Applications
n Process control
n Instrumentation
n Test equipment
ADC10158 Simplified Block Diagram
Features
n 4- or 8- channel configurable multiplexer
n Analog input track/hold function
n 0V to 5V analog input range with single +5V power
supply
n −5V to +5V analog input voltage range with
supplies
n Fully tested in unipolar (single +5V supply) and bipolar
±
(dual
n Programmable resolution/speed and output data format
n Ratiometric or Absolute voltage reference operation
n No zero or full scale adjustment required
n No missing codes over temperature
n Easy microprocessor interface
5V supplies) operation
±
5V
Key Specifications
n Resolution 10-bit plus sign
n Integral linearity error
n Unipolar power dissipation 33 mW (max)
n Conversion time (10-bit + sign) 4.4 µs (max)
n Conversion time (8-bit) 3.2 µs (max)
n Sampling rate (10-bit + sign) 166 kHz
n Sampling rate (8-bit) 207 kHz
n Band-gap reference 2.5V
±
1 LSB (max)
±
2.0%(max)
DS011225-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011225 www.national.com
Page 2
Connection Diagrams
Dual-in-Line and SO Packages
ADC10154/ADC10158
DS011225-2
Top View
Order Number ADC10154
NS Package Number M24B
Pin Descriptions
+
AV
+
DV
DGND This is the digital ground. All logic levels are re-
−
V
V
REF
V
REF
V
REF
CS
This is the positive analog supply. This pin
should be bypassed with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor to the
system analog ground.
This is the positive digital supply. This supply
pin also needs to be bypassed with 0.1 µF ceramic and 10 µF tantalum capacitors to the
system digital ground. AV
+
and DV+should be
bypassed separately and tied to same power
supply.
ferred to this ground.
This is the negative analogsupply.For unipolar
operation this pin may be tied to the system
analog ground or to a negative supply source.
It should not go above DGND by more than
50 mV. When bipolar operation is required, the
voltage on this pin will limit the analog input’s
negative voltage level. In bipolar operation this
supply pin needs to be bypassed with 0.1 µF
ceramic and 10 µF tantalum capacitors to the
system analog ground.
+
,
These are the positive and negative reference
−
inputs. The voltage difference between V
and V
span.
−
will set the analog input voltage
REF
Out This is the internal band-gap voltage reference
output. For proper operation of the voltage reference, this pin needs to be bypassed with a
330 µF tantalum or electrolytic capacitor.
This is the chip select input. When a logic low
is applied to this pin the WR and RD pins are
enabled.
REF
Dual-in-Line and SO Packages
Top View
Order Number ADC10158
NS Package Numbers
M28B or N28B
RD
This is the read control input. When a logic low
is applied to this pin the digital outputs are enabled and the INT output is reset high.
WR This is the write control input. The rising edge
of the signal applied to this pin selects the multiplexer channel and initiates a conversion.
INT
This is the interrupt output. A logic low at this
output indicates the completion of a conversion.
CLK This is the clock input. The clock frequency di-
rectly controls the duration of the conversion
time (for example, in the 10-bit bipolar mode
=
DB0(MA0)
–DB7 (L/R)
t
C
6/f
CLK
These are the digital data inputs/outputs. DB0
is the least significant bit of the digital output
) and the acquisition time (t
22/f
CLK
).
word; DB7 is the most significant bit in the digital output word (see the Output Data Configuration table). MA0 through MA4 are the digital
inputs for the multiplexer channel selection
(see the Multiplexer Addressing tables). U/S
(Unsigned/Signed), 8/10, (8/10-bit resolution)
+
and L/R (Left/Right justification) are the digital
input bits that set the A/D’s output word format
and resolution (see the Output Data Configuration table). The conversion time is modified by
the chosen resolution (see Electrical AC Characteristics table). The lower the resolution, the
faster the conversion will be.
CH0–CH7 These are the analog input multiplexer chan-
nels. They can be configured as single-ended
inputs, differential input pairs, or
pseudo-differential inputs (see the Multiplexer
Addressing tables for the input polarity
assignments).
DS011225-3
=
A
www.national.com 2
Page 3
Absolute Maximum Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage
+
+
=
AV
(V
Negative Supply Voltage (V
Total Supply Voltage (V
Total Reference Voltage
+
(V
REF
Voltage at Inputs and
Outputs V
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
Package Dissipation at
=
25˚C (Note 5) 500 mW
T
A
ESD Susceptibility (Note 6) 2000V
Soldering Information
N Packages (10 Sec) 260˚C
J Packages (10 Sec) 300˚C
SO Package (Note 7):
Vapor Phase (60 Sec) 215˚C
Infrared (15 Sec) 220˚C
+
=
) 6.5V
−V
REF
DV
−
−
) −6.5V
+−V−
) 13V
) 6.6V
−
− 0.3V to V++ 0.3V
±
±
20 mA
5mA
Storage Temperature
Ceramic DIP Packages
Plastic DIP and SO Packages
−65˚C to +150˚C
−40˚C to +150˚C
Operating Ratings (Notes 2, 3)
Temperature Range T
ADC10154CIWM,
ADC10158CIN,
ADC10158CIWM −40˚C ≤ T
Positive Supply
Voltage
+
+
=
AV
(V
+
=
) 4.5 VDCto 5.5 V
DV
Unipolar Negative
Supply Voltage
−
) DGND
(V
Bipolar Negative
Supply Voltage
−
) −4.5V to −5.5V
(V
+−V−
V
+
V
REF
−
V
REF
V
REF
+
−V
REF
−
(V
REF
AV++ 0.05 VDCto V−− 0.05 V
AV++ 0.05 VDCto V−− 0.05 V
) 0.5 VDCto V
MIN
≤ TA≤ T
≤ +85˚C
A
ADC10154/ADC10158
MAX
DC
11V
DC
DC
+
Electrical Characteristics
The following specifications apply for V
lar operation or V
=
for T
A
Symbol Parameter Conditions Typical
−
=
−5.0 V
to T
MAX
DC
; all other limits T
=
T
T
J
MIN
+
+
=
for bipolar operation, and f
AV
+
=
=
DV
=
=
T
25˚C. (Notes 8, 9, 12)
A
J
+
+ 5.0 V
DC,VREF
=
5.0 MHz unless otherwise specified. Boldface limits apply
CLK
=
5.000 V
(Note 10)
UNIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICS
Resolution 10 + Sign Bits
Unipolar Integral V
Linearity Error V
Unipolar Full-Scale Error V
Unipolar Offset Error V
Unipolar Total Unadjusted V
Error (Note 13) V
Unipolar Power Supply V
Sensitivity V
Offset Error
Full-Scale Error
Integral Linearity Error
=
2.5V
REF
+
=
5.0V
REF
+
=
2.5V
REF
+
=
V
5.0V
REF
+
=
2.5V
REF
+
=
V
5.0V
REF
+
=
2.5V
REF
+
=
5.0V
REF
+
=
±
%
10
+5V
+
=
4.5V
REF
±
0.5 LSB
±
0.5 LSB
±
1 LSB
±
1.5 LSB
±
0.25
±
0.25
±
0.25 LSB
+
BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICS
Resolution 10 + Sign Bits
+
Bipolar Integral V
REF
=
5.0V
Linearity Error
+
Bipolar Full-Scale Error V
REF
=
5.0V
DC,VREF
−
=
GND, V
−
=
CIN and CIWM Units
Suffixes
Limits
(Note 11)
±
1 LSB (Max)
±
1.5 LSB (Max)
±
2 LSB (Max)
±
2.5 LSB (Max)
±
1 LSB (Max)
±
1 LSB (Max)
±
1 LSB (Max)
±
1.25 LSB (Max)
GND for unipo-
(Limit)
www.national.com3
Page 4
Electrical Characteristics (Continued)
+
+
The following specifications apply for V
lar operation or V
=
for T
A
−
=
−5.0 V
=
T
to T
T
J
MIN
for bipolar operation, and f
DC
; all other limits T
MAX
=
AV
+
=
=
DV
=
=
T
25˚C. (Notes 8, 9, 12)
A
J
+ 5.0 V
CLK
=
Symbol Parameter Conditions Typical
ADC10154/ADC10158
BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICS
Bipolar Negative Full-Scale V
Error with Positive-Full
Scale Adjusted
Bipolar Offset Error V
Bipolar Total Unadjusted V
Error (Note 13)
Bipolar Power Supply
Sensitivity
Offset Error V
Full-Scale Error V
Integral Linearity Error
Offset Error V
Full-Scale Error V
Integral Linearity Error
UNIPOLAR AND BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICS
Missing Codes 0
DC Common Mode V
Error (Note 14)
Bipolar +5.0V ≥ V
Unipolar +5.0V ≥ V
R
C
V
C
Reference Input Resistance 7 4.5 kΩ (Max)
REF
Reference Input Capacitance 70 pF
REF
Analog Input Voltage (V++0.05) V (Max)
AI
Analog Input Capacitance 30 pF
AI
Off Channel Leakage On Channel=5V −400 −1000 nA (Max)
Current Off Channel=0V
(Note 15) On Channel=0V 400 1000 nA (Max)
+
=
5.0V
REF
+
=
5.0V
REF
+
=
5.0V
REF
+
=
±
%
10
+5V
+
=
4.5V
REF
−
=
±
%
10
−5V
+
=
4.5V
REF
+
−
=
V
IN
IN
=
VINwhere
≥ −5.0V
IN
≥ 0V
IN
Off Channel=5V
+
=
DC,VREF
5.0 MHz unless otherwise specified. Boldface limits apply
5.000 V
(Note 10)
±
0.5
±
0.5
±
0.25 LSB
±
0.25
±
0.25
±
0.25 LSB
±
0.25
±
0.25
DC,VREF
−
=
GND, V
−
=
CIN and CIWM Units
Suffixes
Limits
(Note 11)
±
1.25 LSB (Max)
±
2.5 LSB (Max)
±
3 LSB (Max)
±
2.5 LSB (Max)
±
1.5 LSB (Max)
±
0.75 LSB (Max)
±
0.75 LSB (Max)
±
0.75 LSB (Max)
±
0.5 LSB (Max)
9.5 kΩ (Max)
−
(V
−0.05) V (Min)
GND for unipo-
(Limit)
Electrical Characteristics
The following specifications apply for V
operation or V
=
T
J
Symbol Parameter Conditions Typical Limits
−
=
MIN
to T
−5.0 V
MAX
=
T
for bipolar operation, and f
DC
; all other limits T
+
+
=
=
AV
=
=
T
25˚C. (Notes 8, 9, 12)
A
J
DV
+
=
+ 5.0 V
=
5.0 MHz unless otherwise specified. Boldface limits apply for T
CLK
DC,VREF
+
=
5.000 V
DC,VREF
(Note 10)
−
=
GND, V
(Note 11)
DYNAMIC CONVERTER AND MULTIPLEXER CHARACTERISTICS
=
S/(N+D) Unipolar Signal-to-Noise+ f
Distortion Ratio f
S/(N+D) Bipolar Signal-to-Noise+ f
Distortion Ratio f
www.national.com 4
IN
=
IN
=
IN
=
IN
10 kHz, V
150 kHz, V
10 kHz, V
150 kHz, V
=
4.85 V
IN
IN
IN
IN
p–p
=
4.85 V
=
p-p
±
4.85V 60 dB
=
±
4.85V 58 dB
60 dB
58 dB
−
=
GND for unipolar
Units
(Limit)
A
Page 5
Electrical Characteristics (Continued)
+
+
The following specifications apply for V
operation or V
=
T
J
−
=
MIN
to T
−5.0 V
MAX
=
T
for bipolar operation, and f
DC
; all other limits T
=
=
AV
=
=
T
25˚C. (Notes 8, 9, 12)
A
J
DV
+
=
+ 5.0 V
=
5.0 MHz unless otherwise specified. Boldface limits apply for T
CLK
DC,VREF
+
=
5.000 V
DC,VREF
−
=
Symbol Parameter Conditions Typical Limits
(Note 10)
DYNAMIC CONVERTER AND MULTIPLEXER CHARACTERISTICS
−3 dB Unipolar Full V
=
4.85 V
IN
p–p
200 kHz
Power Bandwidth
=
−3 dB Bipolar Full V
±
4.85V 200 kHz
IN
Power Bandwidth
−
REFERENCE CHARACTERISTICS (Unipolar Operation V
VREFOut Reference Output Voltage 2.5
∆V
/∆t VREFOut Temperature Coefficient 40 ppm/˚C
REF
∆V
/∆ILLoad Regulation Sourcing 0 mA ≤ IL≤ +4 mA 0.003 0.1
REF
Sinking 0 mA ≥ I
Line Regulation 4.5V ≤ V
I
∆V
t
SC
SU
Short Circuit Current VREFOut=0V 14 25 mA (Max)
/∆t Long-Term Stability 200 ppm/1 kHr
REF
Start-Up Time C
=
GND Only)
±
%
1
≥ −1 mA 0.2 0.6
L
+
≤ 5.5V 0.5 6 mV (Max)
=
330 µF 20 ms
L
DIGITAL AND DC CHARACTERISTICS
+
V
V
I
I
V
V
I
+I
−I
IN(1)
IN(0)
OUT
IN(1)
IN(0)
OUT(1)
OUT(0)
SC
SC
Logical “1” Input Voltage V
Logical “0” Input Voltage V
Logical “1” Input Current V
Logical “0” Input Current V
Logical “1” Output Voltage V
Logical “0” Output Voltage V
TRI-STATE®Output Current V
Output Short Circuit Source Current V
Output Short Circuit V
=
5.5V 2.0 V (Min)
+
=
4.5V 0.8 V (Max)
=
5.0V 0.005 2.5 µA (Max)
IN
=
0V −0.005 −2.5 µA (Max)
IN
+
=
4.5V:
=
I
−360 µA 2.4 V (Min)
OUT
=
I
−10 µA 4.25 V (Min)
+
=
4.5V 0.4 V (Max)
=
I
1.6 mA
OUT
=
0V −0.01 −3 µA (Max)
OUT
=
V
5V 0.01 3 µA (Max)
OUT
=
0V −40 −10 mA (Min)
OUT
=
DV
OUT
OUT
+
30 10 mA (Min)
Sink Current
DI+ Digital Supply Current CS=HIGH
CS=HIGH, f
+
AI
Analog Supply Current CS=HIGH 3 4.5 mA (Max)
CS=HIGH, f
−
I
Negative Supply Current CS=HIGH 3.5 4.5 mA (Max)
CS=HIGH, f
+
I
REF
Reference Input Current V
=
5V 0.7 1.1 mA (Max)
REF
CLK
CLK
CLK
=
=
=
0Hz
0Hz
0Hz
0.75 2 mA (Max)
0.15 mA (Max)
3 mA (Max)
3.5 mA (Max)
GND, V
(Note 11)
2.5±2
−
=
GND for unipolar
%
Units
(Limit)
V (Max)
%
/mA (Max)
%
/mA (Max)
ADC10154/ADC10158
A
www.national.com5
Page 6
Electrical Characteristics
The following specifications apply for V
operation or V
=
T
J
−
=
MIN
to T
−5.0 V
MAX
=
T
for bipolar operation, and f
DC
; all other limits T
+
=
=
A
+
=
AV
DV
=
T
25˚C. (Note 16)
J
+
=
+ 5.0 V
=
5.0 MHz unless otherwise specified. Boldface limits apply for T
CLK
DC,VREF
+
=
5.000 V
DC,VREF
−
Symbol Parameter Conditions Typical Limits
(Note 10)
AC CHARACTERISTICS
f
CLK
ADC10154/ADC10158
Clock Frequency 8 5.0 MHz (Max)
10 kHz (Min)
Clock Duty Cycle 20
t
C
Conversion 8-Bit Unipolar Mode 16 1/f
Time f
=
5.0 MHz 3.2 µs (Max)
CLK
8-Bit Bipolar Mode 18 1/f
=
f
5.0 MHz 3.6 µs (Max)
CLK
10-Bit Unipolar Mode 20 1/f
=
f
5.0 MHz 4.0 µs (Max)
CLK
10-Bit Bipolar Mode 22 1/f
=
f
5.0 MHz 4.4 µs (Max)
t
A
t
CR
Acquisition Time 6 1/f
Delay between Falling Edge of 0 5 ns (Min)
CLK
=
f
5.0 MHz 1.2 µs
CLK
CS and Falling Edge of RD
t
RC
Delay betwee Rising Edge 0 5 ns (Min)
RD and Rising Edge of CS
t
CW
Delay between Falling Edge 0 5 ns (Min)
of CS and Falling Edge of WR
t
WC
Delay between Rising Edge 0 5 ns (Min)
of WR and Rising Edge of CS
t
RW
Delay between Falling Edge 0 5 ns (Min)
of RD and Falling Edge of WR
t
W(WR)
t
WS
t
DS
t
DH
t
WR
WR Pulse Width 25 50 ns (Min)
WR High to CLK÷2 Low Set-Up Time 5 ns (Max)
Data Set-Up Time 6 15 ns (Max)
Data Hold Time 0 5 ns (Max)
Delay from Rising Edge 0 5 ns (Min)
of WR to Rising Edge RD
t
ACC
Access Time (Delay from Falling C
=
100 pF 25 45 ns (Max)
L
Edge of RD to Output Data Valid)
tWI,t
RI
Delay from Falling Edge C
=
100 pF 25 40 ns (Max)
L
of WR or RD to Reset of INT
t
INTL
t
1H,t0H
Delay from Falling Edge of CLK÷2to
Falling Edge of INT
TRI-STATE Control (Delay from C
=
L
10 pF, R
40 ns
=
1kΩ 20 35 ns (Max)
L
Rising Edge of RD to Hi-Z State)
t
RR
Delay between Successive 25 50 ns (Min)
RD Pulses
t
P
Delay between Last Rising Edge
of RD and the Next Falling
20 50 ns (Min)
Edge of WR
C
IN
C
OUT
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Capacitance of Logic Inputs 5 pF
Capacitance of Logic Outputs 5 pF
=
GND, V
−
=
(Note 11)
80
GND for unipolar
Units
(Limit)
%
(Min)
%
(Max)
CLK
CLK
CLK
CLK
CLK
A
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Page 7
Electrical Characteristics (Continued)
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: When the input voltage (V
20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
=
150˚C. The typical thermal resistance (θ
T
Jmax
CIJ and CMJ suffixes 49˚C/W, ADC10154 with BIWM and CIWM suffixes 72˚C/W,ADC10158 with BIN and CIN suffixes 59˚C/W,ADC10158with BIJ, CIJ, and CMJ
suffixes 46˚C/W, ADC10158 with BIWM and CIWM suffixes 68˚C/W.
) at any pin exceeds the power supplies (V
IN
=
D
) of these parts when board mounted follow: ADC10154 with BIN and CIN suffixes 65˚C/W, ADC10154 with BIJ,
JA
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
(T
Jmax−TA
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 7: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post-1986 National Semi-
conductor Linear Data Book for other methods of soldering surface mount devices.
Note 8: Two on-chip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below V
one diode drop greater than V
pecially at elevated temperatures, which will cause errors for analog inputs near full-scale. The specification allows 50 mV forward bias of either diode; this means
that as long as the analog V
nel will corrupt the reading of a selected channel. This means that ifAV
.
V
DC
Note 9: A diode exists between AV
+
supply. Be careful during testing at low V+levels (4.5V), as high level analog inputs (5V) can cause an input diode to conduct, es-
does not exceed the supply voltage by more than 50 mV,the output code will be correct. Exceeding this range on an unselected chan-
IN
+
and DV+as shown below.
<
IN
+
and DV+are minimum (4.5 VDC) and V−is a maximum (−4.5 VDC) full scale must be ≤±4.55
>
V−or V
AV+or DV+), the current at that pin should be limited to 5 mA. The
IN
, θJAand the ambient temperature, TA. The maximum
Jmax
DS011225-4
−
supply or
ADC10154/ADC10158
To guarantee accuracy, it is required that the AV+and DV+be connected together to a power supply with separate bypass filter at each V+pin.
DS011225-5
=
=
T
Note 10: Typicals are at T
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
25˚C and represent most likely parametric norm.
J
A
Note 12: One LSB is referenced to 10 bits of resolution.
Note 13: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 14: For DC Common Mode Error the only specification that is measured is offset error.
Note 15: Channel leakage current is measured after the channel selection.
Note 16: All the timing specifications are tested at the TTL logic levels, V
=
0.8V for a falling edge and V
IL
=
2.0V for a rising.
IH
www.national.com7
Page 8
Electrical Characteristics (Continued)
ADC10154/ADC10158
DS011225-6
FIGURE 1. Transfer Characteristic
FIGURE 2. Simplified Error Curve vs Output Code
Ordering Information
Industrial −40˚C ≤ TA≤ 85˚C Package
ADC10154CIWM M24B
ADC10158CIN N28B
ADC10158CIWM M28B
www.national.com 8
DS011225-7
Page 9
Typical Converter Performance Characteristics
ADC10154/ADC10158
Total Positive Supply
Current (DI
+
+AI+)
vs Temperature
Offset Error vs
Reference Voltage
DS011225-27
DS011225-30
Total Positive Power
Supply Current (DI
vs Clock Frequency
Linearity Error
vs Temperature
+
+AI+)
DS011225-28
DS011225-31
Offset Error
vs Temperature
DS011225-29
Linearity Error vs
Reference Voltage
DS011225-32
Linearity Error vs
Clock Frequency
DS011225-33
Spectral Response with
50 kHz Sine Wave
10-Bit Unsigned
Signal-to-Noise + THD Ratio
vs Input Signal Level
DS011225-34
DS011225-35
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Page 10
Typical Reference Performance Characteristics
Load Regulation
ADC10154/ADC10158
Available
Output Current
vs Supply Voltage
DS011225-36
DS011225-39
Line Regulation
(3 Typical Parts)
Output Drift
vs Temperature
(3 Typical Parts)
DS011225-37
DS011225-38
Leakage Current Test Circuit
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DS011225-10
Page 11
TRI-STATE Test Circuits and Waveforms
DS011225-11
DS011225-13
Timing Diagrams
ADC10154/ADC10158
DS011225-12
DS011225-14
DIAGRAM 1. Starting a Conversion with New MUX Channel and Output Configuration
DS011225-15
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Page 12
Timing Diagrams (Continued)
ADC10154/ADC10158
DIAGRAM 2. Starting a Conversion without Changing the MUX Channel or Output Configuration
DS011225-16
DIAGRAM 3. Reading the Conversion Result
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DS011225-17
Page 13
Multiplexer Addressing and Output Data Configuration Tables
TABLE 1. ADC10154 and ADC10158 Output Data Configuration
ADC10154/ADC10158
Output
Resolution Data
Data Format
Control Input Data Bus Output Assignment
8/10
U/S L/R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10-Bits + Sign Right-Justified L L L Sign Sign Sign Sign Sign Sign MSB 9 First Byte Read
8765432LSBSecond Byte Read
10-Bits + Sign Left-Justified L L H Sign MSB 987654First Byte Read
32LSBLLLLLSecond Byte Read
10-Bits Right-Justified L H L LLLLLLMSB9First Byte Read
8765432LSBSecond Byte Read
10-Bits Left-Justified L H H MSB 9876543First Byte Read
2LSBLLLLLLSecond Byte Read
8-Bits + Sign Right-Justified H L L Sign Sign Sign Sign Sign Sign Sign Sign First Byte Read
MSB765432LSBSecond Byte Read
8-Bits + Sign Left-Justified H L H Sign MSB 765432First Byte Read
LSBLLLLLLLSecond Byte Read
8-Bits Right-Justified H H L LLLLLLLLFirst Byte Read
MSB765432LSBSecond Byte Read
8-Bits Left-Justified H H H MSB 765432LSBFirst Byte Read
LLLLLLLLSecond Byte Read
TABLE 2. ADC10158 Multiplexer Addressing
MUX Address CS WR RD Channel Number MUX
MA4 MA3 MA2 MA1 MA0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 V
REF
−
Mode
XLLLLL H+−
XLLLHL H−+
XLLHLL H +−
XLLHHL
L
H − + Differential
XLHLLL H +−
XLHLHL H −+
XLHHLL H +−
XLHHHL H −+
LHLLLL H+ −
LHLLHL H + −
LHLHLL H + −
LHLHHL
L
H + − Single-Ended
LHHLLL H + −
LHHLHL H + −
LHHHLL H + −
LHHHHL H + −
HHLLLL H+ −
HHL LHL H + −
HHLHLL H + −
HHLHHL
L
H + − Pseudo-Differential
HHHL LL H + −
HHHLHL H + −
HHHHLL H +−
XXXXXL
L
L Previous Channel Configuration
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Page 14
Multiplexer Addressing and Output Data Configuration Tables (Continued)
TABLE 3. ADC10154 Multiplexer Addressing
MUX Address CS WR RD Channel Number MUX
MA4 MA3 MA2 MA1 MA0 CH0 CH1 CH2 CH3 V
XXLLLL H+−
XXLLHL
ADC10154/ADC10158
XXLHLL H +−
L
H − + Differential
XXLHHL H −+
XLHLLL H+ −
XLHLHL
L
H + − Single-Ended
XLHHLL H + −
XLHHHL H + −
XHHLLL H+ −
XHHLHL
L
H + − Pseudo-Differential
XHHHLL H +−
XXXXXL
L
L Previous Channel Configuration
REF
−
Mode
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Page 15
Detailed Block Diagram
ADC10154/ADC10158
DS011225-18
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Page 16
1.0 Functional Description
The ADC10154 and ADC10158 use successive approximation to digitize an analog input voltage. Additional logic has
been incorporated in the devicesto allow for the programmability of the resolution, conversion time and digital output format. A capacitive array and a resistive ladder structure are
used in the DAC portion of the A/D converters. The structure
of the DAC allows a very simple switching scheme to provide
ADC10154/ADC10158
a very versatile analog input multiplexer. Also, inherent in
this structure is a sample/hold. A 2.5V CMOS band-gap reference is also provided on the ADC10154 and ADC10158.
1.1 DIGITAL INTERFACE
The ADC10154 and ADC10158 have eight digital outputs
(DB0–DB8) and can be easily interfaced to an 8-bit data
bus. Taking CS and WR low simultaneously will strobe the
data word on the data-bus into the input latch. This word will
be decoded to determine the multiplexer channel selection,
the A/D conversion resolution and the output data format.
The following table shows the input word data-bit assignment.
DB0 through DB4 are assigned to the multiplexer address
data bits zero through four (MA0–MA4).
the multiplexer address assignment. DB5 selects unsigned
or signed (U/S) operation. DB6 selects 8- or 10-bit resolution. DB7 selects left or right justification of the output data.
Refer to
Table 1
for the effect the Control Input Data has on
the digital output word.
The conversion process is started by the rising edge of WR,
which sets the “start conversion” bit inside theADC. If this bit
is set, the converter will start acquiring the input voltage on
the next falling edge of the internal CLK
sition period is 3 CLK
÷
2 periods, or 6 CLK periods. Immedi-
Tables2, 3
÷
2 signal. The acqui-
DS011225-44
describe
ately after the acquisition period the input signal is held and
the actual conversion begins. The number of clocks required
for a conversion is given in the following table:
Conversion Type CLK÷2 CLK
Cycles Cycles (N)
8-Bit 8 16
8-Bit + Sign 9 18
10-Bit 10 20
10-Bit + Sign 11 22
Since the CLK
impossible to know which falling edge of CLK corresponds to
the falling edge of CLK
edge of WR should occur at least t
edge of CLK. If this edge happens to be on the rising edge of
÷
CLK
time. The phase of the CLK
÷
2 signal is internal to the ADC, it is initially
÷
2. For the first conversion, the rising
2, this will add 2 CLK cycles to the total conversion
÷
2 signal can be determined at
ns before any falling
WS
the end of the first conversion, when INT goes low. INT always goes low on the falling edge of the CLK÷2 signal. From
the first falling edge of INT onward, every other falling edge
of CLK will correspond to the falling edge of CLK÷2. With the
phase of CLK
minimized by taking WR high at least t
ing edge of CLK÷2.
÷
2 now known, the conversion time can be
ns before the fall-
WS
Upon completion of the conversion, INT goes low to signal
theA/D conversion result is ready to be read. TakingCS and
RD low will enable the digital output buffer and put byte 1 of
the conversion result on DB0 through DB7. The falling edge
of RD resets the INT output high. Taking CS and RD low a
second time will put byte 2 of the conversion result on
DB7–DB0.
Table1
defines the DB0–DB7 assignment for different Control Input Data. The second read does not have to
be completed before a new conversion is started.
Taking CS, WR and RD low simultaneously will start a conversion without changing the multiplexer channel assignment or output configuration and resolution. The timing diagram in
Figure 3
shows the sequence of events that
implement this function. Refer to Diagrams 1, 2, and 3 in the
Timing Diagrams section for the timing constraints that must
be met.
FIGURE 3. Starting a Conversion without Updating the Channel Configuration, Resolution, or Data Format
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DS011225-19
Page 17
1.0 Functional Description (Continued)
Digital Interface Hints:
Reads and writes can be completely asynchronous to
•
CLK.
In addition to the timing indicated in Diagrams 1–3, CS
•
can be tied low permanently or taken low for entire conversions, eliminating all the CS guardbands (t
tCW,tWC).
If CS is used as shown in Diagrams 1–-3, the CS guard-
•
bands (tCR,tRC,tCW,tWC) between CS and the RD and
WR signals can safely be ignored as long as the following two conditions are met:
1) When initiating a write, CS and WR must be simultaneously low for at least t
“start” conversion” bit will be set on the rising edge of WR
ns (see Diagram 1). The
W(WR)
or CS, whichever is first.
2) When reading data, understand that data will not be valid
until t
data will enter TRI-STATEt1Hns or t0Hns after
ACC
ns after
both
CS and RD go low. The output
or RD goes high (see Diagrams 2 and 3).
1.2 ARCHITECTURE
Before a conversion is started, during the analog input sampling period, the sampled data comparator is zeroed. As the
comparator is being zeroed the channel assigned to be the
positive input is connected to the A/D’s input capacitor. (See
the Digital Interface section for a description of the assignment procedure.) Thischarges the input 32C capacitor of the
DAC to the positive analog input voltage. The switches
shown in the DAC portion of the detailed block diagram are
set for this zeroing/acquisition period. The voltage at the input and output of the comparator are at equilibrium at this
point in time. When the conversion is started the comparator
feedback switches are opened and the 32C input capacitor
is then switched to the assigned negative input voltage.
When the comparator feedback switch opens a fixed amount
of charge is trapped on the common plates of the capacitors.
The voltage at the input of the comparator moves away from
equilibrium when the 32C capacitor is switched to the assigned negative input voltage, causing the output of the comparator to go high (“1”) or low (“0”). The SAR next goes
through an algorithm, controlled by the output state of the
comparator,that redistributes the charge on the capacitor array by switching the voltage on one side of the capacitors in
the array. The objective of the SAR algorithm is to return the
voltage at the input of the comparator as close as possible to
equilibrium.
The switch position information at the completion of the successive approximation routine is a direct representation of
CR,tRC
either
CS
the digital output.This information is then manipulated by the
Digital Output decoder to the programmed format. The reformatted data is then available to be strobed onto the data bus
(DB0–DB7) via the digital output buffers by taking CS and
RD low.
2.0 Applications Information
,
2.1 MULTIPLEXER CONFIGURATION
The design of these converters utilizes a sampled-data comparator structure which allows a differential analog input to
be converted by the successive approximation routine.
The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input terminal.
The polarity of each input terminal or pair of input terminals
being converted indicates which line the converter expects
to be the most positive. If the assigned “+” input is less than
the “−” input the converter responds with an all zeros output
code when configured for unsigned operation. When configured for signed operation the A/D responds with the appropriate output digital code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be
software configured into three modes: differential,
single-ended, or pseudo-differential.
three modes using the 4-channel MUX of the ADC10154.
The eight inputs of the ADC10158 can also be configured in
any of the three modes. The single-ended mode has
CH0–CH3 assigned as the positive input with the negative
input being the V
the ADC10154 channel inputs are grouped in pairs, CH0
−
of the device. In the differential mode,
REF
with CH1 and CH2 with CH3. The polarity assignment of
each channel in the pair is interchangeable. Finally, in the
pseudo-differential mode CH0–CH2 are positive inputs referred to CH3 which is now a pseudo-ground. This
pseudo-ground input can be set to any potential within the input common-mode range of the converter.The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle
ground-referred inputs and true differential inputs as well as
signals referred to a specific voltage.
The analog input voltages for each channel can range from
50 mV below V
−
(typically ground for unipolar operation or
−5V for bipolar operation) to 50 mV above V
(typically 5V) without degrading conversion accuracy. If the
voltage on an unselected channel exceeds these limits it
may corrupt the reading of the selected channel.
Figure 4
shows the
+
=
DV
ADC10154/ADC10158
+
+
=
AV
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Page 18
2.0 Applications Information (Continued)
4 Single-Ended
ADC10154/ADC10158
DS011225-40
3 Pseudo-Differential
DS011225-42
FIGURE 4. Analog Input Multiplexer Options
2.2 REFERENCE CONSIDERATIONS
The voltage difference between the V
defines the analog input voltage span (the difference between V
the programmed resolution) possible output codes apply. In
the pseudo-differential and differential modes the actual voltage applied to V
theAV
When using the single-ended multiplexer mode the voltage
at V
the “zero” reference voltage and, with V
(Max) and VIN(Min)) over which the 2n(where n is
IN
+
and V
+
REF
REF
and V−. Only the difference voltage is of importance.
−
has a dual function. It simultaneously determines
REF
age span.
The value of the voltageon the V
anywhere between AV
+
V
is greater than V
REF
can be used in either ratiometric applications or in systems
+
+ 50 mV and V−− 50 mV, so long as
−
. The ADC10154 and ADC10158
REF
requiring absolute accuracy. The reference pins must be
connected to a voltage source capable of driving the minimum reference input resistance of 4.5 kΩ.
The internal 2.5V bandgap reference in the ADC10154 and
ADC10158 is available as an output on the VREFOut pin. To
ensure optimum performance this output needs to be bypassed to ground with 330 µF aluminum electrolytic or tantalum capacitor. The reference output is unstable with capacitive loads greater than 100 pF and less than 100 µF. Any
capacitive loads ≤100 pF or ≥100 µF will not cause the reference to oscillate. Lower output noise can be obtained by increasing the output capacitance. The 330 µF capacitor will
yield a typical noise floor of 200 nVrms/
+
and V
REF
−
can lie anywhere between
+
, the analog volt-
REF
+
or V
REF
REF
.
− inputs
REF
−
inputs can be
2 Differential
DS011225-41
2 Single Ended and 1 Differential
DS011225-43
The 2.5V reference output is referred to the negative supply
−
pin (V
). Therefore, the voltage at VREFOut will always be
2.5V greater than the voltage applied to V
voltage to V
voltage span of 2.5V. In bipolar operation the voltage at
REF
+
with V
−
tied to V−will yield an analog
REF
VREFOut will be at −2.5V when V
−
. Applying this
−
is tied to −5V. For the
single-ended multiplexer mode the analog input voltage
range will be from −5V to −2.5V. The pseudo-differential and
differential multiplexer modes allow for more flexibility in the
analog input voltage range since the “zero” reference voltage is set by the actual voltage applied to the assigned
negative input pin. The drawback of using the internal reference in the bipolar mode is that any noise on the −5V tied to
−
the V
pin will affect the conversion result. The bandgap reference is specified and tested in unipolar operation with V
tied to the system ground.
Figure 5
In a ratiometric system (
(a)), the analog input voltage is proportional to the voltage used for the A/D reference.
This voltage may also be the system power supply, so V
can also be tied to AV+. This technique relaxes the stablity
REF
requirements of the system reference as the analog input
and A/D reference move together maintaining the same output code for a given input condition.
For absolute accuracy (
Figure 5
(b)), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time- and temperature-stable voltage
source that has excellent initial accuracy. The LM4040 and
LM185 references are suitable for use with the ADC10154
and ADC10158.
−
+
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Page 19
2.0 Applications Information (Continued)
a. Ratiometric Using the Internal Reference
ADC10154/ADC10158
DS011225-21
b. Absolute Using a 4.096V Span
FIGURE 5. Different Reference Configurations
+
−V
REF
−
) can be
=
The minimum value of V
quite small (see Typical Performance Characteristics) to al-
REF(VREF
V
REF
low direct conversion of transducer outputs providing less
than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage
sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals V
REF
/2n).
2.3 THE ANALOG INPUTS
Due to the sampling nature of the analog inputs, at the clock
edges short duration spikes of current will be seen on the selected assigned negative input. Input bypass capacitors
should not be used if the source resistance is greater than
1kΩsince they will average the AC current and cause an ef-
fective DC current to flow through the analog input source resistance. An op amp RC active lowpass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required. Bypass capacitors
may be used when the source impedance is very low without
any degradation in performance.
In a true differential input stage, a signal that is common to
both “+” and “−” inputs is cancelled. For the ADC10154 and
ADC10158, the positive input of a selected channel pair is
only sampled once before the start of a conversion during
DS011225-22
the acquisition time (t
stable during the complete conversion sequence because it
). The negative input needs to be
A
is sampled before each decision in the SAR sequence.
Therefore, any AC common-mode signal present on the analog inputs will not be completely cancelled and will cause
some conversion errors. For a sinusoid common-mode signal this error is:
V
(Max)=V
error
where f
CM
V
is its peak voltage value, and tCis the A/D’s maximum
PEAK
conversion time (t
For example, for a 60 Hz common-mode signal to generate
1
a
⁄4LSB error (1.24 mV) with a 4.5 µs conversion time, its
(2πfCM)(tC)
PEAK
is the frequency of the common-mode signal,
=
C
for 10-bit plus sign resolution).
22/f
CLK
peak value would have to be approximately 731 mV.
2.4 OPTIONAL ADJUSTMENTS
2.4.1 Zero Error
The zero error of the A/D converter relates to the location of
the first riser of the transfer function (see
Figure 1
) and can
be measured by grounding the minus input and applying a
small magnitude positive or negative voltage to the plus input. Zero error is the difference between actual DC input
voltage which is necessary to just cause an output digital
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Page 20
2.0 Applications Information
(Continued)
code transition from 000 0000 0000 to 000 0000 0001
(10-bits plus sign) and the ideal
mV for V
=
+ 5.000V and 10-bit plus sign resolution).
REF
The zero error of the A/D does not require adjustment. If the
minimum analog input voltage value, V
the effetive “zero” voltage can be adjusted to a convenient
ADC10154/ADC10158
value. The converter can be made to output an all zeros digital code for this minimum input voltage by biasing any minus
input to V
pseudo-differential input channel configurations.
(Min). This is useful for either the differential or
IN
2.4.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1
analog full-scale voltage range and then adjusting the V
voltage (V
changing from 011 1111 1110 to 011 1111 1111. In bipolar
REF
=
V
REF
signed operation this only adjusts the positive full scale error.
The negative full-scale error will be as specified in the Electrical Characteristics after a positive full-scale adjustment.
2.4.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A plus input voltage which
equals this desired zero reference plus
LSB is calculated for the desired analog span, using 1 LSB
analog span/2
n
, n being the programmed resolution) is applied to selected plus input and the zero reference voltage at
the corresponding minus input should then be adjusted to
just obtain the 000
HEX
The full-scale adjustment should be made [with the proper
minus input voltage applied] by forcing a voltage to the plus
input which is given by:
where V
V
MIN
and n equals the programmed resolution. Both V
V
MIN
voltage is then adjusted to provide a code change from
3FE
or differential multiplexer mode where V
placed within the V
V
REF
analog input voltage span. This completes the adjustment
equals the high end of the ananlog input range,
MAX
equals the low end (the offsetzero) of the analog range
are ground referred. The V
HEX
+
and V
to 3FF
. Note, when using a pseudo-differential
HEX
+
and V−range, the individual values of
−
do not matter, only the difference sets the
REF
procedure.
2.5 INPUT SAMPLE-AND-HOLD
The ADC10154/8’s sample/hold capacitor is implemented in
the capacitor array.After the channel address is loaded, the
array is switched to sample the selected positive analog input. The rising edge of WR loads the multiplexer addressing
information. The sampling period for the assigned positive
input is maintained for the duration of the acquisition time
(t
), i.e., approximately 6 to 8 clock cycles after the rising
A
edge of WR.
An acquisition window of 6 clock cycles is available to allow
the voltage on the capacitor array to settle to the positive
1
⁄2LSB value (1⁄2LSB=2.44
(Min), is not ground,
IN
1
⁄2LSB down from the desired
+
−
−V
) for a digital output code
REF
1
to 001
code transition.
HEX
REF(VREF
REF
⁄2LSB (where the
=
V
+
REF
and V
analog input voltage. Any change in the analog voltage on a
selected positive input before or after the acquisition window
will not effect the A/D conversion result.
In the simplest case, the array’s acquisition time is determined by the R
stray input capacitance C
and stray (C
source resistance the analog input can be modeled as an
RC network as shown in
(9 kΩ) of the multiplexer switches, the
ON
) capacitance (CL+C
S2
(3.5 pF) and the total array (CL)
S1
Figure 6
=
48 pF). For a large
S2
. The values shown yield an
acquisition time of about 1.1 µs for 10-bit unipolar or 10-bit
plus sign bipolar accuracy with a zero-to-full-scale change in
the input voltage. External source resistance and capacitance will lengthen the acquisition time and should be accounted for. Slowing the clock will lengthen the acquisition
time, thereby allowing a larger external source resistance.
REF
DS011225-23
FIGURE 6. Analog Input Model
The curve “Signal to Noise Ratio vs. Output Frequency” (
ure 7
) gives an indication of the usable bandwidth of the
Fig-
ADC10154/ADC10158. The signal-to-noise ratio of an ideal
A/D is the ratio of the RMS value of the full scale input signal
=
amplitude to the value of the total error amplitude (including
noise) caused by the transfer function of the A/D. An ideal
10-bit plus sign A/D converter with a total unadjusted error of
0 LSB would have a signal-to-noise ratio of about 68 dB,
which can be derived from the equation:
S/N=6.02(n) + 1.76
where S/N is in dB and n is the number of bits.
shows the signal-to-noise ratio vs. input frequency of a typical ADC10154/ADC10158 with
1
⁄2LSB total unadjusted er-
Figure 3
ror. The dotted lines show signal-to-noise ratios for an ideal
(noiseless) 10-bit A/D with 0 LSB error and an A/D with a 1
LSB error.
and
MAX
+
−
−V
)
REF
− are
REF
SNR vs Input Frequency
DS011225-24
FIGURE 7. ADC10154/ADC10158
Signal-to-Noise Ratio vs Input Frequency
The sample-and-hold error specifications are included in the
error and timing specifications of the A/D. The hold step and
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Page 21
2.0 Applications Information
(Continued)
gain error sample/hold specs are included in the ADC10154/
ADC10158’s total unadjusted, linearity, gain and offset error
specifications, while the hold settling time is included in the
Protecting the Analog Inputs
ADC10154/ADC10158
A/D’s maximum conversion time specification. The hold
droop rate can be thought of as being zero since an unlimited amount of time can pass between a conversion and the
reading of data. The data is lost after a new conversion has
been completed.
Diodes are 1N914.
The protection diodes should be able to withstand the output current of the op amp under current limit.
Zero-Shift and Span-Adjust for Signed or Unsigned, Unipolar, Single-Ended
Multiplexer Assignment, Analog Input Range of 2V ≤ V
*1%resistors
IN
DS011225-25
≤ 4.5V
DS011225-26
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Page 22
Physical Dimensions inches (millimeters) unless otherwise noted
ADC10154/ADC10158
Dual-In-Line Package (M)
Order Number ADC10154CIWM
NS Package Number M24B
Dual-In-Line Package (M)
Order Number ADC10158CIWM
NS Package Number M28B
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Page 23
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
ADC10154/ADC10158 10-Bit Plus Sign 4 µs ADCs with 4- or 8-Channel MUX, Track/Hold and
Reference
Order Number ADC10158BIN or ADC10158CIN
Dual-In-Line Package (N)
NS Package Number N28B
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