Page 1
June 1999
ADC10061/ADC10062/ADC10064
10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Using an innovative, patented multistep*conversion technique, the 10-bit ADC10061, ADC10062, and ADC10064
CMOS analog-to-digital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
The ADC10061, ADC10062, and ADC10064 perform a
10-bit conversion in two lower-resolution “flashes”, thus
yielding a fast A/D without the cost, power dissipation, and
other problems associated with true flash approaches. The
ADC10061 is pin-compatible with the ADC1061 but much
faster, thus providing a convenient upgrade path for the
ADC1061.
The analog input voltageto the ADC10061, ADC10062, and
ADC10064 is sampled and held by an internal sampling circuit. Input signals at frequencies from dc to over 200 kHz
can therefore be digitized accurately without the need for an
external sample-and-hold circuit.
The ADC10062 and ADC10064 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns with
only a small increase in linearity error.
For ease of interface to microprocessors, the ADC10061,
ADC10062, and ADC10064 have been designed to appear
as a memory location or I/O port without the need for external interface logic.
*
U.S. Patent Number 4918449
Simplified Block Diagram
Features
n Built-in sample-and-hold
n Single +5V supply
n 1, 2, or 4-input multiplexer options
n No external clock required
n Speed adjust pin for faster conversions (ADC10062
and ADC10064). See ADC10662/4 for high speed
guaranteed performance.
Key Specifications
n Conversion time to 10 bits 600 ns typical,
n 900 ns max over temperature
n Sampling Rate 800 kHz
n Low power dissipation 235 mW (max)
n Total unadjusted error
n No missing codes over temperature
±
1.0 LSB (max)
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
*
ADC10061 Only
**
ADC10062 and ADC10064 Only
***
ADC10064 Only
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011020 www.national.com
DS011020-1
Page 2
Ordering Information
Industrial (−40˚C ≤ TA≤ +85˚C) Package
Connection Diagrams
Top View
ADC10061CIWM M20B Small Outline
ADC10062CIWM M24B Small Outline
ADC10064CIWM M28B Small Outline
DS011020-11
DS011020-12
Top View
Top View
www.national.com 2
DS011020-13
Page 3
Pin Descriptions
DVCC,AVCCThese are the digital and analog positive sup-
INT
S/H This is the Sample/Hold control input. When
RD
CS
S0, S1 On the multiple-input devices (ADC10062 and
V
REF−
V
REF+
ply voltage inputs. They should always be connected to the same voltage source, but are
brought out separately to allow for separate
bypass capacitors. Each supply pin should be
bypassed with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor to
ground.
This is the active low interrupt output. INT
goes low at the end of each conversion, and
returns to a high state following the rising edge
of RD.
this pin is forced low (and CS is low), it causes
the analog input signal to be sampled and initiates a new conversion.
This is the active low Read control input.
When this RD and CS are low, any data
present in the output registers will be placed
on the data bus.
This is the active low Chip Select control input.
When low, this pin enables the RD and S/H
pins.
ADC10064), these pins select the analog input
that will be connected to the A/D during the
conversion. The input is selected based on the
state of S0 and S1 when S/H makes its
High-to-Low transition (See the Timing Diagrams). The ADC10064 includes both S0 and
S1. The ADC10062 includes just S0, and the
ADC10061 includes neither.
,
These are the reference voltage inputs. They
may be placed at any voltage between GND
and V
, but V
CC
V
. An input voltage equal to V
REF−
duces an output code of 0, and an input voltage equal to (V
put code of 1023.
must be greater than
REF+
− 1 LSB) produces an out-
REF+
REF−
pro-
V
,
IN,VIN0
V
IN1,VIN2
V
IN3
These are the analog input pins. The
ADC10061 has one input (V
,
has two inputs (V
ADC10064 has four inputs (V
and V
). The impedance of the source
IN3
should be less than 500Ω for best accuracy
and V
IN0
), the ADC10062
IN
), and the
IN1
IN0,VIN1,VIN2
and conversion speed. For accurate conversions, no input pin (even one that is not selected) should be driven more than 50 mV
GND, AGND,
DGND
above V
These are the power supply ground pins. The
ADC10061 has a single ground pin (GND),
or 50 mV below ground.
CC
and the ADC10062 and ADC10064 have
separate analog and digital ground pins
(AGND and DGND) for separate bypassing of
the analog and digital supplies. The ground
pins should be connected to a stable,
noise-free system ground. For the devices
with two ground pins, both pins should be returned to the same potential.
DB0–DB9 These are the TRI-STATE
®
output pins.
SPEED ADJ (ADC10062 and ADC10064 only). This pin is
normally left unconnected, but by connecting a
resistor between this pin and ground, the conversion time can be reduced. See the Typical
Performance Curves and the table of Electrical Characteristics.
www.national.com3
Page 4
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+
=
Supply Voltage (V
Voltage at Any Input or Output −0.3V to V
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4) 875 mW
ESD Susceptability (Note 5) 2000V
Soldering Information (Note 6)
Vapor Phase (60 Sec)
Infrared (15 Sec)
AV
=
) −0.3V to +6V
DV
CC
CC
+
+ 0.3V
215˚C
220˚C
Storage Temperature Range −65˚C to +150˚C
Junction Temperature 150˚C
Operating Ratings (Notes 1, 2)
Temperature Range T
ADC10061CIWM,
ADC10062CIWM,
ADC10064CIWM −40˚C ≤ T
Supply Voltage Range 4.5V to 5.5V
MIN
≤ TA≤ T
≤ +85˚C
A
MAX
Converter Characteristics
The following specifications apply for V
otherwise specified. Boldface limits apply for T
+
=
+5V, V
A
REF(+)
=
=
+5V, V
REF(−)
=
T
to T
T
J
Min
Max
Symbol Parameter Conditions
Resolution 10 Bits
Integral Linearity Error R
=
18 kΩ
SA
Offset Error
Full-Scale Error
Total Unadjusted Error All Suffixes, R
=
SA
Missing Codes 0 (max)
+
=
Power Supply Sensitivity V
THD Total Harmonic Distortion f
SNR Signal-to-Noise Ratio f
Effective Number of Bits f
R
R
V
V
V
V
V
V
REF
REF
REF(+)
REF(−)
REF(+)
REF(−)
IN
IN
Reference Resistance 650 400 Ω (min)
Reference Resistance 650 900 Ω (max)
V
Input Voltage V++ 0.05 V (max)
REF(+)
V
Input Voltage GND − 0.05 V (min)
REF(−)
V
Input Voltage V
REF(+)
V
Input Voltage V
REF(−)
Input Voltage V++ 0.05 V (max)
Input Voltage GND − 0.05 V (min)
OFF Channel Input Leakage Current
ON Channel Input Leakage Current
±
5V
+
=
±
5V
V
=
10 kHz, 4.85 V
IN
=
f
160 kHz, 4.85 V
IN
=
10 kHz, 4.85 V
IN
=
f
160 kHz, 4.85 V
IN
=
10 kHz, 4.85 V
IN
=
f
160 kHz, 4.85 V
IN
+
CS=V
,V
CS=V+,V
5%,V
10%,V
=
IN
=
IN
REF
REF
+
V
+
V
=
GND, and Speed Adjust pin unconnected unless
; all other limits T
18 kΩ
=
4.5V
=
4.5V
P-P
P-P
P-P
P-P
P-P
P-P
=
A
Typical
(Note 7)
±
0.5
±
0.5
±
1/16
0.06
0.08
61
60
9.6
9.4
0.01
±
1
=
T
+25˚C.
J
Limit
(Note 8)
±
1.0/±1.5 LSB (max)
±
1 LSB (max)
±
1 LSB (max)
±
1.5/±2.0 LSB (max)
3
±
⁄
8
REF(−)
REF(+)
3
−3
Units
(Limit)
LSB
LSB (max)
%
%
dB
dB
Bits
Bits
V (min)
V (max)
µA (max)
µA (max)
DC Electrical Characteristics
The following specifications apply for V
wise specified. Boldface limits apply for T
+
=
+5V, V
=
5V V
REF(+)
=
=
T
A
T
J
MIN
to T
REF(−)
MAX
Symbol Parameter Conditions
+
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
www.national.com 4
Logical “1” Input Voltage V
Logical “0” Input Voltage V
Logical “1” Input Current V
Logical “0” Input Current V
Logical “1” Output Voltage V
=
5.5V 2.0 V (min)
+
=
4.5V 0.8 V (max)
=
5V 0.005 3.0 µA (max)
IN(1)
0V −0.005 −3.0 µA (max)
IN(0)
+
=
4.5V, I
+
=
4.5V, I
V
OUT
OUT
=
=
=
GND, and Speed Adjust pin unconnected unless other-
; all other limits T
−360 µA
−10 µA
=
=
T
+25˚C.
A
J
Typical
(Note 7)
Limit
(Note 8)
2.4
4.25
Units
(Limit)
V (min)
V (min)
Page 5
DC Electrical Characteristics (Continued)
+
The following specifications apply for V
wise specified. Boldface limits apply for T
=
+5V, V
=
A
Symbol Parameter Conditions
V
I
OUT
DI
AI
OUT(0)
CC
CC
Logical “0” Output Voltage V
TRI-STATE®Output Current V
DVCCSupply Current CS=S/H=RD=0, R
AVCCSupply Current CS=S/H=RD=0, R
=
5V V
REF(+)
=
T
T
J
+
=
4.5V, I
=
OUT
=
V
OUT
MIN
5V
0V
REF(−)
to T
; all other limits T
MAX
=
1.6 mA 0.4 V (max)
OUT
CS=S/H=RD=0, R
CS=S/H=RD=0, R
=
GND, and Speed Adjust pin unconnected unless other-
=
∞
SA
=
18 kΩ
SA
=
∞
SA
=
18 kΩ
SA
=
=
T
+25˚C.
A
J
Typical
(Note 7)
0.1
−0.1
1.0
1.0
30
30
Limit
(Note 8)
50
−50
2
45
Units
(Limit)
µA (max)
µA (max)
mA (max)
mA (max)
mA (max)
mA (max)
AC Electrical Characteristics
The following specifications apply for V
nected unless otherwise specified. Boldface limits apply for T
Symbol Parameter Conditions
t
CONV
t
CRD
t
ACC1
t
ACC2
t
SH
t
1H,t0H
t
INTH
t
P
t
MS
t
MH
C
VIN
C
OUT
C
IN
Note 1: Absolute Maximum Ratingsindicatelimitsbeyondwhich damage to the device may occur.Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditons.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
the maximum derated power dissipation will be reached only during fault conditions. For these devices, T
tables below:
Mode 1 Conversion Time from
Rising Edge of S/H to Falling Edge
of INT
Mode 2 Conversion Time R
Access Time (Delay from Falling
Edge of RD to Output Valid)
Access Time (Delay from Falling
Edge of RD to Output Valid)
Minimum Sample Time (
TRI-STATE Control (Delay from
Rising Edge of RD to High-Z State)
Delay from Rising Edge of RD to
Rising Edge of INT
Delay from End of Conversion to
Next Conversion
Multiplexer Control Setup Time 10 75 ns (max)
Multiplexer Hold Time 10 40 ns (max)
Analog Input Capacitance 35 pF (max)
Logic Output Capacitance 5 pF (max)
Logic Input Capacitance 5 pF (max)
) at any pin exceeds the power supply rails (V
IN
+
=
D
+5V, t
=
(T
=
t
r
f
R
SA
R
SA
SA
Mode 2, R
Mode 1; C
Mode 2; C
Figure 1
R
L
C
L
=
20 ns, V
=
∞
=
18k
=
∞
); (Note 8) 250 ns (max)
=
1k, C
=
100 pF
SA
L
L
L
A
=
=
REF(+)
=
T
=
100 pF
100 pF
=
10 pF
J
18k
=
5V, V
=
T
MIN
REF(−)
to T
MAX
(Note 7)
=
GND, and Speed Adjust pin uncon-
; all other limits T
Typical
600
=
A
Limit
(Note 8)
750/900
375
850
1400 ns(max)
530
30 60 ns (max)
900 t
+50 ns (max)
CRD
30 60 ns (max)
25 50 ns (max)
50 ns (max)
<
IN
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
JMAX−TA
GND or V
>
V+) the absolute value of current at that pin should be limited
IN
, θJAand the ambient temperature, TA. The maximum
JMAX
for a board-mounted device can be found from the
JMAX
=
T
+25˚C.
J
Units
(Limit)
ns(max)
ns
ns
Device θJA(˚C/W)
ADC10061CIWM 54
ADC10062CIWM 48
ADC10064CIWM 44
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at +25˚C and represent must likely parametric norm.
www.national.com5
Page 6
AC Electrical Characteristics (Continued)
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if t
is shorter than the value specified. See curves of Accuracy vs tSH.
SH
Typical Performance Characteristics
Zero (Offset) Error
vs Reference Voltage
DS011020-16
Digital Supply Current
vs Temperature
DS011020-19
Conversion Time
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
Linearity Error
vs Reference Voltage
DS011020-17
Conversion Time
vs Temperature
DS011020-20
Conversion Time
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
Analog Supply Current
vs Temperature
DS011020-18
Conversion Time
vs Temperature
DS011020-21
Spectral Response
with100 kHz Sine
Wave Input
DS011020-22
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DS011020-23
DS011020-24
Page 7
Typical Performance Characteristics (Continued)
Spectral Response with
100 kHz Sine Wave Input
DS011020-25
Linearity Change
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
DS011020-28
Signal-to-Noise + THD Ratio
vs Signal Frequency
Linearity Error Change
vs Sample Time
Linearity Change
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
DS011020-26
DS011020-27
DS011020-29
TRI-STATE Test Circuits and Waveforms
DS011020-5
DS011020-7
DS011020-6
DS011020-8
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Page 8
Timing Diagrams
FIGURE 1. Mode 1. The conversion time (t
) is set by the internal timer.
CONV
DS011020-9
FIGURE 2. Mode 2 (RD Mode). The conversion time (t
sampling time and is determined by the internal timer.
Functional Description
The ADC10061, ADC10062 and ADC10064 digitize an analog input signal to 10 bits accuracy by performing two
lower-resolution “flash” conversions. The first flash conversion provides the six most significant bits (MSBs) of data,
and the second flash conversion provides the four least significant bits LSBs).
Figure 3
is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the bottom of the string of resistors are 16 resistors, each of which
www.national.com 8
DS011020-10
) includes the
CRD
has a value 1/1024 the resistance of the whole resistor
string. These lower 16 resistors (the LSB Ladder ) therefore
have a voltage drop of 16/1024, or 1/64 of the total reference
voltage (V
resistor string is made up of eight groups of eight resistors
REF+−VREF−
connected in series. These comprise the MSB Ladder. Each
section of the MSB Ladder has
) across them. The remainder of the
1
⁄8of the total reference volt-
age across it, and each of the LSB resistors has 1/64 of the
Page 9
Functional Description (Continued)
total reference voltage across it. Tap points across these resistors can be connected, in groups of sixteen, to the sixteen
comparators at the right of the diagram.
On the left side of the diagram is a string of seven resistors
connected between V
pare the input voltage with the tap voltages on this resistor
string to provide a low-resolution “estimate” of the input voltage. This estimate is then used to control the multiplexer that
connects the MSB Ladder to the sixteen comparators on the
right. Note that the comparators on the left needn’t be very
accurate; they simply provide an estimate of the input voltage. Only the sixteen comparators on the right and the six on
the left are necessary to perform the initial six-bit flash conversion, instead of the 64 comparators that would be required using conventional half-flash methods.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB Ladder tap points will be connected to the sixteen comparators
on the right. For example, assume that the estimator determines that V
timator decoder will instruct the comparator MUX to connect
is between 11/16 and 13/16 of V
IN
the 16 comparators to the taps on the MSB ladder between
10/16 and 14/16 of V
and V
REF+
. The 16 comparators will then per-
REF
. Six comparators com-
REF−
REF
. The es-
form the first flash conversion. Note that since the comparators are connected to ladder voltages that extend beyond the
range indicated by the estimator circuit, errors in the estimator as large as 1/16 of the reference voltage (64 LSBs) will
be corrected. This first flash conversion produces the six
most significant bits of data— four bits in the flash itself, and
2 bits in the estimator.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 10-bit
result is latched.
Note that the sixteen comparators used in the first flash conversion are reused for the second flash. Thus, the multistep
conversion technique used in the ADC10061, ADC10062,
and ADC10064 needs only a small fraction of the number of
comparators that would be required for a traditional flash
converter, and far fewer than would be used in a conventional half-flash approach. This allows the ADC10061,
ADC10062, and ADC10064 to perform high-speed conversions without excessive power drain.
FIGURE 3. Block Diagram of the Multistep Converter Architecture
Applications Information
1.0 MODES OF OPERATION
The ADC10061, ADC10062, and ADC10064 have two basic
digital interface modes.
grams for the two modes. The ADC10062 and ADC10064
Figure 1
and
Figure 2
are timing dia-
DS011020-14
have input multiplexers that are controlled by the logic levels
on pins S
showing how the input channnels are assigned.
and S1when S/H goes low.
0
Table1
is a truth table
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Page 10
Applications Information (Continued)
Mode 1
In this mode, the S/H pin controls the start of conversion. S/H
is pulled low for a minimum of 250 ns. This causes the comparators in the “coarse” flash converter to become active.
When S/H goes high, the result of the coarse conversion is
latched and the “fine” conversion begins. After 600 ns (typical), INT goes low, indicating that the conversion results are
latched and can be read by pulling RD low. Note that CS
must be low to enable S/H or RD. CS is internally “ANDed”
with S/H and RD; the input voltage is sampled when CS and
S/H are low, and data is read when CS and RD are low. INT
is reset high on the rising edge of RD.
TABLE 1. Input Multiplexer Programming
ADC10064 (a)
S
1
00 V
01 V
10 V
11 V
S
0
0V
1V
Mode 2
In Mode 2, also called “RD mode”, the S/H and RD pins are
tied together. A conversion is initiated by pulling both pins
low. The A/D converter samples the input voltage and
causes the coarse comparators to become active. An internal timer then terminates the coarse conversion and begins
the fine conversion. 850 ns (typical) after S/H and RD are
pull low, INT goes low,indicating that the conversion is completed. Approximately 20 ns later the data appearing on the
TRI-STATE output pins will be valid. Note that data will appear on these pins throughout the conversion, but until INT
goes low the data at the output pins will be the result of the
previous conversion.
2.0 REFERENCE CONSIDERATIONS
The ADC10061, ADC10062, and ADC10064 each have two
reference inputs. These inputs, V
differential and define the zero to full-scale range of the input
signal. The reference inputs can be connected to span the
entire supply voltage range (V
ratiometric applications, or they can be connected to different voltages (as long as they are between ground and V
when other input spans are required. Reducing the overall
V
span to less than 5V increases the sensitivity of the
REF
converter (e.g., if V
S
0
Channel
ADC10062 (b)
Channel
IN0
IN1
and V
REF+
=
0V, V
REF−
=
2V,then 1 LSB=1.953 mV). Note,
REF
REF+
IN0
IN1
IN2
IN3
REF−
, are fully
=
) for
V
CC
CC
however, that linearity and offset errors become larger when
lower reference voltages are used. See the Typical Performance Curves for more information. For this reason, reference voltages less than 2V are not recommended.
In most applications, V
ground, but it is often useful to have an input span that is off-
will simply be connected to
REF−
set from ground. This situation is easily accommodated by
the reference configuration used in the ADC10061,
ADC10062, and ADC10064. V
voltage other than ground as long as the voltage source connected to this pin is capable of sinking the converter’s reference current (12.5 mA Max
nected to a voltage other than ground, bypass it with multiple
can be connected to a
REF−
=
@
V
5V). If V
REF
capacitors.
Since the resistance between the two reference inputs can
be as low as 400Ω, the voltage source driving the reference
inputs should have low output impedance. Any noise on either reference input is a potential cause of conversion errors,
so each of these pins must be supplied with a clean, low
noise voltage source. Each reference pin should be bypassed with a 10 µF tantalum and a 0.1 µF ceramic.
3.0 THE ANALOG INPUT
The ADC10061, ADC10062, and ADC10064 sample the
analog input voltage once every conversion cycle. When this
happens, the input is briefly connected to an impedance approximately equal to 600Ω in series with 35 pF.
Short-duration current spikes can therefore be observed at
the analog input during normal operation. These spikes are
normal and do not degrade the converter’s performance.
Large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy. Therefore, only signal sources with output impedances less than
500Ω should be used if rated accuracy is to be achieved at
the minimum sample time (250 ns maximum). If the sampling time is increased, the source impedance can be larger.
If a signal source has a high output impedance, its output
should be buffered with an operational amplifier. The operational amplifier’s output should be well-behaved when driving
a switched 35 pF/600Ω load. Any ringing or voltage shifts at
the op amp’s output during the sampling period can result in
conversion errors.
Correct conversion results will be obtained for input voltages
greater than GND − 50 mV and less than V
allow the signal source to drive the analog input pin more
than 300 mV higher than AV
300 mV lower than GND. If an analog input pin is forced be-
and DVCC, or more than
CC
yond these voltages, the current flowing through the pin
should be limited to 5 mA or less to avoid permanent damage to the IC. The sum of all the overdrive currents into all
pins must be less than 20 mA. When the input signal is expected to extend more than 300 mV beyond the power sup-
)
ply limits, some sort of protection scheme should be used. A
simple network using diodes and resistors is shown in
Figure 4
.
is con-
REF−
+
+ 50 mV. Do not
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Page 11
Applications Information (Continued)
DS011020-15
FIGURE 4. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. If V
is not grounded, it should also be bypassed to analog ground using multiple capacitors (see 5.0 “Power Supply
Considerations”). AGND and DGND should be at the same potential. V
Pin 17 is normally left open, but optional “speedup” resistor R
4.0 INHERENT SAMPLE-AND-HOLD
Because the ADC10061, ADC10062, and ADC10064
sample the input signal once during each conversion, they
are capable of measuring relatively fast input signals without
the help of an external sample-hold. In a non-sampling
successive-approximation A/D converter, regardless of
±
speed, the input signal must be stable to better than
1/2
LSB during each conversion cycle or significant errors will
result. Consequently, even for many relatively slow input signals, the signals must be externally sampled and held constant during each conversion if a SAR with no internal
sample-and-hold is used.
Because they incorporate a direct sample/hold control input,
the ADC10061, ADC10062, and ADC10064 are suitable for
use in DSP-based systems. The S/H input allows synchronization of the A/D converter to the DSP system’s sampling
rate and to other ADC10061s, ADC10062s, and
ADC10064s.
TheADC10061, ADC10062, and ADC10064 can perform accurate conversions of input signals with frequency components from DC to over 160 kHz.
5.0 POWER SUPPLY CONSIDERATIONS
TheADC10061, ADC10062, and ADC10064 are designed to
operate from a +5V (nominal) power supply. There are two
supply pins, AV
ternal bypass capacitors for the analog and digital portions of
and DVCC. These pins allow separate ex-
CC
the circuit. To guarantee accurate conversions, the two supply pins should be connected to the same voltage source,
and each should be bypassed with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. Depending on
the circuit board layout and other system considerations,
more bypassing may be necessary.
The ADC10061 has a single ground pin, and the ADC10062
and ADC10064 each have separate analog and digital
ground pins for separate bypassing of the analog and digital
supplies. The devices with separate analog and digital
ground pins should have their ground pins connected to the
same potential, and all grounds should be “clean” and free of
noise.
In systems with multiple power supplies, careful attention to
power supply sequencing may be necessary to avoid overdriving inputs. The A/D converter’s power supply pins should
be at the proper voltage before digital or analog signals are
applied to any of the other pins.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC10061, ADC10062, and ADC10064, it is necessary to
use appropriate circuit board layout techniques. The analog
ground return path should be low-impedance and free of
noise from other parts of the system. Noise from digital circuitry can be especially troublesome, so digital grounds
should always be separate from analog grounds. For best
performance, separate ground planes should be provided for
the digital and analog parts of the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a filter capacitor) connected across the converter’s input should
be connected to a very clean ground return point. Grounding
the component at the wrong point will result in reduced conversion accuracy.
7.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but conventional DC integral and differential nonlinearity specifications don’t accurately predict the A/D converter’s performance with AC input signals. The important specifications for AC applications reflect the converter’s ability to
is shown with an input protection network.
IN0
can be used to reduce the conversion time.
SA
REF−
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Applications Information (Continued)
digitize AC signals without significant spectral errors and
without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise ratio (SNR) and total harmonic distortion (THD), are quantitative measures of this capability.
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform. The resulting spectral plot might look like the ones shown in the
typical performance curves. The large peak is the fundamental frequency, and the noise and distortion components (if
any are present) are visible above and below the fundamental frequency. Harmonic distortion components appear at
whole multiples of the input frequency. Their amplitudes are
combined as the square root of the sum of the squares and
compared to the fundamental amplitude to yield the THD
specification. Typical values for THD are given in the table of
Electrical Characteristics.
Signal-to-noise ratio is the ratio of the amplitude at the fundamental frequency to the rms value at all other frequencies,
excluding any harmonic distortion components. Typical values are given in the Electrical Characteristics table. An alternative definition of signal-to-noise ratio includes the distortion components along with the random noise to yield a
signal-to-noise-plus-distortion ratio, or S/(N + D).
The THD and noise performance of the A/D converter will
change with the frequency of the input signal, with more distortion and noise occurring at higher signal frequencies. One
way of describing the A/D’s performance as a function of signal frequency is to make a plot of “effective bits” versus frequency. An ideal A/D converter with no linearity errors or
self-generated noise will have a signal-to-noise ratio equal to
(6.02n + 1.76) dB, where n is the resolution in bits of the A/D
converter. A real A/D converter will have some amount of
noise and distortion, and the effective bits can be found by:
where S/(N + D) is the ratio of signal to noise and distortion,
which can vary with frequency.
As an example, an ADC10061 witha5V
wave input signal will typically have a
signal-to-noise-plus-distortion ratio of 59.2 dB, which is
equivalent to 9.54 effective bits. As the input frequency increases, noise and distortion gradually increase, yielding a
plot of effective bits or S/(N + D) as shown in the typical performance curves.
8.0 SPEED ADJUST
In applications that require faster conversion times, the
Speed Adjust pin (pin 14 on the ADC10062, pin 17 on the
ADC10064) can significantly reduce the conversion time.
The speed adjust pin is connected to an on-chip current
source that determines the converter’s internal timing. By
connecting a resistor between the speed adjust pin and
ground as shown in
rent is increased, which reduces the conversion time. As an
example, an 18k resistor reduces the conversion time of a
typical part from 600 ns to 350 ns with no significant effect on
linearity.Using smaller resistors to further decrease the conversion time is possible as well, although the linearity will begin to degrade somewhat (see curves). Note that the resistor
value needed to obtain a given conversion time will vary from
part to part, so this technique will generally require some
“tweaking” to obtain satisfactory results.
Figure 4
, the internal programming cur-
, 100 kHz sine
P-P
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Page 13
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADC10061CIWM
NS Package Number M20B
Order Number ADC10062CIWM
NS Package Number M24B
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Sample/Hold
Order Number ADC10064CIWM
NS Package Number M28B
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
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accordance with instructions for use provided in the
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can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter with Input Multiplexer and
significant injury to the user.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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