Datasheet ADC0844, ADC0848 Datasheet (National Semiconductor)

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ADC0844/ADC0848 8-Bit µP Compatible A/D Converters with Multiplexer Options

June 1999

General Description

The ADC0844 and ADC0848 are CMOS 8-bit successive approximation A/D converters with versatile analog input multiplexers. The 4-channel or 8-channel multiplexers can be software configured for single-ended, differential or pseudo-differential modes of operation.

The differential mode provides low frequency input common mode rejection and allows offsetting the analog range of the converter. In addition, the A/D’s reference can be adjusted enabling the conversion of reduced analog ranges with 8-bit resolution.

The A/Ds are designed to operate from the control bus of a wide variety of microprocessors. TRI-STATE output latches that directly drive the data bus permit the A/Ds to be configured as memory locations or I/O devices to the microprocessor with no interface logic necessary.

Block and Connection Diagrams

Features

n Easy interface to all microprocessors n Operates ratiometrically or with 5 V

voltage reference

n No zero or full-scale adjust required n 4-channel or 8-channel multiplexer with address logic n Internal clock n 0V to 5V input range with single 5V power supply n 0.3" standard width 20-pin or 24-pin DIP n 28 Pin Molded Chip Carrier Package

Key Specifications

n Resolution 8 Bits n Total Unadjusted Error n Single Supply 5 V n Low Power 15 mW n Conversion Time 40 µs

⁄2LSB and±1 LSB

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*ADC0848 shown in DIP Package CH5-CH8 not included on the ADC0844

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Block and Connection Diagrams (Continued)

Molded Chip Carrier Package

ADC0844/ADC0848

Top View

See Ordering Information

Ordering Information

Temperature Total Unadjusted Error MUX Package

0˚C to +70˚C Molded Dip

−40˚C to +85˚C

Range

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Dual-In-Line Package

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Dual-In-Line Package

Top View

⁄2LSB

1 LSB Channels Outline

ADC0844CCN 4 N20A

ADC0848BCN 8 N24C

ADC0848CCN Molded Dip

ADC0844BCJ 4 J20A

ADC0844CCJ Cerdip

ADC0848BCV 8 V28A

ADC0848CCV Molded Chip Carrier

DS005016-30

Top View

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ADC0844/ADC0848

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (V Voltage

Logic Control Inputs −0.3V to +15V

At Other Inputs and Outputs −0.3V to V Input Current at Any Pin (Note 3) 5 mA Package Input Current (Note 3) 20 mA Storage Temperature −65˚C to +150˚C Package Dissipation at T ESD Susceptibility (Note 4) 800V

) 6.5V

=25˚C 875 mW

+0.3V

Lead Temperature

(Soldering, 10 seconds) Dual-In-Line Package (Plastic) 260˚C Dual-In-Line Package (Ceramic) 300˚C Molded Chip Carrier Package

Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C

Operating Conditions (Notes 1, 2)

Supply Voltage (V Temperature Range T

ADC0844CCN, ADC0848BCN, 0˚C≤TA≤70˚C ADC0848CCN ADC0844BCJ, ADC0844CCJ, −40˚C≤T

) 4.5 VDCto 6.0 V

MIN≤TA≤TMAX

≤85˚C

ADC0848BCV, ADC0848CCV

Electrical Characteristics

The following specifications apply for VCC=5VDCunless otherwise specified.Boldface limits apply from T other limits T

Parameter Conditions

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Maximum Total V Unadjusted Error (Note 8)

ADC0844BCN, ADC0848BCN, BCV ADC0844CCN, ADC0848CCN, CCV

ADC0844CCJ Minimum Reference 2.4 1.1 2.4 1.2 1.1 kΩ Input Resistance Maximum Reference 2.4 5.9 2.4 5.4 5.9 kΩ Input Resistance Maximum Common-Mode (Note 9) V Input Voltage Minimum Common-Mode (Note 9) GND−0.05 GND−0.05 GND−0.05 V Input Voltage DC Common-Mode Error Differential Mode Power Supply Sensitivity V Off Channel Leakage (Note 10) Current On Channel=5V, −1 −0.1 −1 µA

DIGITAL AND DC CHARACTERISTICS

, Logical “1” Input VCC=5.25V 2.0 2.0 2.0 V

IN(1)

Voltage (Min)

, Logical “0” Input VCC=4.75V 0.8 0.8 0.8 V

IN(0)

Voltage (Max)

, Logical “1” Input VIN=5.0V 0.005 1 0.005 1 µA

IN(1)

Current (Max)

, Logical “0” Input

IN(0)

Current (Max)

, Logical “1” VCC=4.75V

OUT(1)

Output Voltage (Min) I

A=Tj

= 25˚C.

ADC0844BCJ ADC0844CCJ

ADC0844CCN ADC0848BCN, ADC0848CCN ADC0848BCV, ADC0848CCV

Typ Tested Design Typ Tested Design

(Note 5) Limit Limit (Note 5) Limit Limit

(Note 6) (Note 7) (Note 6) (Note 7)

=5.00 V

REF

=5V±5%

⁄

1 LSB

+0.05 VCC+0.05 VCC+0.05 V

± ±

1/16 1/16

⁄

± ±

1/16 1/16

⁄

Off Channel=0V On Channel=0V, 1 0.1 1 µA Off Channel=5V

VIN=0V −0.005 −1 −0.005 −1 µA

=−360 µA 2.4 2.8 2.4 V

OUT

=−10 µA 4.5 4.6 4.5 V

OUT

MIN

to T

MAX

⁄

1 LSB

⁄

; all

Limit Units

LSB

LSB LSB

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Electrical Characteristics (Continued)

The following specifications apply for VCC=5VDCunless otherwise specified.Boldface limits apply from T other limits T

ADC0844/ADC0848

DIGITAL AND DC CHARACTERISTICS

OUT(0)

Output Voltage (Max) I I

, TRI-STATE Output V

OUT

Current (Max) V I

SOURCE

Current (Min)

, Output Sink V

SINK

Current (Min)

, Supply Current (Max) CS =1, V

Parameter Conditions

, Logical “0” VCC=4.75V 0.4 0.34 0.4 V

, Output Source V

A=Tj

= 25˚C.

ADC0844BCJ ADC0844CCJ

ADC0848BCN, ADC0848CCN ADC0848BCV, ADC0848CCV

Typ Tested Design Typ Tested Design

(Note 5) Limit Limit (Note 5) Limit Limit

(Note 6) (Note 7) (Note 6) (Note 7)

=1.6 mA

OUT

=0V −0.01 −3 −0.01 −0.3 −3 µA

OUT

=5V 0.01 3 0.01 0.3 3 µA

OUT

=0V −14 −6.5 −14 −7.5 −6.5 mA

OUT

OUT=VCC

Open

REF

16 8.0 16 9.0 8.0 mA

1 2.5 1 2.3 2.5 mA

ADC0844CCN

MIN

to T

AC Electrical Characteristics

The following specifications apply for VCC=5VDC,tr=tf= 10 ns unless otherwise specified. Boldface limits apply from T to T

W(WR)

ACC

RD to Output Data Valid) t

1H,t0H

Edge of RD to Hi-Z State) t

WI,tRI

Reset of INTR tDS, Minimum Data Set-Up Time (Note 11) 50 100 ns t

OUT

; all other limits TA=Tj= 25˚C.

MAX

Tested Design

Parameter Conditions Typ Limit Limit Units

(Note 5) (Note 6) (Note 7)

, Maximum Conversion Time (See Graph) 30 40 60 µs

, Minimum WR Pulse Width (Note 11) 50 150 ns

, Maximum Access Time (Delay from Falling Edge of CL= 100 pF 145 225 ns

(Note 11)

, TRI-STATE Control (Maximum Delay from Rising CL= 10 pF, RL= 10k 125 200 ns

(Note 11)

, Maximum Delay from Falling Edge of WR or RD to (Note 11) 200 400 ns

, Minimum Data Hold Time (Note 11) 0 50 ns

, Capacitance of Logic Inputs 5 pF

, Capacitance of Logic Outputs 5 pF

Note 1: Absolute Maximum Ratingsindicate limits beyond which damageto the device may occur. DC andAC electrical specificationsdo not apply when operating the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to the ground pins. Note 3: When the input voltage (V

to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.

Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Note 5: Typicals are at 25˚C and represent most likely parametric norm. Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 7: Design limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels. Note 8: Total unadjusted error includes offset, full-scale, linearity, and multiplexer error. Note 9: For V

voltages one diode drop below ground or one diode drop greaterthan V can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog V absolute 0 V

Note 10: Off channel leakage current is measured after the channel selection. Note 11: The temperature coefficient is 0.3%/˚C.

(−) ≥ VIN(+) the digital outputcode will be 0000 0000. Twoon-chip diodes are tied to each analog input, which will forward-conduct for analog input

to5VDCinput voltage range willtherefore require a minimum supply voltage of4.950 VDCover temperature variations, initialtolerance and loading.

) at any pin exceeds the power supply rails (V

does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an

supply.Be careful during testingat low VCClevels (4.5V), as high level analog inputs (5V)

V−or V

V+) the absolute value of the current at that pinshould be limited

MAX

; all

Limit Units

MIN

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Typical Performance Characteristics

ADC0844/ADC0848

Logic Input Threshold Voltage vs Supply Voltage

Linearity Error vs V

REF

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Output Current vs Temperature

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Conversion Time vs V

Power Supply Current vs Temperature

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SUPPLY

Conversion Time vs Temperature

DS005016-34

DS005016-36

Unadjusted Offset Error vs V

Voltage

REF

DS005016-35

DS005016-37

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TRI-STATE Test Circuits and Waveforms

ADC0844/ADC0848

Leakage Current Test Circuit

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DS005016-6

t1H,CL=10pF

DS005016-5

tr=20ns

t0H,CL=10pF

DS005016-7

tr=20ns

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Timing Diagrams

Programming New Channel Configuration and Starting a Conversion

Note 12: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR . Note 13: MA stands for MUX address.

Using the Previously Selected Channel Configuration and Starting a Conversion

ADC0844/ADC0848

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ADC0848 Functional Block Diagram

ADC0844/ADC0848

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Functional Description

The ADC0844 and ADC0848 contain a 4-channel and 8-channel analog input multiplexer (MUX) respectively. Each MUX can be configured into one of three modes of operation differential, pseudo-differential, and single ended. These modes are discussed in the Applications Information Section. The specific mode is selected by loading the MUX address latch with the proper address (see

Table 2

). Inputs to the MUX address latch (MA0-MA4) are common with data bus lines (DB0-DB4) and are enabled when the RD line is high. A conversion is initiated via the CS and WR lines. If the data from a previous conversion is not read, the INTR line will be low. The falling edge of WR will reset the INTR line high and ready the A/D for a conversion cycle. The rising edge of WR, with RD high, strobes the data on the MA0/DB0-MA4/DB4 inputs into the MUX address latch to select a new input configuration and start a conversion. If the RD line is held low during the entire low period of WR the previous MUX configuration is retained, and the data of the previous conversion is the output on lines DB0-DB7. After the conversion cycle (t internal clock frequency, the digital data is transferred to the output latch and the INTR is asserted low. Taking CS and RD low resets INTR output high and outputs the conversion result on the data lines (DB0-DB7).

≤ 40 µs), which is set by the

Table 1

and

Applications Information

1.0 MULTIPLEXER CONFIGURATION

The design of these converters utilizes a sampled-data comparator structure which allows a differential analog input to be converted by a successive approximation routine.

TABLE 1. ADC0844 MUX ADDRESSING

The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input terminal. The polarity of each input terminal of the pair being converted indicates which line the converter expects to be the most positive. If the assigned “+” input is less than the “−” input the converter responds with an all zeros output code.

A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be software configured into three modes: differential, single ended, or pseudo-differential. modes using the 4-channel MUX ADC0844. The eight inputs of the ADC0848 can also be configured in any of the three modes. In the differential mode, theADC0844 channel inputs are grouped in pairs, CH1 with CH2 and CH3 with CH4. The polarity assignment of each channel in the pair is interchangeable. The single-ended mode has CH1–CH4 assigned as the positive input with the negative input being the analog ground (AGND) of the device. Finally, in the pseudo-differential mode CH1–CH3 are positive inputs referenced to CH4 which is now a pseudo-ground. This pseudo-ground input can be set to any potential within the input common-mode range of the converter. The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage.

The analog input voltages for each channel can range from 50 mV below ground to 50 mV above V without degrading conversion accuracy.

Figure 1

shows the three

(typically 5V)

ADC0844/ADC0848

MUX Address CS WR RD Channel

MA3 MA2 MA1 MA0 CH1 CH2 CH3 CH4 AGND Mode

XLLLL H+− XLLHL XLHLL H +− XLHHL H −+ LHLLL H+ − LHLHL LHHLL H + − LHHHL H + − H H L L L H + − PseudoHHLHL HHHLL H +− XXXXL

X=don’t care

H − + Differential

H + − Single-Ended

H + − Differential

L Previous Channel Configuration

MUX

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Applications Information (Continued)

4 Single-Ended

ADC0844/ADC0848

DS005016-12

3 Pseudo-Differential

DS005016-14

FIGURE 1. Analog Input Multiplexer Options

2.0 REFERENCE CONSIDERATIONS

The voltage applied to the reference input of these converters defines the voltage span of the analog input (the difference between V possible output codes apply. The devices can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the minimum reference input resistance of 1.1 kΩ. This pin is the top of a resistor divider string used for the successive approximation conversion.

In a ratiometric system ( is proportional to the voltage used for the A/D reference. This voltage is typically the system power supply, so the V can be tied to V requirements of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy ( varies between very specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. The LM385 and LM336 reference diodes are good low current devices to use with these converters.

The maximum value of the reference is limited to the V supply voltage. The minimum value, however, can be quite small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals V

256).

and V

IN(MAX)

Figure 2a

. This technique relaxes the stability

Figure 2b

) over which the 256

IN(MIN)

), the analog input voltage

), where the analog input

REF

2 Differential

DS005016-13

Combined

DS005016-15

3.0 THE ANALOG INPUTS

3.1 Analog Differential Voltage Inputs and Common-Mode Rejection

The differential input of these converters actually reduces the effects of common-mode input noise, a signal common to both selected “+” and “−” inputs for a conversion (60 Hz is most typical). The time interval between sampling the “+” input and then the “−” inputs is

⁄2of a clock period. The change in the common-mode voltage during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:

DS005016-38

where f V

peak

For a 60 Hz common-mode signal to generate a

is the frequency of the common-mode signal,

is its peak voltage value and tCis the conversion time.

⁄4LSB error (≈5 mV) with the converter running at 40 µS, its peak value would have to be 5.43V.This large a common-mode signal is much greater than that generally found in a well designed data acquisition system.

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Applications Information (Continued)

TABLE 2. ADC0848 MUX Addressing

MUX Address CS WR RD Channel MUX

MA4 MA3 MA2 MA1 MA0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 AGND Mode

XLLLLL H+− XLLLHL H−+ XLLHLL H +− XLLHHL XLHLLL H +− XLHLHL H −+ XLHHLL H +− XLHHHL H −+ LHLLLL H+ − LHLLHL H + − LHLHLL H + − LHLHHL LHHLLL H + − LHHLHL H + − LHHHLL H + − LHHHHL H + − HHLLLL H+ − HHLLHL H + − HHLHLL H + − PseudoHHLHHL HHHLLL H + − HHHLHL H + − HHHHLL H +− XXXXXL

H − + Differential

H + − Single-Ended

H + − Differential

L Previous Channel Configuration

ADC0844/ADC0848

3.2 Input Current

Due to the sampling nature of the analog inputs, short duration spikes of current enter the “+” input and exit the “−” input at the clock edges during the actual conversion. These currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should not be used if the source resistance is greater than 1kΩ.

3.3 Input Source Resistance

The limitation of the input source resistance due to the DC leakage currents of the input multiplexer is important. A worst-case leakage current of

1 µA over temperature will createa1mVinput error witha1kΩsource resistance. An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required.

4.0 OPTIONAL ADJUSTMENTS

4.1 Zero Error

The zero of the A/D does not require adjustment. If the minimum analog input voltage value, V

, is not ground,

IN(MIN)

a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum input voltage

by biasing any V

(−) input at this V

IN(MIN)

value. This is useful for either differential or pseudo-differential modes of input channel configuration.

The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the V positive voltage to the V

−

input and applying a small magnitude

input. Zero error is the difference between actual DC input voltage which is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal V

=5.000 VDC).

REF

⁄2LSB value (1⁄2LSB=9.8 mV for

4.2 Full-Scale

The full-scale adjustment can be made by applying a differential input voltage which is 1

⁄2LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the V

input for a digital output code changing

REF

from 1111 1110 to 1111 1111.

4.3 Adjusting for an Arbitrary Analog Input Voltage Range

If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A V equals this desired zero reference plus

(+) voltage which

⁄2LSB (where the LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to selected “+” input and the

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Applications Information (Continued)

zero reference voltage at the corresponding “−” input should then be adjusted to just obtain the 00 transition.

ADC0844/ADC0848

a) Ratiometric

HEX

to 01

DS005016-16

code

HEX

b) Absolute with a Reduced Span

FIGURE 2. Referencing Examples

DS005016-17

The full-scale adjustment should be made [with the proper V

(−) voltage applied] by forcing a voltage to the VIN(+)

input which is given by:

where V V

MIN

=the high end of the analog input range and

MAX

=the low end (the offset zero) of the analog range. (Both

are ground referenced.)

Zero-Shift and Span Adjust (2V≤V

The V change from FE

(or VCC) voltage is then adjusted to provide a code

REF

HEX

to FF

. This completes the adjust-

HEX

ment procedure. For an example see the Zero-Shift and Span Adjust circuit

below.

≤5V)

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Applications Information (Continued)

Differential Voltage Input 9-Bit A/D

Span Adjust (0V≤VIN≤3V)

ADC0844/ADC0848

DS005016-19

Diodes are 1N914

DS005016-20

Protecting the Input

DS005016-21

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Applications Information (Continued)

ADC0844/ADC0848

DO=all 1s if VIN(+)>VIN(−) DO=all 0s if V

(+)<VIN(−)

Operating with Automotive Ratiometric Transducers

High Accuracy Comparators

DS005016-22

*VIN(−)=0.15 V 15% of VCC≤V

≤85% of V

XDR

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Applications Information (Continued)

A Stand Alone Circuit

ADC0844/ADC0848

Note: DUT pin numbers in parentheses are for ADC0844, others are for ADC0848.

Start a Conversion without Updating the Channel Configuration

CS•WR will update the channel configuration and start a conversion. CS•RD will read the conversion data and start a new conversion without updating the channel configuration. Waiting for the end of this conversion is not necessary. A CS•WR can immediately follow the CS•RD .

DS005016-25

DS005016-26

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Applications Information (Continued)

ADC0844/ADC0848

ADC0844—INS8039 Interface

DS005016-27

SAMPLE PROGRAM FOR ADC0844— INS8039 INTERFACE CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS

ORG 0H

0000 04 10 JMP BEGIN ;START PROGRAM AT ADDR 10

ORG 10H ;MAIN PROGRAM

0010 B9 FF BEGIN: MOV R1,

0012 B8 20 MOV R0, 0014 89 FF ORL P1, 0016 23 00 MOV A,00H ;LOAD THE ACC WITH A/D MUX DATA

0018 14 50 CALL CONV ;CALL THE CONVERSION SUBROUTINE 001A 23 02 MOV A,

001C 18 INC R0 ;INCREMENT THE A/D DATA ADDRESS 001D 14 50 CALL CONV ;CALL THE CONVERSION SUBROUTINE

;CONTINUE MAIN PROGRAM

;CONVERSION SUBROUTINE ;ENTRY:ACC—A/D MUX DATA ;EXIT: ACC—CONVERTED DATA

0FFH ;LOAD R1 WITH A UNUSED ADDR

;LOCATION

20H ;A/D DATA ADDRESS

0FFH ;SET PORT 1 OUTPUTS HIGH

;CH1 AND CH2 DIFFERENTIAL

02H ;LOAD THE ACC WITH A/D MUX DATA

;CH3 AND CH4 DIFFERENTIAL

ORG 50H 0050 99 FE CONV: ANL P1, 0052 91 MOVX 0053 09 LOOP: IN A,P1 ;INPUT INTR STATE

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0FEH ;CHIP SELECT THE A/D

R1,A ;LOAD A/D MUX & START CONVERSION

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Applications Information (Continued)

SAMPLE PROGRAM FOR ADC0844—INS8039 INTERFACE CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS (Continued)

0054 32 53 JB1 LOOP ;IF INTR = 1 GOTO LOOP 0056 81 MOVX A,@R1 ;IF INTR = 0 INPUT A/D DATA 0057 89 01 ORL P1,&01H ;CLEAR THE A/D CHIP SELECT 0059 A0 MOV 005A 83 RET ;RETURN TO MAIN PROGRAM

I/O Interface to NSC800

R0,A ;STORE THE A/D DATA

DS005016-28

ADC0844/ADC0848

SAMPLE PROGRAM FOR ADC0848— NSC800 INTERFACE

0008 NCONV EQU 16 000F DEL EQU 15 ;DELAY 50 µsec CONVERSION 001F CS EQU 1FH ;THE BOARD ADDRESS 3C00 ADDTA EQU 003CH ;START OF RAM FOR A/D

;DATA 0000' 08 09 0A 0B MUXDTA: DB 08H,09H,0AH,0BH ;MUX DATA 0004' 0C 0D 0E 0F DB 0CH,0DH,0EH,0FH 0008' 0E 1F START: LD C,CS 000A' 06 16 LD B,NCONV 000C' 21 0000' LD HL,MUXDTA 000F' 11 003C LD DE,ADDTA 0012' ED A3 STCONV: OUTI ;LOAD A/D’S MUX DATA

;AND START A CONVERSION 0014' EB EX DE,HL ;HL=RAM ADDRESS FOR THE

;A/D DATA 0015' 3E 0F LD A,DEL 0017' 3D WAIT: DEC A ;WAIT 50 µsec FOR THE 0018' C2 0013' JP NZ,WAIT ;CONVERSION TO FINISH 001B' ED A2 INI ;STORE THE A/D’S DATA

;CONVERTED ALL INPUTS? 001D' EB EX DE,HL 001E' C2 000E' JP NZ,STCONV ;IF NOT GOTO STCONV

END

Note 14: This routine sequentially programs the MUX data latch in the signal-ended mode. For CH1-CH8 a conversion is started, then a 50 µs wait for the A/D to complete a conversion and the data is stored at address ADDTAfor CH1, ADDTA+ 1 for CH2, etc.

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Physical Dimensions inches (millimeters) unless otherwise noted

ADC0844/ADC0848

Ceramic Dual-In-Line Package (J)

NS Package Number J20A

Molded Dual-In-Line Package (N)

NS Package Number N20A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

ADC0844/ADC0848

Molded Dual-In-Line Package (N)

NS Package Number N24C

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Chip Carrier Package (V)

NS Package Number V28A

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1. Life support devices or systems are devices or

ADC0844/ADC0848 8-Bit µP Compatible A/D Converters with Multiplexer Options

systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the

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