TL/H/5607
ADC0833 8-Bit Serial I/O A/D Converter with 4-Channel Multiplexer
December 1994
ADC0833 8-Bit Serial I/O A/D Converter
with 4-Channel Multiplexer
General Description
The ADC0833 series is an 8-bit successive approximation
A/D converter with a serial I/O and configurable input multiplexer with 4 channels. The serial I/O is configured to comply with the NSC MICROWIRE
TM
serial data exchange stan-
dard for easy interface to the COPS
TM
family of processors,
as well as with standard shift registers or mPs.
The 4-channel multiplexer is software configured for singleended or differential inputs when channel assigned by a 4bit serial word.
The differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input
can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.
Key Specifications
Y
Resolution 8 Bits
Y
Total Unadjusted Error
g
(/2 LSB andg1 LSB
Y
Single Supply 5 V
DC
Y
Low Power 23 mW
Y
Conversion Time 32 ms
Features
Y
NSC MICROWIRE compatible –direct interface to COPS
family processors
Y
Easy interface to all microprocessors, or operates
‘‘stand alone’’
Y
Works with 2.5V (LM336) voltage reference
Y
No full-scale or zero adjust required
Y
Differential analog voltage inputs
Y
4-channel analog multiplexer
Y
Shunt regulator allows operation with high voltage
supplies
Y
0V to 5V input range with single 5V power supply
Y
Remote operation with serial digital data link
Y
TTL/MOS input/output compatible
Y
0.3×standard width 14-pin DIP package
Connection and Functional Diagrams
Dual-In-Line Package (J and N)
TL/H/5607– 14
Top View
Order Number ADC0833CCJ,
ADC0833BCN or ADC0833CCN
See NS Package Number
J14A or N14A
TL/H/5607– 1
COPSTMand MICROWIRETMare trademarks of National Semiconductor Corporation.
TRI-STATE
É
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Current into V
a
(Note 3) 15 mA
Supply Voltage, VCC(Note 3) 6.5V
Voltage
Logic Inputs
b
0.3V to V
CC
a
0.3V
Analog Inputs
b
0.3V to V
CC
a
0.3V
Input Current per Pin (Note 4)
g
5mA
Package Input Current (Note 4)
g
20 mA
Storage Temperature
b
65§Ctoa150§C
Package Dissipation at
T
A
e
25§C (Board Mount) 0.8W
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (Plastic) 260
§
C
Dual-In-Line Package (Ceramic) 300
§
C
ESD Susceptibility (Note 5) 2000V
Operating Conditions (Notes1&2)
Supply Voltage, V
CC
4.5 VDCto 6.3 V
DC
Temperature Range T
MIN
s
T
A
s
T
MAX
ADC0833CCJ
b
40§CsT
A
s
85§C
ADC0833BCN, ADC0833CCN 0
§
CsT
A
s
70§C
Electrical Characteristics The following specifications apply for V
CC
e
V
a
e
5V, f
CLK
e
250 kHz and
V
REF
/2s(V
CC
a
0.1V) unless otherwise specified. Boldface limits apply from T
MIN
to T
MAX
; all other limits
T
A
e
T
j
e
25§C.
Typ
Tested Design
Parameter Conditions
(Note 6)
Limit Limit Units
(Note 7) (Note 8)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error V
REF/
2 Forced to 2.500 V
DC
ADC0833BCN
g
(/2
g
(/2 LSB
ADC0833CCN
g
1
g
1 LSB
ADC0833CCJ
g
1 LSB
Minimum Total Ladder
Resistance (Note 9)
ADC0833CCJ 7.0 2.6 kX
ADC0833BCN/CCN 7.0 2.6 2.6 kX
Maximum Total Ladder
Resistance (Note 9)
ADC0833CCJ 7.0 11.8 kX
ADC0833BCN/CCN 7.0 10.8 11.8 kX
Minimum Common-Mode All MUX Inputs and COM Input
Input Range (Note 10)
ADC0833CCJ GND
b
0.05 V
ADC0833BCN/CCN GND
b
0.05 GNDb0.05 V
Maximum Common-Mode All MUX Inputs and COM Input
Input Range (Note 10)
ADC0833CCJ V
CC
a
0.05 V
ADC0833BCN/CCN V
CC
a
0.05 V
CC
a
0.05 V
DC Common-Mode Error
ADC0833CCJ
g
(/16
g
(/4 LSB
ADC0833BCN/CCN
g
(/16
g
(/4
g
(/4 LSB
Change In Zero 15mA Into V
a
Error From V
CC
e
5V V
CC
e
N.C.
To Internal Zener V
REF
/2e2.500V
Operation (Note 3)
ADC0833CCJ 1 LSB
ADC0833BCN/CCN 1 1 LSB
2
Electrical Characteristics The following specifications apply for V
CC
e
V
a
e
5V, f
CLK
e
250 kHz and
V
REF
/2s(V
CC
a
0.1V) unless otherwise specified. Boldface limits apply from t
MIN
to t
MAX
; all other limits T
A
e
T
j
e
25§C.
(Continued)
Typ
Tested Design
Parameter Conditions
(Note 6)
Limit Limit Units
(Note 7) (Note 8)
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
VZ, Minimum Internal 15mA Into V
a
Diode Breakdown
(At V
a
) (Note 3)
ADC0833CCJ 6.3 V
ADC0833BCN/CCN 6.3 6.3 V
VZ, Maximum Internal 15mA Into V
a
Diode Breakdown
(At Va) (Note 3)
ADC0833CCJ 8.5 V
ADC0833BCN/CCN 8.5 8.5 V
Power Supply Sensitivity V
CC
e
5Vg5%
ADC0833CCJ
g
(/16
g
(/4 LSB
ADC0833BCN/CCN
g
(/16
g
(/4
g
(/4 LSB
I
OFF
, Off Channel Leakage On Channele5V, Off Channele0V
Current (Note 11)
ADC0833CCJ
b
1 mA
b
200 nA
ADC0833BCN/CCN
b
1 mA
b
200 nA
On Channele0V, Off Channele5V
ADC0833CCJ 1 mA
200 nA
ADC0833BCN/CCN 1 mA
200 nA
ION, On Channel Leakage On Channele5V, Off Channele0V
Current (Note 11)
ADC083CCJ 1 mA
200 nA
ADC0833BCN/CCN 1 mA
200 nA
On Channele0V, Off Channele5V
ADC083CCJ
b
1 mA
b
200 nA
ADC0833BCN/CCN
b
1 mA
b
200 nA
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
, Logical ‘‘1’’ Input V
CC
e
5.25V
Voltage
ADC0833CCJ 2.0 V
ADC0833BCN/CCN 2.0 2.0 V
V
IN(0)
, Logical ‘‘0’’ Input V
CC
e
4.75V
Voltage
ADC0833CCJ 0.8 V
ADC0833BCN/CCN 0.8 0.8 V
I
IN(1)
, Logical ‘‘1’’ Input V
IN
e
V
CC
Current
ADC0833CCJ 0.005 1 mA
ADC0833BCN/CCN 0.005 1 1 mA
3
Electrical Characteristics The following specifications apply for V
CC
e
V
a
e
5V, f
CLK
e
250 kHz and
V
REF
/2s(V
CC
a
0.1V) unless otherwise specified. Boldface limits apply from t
MIN
to t
MAX
; all other limits T
A
e
T
j
e
25§C.
(Continued)
Typ
Tested Design
Parameter Conditions
(Note 6)
Limit Limit Units
(Note 7) (Note 8)
DIGITAL AND DC CHARACTERISTICS (Continued)
I
IN(0)
, Logical ‘‘0’’ Input V
IN
e
0V
Current
ADC0833CCJ
b
0.005
b
1 mA
ADC0833BCN/CCN
b
0.005
b
1
b
1 mA
V
OUT(1)
, Logical ‘‘1’’ Output V
CC
e
4.75V
Voltage
ADC0833CCJ I
OUT
eb
360mA 2.4 V
ADC0833BCN/CCN 2.4 2.4 V
ADC0833CCJ I
OUT
eb
10mA 4.5 V
ADC0833BCN/CCN 4.5 4.5 V
V
OUT(0)
, Logical ‘‘0’’ Output I
OUT
e
1.6mA, V
CC
e
4.75V
Voltage
ADC0833CCJ 0.4 V
ADC0833BCN/CCN 0.4 0.4 V
I
OUT
, TRI-STATE Output
Current (DO, SARS)
ADC0833CCJ V
OUT
e
0.4V
b
0.1
b
3 mA
ADC0833BCN/CCN
b
0.1
b
3
b
3 mA
ADC0833CCJ V
OUT
e
5V 0.1 3 mA
ADC0833BCN/CCN 0.1 3 3 mA
I
SOURCE
V
OUT
Short to GND
ADC0833CCJ
b
14
b
6.5 mA
ADC0833BCN/CCN
b
14
b
7.5
b
6.5 mA
I
SINK
V
OUT
Short to V
CC
ADC0833CCJ 16 8.0 mA
ADC0833BCN/CCN 16 9.0 8.0 mA
ICC, Supply Current (Note 3) V
REF
/2 Open Circuit
ADC0833CCJ 0.9 4.5 mA
ADC0833BCN/CCN 0.9 4.5 4.5 mA
4
AC Electrical Characteristics The following specifications apply for V
CC
e
V
a
e
5V and t
r
e
t
f
e
20 ns
unless otherwise specified. These limits apply for T
A
e
T
j
e
25§C.
Typ
Tested Design
Parameter Conditions
(Note 6)
Limit Limit Units
(Note 7) (Note 8)
f
CLK
, Clock Frequency Min 10 kHz
Max 400 kHz
TC, Conversion Time Not including MUX Addressing Time 8 1/f
CLK
Clock Duty Cycle (Note 12) Min 40 %
Max 60 %
t
SET-UP
,CSFalling Edge or 250 ns
Data Input Valid to CLK
Rising Edge
t
HOLD
, Data Input Valid 90 ns
after CLK Rising Edge
t
pd1,tpd0
ÐCLK Falling C
L
e
100 pF
Edge to Output Data Valid Data MSB First 650 1500 ns
(Note 13) Data LSB First 250 600 ns
t1H,tOHÐRising Edge of CS C
L
e
10 pF, R
L
e
10k 125 250 ns
to Data Output and SARS C
L
e
100 pF, R
L
e
2k 500 ns
Hi-Z (see TRI-STATE Test Circuits)
CIN, Capacitance of Logic 5 pF
Input
C
OUT
, Capacitance of Logic 5 pF
Outputs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the ground pins.
Note 3: Internal zener diodes (approx. 7V) are connected from V
a
to GND and VCCto GND. The zener at Vacan operate as a shunt regulator and is connected to
V
CC
via a conventional diode. Since the zener voltage equals the A/D’s breakdown voltage, the diode insures that VCCwill be below breakdown when the device is
powered from V
a
. Functionality is therefore guaranteed for V
a
operation even though the resultant voltage at VCCmay exceed the specified Absolute Max. of
6.5V. It is recommended that a resistor be used to limit the max. current into V
a
.
Note 4: When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
k
Vbor V
IN
l
Va) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 6: Typicals are at 25
§
C and represent most likely parametric norm.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: See Applications, section 3.0.
Note 10: For V
IN
(b)tVIN(a) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater than the V
CC
supply. Be careful, during testing at low VCClevels (4.5V),
as high level analog inputs (5V) can cause this input diode to conductÐespecially at elevated temperatures, and cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog V
IN
or V
REF
does not exceed the supply voltage by more than 50 mV, the
output code will be correct. To achieve an absolute 0 V
DC
to5VDCinput voltage range will therefore require a minimum supply voltage of 4.950 VDCover
temperature variations, initial tolerance and loading.
Note 11: Leakage current is measured with the clock not switching.
Note 12: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of
these limits, the minimum time the clock is high or the minimum time the clock is low must be at least 1 ms. The maximum time the clock can be high is 60 ms. The
clocked can be stopped when low so long as the analog input voltage remains stable.
Note 13: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to
allow for comparator response time.
5
Timing Diagrams
Data Input Timing Data Output Timing
TRI-STATE Test Circuits and Waveforms
Leakage Current Test Circuit
TL/H/5607– 2
6
Typical Performance Characteristics
Error vs V
REF
/2 Voltage
Effect of Unadjusted Offset
V
REF
Voltage
Linearity Error vs
vs Temperature
Linearity Error
Linearity Error vs f
CLK
vs Temperature
Power Supply Current
vs Temperature
Output Current
Current vs f
CLK
Power Supply
TL/H/5607– 3
7
ADC0833 Functional Block Diagram
TL/H/5607– 4
8
Timing Diagram
TL/H/5607– 5
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of the ADC0833 utilizes a sample-data comparator structure which provides for a differential analog input
to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned ‘‘
a
’’ input terminal and a ‘‘b’’ input terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned ‘‘
a
’’ input is less than the
‘‘
b
’’ input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended (ground referred) or differential inputs. The analog signal conditioning required in transducer-based data
acquisition systems is significantly simplified with this type
of input flexibility. One converter package can now handle
ground referenced inputs and true differential inputs.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential. In the differential case, it also assigns the polarity of the
channels. Differential inputs are restricted to adjacent channel pairs. For example channel 0 and channel 1 may be
selected as a differential pair. Channel 0 or 1 cannot act
differentially with any other channel. In addition to selecting
differential mode the sign may also be selected. Channel 0
may be selected as the positive input and channel 1 as the
negative input or vice versa. This programmability is best
illustrated by the MUX addressing codes shown in the following table. The MUX address is shifted into the converter
through the DI line.
TABLE I. MUX Addressing
Single-Ended MUX Mode
Address Channel
Ý
SGL/ ODD/ SELECT
0123
DIF SIGN 10
1001
a
1011
a
1101
a
1111
a
COM is internally ties to a GND
Differential MUX Mode
Address Channel
Ý
SGL/ ODD/ SELECT
0123
DIF SIGN 10
0001
ab
0011
ab
0101
ba
0111
ba
9
Functional Description (Continued)
Since the input configuration is under software control, it
can be modified, as required, at each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion.
Figure 1
illus-
trates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50 mV below ground to 50mV above V
CC
(typically 5V) with-
out degrading conversion accuracy.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows more function to be included in the
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor; transmit-
ting highly noise immune digital data back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagram and Functional Block Diagram
and to follow a complete conversion sequence.
1. A conversion is initiated by first pulling the CS
(chip select) line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
2. A clock is then generated by the processor (if not provided continuously) and output to the A/D clock input.
3. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register. The
start bit is the first logic ‘‘1’’ that appears on this line (all
leading zeros are ignored). Following the start bit the converter expects the next 4 bits to be the MUX assignment
word.
4 Single-Ended 2 Differential
Mixed Mode
TL/H/5607– 6
FIGURE 1. Analog Input Multiplexer Options for the ADC0833
10
Functional Description (Continued)
4. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of (/2 clock
period (where nothing happens) is automatically inserted to
allow the selected MUX channel to settle. The SAR status
line goes high at this time to signal that a conversion is now
in progress and the DI line is disabled (it no longer accepts
data).
5. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero for this one clock period of MUX
settling time.
6. When the conversion begins, the output of the SAR comparator, which indicates whether the analog input is greater
than (high) or less than (low) each successive voltage from
the internal resistor ladder, appears at the DO line on each
falling edge of the clock. This data is the result of the conversion being shifted out (with the MSB coming first) and
can be read by the processor immediately.
7. After 8 clock periods the conversion is completed. The
SAR status line returns low to indicate this (/2 clock cycle
later.
8. If the programmer prefers, the data can be read in an LSB
first format. All 8 bits of the result are stored in an output
shift register. The conversion result, LSB first, is automatically shifted out the DO line, after the MSB first data stream.
The DO line then goes low and stays low until CS
is re-
turned high.
9. All internal registers are cleared when the CS
line is high.
If another conversion is desired, CS
must make a high to
low transition followed by address information.
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire. This
is possible because the DI input is only ‘‘looked-at’’ during
the MUX addressing interval while the DO line is still in a
high impedance state.
3.0 REFERENCE CONSIDERATIONS
The ADC0833 is intended primarily for use in circuits requiring absolute accuracy. In this type of system, the analog
inputs vary between very specific voltage limits and the reference voltage for the A/D converter must remain stable
with time and temperature. For ratiometric applications, an
ADC0834 is a pin-for-pin compatible alternative since it has
aV
REF
input (note the ADC0834 needs one less bit of mux
addressing information).
The voltage applied to the V
REF
/2 pin defines the voltage
span of the analog input[the difference between V
IN
(a)
and V
IN
(b)]over which the 256 possible output codes apply. A full-scale conversion (an all 1s output code) will result
when the voltage difference between a selected ‘‘
a
’’ input
and ‘‘
b
’’ input is approximately
twice
the voltage at the
V
REF
/2 pin. This internal gain of 2 from the applied reference to the full-scale input voltage allows biasing a low voltage reference diode from the 5V
DC
converter supply. To
accommodate a 5V input span, only a 2.5V reference is
required. The LM385 and LM336 reference diodes are good
low current devices to use with these converters. The output code changes in accordance with the following equation:
Output Code
e
256
#
VIN(a)bVIN(b)
2(V
REF
/2)
J
where the output code is the decimal equivalent of the 8-bit
binary output (ranging from 0 to 255) and the term V
REF
/2 is
the voltage from pin 9 to ground.
The V
REF
/2 pin is the center point of a two resistor divider
(each resistor is 3.5 kX) connected from V
CC
to ground.
Total ladder input resistance is the sum of these two equal
resistors. As shown in
Figure 2,
a reference diode with a
voltage less than V
CC
/2 can be connected without requiring
an external biasing resistor if its current requirements meet
the indicated level.
The minimum value of V
REF
/2 can be quite small (see Typical Performance Characteristics) to allow direct conversions
of transducer outputs providing less than a 5V output span.
Particular care must be taken with regard to noise pickup,
circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of
the converter (1 LSB equals V
REF
/256).
TL/H/5607– 7
V
FULL-SCALE
j
2.4V V
FULL-SCALE
j
5.0V
Note: No external biasing resistor needed if V
Z
k
V
CC
2
and I
Z
min
k
VCC/2bV
Z
1.75 kX
FIGURE 2. Reference Biasing Examples
11
Functional Description (Continued)
4.0 THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the inputs be noisy to begin with or possibly
riding on a large common-mode voltage.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected ‘‘
a
’’ and ‘‘b’’ inputs for a conversion (60
Hz is most typical). The time interval between sampling the
‘‘
a
’’ input and then the ‘‘b’’ input is (/2 of a clock period.
The change in the common-mode voltage during this short
time interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
V
error
(max)eV
PEAK
(2qfCM)
#
0.5
f
CLK
J
where fCMis the frequency of the common-mode signal,
V
PEAK
is its peak voltage value
and f
CLK
is the A/D clock frequency.
For a 60 Hz common-mode signal to generate a (/4 LSB
error (&5 mV) with the converter running at 250 kHz, its
peak value would have to be 6.63V which would be larger
than allowed as it exceeds the maximum analog input limits.
Due to the sampling nature of the analog inputs short spikes
of current enter the ‘‘
a
’’ input and exit the ‘‘b’’ input at the
clock edges during the actual conversion. These currents
decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause
an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should
not be used if the source resistance is greater than 1 kX.
This source resistance limitation is important with regard to
the DC leakage currents of input multiplexer as well. The
worst-case leakage current of
g
1 mA over temperature will
createa1mVinut error witha1kXsource resistance. An
op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
signal source be required.
5.0 OPTIONAL ADJUSTMENTS
5.1 Zero Error
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V
IN(MIN)
, is not ground
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any V
IN
(b) input at this V
IN(MIN)
value. This
utilizes the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be measured by grounding the V
IN
(b) input and applying a small
magnitude positive voltage to the V
IN
(a) input. Zero error is
the difference between the actual DC input voltage which
is necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal (/2 LSB value
((/2 LSB
e
9.8 mV for V
REF
/2e2.500 VDC).
5.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 (/2 LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the V
REF
input or VCCfor a digital output code
which is just changing from 1111 1110 to 1111 1111.
5.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A V
IN
(a) voltage which
equals this desired zero reference plus (/2 LSB (where the
LSB is calculated for the desired analog span, using
1 LSB
e
analog span/256) is applied to selected ‘‘a’’ input
and the zero reference voltage at the corresponding ‘‘
b
’’
input should then be adjusted to just obtain the 00
HEX
to
01
HEX
code transition.
The full-scale adjustment should be made[with the proper
V
In
(b) voltage applied]by forcing a voltage to the VIN(a)
input which is given by:
V
IN
(a)fsadjeV
MAX
b
1.5
Ð
(V
MAX
b
V
MIN
)
256
(
where:
V
MAX
e
the high end of the analog input range
and
V
MIN
e
the low end (the offset zero) of the analog
range.
(Both are ground referenced.)
The V
REF
/2 voltage is then adjusted to provide a code
change from FE
HEX
to FF
HEX
. This completes the adjust-
ment procedure.
6.0 POWER SUPPLY
A unique feature of the ADC0833 is the inclusion of a 7V
zener diode connected from the V
a
terminal to ground
which also connects to the V
CC
terminal (which is the actual
converter supply) through a silicon diode, as shown in
Fig-
ure 3.
TL/H/5607– 8
FIGURE 3. An On-Chip Shunt Regulator Diode
12
Functional Description (Continued)
This zener is intended for use as a shunt voltage regulator
to eliminate the need for any additional regulating components. This is most desirable if the converter is to be remotely located from the system power source.
Figures 4
and5illustrate two useful applications of this on-board zener when an external transistor can be afforded.
An important use of the interconnecting diode between V
a
and VCCis shown in
Figures 6
and7.Here, this diode is
used as a rectifier to allow the V
CC
supply for the converter
to be derived from the clock. The low current requirements
of the A/D (E3 mA) and the relatively high clock frequencies used (typically in the range of 10k-400 kHz) allows using the small value filter capacitor shown to keep the ripple
on the V
CC
line to well under (/4 of an LSB. The shunt zener
regulator can also be used in this mode. This requires a
clock voltage swing which is in excess of V
Z
. A current limit
for the zener is needed, either built into the clock generator
or a resistor can be used from the CLK pin to the V
a
pin.
Applications
TL/H/5607– 15
TL/H/5607– 16
FIGURE 4. Operating with a Temperature
Compensated Reference
TL/H/5607– 17
*Note 4.5VsV
CC
s
6.3V
FIGURE 6. Generally VCCfrom the Converter Clock
FIGURE 5. Using the A/D as the
System Supply Regulator
TL/H/5607– 9
FIGURE 7. Remote SensingÐClock
and Power on 1 Wire
13
Applications (Continued)
Digital Link and Sample Controlling Software for the
Serially Oriented COP420 and the Bit Programmable I/O INS8048
TL/H/5607– 10
COP CODING EXAMPLE
Mnemonic Instruction
LEI ENABLES SIO’s INPUT AND OUTPUT
SC C
e
1
OGI G0
e
0 (CSe0)
CLR A CLEARS ACCUMULATOR
AISC 1 LOADS ACCUMULATOR WITH 1
XAS EXCHANGES SIO WITH ACCUMULATOR
AND STARTS SK CLOCK
LDD LOADS MUX ADDRESS FROM RAM
INTO ACCUMULATOR
NOP Ð
XAS LOADS MUX ADDRESS FROM
ACCUMULATOR TO SIO REGISTER
u
8 INSTRUCTIONS
v
XAS READS HIGH ORDER NIBBLE (4 BITS)
INTO ACCUMULATOR
XIS PUTS HIGH ORDER NIBBLE INTO RAM
CLR A CLEARS ACCUMULATOR
RC C
e
0
XAS READS LOW ORDER NIBBLE INTO
ACCUMULATOR AND STOPS SK
XIS PUTS LOW ORDER NIBBLE INTO RAM
OGI G0
e
1 (CSe1)
LEI DISABLES SIO’s INPUT AND OUTPUT
8048 CODING EXAMPLE
Mnemonic Instruction
START: ANL P1,
Ý
0F7H ;SELECT A/D (CSe0)
MOV B,
Ý
5 ;BIT COUNTERw5
MOV A,
Ý
ADDR ;AwMUX ADDRESS
LOOP 1: RRC A ;CY
w
ADDRESS BIT
JC ONE ;TEST BIT
;BIT
e
0
ZERO: ANL P1,
Ý
0FEH ;DIw0
JMP CONT ;CONTINUE
;BIT
e
1
ONE: ORL P1,
Ý
1 ;DIw1
CONT: CALL PULSE ;PULSE SK 0
x1x
0
DJNZ B, LOOP 1 ;CONTINUE UNTIL DONE
CALL PULSE ;EXTRA CLOCK FOR SYNC
MOV B,
Ý
8 ;BIT COUNTERw8
LOOP 2: CALL PULSE ;PULSE SK 0
x1x
0
IN A, P1 ;CY
w
DO
RRC A
RRC A
MOV A, C ;A
w
RESULT
RLC A ;A(0)
w
BIT AND SHIFT
MOV C, A ;C
w
RESULT
DJNZ B, LOOP 2 ;CONTINUE UNTIL DONE
RETR
;PULSE SUBROUTINE
PULSE: ORL P1,
Ý
04 ;SKw1
NOP ;DELAY
ANL P1,
Ý
0FBH ;SKw0
RET
14
Applications (Continued)
A ‘‘Stand-Alone’’ Hook-Up for ADC0833 Evaluation
Low Cost Remote Temperature Sensor
TL/H/5607– 11
15
Applications (Continued)
Digitizing a Current Flow
Operating with Automotive Ratiometric Transducers
*VIN(b)e0.15 V
CC
15% of V
CC
s
V
XDR
s
85% of V
CC
TL/H/5607– 12
16
Applications (Continued)
Span Adjust: OV
s
V
IN
s
3V
TL/H/5607– 18
Zero-Shift and Span Adjust: 2VsV
IN
s
5V
TL/H/5607– 19
Protecting the Input
Diodes are 1N914
TL/H/5607– 20
High Accuracy Comparators
DOeall 1s ifaV
IN
l
b
V
IN
DOeall 0s ifaV
IN
k
b
V
IN
TL/H/5607– 13
For additional application ideas, refer to the data sheet for the ADC0831 family of serial data converters.
17
Ordering Information
Temperature
Total
Part Number
Range
Unadjusted
Error
ADC0833BCN 0§Ctoa70§C
g
1/2 LSB
ADC0833CCJ
b
40§Ctoa85§C
g
1 LSB
ADC0833CCN 0§Ctoa70§C
18
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number ADC0833CCJ
NS Package Number J14A
19
ADC0833 8-Bit Serial I/O A/D Converter with 4-Channel Multiplexer
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number ADC0833BCN or ADC0833CCN
NS Package Number N14A
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