Page 1
TL/H/11015
ADC08231/ADC08234/ADC08238 8-Bit 2 ms Serial I/O A/D Converters
with MUX, Reference, and Track/Hold
December 1994
ADC08231/ADC08234/ADC08238 8-Bit 2 ms Serial I/O
A/D Converters with MUX, Reference, and Track/Hold
General Description
The ADC08231/ADC08234/ADC08238 are 8-bit successive approximation A/D converters with serial I/O and configurable input multiplexers with up to 8 channels. The serial
I/O is configured to comply with the NSC MICROWIRE
TM
serial data exchange standard for easy interface to the
COPS
TM
family of controllers, and can easily interface with
standard shift registers or microprocessors.
Designed for high-speed/low-power applications, the devices are capable of a fast 2 ms conversion when used with a
4 MHz clock.
All three devices provide a 2.5V band-gap derived reference
with guaranteed performance over temperature.
A track/hold function allows the analog voltage at the positive input to vary during the actual A/D conversion.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differential modes. In addition, input voltage spans as small as 1V
can be accommodated.
Applications
Y
High-speed data acquisition
Y
Digitizing automotive sensors
Y
Process control/monitoring
Y
Remote sensing in noisy environments
Y
Disk drives
Y
Portable instrumentation
Y
Test systems
Features
Y
Serial digital data link requires few I/O pins
Y
Analog input track/hold function
Y
4- or 8-channel input multiplexer options with address
logic
Y
On-chip 2.5V band-gap reference (g2% over temperature guaranteed)
Y
No zero or full scale adjustment required
Y
TTL/CMOS input/output compatible
Y
0V to 5V analog input range with single 5V power
supply
Y
Pin compatible with Industry-Standards ADC0831/4/8
Key Specifications
Y
Resolution 8 Bits
Y
Conversion time (f
C
e
4 MHz) 2 ms (Max)
Y
Power dissipation 20 mW (Max)
Y
Single supply 5 VDC(g5%)
Y
Total unadjusted error
g
(/2 LSB andg1 LSB
Y
Linearity Error (V
REF
e
2.5V)
g
(/2 LSB
Y
No missing codes (over temperature)
Y
On-board Reference
a
2.5Vg1.5% (Max)
ADC08238 Simplified Block Diagram
TL/H/11015– 4
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
COPS
TM
microcontrollers and MICROWIRETMare trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Page 2
Ordering Information
Industrial
Package
(
b
40§CsT
A
s
a
85§C)
ADC08231BIN, ADC08231CIN N08E, DIP
ADC08234BIN, ADC08234CIN N14A, DIP
ADC08234CIMF MTB24, TSSOP
ADC08238BIN, ADC08238CIN N20A, DIP
ADC08231BIWM, ADC08231CIWM M14B, SO
ADC08234BIWM, ADC08234CIWM M14B, SO
ADC08238BIWM, ADC08238CIWM M20B, SO
Connection Diagrams
ADC08238
SO and DIP
TL/H/11015– 1
ADC08231
DIP
TL/H/11015– 3
ADC08231
SO
TL/H/11015– 26
ADC08234
SO and DIP
TL/H/11015– 2
ADC08234
TSSOP
TL/H/11015– 27
2
Page 3
Absolute Maximum Ratings (Notes1&3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
) 6.5V
Voltage at Inputs and Outputs
b
0.3V to V
CC
a
0.3V
Input Current at Any Pin (Note 4)
g
5mA
Package Input Current (Note 4)
g
20 mA
Power Dissipation at T
A
e
25§C (Note 5) 800 mW
ESD Susceptibility (Note 6) 1500V
Soldering Information
N Package (10 sec.) 260
§
C
TSSOP and SO Package (Note 7):
Vapor Phase (60 sec.) 215
§
C
Infrared (15 sec.) 220
§
C
Storage Temperature
b
65§Ctoa150§C
Operating Ratings (Notes2&3)
Temperature Range T
MIN
s
T
A
s
T
MAX
ADC08231BIN, ADC08231CIN,
b
40§CsT
A
s
a
85§C
ADC08234BIN, ADC08234CIN,
ADC08238BIN, ADC08238CIN,
ADC08231BIWM, ADC08231CIWM,
ADC08234BIWM, ADC08238BIWM,
ADC08234CIWM, ADC08238CIWM,
ADC08234CIMF
Supply Voltage (V
CC
) 4.5 VDCto 6.3 V
DC
Electrical Characteristics
The following specifications apply for V
CC
ea
5VDC,V
REF
ea
2.5 VDCand f
CLK
e
4 MHz, R
Source
e
50X unless otherwise
specified. Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25§C.
ADC08231,
ADC08234 and
ADC08238 with BIN,
Units
Symbol Parameter Conditions CIN, BIWM,
(Limits)
CIWM, or CIMF Suffixes
Typical Limits
(Note 8) (Note 9)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Linearity Error V
REF
ea
2.5 V
DC
BIN, BIWM
g
(/2 LSB (max)
CIN, CIMF, CIWM
g
1 LSB (max)
Gain Error V
REF
ea
2.5 V
DC
BIN, BIWM
g
1 LSB (max)
CIN, CIMF, CIWM
g
1 LSB (max)
Zero Error V
REF
ea
2.5 V
DC
BIN, BIWM
g
1 LSB (max)
CIN, CIMF, CIWM
g
1 LSB (max)
Total Unadjusted Error V
REF
ea
5V
DC
BIN, BIWM (Note 10)
g
1 LSB (max)
CIN, CIMF, CIWM
g
1 LSB (max)
Differential Linearity V
REF
ea
2.5 V
DC
8 Bits (min)
R
REF
Reference Input Resistance (Note 11) 3.5 kX
1.3 kX (min)
6.0 kX (max)
V
IN
Analog Input Voltage (Note 12) (V
CC
a
0.05) V (max)
(GND
b
0.05) V (min)
3
Page 4
Electrical Characteristics (Continued)
The following specifications apply for V
CC
ea
5VDC,V
REF
ea
2.5 VDCand f
CLK
e
4 MHz, R
source
e
50X unless otherwise
specified. Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25§C.
ADC08231,
ADC08234 and
ADC08238 with BIN,
Units
Symbol Parameter Conditions CIN, BIWM,
(Limits)
CIWM, or CIMF Suffixes
Typical Limits
(Note 8) (Note 9)
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
DC Common-Mode Error V
REF
ea
2.5 V
DC
g
(/2 LSB (max)
Power Supply Sensitivity V
CC
ea
5Vg5%,
g
(/4 LSB (max)
V
REF
ea
2.5 V
DC
On Channel Leakage On Channele5V, 0.2
mA (max)
Current (Note 13) Off Channel
e
0V 1
On Channele0V,
b
0.2
mA (max)
Off Channele5V
b
1
Off Channel Leakage On Channele5V,
b
0.2
mA (max)
Current (Note 13) Off Channel
e
0V
b
1
On Channele0V, 0.2
mA (max)
Off Channel
e
5V 1
DYNAMIC CHARACTERISTICS (see Typical Converter Performance Characteristics)
S
NaD
Signal-to- V
REF
ea
5V
(Noise
a
Distortion) Sample Ratee286 kHz
Ratio V
IN
ea
5V
p-p
f
IN
e
10 kHz 48.35 dB
f
IN
e
50 kHz 48.00 dB
f
IN
e
100 kHz 47.40 dB
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
Logical ‘‘1’’ Input Voltage V
CC
e
5.25V 2.0 V (min)
V
IN(0)
Logical ‘‘0’’ Input Voltage V
CC
e
4.75V 0.8 V (max)
I
IN(1)
Logical ‘‘1’’ Input Current V
IN
e
5.0V 1 mA (max)
I
IN(0)
Logical ‘‘0’’ Input Current V
IN
e
0V
b
1 mA (max)
V
OUT(1)
Logical ‘‘1’’ Output Voltage V
CC
e
4.75V:
I
OUT
eb
360 mA 2.4 V (min)
I
OUT
eb
10 mA 4.5 V (min)
V
OUT(0)
Logical ‘‘0’’ Output Voltage V
CC
e
4.75V 0.4 V (max)
I
OUT
e
1.6 mA
I
OUT
TRI-STATEÉOutput Current V
OUT
e
0V
b
3.0 mA (max)
V
OUT
e
5V 3.0 mA (max)
I
SOURCE
Output Source Current V
OUT
e
0V
b
6.5 mA (min)
I
SINK
Output Sink Current V
OUT
e
V
CC
8.0 mA (min)
I
CC
Supply Current CSeHIGH
ADC08234, ADC08238 3.0 mA (max)
ADC08231 (Note 16) 6.0 mA (max)
4
Page 5
Electrical Characteristics (Continued)
The following specifications apply for V
CC
ea
5VDCand f
CLK
e
4 MHz unless otherwise specified. Boldface limits apply for
T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25§C.
ADC08231,
ADC08234 and
ADC08238 with BIN,
Units
Symbol Parameter Conditions CIN, BIWM,
(Limits)
CIWM, or CIMF Suffixes
Typical Limits
(Note 8) (Note 9)
REFERENCE CHARACTERISTICS
V
REF
OUT Output Voltage BIN, BIJ, 2.5
2.5
g
1.5%
V
BIWM
g
2%
CIN, CIJ, 2.5
2.5
g
3.0%
CIWM, CMJ
g
3.5%
DV
REF
/DT Temperature Coefficient 40 ppm/§C
DV
REF
/DI
L
Load Regulation Sourcing
%/mA
(max)
(Note 17) (0sI
L
s
a
4 mA)
ADC08234,
0.003 0.1
ADC08238
Sourcing
(0
s
I
L
s
a
2 mA)
ADC08231 0.003 0.1
Sinking
(b1sI
L
s
0 mA)
ADC08234,
0.2 0.5
ADC08238
Sinking
(
b
1sI
L
s
0 mA)
ADC08231 0.2 0.5
Line Regulation 4.75VsV
CC
s
5.25V
0.5 6
mV
(max)
I
SC
Short Circuit Current V
REF
e
0V
(max)
mA
ADC08234,
8 25
ADC08238
V
REF
e
0V
ADC08231 8 25
T
SU
Start-Up Time VCC:0Vx5V
20 ms
C
L
e
100 mF
DV
REF
/Dt Long Term Stability 200 ppm/1 kHr
5
Page 6
Electrical Characteristics (Continued)
The following specifications apply for V
CC
ea
5VDC,V
REF
ea
2.5 VDCand t
r
e
t
f
e
20 ns unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25§C.
Symbol Parameter Conditions
Typical Limits Units
(Note 8) (Note 9) (Limits)
f
CLK
Clock Frequency 10 kHz (min)
4 MHz (max)
Clock Duty Cycle 40 % (min)
(Note 14) 60 % (max)
T
C
Conversion Time (Not Including f
CLK
e
4 MHz 8 1/f
CLK
(max)
MUX Addressing Time) 2 ms (max)
t
CA
Acquisition Time 1(/2 1/f
CLK
(max)
t
SELECT
CLK High while CS is High 50 ns
t
SET-UP
CS Falling Edge or Data Input
25 ns (min)
Valid to CLK Rising Edge
t
HOLD
Data Input Valid after CLK
20 ns (min)
Rising Edge
t
pd1,tpd0
CLK Falling Edge to Output C
L
e
100 pF:
Data Valid (Note 15) Data MSB First 250 ns (max)
Data LSB First 200 ns (max)
t1H,t
0H
TRI-STATE Delay from Rising Edge C
L
e
10 pF, R
L
e
10 kX
50 ns
of CS
to Data Output and SARS Hi-Z (see TRI-STATE Test Circuits)
C
L
e
100 pF, R
L
e
2kX 180 ns (max)
C
IN
Capacitance of Logic Inputs 5 pF
C
OUT
Capacitance of Logic Outputs 5 pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to AGND
e
DGNDe0VDC, unless otherwise specified.
Note 4: When the input voltage (V
IN
) at any pin exceeds the power supplies (V
IN
k
(AGND or DGND) or V
IN
l
AVCC,) the current at that pin should be limited to
5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four
pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
J
MAX
, iJAand the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is P
D
e
(T
J
MAX
b
TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For devices
with suffixes BIN, CIN, BIJ, CIJ, BIWM, and CIWM T
J
MAX
e
125§C. For devices with suffix CMJ, T
J
MAX
e
150§C. The typical thermal resistances (iJA) of these
parts when board mounted follow: ADC08231 with BIN and CIN suffixes 120
§
C/W, ADC08234 with BIN and CIN suffixes 95§C/W, ADC08234 with CIMF suffix
167
§
C/W, ADC08238 with BIN and CIN suffixes 80§C/W. ADC08231 with BIWM and CIWM suffixes 140§C/W, ADC08234 with BIWM and CIWM suffixes 140§C/W,
ADC08238 with BIWM and CIWM suffixes 91
§
C/W,
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kX resistor.
Note 7: See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or
Linear Data Book
section ‘‘Surface Mount’’ for other methods of
soldering surface mount devices.
Note 8: Typicals are at T
J
e
25§C and represent the most likely parametric norm.
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with V
REF
ea
5V only applies to the ADC08234
and ADC08238. See Note 16.
Note 11: Cannot be tested for the ADC08231.
Note 12: For V
IN(b)
t
V
IN(a)
the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct
for analog input voltages one diode drop below ground or one diode drop greater than V
CC
supply. During testing at low VCClevels (e.g., 4.5V), high level analog
inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification
allows 50 mV forward bias of either diode; this means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code will
be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V
DC
to5VDCinput voltage
range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading.
Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (5 V
DC
) and the remaining off channels tied low (0 VDC), total current flow through the off
channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these
limits the minimum time the clock is high or low must be at least 120 ns. The maximum time the clock can be high or low is 100 m s.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to
allow for comparator response time.
Note 16: For the ADC08231 V
REF
IN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger because it includes the
reference current (700 mA typical, 2 mA maximum).
Note 17: Load regulation test conditions and specifications for the ADC08231 differ from those of the ADC08234 and ADC08238 because the ADC08231 has the
on-board reference as a permanent load.
6
Page 7
Typical Performance Characteristics
Reference Voltage
Linearity Error vs
Temperature
Linearity Error vs
Clock Frequency
Linearity Error vs
ADC08234)
Temperature (ADC08238,
Power Supply Current vs
Temperature
Output Current vs
vs Clock Frequency
Power Supply Current
Note: For ADC08231 add I
REF
(Note 16) TL/H/11015– 5
10 kHz Sine Wave Input
Spectral Response with
50 kHz Sine Wave Input
Spectral Response with
100 kHz Sine Wave Input
Spectral Response with
Ratio vs Input Frequency
Signal-to-Noise
a
Distortion
TL/H/11015– 6
7
Page 8
Typical Reference Performance Characteristics
Load Regulation (3 Typical Parts)
Line Regulation
(3 Typical Parts)
vs Temperature
Output Drift
vs Supply Voltage
Output Current
Available
TL/H/11015– 7
8
Page 9
TRI-STATE Test Circuits and Waveforms
t
1H
t
0H
TL/H/11015– 8
t
1H
t
0H
TL/H/11015– 9
Timing Diagrams
Data Input Timing
TL/H/11015– 10
*To reset these devices, CLK and CS must be simultaneously high for a period of t
SELECT
or greater.
Data Output Timing
TL/H/11015– 11
ADC08231 Start Conversion Timing
TL/H/11015– 12
9
Page 10
Timing Diagrams (Continued)
ADC08231 Timing
TL/H/11015– 13
*LSB first output not available on ADC08231.
LSB information is maintained for remainder of clock periods until CS
goes high.
To reset the ADC08231, CLK and CS
must be simultaneusly high for a period of t
SELECT
or greater. The ADC08231 also has one extra clock period for sampling
the analog signal (t
ca
). Otherwise it is compatible with the ADC0831.
ADC08234 Timing
TL/H/11015– 14
To reset the ADC08234, CLK and CS must be simultaneously high for a period of t
SELECT
or greater. The ADC08234 also has one extra clock period for sampling
the analog signal (t
ca
). Otherwise it is compatible with the ADC0834.
10
Page 11
Timing Diagrams (Continued)
ADC08238 Timing
TL/H/11015– 15
*Make sure clock edge
Ý
19 clocks in the LSB before SE is taken low
To reset the ADC08238, CLK and CS
must be simultaneously high for a period of t
SELECT
or greater. The ADC08238 also has one extra clock period for sampling the analog signal (t
ca
). Otherwise it is compatible with the ADC0838.
11
Page 12
ADC08238 Functional Block Diagram
TL/H/11015– 16
*Some of these functions/pins are not available with other options.
Note 1: For the ADC08234, the ‘‘SEL 1’’ Flip-Flop is bypassed. For the ADC08231, V
REFOUT
and V
REFIN
are internally tied together.
12
Page 13
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a comparator structure with built-in sample-and-hold which provides for a differential analog input to be converted by a successiveapproximation routine.
The actual voltage converted is always the difference between an assigned ‘‘
a
’’ input terminal and a ‘‘b’’ input terminal. The polarity of each input terminal of the pair indicates which line the converter expects to be the most positive. If the assigned ‘‘
a
’’ input voltage is less than the ‘‘b’’
input voltage the converter responds with an all zeros output code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog
input and a common terminal) operation. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential. Differential inputs are restricted to adjacent channel
pairs. For example, channel 0 and channel 1 may be selected as a differential pair but channel 0 or 1 cannot act
differentially with any other channel. In addition to selecting
differential mode the polarity may also be selected. Channel
0 may be selected as the positive input and channel 1 as
the negative input or vice versa. This programmability is
best illustrated by the MUX addressing codes shown in the
following tables for the various product options.
The MUX address is shifted into the converter via the DI
line. Because the ADC08231 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.
The common input line (COM) on the ADC08238 can be
used as a pseudo-differential input. In this mode the voltage
on this pin is treated as the ‘‘
b
’’ input for any of the other
input channels. This voltage does not have to be analog
ground; it can be any reference potential which is common
to all of the inputs. This feature is most useful in single-supply applications where the analog circuitry may be biased up
to a potential other than ground and the output signals are
all referred to this potential.
TABLE I. Multiplexer/Package Options
Part Number of Analog Channels Number of
Number
Single-Ended Differential
Package Pins
ADC08231 1 1 8
ADC08234 4 2 14
ADC08238 8 4 20
TABLE II. MUX Addressing: ADC08238
Single-Ended MUX Mode
MUX Address Analog Single-Ended Channel
Ý
START
SGL/ ODD/ SELECT
01234567COM
DIF SIGN
10
11000
a b
11001
ab
11010
ab
11011
ab
11100
ab
11101
ab
11110
ab
11111
ab
13
Page 14
Functional Description (Continued)
TABLE II. MUX Addressing: ADC08238 (Continued)
Differential MUX Mode
MUX Address Analog Differential Channel-Pair
Ý
START
SGL/ ODD/ SELECT 0 1 2 3
DIF SIGN
1001234567
10000
ab
10001
ab
10010
ab
10011
ab
10100
ba
10101
ba
10110
ba
10111
ba
TABLE III. MUX Addressing: ADC08234
Single-Ended MUX Mode
MUX Address Channel
Ý
START
SGL/ ODD/ SELECT
0123
DIF SIGN
1
110 0
a
110 1
a
111 0
a
111 1
a
COM is internally tied to AGND
Differential MUX Mode
MUX Address Channel
Ý
START
SGL/ ODD/ SELECT
0123
DIF SIGN
1
100 0
ab
100 1
ab
101 0
ba
101 1
ba
14
Page 15
Functional Description (Continued)
Since the input configuration is under software control, it
can be modified as required before each conversion. A
channel can be treated as a single-ended, ground referenced input for one conversion; then it can be reconfigured
as part of a differential channel for another conversion.
Fig-
ure 1
illustrates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50mV below ground to 50mV above V
CC
(typically 5V) with-
out degrading conversion accuracy.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.
1. A conversion is initiated by pulling the CS
(chip select)
line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
2. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register.
The start bit is the first logic ‘‘1’’ that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX
assignment word.
8 Single-Ended 8 Pseudo-Differential
4 Differential Mixed Mode
TL/H/11015– 17
FIGURE 1. Analog Input Multiplexer Options for the ADC08238
15
Page 16
Functional Description (Continued)
3. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of 1(/2
clock periods is automatically inserted to allow for sampling the analog input. The SARS line goes high at the
end of this time to signal that a conversion is now in progress and the DI line is disabled (it no longer accepts
data).
4. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero.
5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages generated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator’s output is shipped to the DO line on the
falling edge of CLK. This data is the result of the conversion being shifted out (with the MSB first) and can be
read by the processor immediately.
6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this (/2 clock cycle later.
7. The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers, the data can be provided in an LSB first format
[
this makes use of the shift enable (SE
) control line].On
the ADC08238 the SE
line is brought out and if held high
the value of the LSB remains valid on the DO line. When
SE
is forced low the data is clocked out LSB first. On
devices which do not include the SE
control line, the
data, LSB first, is automatically shifted out the DO line
after the MSB first data stream. The DO line then goes
low and stays low until CS
is returned high. The
ADC08231 is an exception in that its data is only output in
MSB first format.
8. All internal registers are cleared when the CS
line is high
and the t
SELECT
requirement is met. See Data Input Timing under Timing Diagrams. If another conversion is desired CS
must make a high to low transition followed by
address information.
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.
This is possible because the DI input is only ‘‘looked-at’’
during the MUX addressing interval while the DO line is
still in a high impedance state.
3.0 REFERENCE CONSIDERATIONS
The V
REF
IN pin on these converters is the top of a resistor
divider string and capacitor array used for the successive
approximation conversion. The voltage applied to this reference input defines the voltage span of the analog input (the
difference between V
IN(MAX)
and V
IN(MIN)
over which the
256 possible output codes apply). The reference source
must be capable of driving the reference input resistance,
which can be as low as 1.3 kX.
For absolute accuracy, where the analog input varies between specific voltage limits, the reference input must be
biased with a stable voltage source. The ADC08234 and the
ADC08238 provide the output of a 2.5V band-gap reference
at V
REF
OUT. This voltage does not vary appreciably with
temperature, supply voltage, or load current (see Reference
Characteristics in the Electrical Characteristics tables) and
can be tied directly to V
REF
IN for an analog input span of 0V
to 2.5V. This output can also be used to bias external circuits and can therefore be used as the reference in ratiometric applications. Bypassing V
REF
OUT with a 100 mF ca-
pacitor is recommended.
For the ADC08231, the output of the on-board reference is
internally tied to the reference input. Consequently, the analog input span for this device is set at 0V to 2.5V. The pin
V
REF
C is provided for bypassing purposes and biasing ex-
ternal circuits as suggested above.
The maximum value of the reference is limited to the V
CC
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals V
REF/
256).
TL/H/11015– 18
a) Ratiometric
TL/H/11015– 19
b) Absolute
FIGURE 2. Reference Examples
16
Page 17
Functional Description (Continued)
4.0 THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected ‘‘
a
’’ and ‘‘b’’ inputs for a conversion
(60 Hz is most typical). The time interval between sampling
the ‘‘
a
’’ input and then the ‘‘b’’ input is (/2 of a clock period. The change in the common-mode voltage during this
short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:
V
error
(max)eV
PEAK
(2qfCM)
#
0.5
f
CLK
J
where fCMis the frequency of the common-mode signal,
V
PEAK
is its peak voltage value
and f
CLK
is the A/D clock frequency.
For a 60Hz common-mode signal to generate a (/4 LSB error (&5mV) with the converter running at 250kHz, its peak
value would have to be 6.63V which would be larger than
allowed as it exceeds the maximum analog input limits.
Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. While operating near or at maximum speed, bypass capacitors should
not be used if the source resistance is greater than 1kX.
The worst-case leakage current of
g
1mA over temperature
will create a 1mV input error with a 1kX source resistance.
An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required.
5.0 OPTIONAL ADJUSTMENTS
5.1 Zero Error
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V
IN(MIN)
, is not ground
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any V
IN
(b) input at this V
IN(MIN)
value. This
utilizes the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be measured by grounding the V
IN
(b) input and applying a small
magnitude positive voltage to the V
IN
(a) input. Zero error
is the difference between the actual DC input voltage which
is necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal (/2 LSB value
((/2 LSB
e
9.8mV for V
REF
e
5.000VDC).
5.2 Full Scale
A full-scale adjustment can be made by applying a differential input voltage which is 1(/2 LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the V
REF
IN input for a digital output code which is
just changing from 1111 1110 to 1111 1111 (See figure entitled ‘‘Span Adjust; 0V
s
V
IN
s
3V’’). This is possible only
with the ADC08234 and ADC08238. (The reference is internally connected to V
REF
IN of the ADC08231).
5.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A V
IN
(a) voltage which
equals this desired zero reference plus (/2 LSB (where the
LSB is calculated for the desired analog span, using 1 LSB
e
analog span/256) is applied to selected ‘‘a’’ input and
the zero reference voltage at the corresponding ‘‘
b
’’ input
should then be adjusted to just obtain the 00
HEX
to 01
HEX
code transition.
The full-scale adjustment should be made[with the proper
V
IN
(b) voltage applied]by forcing a voltage to the VIN(a)
input which is given by:
V
IN
(a)fsadjeV
MAX
b
1.5
Ð
(V
MAX
b
V
MIN
)
256
(
where:
V
MAX
e
the high end of the analog input range
and
V
MIN
e
the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The V
REF
IN (or VCC) voltage is then adjusted to provide a
code change from FE
HEX
to FF
HEX
. This completes the ad-
justment procedure.
17
Page 18
Applications
A ‘‘Stand-Alone’’ Hook-Up for ADC08238 Evaluation
*Pinouts shown for ADC08238.
For all other products tie to pin functions as shown.
Low-Cost Remote Temperature Sensor
TL/H/11015– 21
18
Page 19
Applications (Continued)
Protecting the Input
Diodes are 1N914
TL/H/11015– 22
Operating with Ratiometric Transducers
*VIN(b)e0.15 V
REF
15% of V
REF
s
V
XDR
s
85% of V
REF
TL/H/11015– 23
Span Adjust; 0VsV
IN
s
3V
TL/H/11015– 24
19
Page 20
Applications (Continued)
Zero-Shift and Span Adjust: 2V
s
V
IN
s
5V
TL/H/11015– 25
20
Page 21
Physical Dimensions inches (millimeters)
Order Number ADC08231BIWM, ADC08231CIWM,
ADC08234BIWM or ADC08234CIWM
NS Package Number M14B
Order Number ADC08238BIWM or ADC08238CIWM
NS Package Number M20B
21
Page 22
Physical Dimensions inches (millimeters) (Continued)
TSSOP Molded Package
Order Number ADC08234CIMF
NS Package Number MTB24
Order Number ADC08231BIN or ADC08231CIN
NS Package Number N08E
22
Page 23
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number ADC08234BIN or ADC08234CIN
NS Package Number N14A
23
Page 24
ADC08231/ADC08234/ADC08238 8-Bit 2 ms Serial I/O A/D Converters
with MUX, Reference, and Track/Hold
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number ADC08238CIN or ADC08238BIN
NS Package Number N20A
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