How it Works
Datasheet
Loading...
ADC08161CIN
Datasheet (NSC)
15 pgs262.7 Kb0

Datasheet ADC08161CIN, ADC08161BIWMX, ADC08161BIWM, ADC08161BIN Datasheet (NSC)

Download
Page 1
ADC08161 500 ns A/D Converter with S/H Function and
2.5V Bandgap Reference
General Description
Using a patented multi-step A/D conversion technique, the 8-bit ADC08161 CMOS A/D converter offers 500 ns conver­sion time, internal sample-and-hold (S/H), a 2.5V bandgap reference, and dissipates only 100 mW of power. The ADC08161 performs an 8-bit conversion with a 2-bit voltage estimator that generates the 2 MSBs and two low-resolution (3-bit) flashes that generate the 6 LBSs.
Input signals are tracked and held by the input sampling circuitry, eliminating the need for an external sample-and-hold. TheADC08161 can perform accurate con­versions of full-scale input signals at frequencies from DC to typically more than 300 kHz (full power bandwidth) without the need of an external sample-and-hold (S/H).
For ease of interface to microprocessors, this part has been designed to appear as a memory location or I/O port without the need for external interfacing logic.
Key Specifications
n Resolution 8 Bits n Conversion time (t
CONV
) 560 ns max (WR-RD Mode)
n Full power bandwidth 300 kHz (typ) n Throughput rate 1.5 MHz min n Power dissipation 100 mW max n Total unadjusted error
±
1
⁄2LSB and±1 LSB max
Features
n No external clock required n Analog input voltage range from GND to V
+
n 2.5V bandgap reference
Applications
n Mobile telecommunications n Hard-disk drives n Instrumentation n High-speed data acquisition systems
Block Diagram
DS011149-1
June 1999
ADC08161 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference
© 2001 National Semiconductor Corporation DS011149 www.national.com
Page 2
Connection Diagram
Ordering Information
Industrial (−40˚C ≤ TA≤ 85˚C) Package
ADC08161CIWM M20B
Pin Description
V
IN
This is the analog input. The input range is GND–50 mV ≤ V
INPUT
≤ V++50mV.
DB0–DB7 TRI-STATE data outputs—bit 0 (LSB)
through bit 7 (MSB).
WR /RDY
WR-RD Mode (Logic high applied to MODE pin)
WR: With CS low, the conversion is started on the rising edge of WR. The digital result will be strobed into the output latch at the end of conversion (
Figures 2,
3, 4
).
RD Mode (Logic low applied to MODE pin)
RDY: This is an open drain output (no internal pull-up device). RDY will go low after the falling edge of CS and returns high at the end of conversion.
MODE Mode: Mode (RD or WR-RD ) selection
input– This pin is pulled to a logic low through an internal 50 µA current sink when left unconnected.
RD Mode is selected if the MODE pin is left unconnected or externally forced low. Acomplete conversion is accomplished by pulling RD low until output data appears.
WR-RD Mode is selected when a high is applied to the MODE pin. A conversion starts with the WR signal’s rising edge and then using RD to access the data.
RD WR-RD Mode (logic high on the MODE
pin) This is the active low Read input. With a
logic low applied to the CS pin, the TRI-STATE data outputs (DB0–DB7) will be activated when RD goes low (
Figures
2, 3, 4
).
RD Mode (logic low on the MODE pin) With CS low, a conversion starts on the
falling edge of RD. Output data appears on DB0–DB7 at the end of conversion (
Figures 1, 5
).
INT
This is an active low output that indicates that a conversion is complete and the data is in the output latch. INT is reset by the rising edge of RD.
GND This is the power supply ground pin. The
ground pin should be connected to a “clean” ground reference point.
V
REF−,VREF+
These are the reference voltage inputs. They may be placed at any voltage be­tween GND − 50 mV and V
+
+50mV,but
V
REF+
must be greater than V
REF−
. Ideally,
an input voltage equal to V
REF−
produces an output code of 0, and an input voltage greater than V
REF+
− 1.5 LSB produces an
output code of 255. For the ADC08161 an input voltage that
exceeds V
+
by more than 100 mV or is below GND by more than 100 mV will create conversion errors.
CS
This is the active low Chip Select input. A logic low signal applied to this input pin enables the RD and WR inputs. Internally, the CS signal is ORed with RD and WR signals.
OFL
Overflow Output. If the analog input is higher than V
REF+
, OFL will be low at the end of conversion. It can be used when cascading two ADC08161s to achieve higher resolution (9 bits). This output is always active and does not go into TRI-STATE as DB0–DB7 do. When OFL is set, all data outputs remain high when the ADC08061’s output data is read.
V
+
Positive power supply voltage input. Nomi­nal operating supply voltage is +5V. The supply pin should be bypassed with a 10 µF bead tantalum in parallel with a 0.1 ceramic capacitor. Lead length should be as short as possible.
V
REFOUT
The internal bandgap reference’s 2.5V output is available on this pin. Use a 220 µF bypass capacitor between this pin and analog ground.
Wide-Body Small-Outline Package
DS011149-14
See NS Package Number M20B
ADC08161
www.national.com 2
Page 3
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (V
+
)6V
Logic Control Inputs −0.3V to V
+
+ 0.3V
Voltage at Other Inputs and Outputs −0.3V to V
+
+ 0.3V Input Current at Any Pin (Note 3) 5 mA Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4) 875 mW Lead Temperature (Note 5)
(Vapor Phase, 60 sec.) +215˚C
(Infrared, 15 sec.) +220˚C Storage Temperature −65˚C to +150˚C ESD Susceptibility (Note 6) 750V
Operating Ratings(Notes 1, 2)
Temperature Range T
MIN
≤ TA≤ T
MAX
ADC08161CIWM −40˚C ≤ TA≤ 85˚C Supply Voltage, (V
+
) 4.5V to 5.5V
Converter Characteristics
The following specifications apply for RD Mode, V+= 5V, V
REF+
= 5V, and V
REF−
= GND unless otherwise specified. Boldface
limits apply for TA=TJ=T
MIN
to T
MAX
; all other limits TA=TJ= 25˚C.
Symbol Parameter Conditions Typical Limits Units
(Note 7) (Note 8) (Limit)
INL Integral Non Linearity V
REF
=5V
±
1 LSB (max)
TUE Total Unadjusted Error (Note 9) V
REF
=5V
±
1 LSB (max)
INL Integral Non Linearity V
REF
= 2.5V
±
1 LSB (max)
TUE Total Unadjusted Error V
REF
= 2.5V
±
1 LSB (max)
Missing Codes V
REF
=5V 0 Bits (max)
V
REF
= 2.5V 0 Bits (max)
Reference Input Resistance 700 500 Ω (min)
700 1250 Ω (max)
V
REF+
Positive Reference Input Voltage V
REF−
V (min)
V
+
V (max)
V
REF−
Negative Reference GND V (min) Input Voltage V
REF+
V (max)
V
IN
Analog (Note 10) GND − 0.1 V (min) Input Voltage V
+
+ 0.1 V (max)
On-Channel Input Current On Channel Input = 5V,
Off Channel Input = 0V −0.4 −20 µA (max) (Note 11) On Channel Input = 0V, Off Channel Input = 5V −0.4 −20 µA (max) (Note 11)
PSS Power Supply Sensitivity V
+
=5V±5%,
V
REF
= 4.75V
±
1/16
±
1
⁄
2
LSB (max)
All Codes Tested
Effective Bits V
IN
= 4.85 V
p-p
7.8 Bits
f
IN
=20Hzto20kHz
Full-Power Bandwidth V
IN
= 4.85 V
p-p
300 kHz
THD Total Harmonic Distortion V
IN
= 4.85 V
p-p
0.5 %
f
IN
=20Hzto20kHz
S/N Signal-to-Noise Ratio V
IN
= 4.85 V
p-p
50 dB
f
IN
=20Hzto20kHz
IMD Intermodulation Distortion V
IN
= 4.85 V
p-p
50 dB
f
IN
=20Hzto20kHz
C
VIN
Analog Input Capacitance 25 pF
ADC08161
www.national.com3
Page 4
AC Electrical Characteristics
The following specifications apply for V+= 5V, tr=tf= 10 ns, V
REF+
= 5V, V
REF−
= 0V unless otherwise specified. Boldface
limits apply for T
A=TJ=TMIN
to T
MAX
; all other limits TA=TJ= 25˚C.
Symbol Parameter Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
t
WR
Write Time Mode Pin to V
+
100 100 ns (min)
(
Figures 2, 3, 4
)
t
RD
Read Time (Time from Rising Edge Mode Pin to V+,(
Figure 2
) 350 350 ns (min)
of WR to Falling Edge of RD )
t
RDW
RD Width Mode Pin to GND (
Figure 5
) 200 250 ns (min)
400 400 ns (max)
t
CONV
WR -RD Mode Conversion Time Mode Pin to V+,(
Figure 2
) 500 560 ns (max)
(t
WR+tRD+tACC1
)
t
CRD
RD Mode Conversion Time Mode Pin to GND, (
Figure 1
) 655 900 ns (max)
t
ACCO
Access Time (Delay from Falling CL≤ 100 pF, Mode Pin to GND 640 900 ns (max) Edge of RD to Output Valid)
(
Figure 1
)
t
ACC1
Access Time (Delay from CL≤ 10 pF 45 ns Falling Edge of RD
CL= 100 pF 50 110 ns (max)
to Output Valid) Mode Pin to V
+
,tRD≤ t
INTL
(
Figure 2
)
t
ACC2
Access Time (Delay from CL≤ 10 pF 25 ns Falling Edge of RD
CL= 100 pF 30 55 ns (max)
to Output Valid) t
RD
>
t
INTL
,
(
Figures 3, 5
)
t
1H,t0H
TRI-STATE Control RL=3kΩ,CL=10pF (Delay from Rising Edge (
Figures 1, 2, 3, 4, 5
)3060 ns (max)
of RD to HI-Z State)
t
INTL
Delay from Rising Edge of Mode Pin = V+,CL= 50 pF 520 690 ns (max) WR to Falling Edge of INT
(
Figures 3, 4
)
t
INTH
Delay from Rising Edge of CL= 50 pF, 50 95 ns (max) RD to Rising Edge of INT
(
Figures 1, 2, 3, 5
)
t
INTH
Delay from Rising Edge of CL= 50 pF, (
Figure 4
)4595 ns (max)
WR to Rising Edge of INT
t
RDY
Delay from CS to RDY Mode Pin = 0V, CL= 50 pF, 25 45 ns (max)
R
L
=3kΩ,(
Figure 1
)
t
ID
Delay from INT RL=3kΩ,CL= 100 pF 0 15 ns (max) to Output Valid (
Figure 4
)
t
RI
Delay from RD to INT Mode Pin = V+,tRD≤ t
INTL
60 115 ns (max)
(
Figure 2
)
t
N
Time between End of RD (
Figures 1, 2, 3, 4, 5
)5050 ns (min)
and Start of New Conversion
t
CSS
CS Setup Time (
Figures 1, 2, 3, 4, 5
)00ns (max)
t
CSH
CS Hold Time (
Figures 1, 2, 3, 4, 5
)00ns (max)
DC Electrical Characteristics
The following specifications apply for V+= 5V unless otherwise specified. Boldface limits apply for TA=TJ=T
MIN
to T
MAX
;
all other limits T
A=TJ
= 25˚C.
Symbol Parameter Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
V
IH
Logic “1” Input Voltage V+= 5.5 V
CS, WR, RD, A0, A1, A2 Pins
2.0 V (min)
Mode Pin 3.5
ADC08161
www.national.com 4
Page 5
DC Electrical Characteristics (Continued)
The following specifications apply for V+= 5V unless otherwise specified. Boldface limits apply for TA=TJ=T
MIN
to T
MAX
;
all other limits T
A=TJ
= 25˚C.
Symbol Parameter Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
V
IL
Logic “0” Input Voltage V+= 4.5V
CS, WR, RD, A0, A1, A2 Pins
0.8 V (max)
Mode Pin 1.5
I
IH
Logic “1” Input Current VH=5V
CS, RD, A0, A, A2 Pins
0.005 1
WR Pin
0.1 3 µA (max)
Mode Pin 50 200
I
IL
Logic “0” Input Current VL=0V
CS, RD, WR, A0, A1, A2 Mode Pins −0.005 −2 µA (max)
V
OH
Logic “1” Output Voltage V+= 4.75V
I
OUT
= −360 µA 2.4 V (min) DB0–DB7, OFL, INT I
OUT
= −10 µA 4.5 V (min) DB0–DB7, OFL, INT
V
OL
Logic “0” Output Voltage V+= 4.75V
I
OUT
= 1.6 mA 0.4 V (max) DB0–DB7, OFL, INT, RDY
I
O
TRI-STATE Output Current V
OUT
= 5.0V 0.1 3 µA (max) DB0–DB7, RDY V
OUT
= 0V −0.1 −3 µA (max) DB0–DB7, RDY
I
SOURCE
Output Source Current V
OUT
= 0V −26 −6 mA (min) DB0–DB7, OFL, INT
I
SINK
Output Sink Current V
OUT
=5V 24 7 mA (min) DB0–DB7, OFL, INT, RDY
I
C
Supply Current CS = WR = RD = 0 11.5 20 mA (max)
C
OUT
Logic Output Capacitance 5 pF
C
IN
Logic Input Capacitance 5 pF
Bandgap Reference Electrical Characteristics
The following specifications apply for V+= 5V unless otherwise specified. Boldface limits apply for T
MIN
to T
MAX
; all other
limits T
A=TJ
= 25˚C.
Symbol Parameter Conditions Typical Limits Units
(Note 7) (Note 8) (Limit)
V
REFOUT
Internal Reference Output Voltage 2.5±2.0% V (max)
∆V
REF
/∆T Internal Reference Temperature 40 ppm/˚C
Coefficient
∆V
REF
/∆ILInternal Reference Load Sourcing (0 ≤ IL≤ +10 mA) 0.01 0.1 %/mA (max)
Regulation Line Regulation 4.75V ≤ V
+
≤ 5.25V 0.5 6.0 mV (max)
I
SC
Short Circuit Current V
REV
= 0V 35 mA (max)
∆V
REF/∆t
Long Term Stability 200 ppm/kHr Start-Up Time V
+
:0V→5V, CL= 220 µF 40 ms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications do not apply when operating the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
ADC08161
www.national.com5
Page 6
Bandgap Reference Electrical Characteristics (Continued)
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified. Note 3: When the input voltage (V
IN
) at any pin exceeds the power supply voltage (V
IN
<
GND or V
IN
>
V+), the absolute value of the current at that pin should be limited to 5 mA or less. The 20 mA package input current specification limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.
Note 4: The power dissipation of this device under normal operation should never exceed 875 mW (Quiescent Power Dissipation + TTL Loads on the digital outputs). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (e.g., when any input or output exceeds the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
(maximum junction
temperature), θ
JA
(package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any temperature
is PD
max
=(T
JMAX−TA
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
JMAX
= 105˚C and θJA= 85˚C/W.
Note 5: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. Note 6: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Note 7: Typicals are at 25˚C and represent most likely parametric norm. Note 8: Limits are guaranteed to National’s AOQL (Average Output Quality Level). Note 9: Total unadjusted error includes offset, full-scale, and linearity errors. Note 10: Two on-chip diodes are tied to each analog input and are reversed biased during normal operation. One is connected to V
+
and the other is connected
to GND. They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V
+
or below GND. Therefore,
caution should be exercised when testing with V
+
= 4.5V. Analog inputs with magnitudes equal to 5V can cause an input diode to conduct, especially at elevated temperatures. This can create conversion errors for analog signals near full-scale. The specification allows 50 mV forward bias on either diode; e.g., the output code will be correct as long as the analog input signal does not exceed the supply voltage by more than 50 mV. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. An absolute analog input signal voltage range of 0V ≤ V
IN
≤ 5V can be achieved by ensuring that the minimum supply voltage
applied to V
+
is 4.950V over temperature variations, initial tolerance, and loading.
Note 11: Off-channel leakage current is measured on the on-channel selection.
ADC08161
www.national.com 6
Page 7
TRI-STATE Test Circuit and Waveforms
t
1H
DS011149-2
t1H,CL=10pF
DS011149-4
tr=10ns
t
0H
DS011149-3
t0H,CL=10pF
DS011149-5
tr=10ns
DS011149-6
FIGURE 1. RD Mode (Mode Pin is Low)
ADC08161
www.national.com7
Page 8
TRI-STATE Test Circuit and Waveforms (Continued)
DS011149-7
FIGURE 2. WR-RD Mode with tRD≤ t
INTL
(Mode Pin is High)
DS011149-8
FIGURE 3. WR-RD Mode with t
RD
>
t
INTL
(Mode Pin is High)
ADC08161
www.national.com 8
Page 9
TRI-STATE Test Circuit and Waveforms (Continued)
Typical Performance Characteristics
DS011149-9
FIGURE 4. WR-RD Mode Reduced Interface System Connection with CS = RD = 0 (Mode Pin is High)
DS011149-10
FIGURE 5. RD Mode (Pipeline Operation); t
RDW
must be between 200 ns and 400 ns.
(Mode Pin is Low)
t
CRD
vs Temperature
DS011149-23
Linearity Error vs Reference Voltage
DS011149-24
Offset Error vs Reference Voltage
DS011149-25
ADC08161
www.national.com9
Page 10
Typical Performance Characteristics (Continued)
Supply Current vs Temperature
DS011149-26
Reference Output Voltage vs Temperature
DS011149-27
Logic Threshold vs Temperature
DS011149-28
Output Current vs Temperature
DS011149-29
ADC08161
www.national.com 10
Page 11
Application Information
1.0 FUNCTIONAL DESCRIPTION
Figure
6
shows the major functional blocks of the ADC08161 multi-step flash converter. It consists of an over-encoded 2
1
⁄2-bit Voltage Estimator, an internal DAC with two different voltage spans, a 3-bit half-flash converter and a comparator multiplexer.
Figure 6
forms the internal main DAC. Each of the eight resistors at the bottom of the string is equal to 1/256 of the total string resistance. These resistors form the LSB Ladder and have a voltage drop of 1/256 of the total reference voltage (V
REF+−VREF−
) across them. The remaining resis­tors make up the MSB Ladder . They are made up of eight groups of four resistors connected in series. Each MSB Ladder section has
1
⁄8of the total reference voltage across it. Within a given MSB Ladder section, each of the MSB resis­tors has 8/256, or
1
⁄32 of the total reference voltage across it.
Tap points are found between all of the resistors in both the
MSB and LSB Ladders. Through the Comparator Multiplexer these tap points can be connected, in groups of eight, to the eight comparators shown at the right of
Figure 6
. This func­tion provides the necessary reference voltages to the com­parators during each flash conversion.
The six comparators, seven-resistor string (estimator DAC), and Estimator Decoder at the left of
Figure 6
form the Voltage Estimator. The estimator DAC connected between V
REF+
and V
REF−
generates the reference voltages for the six Voltage Estimator comparators. These comparators per­form a very low resolution A/D conversion to obtain an “estimate” of the input voltage. This estimate is then used to control the Comparator Multiplexer, connecting the appropri­ate MSB Ladder section to the eight flash comparators. Only 14 comparators, six in the Voltage Estimator and eight in the flash converter, are needed to achieve the full eight-bit reso­lution, instead of 32 comparators that would be needed by traditional half-flash methods.
A conversion begins with the Voltage Estimator comparing the analog input signal against the six tap voltages on the estimator DAC. The estimator decoder then selects one of the groups of tap points along the MSB Ladder. These eight
DS011149-17
FIGURE 6. Block Diagram of the ADC08161 Multi-Step Flash Architecture
ADC08161
www.national.com11
Page 12
Application Information (Continued)
tap points are then connected to the eight flash comparators. For example, if the analog input signal applied to V
IN
is
between 0 and 3/16 of V
REF(VREF=VREF+−VREF−
), the estimator decoder instructs the comparator multiplexer to select the eight tap points between 8/256 and 2/8 of V
REF
and connects them to the eight flash comparators. The first flash conversion is now performed, producing the five MSBs of data.
By using the same eight comparators for both flash conver­sions, the number of comparators needed by the multi-step converter is significantly reduced when compared to stan­dard half-flash techniques.
Voltage Estimator errors as large as 1/16 of V
REF
(16 LSBs) will be corrected since the flash comparators are connected to ladder voltages that extend beyond the range specified by the Voltage Estimator. For example, if 7/16 V
REF
<
V
IN
<
9/16 V
REF
the Voltage Estimator’s comparators tied to the
tap points below 9/16 V
REF
will output “1”s (000111). This is decoded by the estimator decoder to “10”. The eight flash comparators will be placed at the MSB Ladder tap points between
3
⁄8V
REF
and5⁄8V
REF
. The overlap of 1/16 V
REF
on each side of the Voltage Estimator’s span will automatically correct an error of up to 16 LSBs (16 LSBs = 312.5 mV for V
REF
= 5V). If the first flash conversion determines that the
input voltage is between
3
⁄8V
REF
and 4/8 V
REF
− LSB/2, the Voltage Estimator’s output code will be corrected by sub­tracting “1”. This results in a corrected value of “01”. If the first flash conversion determines that the input voltage is between 8/16 V
REF
− LSB/2 and5⁄8V
REF
, the Voltage Esti-
mator’s output code remains unchanged. After correction, the 2-bit data from both the Voltage Estima-
tor and the first flash conversion are decoded to produce the five MSBs. Decoding is similar to that of a 5-bit flash con­verter since there are 32 tap points on the MSB Ladder. However, 31 comparators are not needed since the Voltage Estimator places the eight comparators along the MSB Lad­der where reference tap voltages are present that fall above and below the magnitude of V
IN
. Comparators are not needed outside this selected range. If a comparator’s output is a “0”, all comparators above it will also have outputs of “0” and if a comparator’s output is a “1”, all comparators below it will also have outputs of “1”.
2.0 DIGITAL INTERFACE
The ADC08161 has two basic interface modes which are selected by connecting the MODE pin to a logic high or low.
2.1 RD Mode
With a logic low applied to the MODE pin, the converter is set to Read mode. In this configuration (
Figure 1
), a complete conversion is done by pulling RD low, and holding low, until the conversion is complete and output data appears. This typically takes 655 ns. The INT (interrupt) line goes low at the end of conversion. A typical delay of 50 ns is needed between the rising edge of CS (after the end of a conversion)
and the start of the next conversion (by pulling RD low). The RDY output goes low after the falling edge of CS and goes high at the end-of-conversion. It can be used to signal a processor that the converter is busy or serve as a system Transfer Acknowledge signal.
2.2 RD Mode Pipelined Operation
Applications that require shorter RD pulse widths than those used in the Read mode as described above can be achieved by setting RD’s width between 200 ns–400 ns (
Figure 5
). RD pulse widths outside this range will create conversion linear­ity errors. These errors are caused by exercising internal interface logic circuitry using CS and/or RD during a conver­sion.
When RD goes low, a conversion is initiated and the data from the previous conversion is available on the DB0–DB7 outputs. Reading DB0–DB7 for the first two times after power-up produces random data. The data will be valid during the third RD pulse that occurs after the first conver­sion.
2.3 WR-RD (WR then RD ) Mode
The ADC08161 is in the WR-RD mode with the MODE pin tied high. A conversion starts on the rising edge of the WR signal. There are two options for reading the output data which relate to interface timing. If an interrupt-driven scheme is desired, the user can wait for the INT output to go low before reading the conversion result (
Figure 3
). Typically, INT will go low 690 ns, maximum, after WR’s rising edge. However, if a shorter conversion time is desired, the proces­sor need not wait for INT and can exercise a read after only 350 ns (
Figure 2
). If RD is pulled low before INT goes low, INT will immediately go low and data will appear at the outputs. This is the fastest operating mode (tRD≤ t
INTL
) with a conversion time, including data access time, of 560 ns. Allowing 100 ns for reading the conversion data and the delay between conversions gives a total throughput time of 660 ns (throughput rate of 1.5 MHz).
2.4 WR-RD Mode with Reduced Interface System Connection
CS and RD can be tied low, using only WR to control the start of conversion for applications that require reduced digi­tal interface while operating in the WR-RD mode (
Figure 4
). Data will be valid approximately 705 ns following WR’s rising edge.
3.0 REFERENCE INPUTS
The ADC08161’s two V
REF
inputs are fully differential and define the zero to full-scale input range of the A to D con­verter. This allows the designer to vary the span of the analog input since this range will be equivalent to the voltage difference between V
REF+
and V
REF−
. Transducers that have outputs that minimum output voltages above GND can also be compensated by connecting V
REF−
to a voltage that is
equal to this minimum voltage. By reducing V
REF(VREF
=
V
REF+–VREF−
) to less than 5V,the sensitivity of the converter
can be increased (i.e., if V
REF
= 2.5V, then 1 LSB = 9.8 mV). The reference arrangement also facilitates ratiometric opera­tion and in may cases the power supply can be used for transducer power as well as the V
REF
source. Ratiometric
operation is achieved by connecting V
REF−
to GND and
connecting V
REF+
and a transducer’s power supply input to
V
+
. The ADC08161s accuracy degrades when
V
REF+
–|V
REF−
| is less than 2.0V.
ADC08161
www.national.com 12
Page 13
Application Information (Continued)
The voltage at V
REF−
sets the input level that produces a
digital output of all zeroes. Through V
IN
is not itself differen­tial, the reference design affords nearly differential-input ca­pability for some measurement applications.
Figure 7
shows
one possible differential configuration. It should be noted that, while the two V
REF
inputs are fully differential, the digital output will be zero for any analog input voltage if V
REF−
≥ V
REF+
.
4.0 ANALOG INPUT AND SOURCE IMPEDANCE
The ADC08161’s analog input circuitry includes an analog switch with an “on” resistance of 70Ω and a 1.4 pF capacitor (
Figure 7
). The switch is closed during the A/D’s input signal acquisition time (while WR is low when using the WR-RD Mode). A small transient current flows into the inputpin each time the switch closes. Atransient voltage, whose magnitude can increase as the source impedance increases, may be present at the input. So long as the source impedance is less than 500Ω, the input voltage transient will not cause errors and need not be filtered.
Large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy. Therefore, only signal sources with output impedances less than 500Ω should be used if rated accuracy is to be achieved at the minimum sample time (100 ns maximum). A signal source with a high output impedance should have its output buffered with an operational amplifier. Any ringing or voltage shifts at the op amp’s output during the sampling period can result in conversion errors.
Some suggested input configurations using the internal 2.5V reference, an external reference, and adjusting the input span are shown in
Figure 8
.
Correct conversion results will be obtained for inputvoltages greater than GND − 100 mV and less than V
+
+ 100 mV. Do not allow the signal source to drive the analog input pin more than 300 mV higher than V
+
, or more than 300 mV lower than GND. The current flowing through any analog input pin should be limited to 5 mA or less to avoid permanent dam­age to the IC if an analog input pin is forced beyond these voltages. The sum of all the overdrive currents into all pins must be less than 20 mA. Some sort of protection scheme should be used when the input signal is expected to extend more than 300 mV beyond the power supply limits. A simple protection network using resistors and diodes is shown in
Figure 9
.
5.0 INHERENT SAMPLE-AND-HOLD
An important benefit of the ADC08161’s input architecture is the inherent sample-and-hold (S/H) and its ability to mea­sure relatively high speed signals without the help of an
external S/H. In a non-sampling converter, regardless of its speed, the input must remain stable to at least
1
⁄2LSB throughout the conversion process if full accuracy is to be maintained. Consequently, for many high speed signals, this signal must be externally sampled and held stationary during the conversion.
The ADC08161 is suitable for DSP-based systems because of the direct control of the S/H through the WR signal. The WR input signal allows theA/D to be synchronized to a DSP system’s sampling rate or to other ADC08161s.
The ADC08161 can perform accurate conversions of full-scale input signals at frequencies from DC to more than 300 kHz (full power bandwidth) without the need of an ex­ternal sample-and-hold (S/H).
6.0 INTERNAL BANDGAP REFERENCE
The ADC08161 has an internal bandgap 2.5V reference that can be used as the V
REF+
input. A parallel combination of a
REFOUT
pin. This reduces
possible noise pickup that could cause conversion errors.
7.0 LAYOUT, GROUNDS, AND BYPASSING
In order to ensure fast, accurate conversions from the ADC08161, it is necessary to use appropriate circuit board layout techniques. Ideally, the analog-to-digital converter’s ground reference should be low impedance and free of noise from other parts of the system. Digital circuits can produce a great deal of noise on their ground returns and, therefore, should have their own separate ground lines. Best perfor­mance is obtained using separate ground planes should be provided for the digital and analog parts of the system.
The analog inputs should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., an input filter capacitor) con­nected across the inputs should be returned to a very clean ground point. Incorrectly grounding the ADC08161 may re­sult in reduced conversion accuracy.
The V
+
supply pin, V
REF+
, and V
REF−
(if not grounded) should be bypassed with a parallel combination of a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor placed as close as possible to the pins usingshort circuit board traces. See
Figures 8, 9
.
DS011149-18
FIGURE 7. ADC08161 Equivalent Input Circuit Model
ADC08161
www.national.com13
Page 14
Application Information (Continued)
Internal Reference 2.5V Full-Scale
(Standard Application)
DS011149-19
Power Supply as Reference
DS011149-20
Input Not Referred to GND
DS011149-21
*
Signal source driving VIN(−) must be capable
of sinking 5 mA.
Note: Bypass capacitors consist of a 0.1 µF ceramic in parallel with a 10 µF bead tantalum, unless otherwise specified.
FIGURE 8. Analog Input Options
DS011149-22
FIGURE 9. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. V
REF−
should be bypassed to analog ground using multiple capacitors if it is not grounded (See Section 7.0 “LAYOUT,
GROUNDS, and BYPASSING”). V
IN1
is shown with an optional input protection network.
ADC08161
www.national.com 14
Page 15
Physical Dimensions inches (millimeters) unless otherwise noted
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor Corporation
Americas Email: support@nsc.com
National Semiconductor Europe
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790
National Semiconductor Asia Pacific Customer Response Group
Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com
National Semiconductor Japan Ltd.
Tel: 81-3-5639-7560 Fax: 81-3-5639-7507
www.national.com
Wide-Body Small-Outline
Order Number ADC08161CIWM
NS Package Number M20B
ADC08161 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Loading...
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use