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查询ADC08131供应商查询ADC08131供应商
ADC08131/ADC08134/ADC08138
8-Bit High-Speed Serial I/O A/D Converters with
Multiplexer Options, Voltage Reference, and Track/Hold
Function
June 1999
ADC08131/ADC08134/ADC08138 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer
Options, Voltage Reference, and Track/Hold Function
General Description
The ADC08131/ADC08134/ADC08138 are 8-bit successive
approximation A/D converters with serial I/O and configurable input multiplexers with up to 8 channels. The serial
I/O is configuredto comply with the NSC MICROWIRE
rial data exchange standard for easy interface to the
™
COPS
family of controllers, and can easily interface with
standard shift registers or microprocessors.
All three devices provide a 2.5V band-gap derived reference
with guaranteed performance over temperature.
Atrack/hold function allows the analog voltage at the positive
input to vary during the actual A/D conversion.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes. In addition, input voltage spans
as small as 1V can be accommodated.
™
se-
Ordering Information
Industrial Package
(−40˚C ≤ T
ADC08131CIWM M14B
ADC08134CIWM M14B
ADC08138CIWM M20B
A
Applications
n Digitizing automotive sensors
n Process control/monitoring
n Remote sensing in noisy environments
n Embedded diagnostics
Features
n Serial digital data link requires few I/O pins
n Analog input track/hold function
n 4- or 8-channel input multiplexer options with address
logic
n On-chip 2.5V band-gap reference (
temperature guaranteed)
n No zero or full scale adjustment required
n TTL/CMOS input/output compatible
n 0V to 5V analog input range with single 5V power
supply
±
2%over
Key Specifications
n Resolution 8 Bits
n Conversion time (f
n Power dissipation 20 mW (Max)
n Single supply 5 V
n Total unadjusted error
n Linearity Error (V
n No missing codes (over temperature)
n On-board Reference +2.5V
≤ +85˚C)
=
1 MHz) 8 µs (Max)
C
1
±
⁄2LSB and±1 LSB
REF
=
2.5V)
(±5%)
DC
1
±
⁄2LSB
±
1.5%(Max)
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
COPS
microcontrollers and MICROWIRE™are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS010749 www.national.com
Page 2
Connection Diagrams
ADC08138CIWM
Small Outline
Packages
DS010749-2
ADC08134CIWM
Small Outline
Packages
DS010749-3
ADC08131CIWM
Small Outline Package
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DS010749-4
Page 3
Absolute Maximum Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Voltage at Inputs and Outputs −0.3V to V
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
Power Dissipation at T
(Note 5) 800 mW
ESD Susceptibility (Note 6) 1500V
) 6.5V
CC
CC
±
=
25˚C
A
+ 0.3V
±
5mA
20 mA
Soldering Information
N Package (10 sec.)
SO Package:
Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)
260˚C
215˚C
220˚C
Storage Temperature −65˚C to +150˚C
Operating Ratings (Notes 2, 3)
Temperature Range T
Supply Voltage (V
) 4.5 VDCto 6.3 V
CC
≤ TA≤ T
MIN
MAX
−40˚C ≤ TA≤ +85˚C
DC
Electrical Characteristics
The following specifications apply for V
face limits apply for T
=
=
T
A
J
=
+5 V
CC
to T
T
MIN
DC,VREF
; all other limits T
MAX
Symbol Parameter Conditions
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Linearity Error V
Full Scale Error V
Zero Error V
Total Unadjusted Error
Differential Linearity V
R
REF
V
IN
Reference Input Resistance (Note 11)
Analog Input Voltage (Note 12)
DC Common-Mode Error V
Power Supply Sensitivity
On Channel Leakage Current
(Note 13)
Off Channel Leakage Current
(Note 13)
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
V
OUT(0)
I
OUT
I
SOURCE
Logical “1” Input Voltage V
Logical “0” Input Voltage V
Logical “1” Input Current V
Logical “0” Input Current V
Logical “1” Output Voltage I
Logical “0” Output Voltage
TRI-STATE®Output Current
Output Source Current V
=
+2.5 V
=
+2.5 V
REF
=
+2.5 V
REF
=
+2.5 V
REF
=
+5 V
V
REF
(Note 10)
=
+2.5 V
REF
=
2.5 V
REF
=
V
+5V
CC
=
+2.5 V
V
REF
On Channel=5V, 0.2
Off Channel=0V 1
On Channel=0V, −0.2
Off Channel=5V −1
On Channel=5V, −0.2
Off Channel=0V −1
On Channel=0V, 0.2
Off Channel=5V 1
=
5.25V 2.0 V (min)
CC
=
4.75V 0.8 V (max)
CC
=
5.0V 1 µA (max)
IN
=
0V −1 µA (max)
IN
=
V
4.75V:
CC
=
−360 µA 2.4 V (min)
OUT
=
I
−10 µA 4.5 V (min)
OUT
=
V
4.75V 0.4 V (max)
CC
=
I
1.6 mA
OUT
=
V
0V −3.0 µA (max)
OUT
=
V
5V 3.0 µA (max)
OUT
=
0V −6.5 mA (min)
OUT
=
and f
DC
=
=
T
A
J
DC
DC
DC
DC
DC
1 MHz unless otherwise specified. Bold-
CLK
25˚C.
Typical
(Note 8)
Limits
(Note 9)
±
1 LSB (max)
±
1 LSB (max)
±
1 LSB (max)
±
1 LSB (max)
8 Bits (min)
Units
(Limits)
3.5 kΩ
1.3 kΩ (min)
6.0 kΩ (max)
(V
+ 0.05) V (max)
CC
(GND − 0.05) V (min)
1
±
⁄
DC
±
5%,
DC
2
1
±
⁄
4
LSB (max)
LSB (max)
µA (max)
µA (max)
µA (max)
µA (max)
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Page 4
Electrical Characteristics (Continued)
The following specifications apply for V
face limits apply for T
=
=
T
A
J
=
+5 V
CC
to T
T
MIN
DC,VREF
; all other limits T
MAX
Symbol Parameter Conditions
DIGITAL AND DC CHARACTERISTICS
I
SINK
Output Sink Current V
Supply Current
I
CC
ADC08134, ADC08138 CS=HIGH 3.0 mA (max)
ADC08131 (Note 16) 6.0 mA (max)
OUT
=
+2.5 V
=
V
CC
=
and f
DC
=
=
T
A
J
1 MHz unless otherwise specified. Bold-
CLK
25˚C.
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
8.0 mA (min)
Electrical Characteristics
The following specifications apply for V
=
=
to T
T
T
A
T
J
MIN
; all other limits T
MAX
=
, and f
+5 V
CC
DC
=
=
T
25˚C.
A
J
Symbol Parameter Conditions
REFERENCE CHARACTERISTICS
V
OUT Output Voltage DC08134, ADC08138
REF
/∆T Temperature Coefficient 40 ppm/˚C
∆V
REF
Sourcing
(0 ≤ I
ADC08134,
ADC08138
Sourcing
(0 ≤ I
/∆ILLoad Regulation (Note 17)
∆V
REF
ADC08131
Sinking
(−1 ≤ I
ADC08134,
ADC08138
Sinking
(−1 ≤ I
ADC08131
Line Regulation 4.75V ≤ V
V
REF
ADC08134, 8 25
I
SC
Short Circuit Current ADC08138
V
REF
ADC08131
V
T
∆V
SU
REF
Start-Up Time
/∆t Long Term Stability 200 ppm/1 kHr
CC
C
L
CLK
≤ +4 mA)
L
≤ +2 mA)
L
≤ 0 mA)
L
≤ 0 mA)
L
CC
=
0V
=
0V
:0V→5V
=
100 µF
=
1 MHz unless otherwise specified. Boldface limits apply for
Typical
(Note 8)
2.5
±
%
2
Limits
(Note 9)
±
2.5
1.5
%
0.003 0.1
0.003 0.1
0.2 0.5
0.2 0.5
≤ 5.25V 0.5 6 mV (max)
8 25
20 ms
Units
(Limits)
V
%
/mA
(max)
mA
(max)
Electrical Characteristics
The following specifications apply for V
limits apply for T
=
=
T
T
A
J
MIN
to T
MAX
CC
=
+5 V
DC,VREF
; all other limits T
Symbol Parameter Conditions
f
CLK
Clock Frequency
Clock Duty Cycle 40
(Note 14) 60
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=
A
+2.5 V
=
T
J
=
DC
25˚C.
and t
=
=
t
20 ns unless otherwise specified. Boldface
r
f
Typical
(Note 8)
Limits
(Note 9)
10 kHz (min)
1 MHz (max)
Units
(Limits)
%
(min)
%
(max)
Page 5
Electrical Characteristics (Continued)
The following specifications apply for V
limits apply for T
=
=
T
T
A
J
MIN
to T
MAX
CC
=
+5 V
DC,VREF
; all other limits T
Symbol Parameter Conditions
T
C
t
CA
t
SELECT
t
SET-UP
t
HOLD
t
pd1,tpd0
Conversion Time (Not Including
MUX Addressing Time) 8 µs (max)
Acquisition Time
CLK High while CS is High 50 ns
CS Falling Edge or Data Input
Valid to CLK Rising Edge
Data Input Valid after CLK Rising
Edge
CLK Falling Edge to Output Data
Valid (Note 15)
TRI-STATE Delay from Rising Edge
t
1H,t0H
C
IN
C
OUT
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci-
fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to AGND=DGND=0V
Note 4: When the input voltage (V
5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four
pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at anytemperatureisP
T
JMAX
ADC08138.
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Data Book section “Surface Mount” for other methods of soldering
surface mount devices.
Note 8: Typicals are at T
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with V
ADC08138. See (Note 16).
Note 11: Cannot be tested for the ADC08131.
Note 12: For V
analog input voltages one diode drop below ground or one diode drop greater than V
(e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification allows
50 mV forward bias of either diode; this means that as long as the analog V
Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V
therefore require a minimum supply voltage of 4.950 V
Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following two
cases are considered: one, with the selected channel tied high (5 V
nels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two cases
considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A40%to 60%duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits
the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 µs.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow
for comparator response time.
Note 16: For the ADC08131 V
reference current (700 µA typical, 2 mA maximum).
Note 17: Load regulation test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the ADC08131 has the
on-board reference as a permanent load.
of CS to Data Output and SARS
Hi-Z
Capacitance of Logic Inputs 5 pF
Capacitance of Logic Outputs 5 pF
) at any pin exceeds the power supplies (V
IN
=
(T
D
=
125˚C. The typical thermal resistances (θ
=
25˚C and represent the most likely parametric norm.
J
≥ V
IN(−)
the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct for
IN(+)
IN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger because it includes the
REF
JMAX−TA
) of these parts when board mounted for the ADC 08131 and the ADC08134 is 140˚C/W and 91˚C/W for the
JA
over temperature variations, initial tolerance and loading.
DC
=
+2.5 V
DC
=
=
T
A
J
=
1 MHz
f
CLK
25˚C.
and t
=
=
t
20 ns unless otherwise specified. Boldface
r
f
Typical
(Note 8)
Limits
(Note 9)
8 1/f
1
⁄
2
Units
(Limits)
CLK
1/f
CLK
25 ns (min)
20 ns (min)
=
C
100 pF:
L
Data MSB First 250 ns (max)
Data LSB First 200 ns (max)
=
C
10 pF, R
L
(see TRI-STATE Test Circuits)
=
100 pF, R
C
L
DC
)/θJAor the number given intheAbsoluteMaximumRatings,whicheveris lower. For these devices
IN
) and the remaining seven off channels tied low (0 VDC), total current flow through the off chan-
DC
=
10 kΩ
L
=
2kΩ 180 ns (max)
L
, unless otherwise specified.
<
(AGND or DGND) or V
IN
JMAX
supply.During testing at low VCClevels (e.g., 4.5V), high level analog inputs
CC
does not exceed the supply voltage by more than 50 mV, the output code will be correct.
50 ns
>
AVCC) the current at that pin should be limited to
IN
, θJAand the ambient temperature, TA. The maximum
=
+5V only applies to the ADC08134 and
REF
to5VDCinput voltage range will
DC
(max)
(max)
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Page 6
ADC08138 Simplified Block Diagram
DS010749-1
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Page 7
Typical Converter Performance Characteristics
Linearity Error vs
Reference Voltage
Power Supply Current vs
Temperature (ADC08138,
ADC08134)
Note: For ADC08131 add I
DS010749-27
DS010749-30
REF
Linearity Error vs
Temperature
Output Current vs
Temperature
DS010749-28
DS010749-31
Linearity Error vs
Clock Frequency
DS010749-29
Power Supply Current
vs Clock Frequency
DS010749-32
Typical Reference Performance Characteristics
Load Regulation
DS010749-33
Line Regulation
(3 Typical Parts)
DS010749-34
Output Drift
vs Temperature
(3 Typical Parts)
DS010749-35
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Page 8
Typical Reference Performance Characteristics (Continued)
Available
Output Current
vs Supply Voltage
DS010749-36
TRI-STATE Test Circuits and Waveforms
Timing Diagrams
t
1H
DS010749-37
t
0H
DS010749-38
t
1H
DS010749-39
t
0H
DS010749-40
Data Input Timing
*
To reset these devices, CLK and CS must be simultaneously high for a period of t
standards ADC0831/4/8.
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or greater. Otherwise these devices are compatible with industry
SELECT
DS010749-9
Page 9
Timing Diagrams (Continued)
Data Output Timing
DS010749-10
ADC08131 Start Conversion Timing
DS010749-11
ADC08131 Timing
*LSB first output not available on ADC08131.
LSB information is maintained for remainder of clock periods until CS goes high.
ADC08134 Timing
DS010749-12
DS010749-13
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Page 10
Timing Diagrams (Continued)
DS010749-14
ADC08138 Timing
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18 clocks in the LSB before SE is taken low
#
*Make sure clock edge
Page 11
ADC08138 Functional Block Diagram
DS010749-15
are internally tied together.
REFIN
and V
REFOUT
*Some of these functions/pins are not available with other options.
Note 18: For the ADC08134, the “SEL 1” Flip-Flop is bypassed. For the ADC08131, V
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Page 12
Functional Description
MULTIPLEXER ADDRESSING
The design of these converters utilizes a comparator structure with built-in sample-and-hold which provides for a differential analog input to be converted by a successiveapproximation routine.
The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input terminal.
The polarity of each input terminal of the pair indicates which
line the converter expects to be the most positive. If the assigned “+” input voltage is less than the “−” input voltage the
converter responds with an all zeros output code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog input and a common terminal) operation. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential.
Differential inputs are restricted to adjacent channel pairs.
For example, channel 0 and channel 1 may be selected as a
differential pair but channel 0 or 1 cannot act differentially
with any other channel. In addition to selecting differential
TABLE 2. MUX Addressing: ADC08138
mode the polarity may also be selected. Channel 0 may be
selected as the positive input and channel 1 as the negative
input or vice versa. This programmability is best illustrated by
the MUX addressing codes shown in the following tables for
the various product options.
The MUX address is shifted into the converter via the DI line.
Because the ADC08131 contains only one differential input
channel with a fixed polarity assignment, it does not require
addressing.
The common input line (COM) on the ADC08138 can be
used as a pseudo-differential input. In this mode the voltage
on this pin is treated as the “−” input for any of the other input
channels. This voltage does not have to be analog ground; it
can be any reference potential which is common to all of the
inputs. This feature is most useful in single-supply applications where the analog circuity may be biased up to a potential other than ground and the output signals are all referred
to this potential.
TABLE 1. Multiplexer/Package Options
Part Number of Analog Channels Number of
Number Single-Ended Differential Package
Pins
ADC08131 1 1 8
ADC08134 4 2 14
ADC08138 8 4 20
Single-Ended MUX Mode
MUX Address Analog Single-Ended Channel
#
START SGL/ ODD/ SELECT 01234567COM
DIF
SIGN 1 0
11000+ −
11001 + −
11010 + −
11011 + −
11100 + −
11101 + −
11110 + −
11111 +−
TABLE 3. MUX Addressing: ADC08138
Differential MUX Mode
MUX Address Analog Differential Channel-Pair
#
START SGL/ ODD/ SELECT 0123
DIF
SIGN 1001234567
10000+−
10001 +−
10010 +−
10011 +−
10100−+
10101 −+
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Page 13
Functional Description (Continued)
TABLE 3. MUX Addressing: ADC08138 (Continued)
Differential MUX Mode
MUX Address Analog Differential Channel-Pair
START SGL/ ODD/ SELECT 0123
DIF
SIGN 1001234567
10110 −+
10111 −+
TABLE 4. MUX Addressing: ADC08134
Single-Ended MUX Mode
MUX Address Channel
#
START SGL/ ODD/ SELECT 0123
DIF
SIGN 1
110 0+
110 1 +
111 0 +
111 1 +
COM is internally tied to AGND
Differential MUX Mode
MUX Address Channel
#
START SGL/ ODD/ SELECT 0123
DIF
SIGN 1
100 0+−
100 1 +−
101 0−+
101 1 −+
Since the input configuration is under software control, it can
be modified as required before each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion.
Figure 1
illus-
trates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above V
out degrading conversion accuracy.
(typically 5V) with-
CC
THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.
1. A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
The start bit is the first logic “1” that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX assignment word.
3. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned and a conversion is about to begin. An interval of
1
⁄2clock period is automatically inserted to allow for sampling the analog input. The SARS line goes high at the
end of this time to signal that a conversion is now in
progress and the DI line is disabled (it no longer accepts
data).
4. The data out (DO) line now comes out of TRI-STATE
and provides a leading zero.
5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages generated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator’s output is shipped to the DO line on the
falling edge of CLK. This data is the result of the conversion being shifted out (with the MSB first) and can be
read by the processor immediately.
6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this
MUX assignment word.
2. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register.
#
1
⁄2clock cycle later.
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Page 14
Functional Description (Continued)
7. The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers the data can be provided in an LSB first format
[this makes use of the shift enable (SE) control line]. On
theADC08138 the SE line is brought out and if held high
the value of the LSB remains valid on the DO line. When
SE is forced low the data is clocked out LSB first. On devices which do not include the SE control line, the data,
LSB first, is automatically shifted out the DO line after
the MSB first data stream. The DO line then goes low
and stays low until CS is returned high. The ADC08131
is an exception in that its data is only output in MSB first
format.
8. All internal registers are cleared when the CS line is high
and the t
ing under Timing Diagrams. If another conversion is de-
requirement is met. See Data Input Tim-
SELECT
sired CS must make a high to low transition followed by
address information.
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.
This is possible because the DI input is only “looked-at”
during the MUX addressing interval while the DO line is
still in a high impedance state.
8 Single-Ended
DS010749-41
8 Psuedo-Differential
DS010749-42
FIGURE 1. Analog Input Multiplexer Options for the ADC08138
4 Differential
DS010749-43
Mixed Mode
DS010749-44
REFERENCE CONSIDERATIONS
The V
divider string and capacitor array used for the successive ap-
IN pin on these converters is the top of a resistor
REF
proximation conversion. The voltage applied to this reference input defines the voltage span of the analog input (the
difference between V
possible output codes apply). The reference source must be
IN(MAX)
and V
over which the 256
IN(MIN)
capable of driving the reference input resistance, which can
be as low as 1.3 kΩ.
For absolute accuracy, where the analog input varies between specific voltage limits, the reference input must be biased with a stable voltage source. The ADC08134 and the
ADC08138 provide the output of a 2.5V band-gap reference
at V
OUT. This voltage does not vary appreciably with
REF
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temperature, supply voltage, or load current (see Reference
Characteristics in the Electrical Characteristics tables) and
can be tied directly to V
to 2.5V.This output can also be used to bias external circuits
IN for an analog input span of 0V
REF
and can therefore be used as the reference in ratiometric applications. Bypassing V
recommended.
OUT with a 100 µF capacitor is
REF
For the ADC08131, the output of the on-board reference is
internally tied to the reference input. Consequently, the analog input span for this device is set at 0V to 2.5V. The pin
V
C is provided for bypassing purposes and biasing exter-
REF
nal circuits as suggested above.
The maximum value of the reference is limited to the V
supply voltage. The minimum value, however, can be quite
CC
Page 15
Functional Description (Continued)
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources
when operating with a reduced span due to the increased
sensitivity of the converter (1 LSB equals V
REF/
256).
DS010749-17
a) Ratiometric
FIGURE 2. Reference Examples
THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected “+” and “−” inputs for a conversion (60 Hz is
most typical). The time interval between sampling the “+” input and then the “−” input is
1
⁄2of a clock period. The change
in the common-mode voltage during this short time interval
can cause conversion errors. For a sinusoidal
common-mode signal this error is:
where fCMis the frequency of the common-mode signal,
is its peak voltage value
V
PEAK
is the A/D clock frequency.
and f
CLK
For a 60Hz common-mode signal to generate a
1
⁄4LSB error
(≈5 mV) with the converter running at 250kHz, its peak value
would have to be 6.63V which would be larger than allowed
as it exceeds the maximum analog input limits.
Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. While operating
near or at maximum speed bypass capacitors should not be
used if the source resistance is greater than 1kΩ. The
worst-case leakage current of
±
1µA over temperature will
create a 1mV input error with a 1kΩ source resistance. An op
DS010749-18
b) Absolute
amp RC active low pass filter can provide both impedance
buffering and noise filtering should a high impedance signal
source be required.
OPTIONAL ADJUSTMENTS
Zero Error
The zero of the A/D does not require adjustment. If the minimum analog input voltage value, V
zero offset can be done. The converter can be made to out-
, is not ground a
IN(MIN)
put 0000 0000 digital code for this minimum input voltage by
biasing any V
the differential mode operation of the A/D.
(−) input at this V
IN
value. This utilizes
IN(MIN)
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V
positive voltage to the V
ence between the actual DC input voltage which is necessary to just cause an output digital code transition from 0000
0000 to 0000 0001 and the ideal
9.8mV for V
(−) input and applying a small magnitude
REF
IN
=
(+) input. Zero error is the differ-
IN
1
⁄2LSB value (1⁄2LSB
).
5.000V
DC
Full Scale
A full-scale adjustment can be made by applying a differential input voltage which is 1
1
⁄2LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the V
just changing from 1111 1110 to 1111 1111 (See figure entitled “Span Adjust; 0V ≤ V
the ADC08134 and ADC08138. (The reference is internally
connected to V
IN input for a digital output code which is
REF
≤ 3V”). This is possible only with
IN
IN of the ADC08131).
REF
=
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Page 16
Functional Description (Continued)
Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A V
equals this desired zero reference plus
(+) voltage which
IN
1
⁄2LSB (where the
LSB is calculated for the desired analog span, using 1 LSB
analog span/256) is applied to selected “+” input and the
zero reference voltage at the corresponding “−” input should
then be adjusted to just obtain the 00
sition.
HEX
to 01
HEX
code tran-
The full-scale adjustment should be made [with the proper
V
(−) voltage applied] by forcing a voltage to the VIN(+) in-
IN
put which is given by:
Applications
A “Stand-Alone” Hook-Up for ADC08138 Evaluation
where:
=
V
MAX
and
=
V
MIN
(Both are ground referenced.)
=
The V
REF
code change from FE
justment procedure.
the high end of the analog input range
the low end (the offset zero) of the analog range.
IN (or VCC) voltage is then adjusted to provide a
to FF
HEX
. This completes the ad-
HEX
*Pinouts shown for ADC08138.
For all other products tie to pin functions as shown.
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DS010749-45
Page 17
Applications (Continued)
Low-Cost Remote Temperature Sensor
DS010749-46
Protecting the Input
Diodes are 1N914
DS010749-22
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Page 18
Applications (Continued)
Operating with Ratiometric Transducers
*VIN(−)=0.15 V
15%of V
REF
≤ V
REF
XDR
≤ 85%of V
DS010749-23
REF
Span Adjust; 0V ≤ VIN≤ 3V
DS010749-24
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Page 19
Applications (Continued)
Zero-Shift and Span Adjust: 2V ≤ V
≤ 5V
IN
DS010749-25
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Page 20
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADC08134CIWM
NS Package Number M14B
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Page 21
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number ADC08138CIWM
NS Package Number M20B
ADC08131/ADC08134/ADC08138 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer
Options, Voltage Reference, and Track/Hold Function
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www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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