Datasheet ADC08131CIN, ADC08131BIWM, ADC08131BIN Datasheet (NSC)

ADC08131/ADC08134/ADC08138
8-Bit High-Speed Serial I/O A/D Converters with
Multiplexer Options, Voltage Reference, and Track/Hold
Function

General Description

The ADC08131/ADC08134/ADC08138 are 8-bit successive
approximation A/D converters with serial I/O and config­urable input multiplexers with up to 8 channels. The serial
I/O is configured to comply with the NSC MICROWIRE

™

serial data exchange standard for easy interface to the
COPS

™

family of controllers, and can easily interface with

standard shift registers or microprocessors.
All three devices providea 2.5V band-gap derived reference

with guaranteed performance over temperature.
Atrack/hold function allows the analog voltage at the positive

input to vary during the actual A/D conversion.
The analog inputs can be configured to operate in various

combinations of single-ended, differential, or
pseudo-differential modes. In addition, input voltage spans
as small as 1V can be accommodated.

Applications

n Digitizing automotive sensors
n Process control/monitoring
n Remote sensing in noisy environments
n Embedded diagnostics

Features

n Serial digital data link requires few I/O pins
n Analog input track/hold function
n 4- or 8-channel input multiplexer options with address

logic

n On-chip 2.5V band-gap reference (

±

2% over

temperature guaranteed)

n No zero or full scale adjustment required
n TTL/CMOS input/output compatible
n 0V to 5V analog input range with single 5V power

supply

Key Specifications

n Resolution 8 Bits
n Conversion time (f

C

= 1 MHz) 8 µs (Max)

n Power dissipation 20 mW (Max)
n Single supply 5 V

DC

(±5%)

n Total unadjusted error

±

1

⁄2LSB and±1 LSB

n Linearity Error (V

REF

= 2.5V)

±

1

⁄2LSB

n No missing codes (over temperature)
n On-board Reference +2.5V

±

1.5% (Max)

Ordering Information

Industrial Package

(−40˚C ≤ T

A

≤ +85˚C)

ADC08131CIWM M14B
ADC08134CIWM M14B
ADC08138CIWM M20B

TRI-STATE®is a registered trademark of National Semiconductor Corporation.
COPS

™

microcontrollers and MICROWIRE™are trademarks of National Semiconductor Corporation.

June 1999

ADC08131/ADC08134/ADC08138 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer

Options, Voltage Reference, and Track/Hold Function

© 2001 National Semiconductor Corporation DS010749 www.national.com

Connection Diagrams

ADC08138CIWM

Small Outline

Packages

DS010749-2

ADC08134CIWM

Small Outline

Packages

DS010749-3

ADC08131CIWM

Small Outline Package

DS010749-4

ADC08131/ADC08134/ADC08138

www.national.com 2

Absolute Maximum Ratings (Notes 1, 3)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

CC

) 6.5V

Voltage at Inputs and Outputs −0.3V to V

CC

+ 0.3V

Input Current at Any Pin (Note 4)

±

5mA

Package Input Current (Note 4)

±

20 mA

Power Dissipation at T

A

= 25˚C

(Note 5) 800 mW

ESD Susceptibility (Note 6) 1500V

Soldering Information

N Package (10 sec.)
SO Package:

Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)

260˚C
215˚C
220˚C

Storage Temperature −65˚C to +150˚C

Operating Ratings (Notes 2, 3)

Temperature Range T

MIN

≤ TA≤ T

MAX

−40˚C ≤ TA≤ +85˚C

Supply Voltage (V

CC

) 4.5 VDCto 6.3 V

DC

Electrical Characteristics

The following specifications apply for VCC=+5VDC,V

REF

= +2.5 VDCand f

CLK

= 1 MHz unless otherwise specified. Boldface

limits apply for T

A=TJ=TMIN

to T

MAX

; all other limits TA=TJ= 25˚C.

Symbol Parameter Conditions

Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Linearity Error V

REF

= +2.5 V

DC

±

1 LSB (max)

Full Scale Error V

REF

= +2.5 V

DC

±

1 LSB (max)

Zero Error V

REF

= +2.5 V

DC

±

1 LSB (max)

Total Unadjusted Error

V

REF

=+5V

DC

(Note 10)

±

1 LSB (max)

Differential Linearity V

REF

= +2.5 V

DC

8 Bits (min)

R

REF

Reference Input Resistance (Note 11)

3.5 kΩ

1.3 kΩ (min)

6.0 kΩ (max)

V

IN

Analog Input Voltage (Note 12)

(V

CC

+ 0.05) V (max)

(GND − 0.05) V (min)

DC Common-Mode Error V

REF

= 2.5 V

DC

±

1

⁄

2

LSB (max)

Power Supply Sensitivity

V

CC

= +5V±5%,

±

1

⁄

4

LSB (max)

V

REF

= +2.5 V

DC

On Channel Leakage Current
(Note 13)

On Channel = 5V, 0.2

µA (max)

Off Channel = 0V 1
On Channel = 0V, −0.2

µA (max)

Off Channel = 5V −1

Off Channel Leakage Current
(Note 13)

On Channel = 5V, −0.2

µA (max)

Off Channel = 0V −1
On Channel = 0V, 0.2

µA (max)

Off Channel = 5V 1

DIGITAL AND DC CHARACTERISTICS

V

IN(1)

Logical “1” Input Voltage VCC= 5.25V 2.0 V (min)

V

IN(0)

Logical “0” Input Voltage VCC= 4.75V 0.8 V (max)

I

IN(1)

Logical “1” Input Current VIN= 5.0V 1 µA (max)

I

IN(0)

Logical “0” Input Current VIN=0V −1 µA (max)

V

CC

= 4.75V:

V

OUT(1)

Logical “1” Output Voltage I

OUT

= −360 µA 2.4 V (min)

I

OUT

= −10 µA 4.5 V (min)

V

OUT(0)

Logical “0” Output Voltage

V

CC

= 4.75V 0.4 V (max)

I

OUT

= 1.6 mA

I

OUT

TRI-STATE®Output Current

V

OUT

=0V −3.0 µA (max)

V

OUT

=5V 3.0 µA (max)

I

SOURCE

Output Source Current V

OUT

=0V −6.5 mA (min)

ADC08131/ADC08134/ADC08138

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Electrical Characteristics (Continued)

The following specifications apply for VCC=+5VDC,V

REF

= +2.5 VDCand f

CLK

= 1 MHz unless otherwise specified. Boldface

limits apply for T

A=TJ=TMIN

to T

MAX

; all other limits TA=TJ= 25˚C.

Symbol Parameter Conditions

Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

DIGITAL AND DC CHARACTERISTICS

I

SINK

Output Sink Current V

OUT=VCC

8.0 mA (min)

Supply Current

I

CC

ADC08134, ADC08138 CS = HIGH 3.0 mA (max)
ADC08131 (Note 16) 6.0 mA (max)

Electrical Characteristics

The following specifications apply for VCC=+5VDC, and f

CLK

= 1 MHz unless otherwise specified. Boldface limits apply for

T

A=TJ=TMIN

to T

MAX

; all other limits TA=TJ= 25˚C.

Symbol Parameter Conditions

Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

REFERENCE CHARACTERISTICS

V

REF

OUT Output Voltage DC08134, ADC08138

2.5

±

2%

2.5

±

1.5% V

∆V

REF

/∆T Temperature Coefficient 40 ppm/˚C

∆V

REF

/∆ILLoad Regulation (Note 17)

Sourcing
(0 ≤ I

L

≤ +4 mA)
ADC08134,
ADC08138

0.003 0.1

%/mA

(max)

Sourcing
(0 ≤ I

L

≤ +2 mA)
ADC08131

0.003 0.1

Sinking
(−1 ≤ I

L

≤ 0 mA)
ADC08134,
ADC08138

0.2 0.5

Sinking
(−1 ≤ I

L

≤ 0 mA)
ADC08131

0.2 0.5

Line Regulation 4.75V ≤ V

CC

≤ 5.25V 0.5 6 mV (max)

V

REF

=0V

mA

(max)

ADC08134, 8 25

I

SC

Short Circuit Current ADC08138

V

REF

=0V

8 25

ADC08131

T

SU

Start-Up Time

V

CC

:0V→5V

20 ms

C

L

= 100 µF

∆V

REF

/∆t Long Term Stability 200 ppm/1 kHr

Electrical Characteristics

The following specifications apply for VCC=+5VDC,V

REF

= +2.5 VDCand tr=tf= 20 ns unless otherwise specified. Boldface

limits apply for T

A=TJ=TMIN

to T

MAX

; all other limits TA=TJ= 25˚C.

Symbol Parameter Conditions

Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

f

CLK

Clock Frequency

10 kHz (min)

1 MHz (max)
Clock Duty Cycle 40 % (min)
(Note 14) 60 % (max)

ADC08131/ADC08134/ADC08138

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Electrical Characteristics (Continued)

The following specifications apply for VCC=+5VDC,V

REF

= +2.5 VDCand tr=tf= 20 ns unless otherwise specified. Boldface

limits apply for T

A=TJ=TMIN

to T

MAX

; all other limits TA=TJ= 25˚C.

Symbol Parameter Conditions

Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

T

C

Conversion Time (Not Including

f

CLK

= 1 MHz

8 1/f

CLK

(max)

MUX Addressing Time) 8 µs (max)

t

CA

Acquisition Time

1

⁄

2

1/f

CLK

(max)

t

SELECT

CLK High while CS is High 50 ns

t

SET-UP

CS Falling Edge or Data Input

25 ns (min)

Valid to CLK Rising Edge

t

HOLD

Data Input Valid after CLK Rising
Edge

20 ns (min)

t

pd1,tpd0

CLK Falling Edge to Output Data
Valid (Note 15)

C

L

= 100 pF:
Data MSB First 250 ns (max)
Data LSB First 200 ns (max)

t

1H,t0H

TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS
Hi-Z

C

L

= 10 pF, RL=10kΩ

50 ns

(see TRI-STATE Test Circuits)
C

L

= 100 pF, RL=2kΩ 180 ns (max)

C

IN

Capacitance of Logic Inputs 5 pF

C

OUT

Capacitance of Logic Outputs 5 pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed

specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.

Note 3: All voltages are measured with respect to AGND = DGND = 0 V

DC

, unless otherwise specified.

Note 4: When the input voltage (V

IN

) at any pin exceeds the power supplies (V

IN

<

(AGND or DGND) or V

IN

>

AVCC) the current at that pin should be limited to
5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four
pins.

Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

JMAX

, θJAand the ambient temperature, TA. The maximum

allowable power dissipation at any temperature is P

D

=(T

JMAX−TA

)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For these

devices T

JMAX

= 125˚C. The typical thermal resistances (θJA) of these parts when board mounted for the ADC 08131 and the ADC08134 is 140˚C/W and 91˚C/W

for the ADC08138.

Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Data Book section “Surface Mount” for other methods of soldering

surface mount devices.
Note 8: Typicals are at T

J

= 25˚C and represent the most likely parametric norm.

Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with V

REF

= +5V only applies to the ADC08134 and

ADC08138. See (Note 16).

Note 11: Cannot be tested for the ADC08131.
Note 12: For V

IN(−)

≥ V

IN(+)

the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct

for analog input voltages one diode drop below ground or one diode drop greater than V

CC

supply. During testing at low VCClevels (e.g., 4.5V), high level analog
inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification
allows 50 mV forward bias of either diode; this means that as long as the analog V

IN

does not exceed the supply voltage by more than 50 mV, the output code will

be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V

DC

to5VDCinput voltage

range will therefore require a minimum supply voltage of 4.950 V

DC

over temperature variations, initial tolerance and loading.

Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (5 V

DC

) and the remaining seven off channels tied low (0 VDC), total current flow through the off
channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.

Note 14: A 40% to 60% duty cycle range insures proper operation at all clockfrequencies.Inthecasethatanavailableclockhasadutycycleoutsideoftheselimits
the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 µs.

Note 15: Since data, MSB first, is theoutputofthecomparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow
for comparator response time.

Note 16: For the ADC08131 V

REF

IN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger because it includes the

reference current (700 µA typical, 2 mA maximum).
Note 17: Load regulation test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the ADC08131 has the

on-board reference as a permanent load.

ADC08131/ADC08134/ADC08138

www.national.com5

ADC08138 Simplified Block Diagram

DS010749-1

ADC08131/ADC08134/ADC08138

www.national.com 6

Typical Converter Performance Characteristics

Typical Reference Performance Characteristics

Linearity Error vs
Reference Voltage

DS010749-27

Linearity Error vs
Temperature

DS010749-28

Linearity Error vs
Clock Frequency

DS010749-29

Power Supply Current vs
Temperature (ADC08138,
ADC08134)

DS010749-30

Output Current vs
Temperature

DS010749-31

Power Supply Current
vs Clock Frequency

DS010749-32

Note: For ADC08131 add I

REF

Load Regulation

DS010749-33

Line Regulation
(3 Typical Parts)

DS010749-34

Output Drift
vs Temperature
(3 Typical Parts)

DS010749-35

ADC08131/ADC08134/ADC08138

www.national.com7

Typical Reference Performance Characteristics (Continued)

TRI-STATE Test Circuits and Waveforms

Timing Diagrams

Available
Output Current
vs Supply Voltage

DS010749-36

t

1H

DS010749-37

t

1H

DS010749-39

t

0H

DS010749-38

t

0H

DS010749-40

Data Input Timing

DS010749-9

*

To reset these devices, CLK and CS must be simultaneously high for a period of t

SELECT

or greater. Otherwise these devices are compatible with industry

standards ADC0831/4/8.

ADC08131/ADC08134/ADC08138

www.national.com 8

Timing Diagrams (Continued)

Data Output Timing

DS010749-10

ADC08131 Start Conversion Timing

DS010749-11

ADC08131 Timing

DS010749-12

*LSB first output not available on ADC08131.
LSB information is maintained for remainder of clock periods until CS goes high.

ADC08134 Timing

DS010749-13

ADC08131/ADC08134/ADC08138

www.national.com9

Timing Diagrams (Continued)

ADC08138 Timing

DS010749-14

*Make sure clock edge

#

18 clocks in the LSB before SE is taken low

ADC08131/ADC08134/ADC08138

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ADC08138 Functional Block Diagram

DS010749-15

*Some of these functions/pins are not available with other options.

Note 18: For the ADC08134, the “SEL 1” Flip-Flop is bypassed. For the ADC08131, V

REFOUT

and V

REFIN

are internally tied together.

ADC08131/ADC08134/ADC08138

www.national.com11

Functional Description

MULTIPLEXER ADDRESSING

The design of these converters utilizes a comparator struc­ture with built-in sample-and-hold which provides for a differ­ential analog input to be converted by a successiveapproxi­mation routine.

The actual voltage converted is always the difference be­tween an assigned “+” input terminal and a “−” input terminal.
The polarity of each input terminal of the pair indicates which
line the converter expects to be the most positive. If the
assigned “+” input voltage is less than the “−” input voltage
the converter responds with an all zeros output code.

A unique input multiplexing scheme has been utilized to
provide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog
input and a common terminal) operation. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input
flexibility. One converter package can now handle ground
referenced inputs and true differential inputs as well as
signals with some arbitrary reference voltage.

A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential.
Differential inputs are restricted to adjacent channel pairs.
For example, channel 0 and channel 1 may be selected as a
differential pair but channel 0 or 1 cannot act differentially
with any other channel. In addition to selecting differential

mode the polarity may also be selected. Channel 0 may be
selected as the positive input and channel 1 as the negative
input or vice versa. This programmability is best illustrated by
the MUX addressing codes shown in the following tables for
the various product options.

The MUX address is shifted into the converter via the DI line.
Because the ADC08131 contains only one differential input
channel with a fixed polarity assignment, it does not require
addressing.

The common input line (COM) on the ADC08138 can be
used as a pseudo-differential input. In this mode the voltage
on this pin is treated as the “−” input for any of the other input
channels. This voltage does not have to be analog ground; it
can be any reference potential which is common to all of the
inputs. This feature is most useful in single-supply applica­tions where the analog circuity may be biased up to a
potential other than ground and the output signals are all
referred to this potential.

TABLE 1. Multiplexer/Package Options

Part Number of Analog Channels Number of

Number Single-Ended Differential Package

Pins

ADC08131 1 1 8
ADC08134 4 2 14
ADC08138 8 4 20

TABLE 2. MUX Addressing: ADC08138

Single-Ended MUX Mode

MUX Address Analog Single-Ended Channel

#

START SGL/ ODD/ SELECT 01234567COM

DIF

SIGN 1 0

11000+ −
11001 + −
11010 + −
11011 + −
11100 + −
11101 + −
11110 + −
11111 +−

TABLE 3. MUX Addressing: ADC08138

Differential MUX Mode

MUX Address Analog Differential Channel-Pair

#

START SGL/ ODD/ SELECT 0123

DIF

SIGN 1001234567

10000+−
10001 +−
10010 +−
10011 +−
10100−+
10101 −+
10110 −+

ADC08131/ADC08134/ADC08138

www.national.com 12

Functional Description (Continued)

TABLE 3. MUX Addressing: ADC08138 (Continued)

Differential MUX Mode

MUX Address Analog Differential Channel-Pair

#

START SGL/ ODD/ SELECT 0123

DIF

SIGN 1001234567

10111 −+

TABLE 4. MUX Addressing: ADC08134

Single-Ended MUX Mode

MUX Address Channel

#

START SGL/ ODD/ SELECT 0123

DIF

SIGN 1

110 0+
110 1 +
111 0 +
111 1 +

COM is internally tied to AGND

Differential MUX Mode

MUX Address Channel

#

START SGL/ ODD/ SELECT 0123

DIF

SIGN 1

100 0+−
100 1 +−
101 0−+
101 1 −+

Since the input configuration is under software control, it can
be modified as required before each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion.

Figure 1

illus-

trates the input flexibility which can be achieved.
The analog input voltages for each channel can range from

50 mV below ground to 50 mV above V

CC

(typically 5V)

without degrading conversion accuracy.

THE DIGITAL INTERFACE

A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system
improvements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.

To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.

1. A conversion is initiated by pulling the CS (chip select)

line low. This line must be held low for the entire con­version. The converter is now waiting for a start bit and
its MUX assignment word.

2. On each rising edge of the clock the status of the data in

(DI) line is clocked into the MUX address shift register.
The start bit is the first logic “1” that appears on this line
(all leading zeros are ignored). Following the start bit the

converter expects the next 2 to 4 bits to be the MUX
assignment word.

3. When the start bit has been shifted into the start location
of the MUX register, the input channel has been as­signed and a conversion is about to begin. An interval of

1

⁄2clock period is automatically inserted to allow for
sampling the analog input. The SARS line goes high at
the end of this time to signal that a conversion is now in
progress and the DI line is disabled (it no longer accepts
data).

4. The data out (DO) line now comes out of TRI-STATE
and provides a leading zero.

5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages gen­erated internally from a ratioed capacitor array (first 5
bits) and a resistor ladder (last 3 bits). After each com­parison the comparator’s output is shipped to the DO
line on the falling edge of CLK. This data is the result of
the conversion being shifted out (with the MSB first) and
can be read by the processor immediately.

6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this

1

⁄2clock cycle later.

ADC08131/ADC08134/ADC08138

www.national.com13

Functional Description (Continued)

7. The stored data in the successive approximation register
is loaded into an internal shift register.If the programmer
prefers the data can be provided in an LSB first format
[this makes use of the shift enable (SE) control line]. On
theADC08138 the SE line is brought out and if held high
the value of the LSB remains valid on the DO line. When
SE is forced low the data is clocked out LSB first. On
devices which do not include the SE control line, the
data, LSB first, is automatically shifted out the DO line
after the MSB first data stream. The DO line then goes
low and stays low until CS is returned high. The

ADC08131 is an exception in that its data is only output
in MSB first format.

8. All internal registers are cleared when the CS line is high
and the t

SELECT

requirement is met. See Data Input
Timing under Timing Diagrams. If another conversion is
desired CS must make a high to low transition followed
by address information.

The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.
This is possible because the DI input is only “looked-at”
during the MUX addressing interval while the DO line is
still in a high impedance state.

REFERENCE CONSIDERATIONS

The V

REF

IN pin on these converters is the top of a resistor
divider string and capacitor array used for the successive
approximation conversion. The voltage applied to this refer­ence input defines the voltage span of the analog input (the
difference between V

IN(MAX)

and V

IN(MIN)

over which the 256
possible output codes apply). The reference source must be
capable of driving the reference input resistance, which can
be as low as 1.3 kΩ.

For absolute accuracy, where the analog input varies be­tween specific voltage limits, the reference input must be
biased with a stable voltage source. The ADC08134 and the
ADC08138 provide the output of a 2.5V band-gap reference
at V

REF

OUT. This voltage does not vary appreciably with

temperature, supply voltage, or load current (see Reference
Characteristics in the Electrical Characteristics tables) and
can be tied directly to V

REF

IN for an analog input span of 0V
to 2.5V.This output can also be used to bias external circuits
and can therefore be used as the reference in ratiometric
applications. Bypassing V

REF

OUT with a 100 µF capacitor is

recommended.
For the ADC08131, the output of the on-board reference is

internally tied to the reference input. Consequently, the ana­log input span for this device is set at 0V to 2.5V. The pin
V

REF

C is provided for bypassing purposes and biasing ex-

ternal circuits as suggested above.
The maximum value of the reference is limited to the V

CC

supply voltage. The minimum value, however, can be quite

8 Single-Ended

DS010749-41

4 Differential

DS010749-43

8 Psuedo-Differential

DS010749-42

Mixed Mode

DS010749-44

FIGURE 1. Analog Input Multiplexer Options for the ADC08138

ADC08131/ADC08134/ADC08138

www.national.com 14

Functional Description (Continued)

small (see Typical Performance Characteristics) to allow
direct conversions of transducer outputs providing less than
a 5V output span. Particular care must be taken with regard

to noise pickup, circuit layout and system error voltage
sources when operating with a reduced span due to the
increased sensitivity of the converter (1 LSB equals
V

REF/

256).

THE ANALOG INPUTS

The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces­sor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accu­racy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.

The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected “+” and “−” inputs for a conversion (60 Hz is
most typical). The time interval between sampling the “+”
input and then the “−” input is

1

⁄2of a clock period. The
change in the common-mode voltage during this short time
interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:

where fCMis the frequency of the common-mode signal,

V

PEAK

is its peak voltage value

and f

CLK

is the A/D clock frequency.

For a 60Hz common-mode signal to generate a

1

⁄4LSB error
(≈5 mV) with the converter running at 250kHz, its peak value
would have to be 6.63V which would be larger than allowed
as it exceeds the maximum analog input limits.

Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. While operating
near or at maximum speed bypass capacitors should not be
used if the source resistance is greater than 1kΩ. The
worst-case leakage current of

±

1µA over temperature will

create a 1mV input error with a 1kΩ source resistance. An op

amp RC active low pass filter can provide both impedance
buffering and noise filtering should a high impedance signal
source be required.

OPTIONAL ADJUSTMENTS

Zero Error

The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V

IN(MIN)

, is not ground
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any V

IN

(−) input at this V

IN(MIN)

value. This

utilizes the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location of

the first riser of the transfer function and can be measured by
grounding the V

IN

(−) input and applying a small magnitude

positive voltage to the V

IN

(+) input. Zero error is the differ­ence between the actual DC input voltage which is neces­sary to just cause an output digital code transition from 0000
0000 to 0000 0001 and the ideal

1

⁄2LSB value (1⁄2LSB =

9.8mV for V

REF

= 5.000VDC).

Full Scale

A full-scale adjustment can be made by applying a differen­tial input voltage which is 1

1

⁄2LSB down from the desired
analog full-scale voltage range and then adjusting the mag­nitude of the V

REF

IN input for a digital output code which is
just changing from 1111 1110 to 1111 1111 (See figure en­titled “Span Adjust; 0V ≤ V

IN

≤ 3V”). This is possible only with
the ADC08134 and ADC08138. (The reference is internally
connected to V

REF

IN of the ADC08131).

DS010749-17

a) Ratiometric

DS010749-18

b) Absolute

FIGURE 2. Reference Examples

ADC08131/ADC08134/ADC08138

www.national.com15

Functional Description (Continued)

Adjusting for an Arbitrary Analog Input
Voltage Range

If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A V

IN

(+) voltage which

equals this desired zero reference plus

1

⁄2LSB (where the
LSB is calculated for the desired analog span, using 1 LSB =
analog span/256) is applied to selected “+” input and the
zero reference voltage at the corresponding “−” input should
then be adjusted to just obtain the 00

HEX

to 01

HEX

code

transition.
The full-scale adjustment should be made [with the proper

V

IN

(−) voltage applied] by forcing a voltage to the VIN(+)

input which is given by:

where:

V

MAX

= the high end of the analog input range

and

V

MIN

= the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The V

REF

IN (or VCC) voltage is then adjusted to provide a

code change from FE

HEX

to FF

HEX

. This completes the

adjustment procedure.

Applications

A “Stand-Alone” Hook-Up for ADC08138 Evaluation

DS010749-45

*Pinouts shown for ADC08138.
For all other products tie to pin functions as shown.

ADC08131/ADC08134/ADC08138

www.national.com 16

Applications (Continued)

Low-Cost Remote Temperature Sensor

DS010749-46

Protecting the Input

DS010749-22

Diodes are 1N914

ADC08131/ADC08134/ADC08138

www.national.com17

Applications (Continued)

Operating with Ratiometric Transducers

DS010749-23

*VIN(−) = 0.15 V

REF

15% of V

REF

≤ V

XDR

≤ 85% of V

REF

Span Adjust; 0V ≤ VIN≤ 3V

DS010749-24

ADC08131/ADC08134/ADC08138

www.national.com 18

Applications (Continued)

Zero-Shift and Span Adjust: 2V ≤ V

IN

≤ 5V

DS010749-25

ADC08131/ADC08134/ADC08138

www.national.com19

Physical Dimensions inches (millimeters) unless otherwise noted

Order Number ADC08134CIWM

NS Package Number M14B

ADC08131/ADC08134/ADC08138

www.national.com 20

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

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COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

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whose failure to perform when properly used in
accordance with instructions for use provided in the
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2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
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www.national.com

Order Number ADC08138CIWM

NS Package Number M20B

ADC08131/ADC08134/ADC08138 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer

Options, Voltage Reference, and Track/Hold Function

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.