Datasheet ADAV803 Datasheet (ANALOG DEVICES)

Audio Codec for Recordable DVD

FEATURES

Stereo analog-to-digital converter (ADC) Supports 48 kHz/96 kHz sample rates 102 dB dynamic range Single-ended input Automatic level control Stereo digital-to-analog converter (DAC) Supports 32 kHz/44.1 kHz/48 kHz/96 kHz/192 kHz

sample rates 101 dB dynamic range Single-ended output Asynchronous operation of ADC and DAC Stereo sample rate converter (SRC) Input/output range: 8 kHz to 192 kHz 140 dB dynamic range Digital interfaces Record Playback Auxiliary record Auxiliary playback S/PDIF (IEC 60958) input and output Digital interface receiver (DIR) Digital interface transmitter (DIT) PLL-based audio MCLK generators Generates required DVDR system MCLKs Device control via I 64-lead LQFP package

C-compatible serial port

FUNCTIONAL BLOCK DIAGRAM

MCLKI

XOUT

XIN

MCLKO

VINL

VINR

VREF

VOUTL

VOUTR

FILTD

ANALOG-TO-DI GITAL

CONVERTER

REFERENCE SRC

DIGITAL-TO-ANALO G

CONVERTER

ADAV803

APPLICATIONS

DVD-recordable All formats CD-R/W

SYSCLK1

PLL

PLAYBACK

DATA INPUT

IBCLK

ILRCLK

SYSCLK3

SYSCLK2

DIGITAL

INPUT/OUTPUT

SWITCHING MATRIX

(DATAPATH)

AUX DATA

INPUT

ISDATA

IAUXBCLK

IAUXSDATA

IAUXLRCLK

Figure 1.

ADAV803

SDA

SCL

AD0

AD1

CONTROL

REGISTERS

RECORD

DATA

OUTPUT

AUX DATA

OUTPUT

DIT

DIR

DIRIN

OLRCLK

OBCLK

OSDATA

OAUXLRCLK

OAUXBCLK

OAUXSDATA

DITOUT

ZEROL/INT

ZEROR

04756-001

GENERAL DESCRIPTION

The ADAV803 is a stereo audio codec intended for applications such as DVD or CD recorders that require high performance and flexible, cost-effective playback and record functionality. The ADAV803 features Analog Devices, Inc. proprietary, high performance converter cores to provide record (ADC), playback (DAC), and format conversion (SRC) on a single chip. The ADAV803 record channel features variable input gain to allow for adjustment of recorded input levels and automatic level control, followed by a high performance stereo ADC whose digital output is sent to the record interface. The record channel also features level detectors that can be used in feedback loops to adjust input levels for optimum recording. The playback channel features a high performance stereo DAC with independent digital volume control.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The sample rate converter (SRC) provides high performance sample rate conversion to allow inputs and outputs that require different sample rates to be matched. The SRC input can be selected from playback, auxiliary, DIR, or ADC (record). The SRC output can be applied to the playback DAC, both main and auxiliary record channels, and a DIT. Operation of the ADAV803 is controlled via an I

C®-compatible serial interface, which allows the programming of individual control register settings. The ADAV803 operates from a single analog 3.3 V power supply and a digital power supply of 3.3 V with an optional digital interface range of 3.0 V to 3.6 V.

The part is housed in a 64-lead LQFP package and is characterized for operation over the commercial temperature range of

−40°C to +85°C.

ADAV803

Features.............................................................................................. 1

Functional Block Diagram .............................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Test Conditions............................................................................. 3

ADAV803 Specifications ............................................................. 3

Timing Specifications .................................................................. 7

Temperature Range ...................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ...........................................11

Functional Description.................................................................. 15

ADC Section ............................................................................... 15

DAC Section................................................................................ 18

Sample Rate Converter (SRC) Functional Overview ............ 19

PLL Section ................................................................................. 22

S/PDIF Transmitter and Receiver............................................ 23

Serial Data Ports......................................................................... 27

Interface Control ............................................................................ 30

C Interface ................................................................................ 30

Block Reads and Writes ............................................................. 31

Layout Considerations................................................................... 59

ADC ............................................................................................. 59

DAC.............................................................................................. 59

PLL ............................................................................................... 59

Reset and Power-Down Considerations ................................. 59

Outline Dimensions....................................................................... 60

Ordering Guide .......................................................................... 60

REVISION HISTORY

7/07—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 3

Changes to ADC Section ............................................................... 15

Changes to Figure 25...................................................................... 15

Changes to Figure 33...................................................................... 21

Changes to SRC Architecture Section ......................................... 21

Changes to Table 7.......................................................................... 22

Changes to Figure 36...................................................................... 22

Changes to Figure 39, Figure 40, Figure 41, Figure 42 .............. 23

Changes to Transmitter Operation Section ................................ 27

Changes to Interrupts Section ...................................................... 27

Changes to Figure 50...................................................................... 28

Changes to Table 97........................................................................ 47

Changes to Table 101...................................................................... 48

Changes to Table 136 and Table 137............................................ 56

Updated Outline Dimensions....................................................... 60

Changes to Ordering Guide.......................................................... 60

7/04—Revision 0: Initial Version

Rev. A | Page 2 of 60

ADAV803

SPECIFICATIONS

TEST CONDITIONS

Test conditions, unless otherwise noted.

Table 1.

Test Parameter Condition

Supply Voltage Analog 3.3 V Digital 3.3 V Ambient Temperature 25°C Master Clock (MCLKI) 12.288 MHz Measurement Bandwidth 20 Hz to 20 kHz Word Width (All Converters) 24 bits Load Capacitance on Digital Outputs 100 pF ADC Input Frequency 1007.8125 Hz at −1 dBFS DAC Output Frequency 960.9673 Hz at 0 dBFS Digital Input Slave Mode, I2S Justified Format Digital Output Slave Mode, I2S Justified Format

ADAV803 SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Comments

PGA SECTION

Input Impedance 4 kΩ Minimum Gain 0 dB Maximum Gain 24 dB Gain Step 0.5 dB

REFERENCE SECTION

Absolute Voltage, V V

Temperature Coefficient 80 ppm/°C

REF

ADC SECTION

Number of Channels 2 Resolution 24 Bits Dynamic Range −60 dB input

Unweighted 99 dB fS = 48 kHz 98 dB fS = 96 kHz A-Weighted 98 102 dB fS = 48 kHz 101 dB fS = 96 kHz

Total Harmonic Distortion + Noise Input = −1.0 dBFS

−88 dB fS = 48 kHz

−87 dB fS = 96 kHz Analog Input

Input Range (± Full Scale) 1.0 V rms

DC Accuracy

Gain Error −1.5 −0.8 dB Interchannel Gain Mismatch 0.05 dB Gain Drift 1 mdB/°C Offset −10 mV

1.5 V

REF

Rev. A | Page 3 of 60

ADAV803

Parameter Min Typ Max Unit Comments

Crosstalk (EIAJ Method) −110 dB Volume Control Step Size (256 Steps) 0.39 % per step Maximum Volume Attenuation −48 dB Mute Attenuation ∞ dB ADC outputs all zero codes Group Delay

fS = 48 kHz 910 μs fS = 96 kHz 460 μs

ADC LOW-PASS DIGITAL DECIMATION FILTER CHARACTERISTICS

Pass-Band Frequency 22 kHz fS = 48 kHz 44 kHz fS = 96 kHz Stop-Band Frequency 26 kHz fS = 48 kHz 52 kHz fS = 96 kHz Stop-Band Attenuation 120 dB fS = 48 kHz 120 dB fS = 96 kHz Pass-Band Ripple ±0.01 dB fS = 48 kHz ±0.01 dB fS = 96 kHz

ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS

Cutoff Frequency 0.9 Hz fS = 48 kHz

SRC SECTION

Resolution 24 Bits Sample Rate 8 192 kHz XIN = 27 MHz SRC MCLK

Maximum Sample Rate Ratios

Upsampling 1:8 Downsampling 7.75:1

Dynamic Range 140

Total Harmonic Distortion + Noise 120 dB

DAC SECTION

Number of Channels 2 Resolution 24 Dynamic Range 20 Hz to 20 kHz, −60 dB input

Unweighted 99 98 A-Weighted 97 101 100

Total Harmonic Distortion + Noise

−91

−90 Analog Outputs

Output Range (± Full Scale) 1.0 Output Resistance 60 Common-Mode Output Voltage 1.5

DC Accuracy

Gain Error −2 −0.8 Interchannel Gain Mismatch 0.05 Gain Drift 1 DC Offset −30

138 × f

MAX

33 MHz

S-

+30

Bits

dB fS = 48 kHz dB fS = 96 kHz dB fS = 48 kHz dB fS = 96 kHz Referenced to 1V rms dB fS = 48 kHz dB fS = 96 kHz

V rms Ω V

dB dB mdB/°C mV

is the greater of the input or

S-MAX

output sample rate

20 Hz to f f

= 44.1 kHz, f

/2, 1 kHz, −60 dBFS input,

= 48 kHz

OUT

/2, 1 kHz, 0 dBFS input,

= 48 kHz

OUT

Rev. A | Page 4 of 60

ADAV803

Parameter Min Typ Max Unit Comments

Crosstalk (EIAJ Method) −110 Phase Deviation 0.05 Mute Attenuation −95.625 Volume Control Step Size (256 Steps) 0.375 Group Delay

48 kHz 630 96 kHz 155 192 kHz 66

DAC LOW-PASS DIGITAL INTERPOLATION FILTER CHARACTERISTICS

Pass-Band Frequency 20 kHz fS = 44.1 kHz 22 kHz fS = 48 kHz 42 kHz fS = 96 kHz Stop-Band Frequency 24 kHz fS = 44.1 kHz 26 kHz fS = 48 kHz 60 kHz fS = 96 kHz Stop-Band Attenuation 70 dB fS = 44.1 kHz 70 dB fS = 48 kHz 70 dB fS = 96 kHz

Pass-Band Ripple ±0.002 dB fS = 44.1 kHz ±0.002 dB fS = 48 kHz ±0.005 dB fS = 96 kHz PLL SECTION

Master Clock Input Frequency 27/54 MHz

Generated System Clocks

MCLKO 27/54 MHz SYSCLK1 256 768 × fS

SYSCLK2 256 768 × fS

SYSCLK3 256 512 × fS 256/512 × 32 kHz/44.1 kHz/48 kHz

Jitter

SYSCLK1 65 ps rms SYSCLK2 75 ps rms SYSCLK3 75 ps rms

DIR SECTION

Input Sample Frequency 27.2 200 kHz

Differential Input Voltage 200 mV DIT SECTION

Output Sample Frequency 27.2 DIGITAL I/O

Input Voltage High, VIH 2.0

Input Voltage Low, VIL

Input Leakage, IIH @ VIH = 3.3 V

Input Leakage, IIL @ VIL = 0 V

Output Voltage High, VOH @ IOH = 0.4 mA 2.4 V

Output Voltage Low, VOL @ IOL = −2 mA

Input Capacitance

dB Degrees dB dB

μs μs μs

256/384/512/768 × 32 kHz/44.1 kHz/48 kHz

200 kHz

DVDD V

0.8 V 10 μA 10 μA

0.4 V 15 pF

Rev. A | Page 5 of 60

ADAV803

Parameter Min Typ Max Unit Comments

POWER

Supplies

Voltage, AVDD 3.0 3.3 3.6 V Voltage, DVDD 3.0 3.3 3.6 V Voltage, ODVDD 3.0 3.3 3.6 V

Operating Current All supplies at 3.3 V

Analog Current 60 mA Digital Current 38 mA Digital Interface Current 13 mA DIRIN/DIROUT Current 5 mA PLL Current 18 mA

Power-Down Current

Analog Current 18 mA Digital Current 2.5 mA Digital Interface Current 700 μA DIRIN/DIROUT Current 3.5 mA PLL Current 900 μA

Power Supply Rejection

Signal at Analog Supply Pins −70 dB 1 kHz, 300 mV p-p

−70 dB 20 kHz, 300 mV p-p

Guaranteed by design.

RESET low, no MCLK

Rev. A | Page 6 of 60

ADAV803

TIMING SPECIFICATIONS

Timing specifications are guaranteed over the full temperature and supply range.

Table 3.

Parameter Symbol Min Typ Max Unit Comments

MASTER CLOCK AND RESET

MCLKI Frequency f

XIN Frequency f

RESET Low I2C PORT

SCL Clock Frequency f

SCL High t

SCL Low t

Start Condition

Setup Time t

Hold Time t Data Setup Time tDS 100 ns SCL Rise Time t SCL Fall Time t SDA Rise Time t SDA Fall Time t

Stop Condition

Setup Time t

SERIAL PORTS

Slave Mode

xBCLK High t xBCLK Low t xBCLK Frequency f xLRCLK Setup t xLRCLK Hold t xSDATA Setup t xSDATA Hold t xSDATA Delay t

Master Mode

xLRCLK Delay t xSDATA Delay t xSDATA Setup t xSDATA Hold t

The prefix x refers to I-, O-, IAUX-, or OAUX- for the full pin name.

12.288 54 MHz

MCLK

27 54 MHz

XIN

20 ns

RESET

400 kHz

SCL

0.6 μs

SCLH

1.3 μs

SCLL

0.6 μs Relevant for repeated start condition

SCS

0.6 μs After this period, the first clock is generated

SCH

300 ns

SCR

300 ns

SCF

300 ns

SDR

300 ns

SDF

0.6 μs

SCS

40 ns

SBH

40 ns

SBL

64 × fS

SBF

10 ns To xBCLK rising edge

SLS

10 ns From xBCLK rising edge

SLH

10 ns To xBCLK rising edge

SDS

10 ns From xBCLK rising edge

SDH

10 ns From xBCLK falling edge

SDD

5 ns From xBCLK falling edge

MLD

10 ns From xBCLK falling edge

MDD

10 ns From xBCLK rising edge

MDS

10 ns From xBCLK rising edge

MDH

TEMPERATURE RANGE

Table 4.

Parameter Min Typ Max Unit

Specifications Guaranteed 25 °C Functionality Guaranteed −40 +85 °C Storage −65 +150 °C

Rev. A | Page 7 of 60

ADAV803

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

DVDD to DGND and ODVDD

to DGND AVDD to AGND 0 V to 4.6 V Digital Inputs DGND − 0.3 V to DVDD + 0.3 V Analog Inputs AGND − 0.3 V to AVDD + 0.3 V AGND to DGND −0.3 V to +0.3 V Reference Voltage

Soldering (10 sec) 300°C

0 V to 4.6 V

Indefinite short circuit to ground

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 8 of 60

ADAV803

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

VOUTLNCVOUTR

AVD D

ADVDD

ADGND

PLL_LF2

PLL_LF1

PLL_GND

PLL_VDD

DGND

SYSCLK1

SYSCLK2

SYSCLK3

XIN

XOUT

MCLKO

MCLKI

DVDD

DGND

VINR

VINL

AGND

AVD D

DIR_LF

DIR_GND

DIR_VDD

RESET

AD0

SDA

SCL

AD1

EROL/INT

ZEROR

DVDD

DGND

CAPLN

CAPLP

AGND

PIN 1 INDICATOR

CAPRP

64 63 62 61 60 59 58

17 18 19 20 21 22 23 24

CAPRN

AVD D

AGND

VREF

AGND

FILTD

57 56 55 54 53 52 51 50 49

ADAV803

TOP VIEW

(Not to Scale)

25 26 27 31302928 32

DIRIN

OBCLK

ODVDD

DITOUT

ODGND

OSDATA

OLRCLK

OAUXLRCLK

IAUXBCLK

OAUXBCLK

IAUXSDATA

IAUXLRCLK

OAUXSDATA

04756-002

NC = NO CONNECT

IBCLK

ISDATA

ILRCLK

Figure 2. ADAV803 Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 VINR I Analog Audio Input, Right Channel. 2 VINL I Analog Audio Input, Left Channel. 3 AGND Analog Ground. 4 AVDD Analog Voltage Supply. 5 DIR_LF DIR Phase-Locked Loop (PLL) Filter Pin. 6 DIR_GND Supply Ground for DIR Analog Section. This pin should be connected to AGND. 7 DIR_VDD Supply for DIR Analog Section. This pin should be connected to AVDD. 8

RESET

I Asynchronous Reset Input (Active Low).

9 AD0 I I2C Address LSB. 10 SDA I/O Data Input/Output of I2C-Compatible Control Interface. 11 SCL I Clock Input of I2C Compatible Control Interface. 12 AD1 I I2C Address MSB. 13 ZEROL/INT O

Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined by

the INTRPT bit in DAC Control Register 4. 14 ZEROR O Right Channel (Output) Zero Flag. 15 DVDD Digital Voltage Supply. 16 DGND Digital Ground. 17 ILRCLK I/O Sampling Clock (LRCLK) of Playback Digital Input Port. 18 IBCLK I/O Serial Clock (BCLK) of Playback Digital Input Port. 19 ISDATA I Data Input of Playback Digital Input Port. 20 OLRCLK I/O Sampling Clock (LRCLK) of Record Digital Output Port. 21 OBCLK I/O Serial Clock (BCLK) of Record Digital Output Port. 22 OSDATA O Data Output of Record Digital Output Port. 23 DIRIN I Input to Digital Input Receiver (S/PDIF). 24 ODVDD Interface Digital Voltage Supply. 25 ODGND Interface Digital Ground. 26 DITOUT O S/PDIF Output from DIT.

Rev. A | Page 9 of 60

ADAV803

Pin No. Mnemonic I/O Description

27 OAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Output Port. 28 OAUXBCLK I/O Serial Clock (BCLK) of Auxiliary Digital Output Port. 29 OAUXSDATA O Data Output of Auxiliary Digital Output Port. 30 IAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Input Port. 31 IAUXBCLK I/O Serial Clock (BCLK) of Auxiliary Digital Input Port. 32 IAUXSDATA I Data Input of Auxiliary Digital Input Port. 33 DGND Digital Ground. 34 DVDD Digital Supply Voltage. 35 MCLKI I External MCLK Input. 36 MCLKO O Oscillator Output. 37 XOUT I Crystal Input. 38 XIN I Crystal or External MCLK Input. 39 SYSCLK3 O System Clock 3 (from PLL2). 40 SYSCLK2 O System Clock 2 (from PLL2). 41 SYSCLK1 O System Clock 1 (from PLL1). 42 DGND Digital Ground. 43 PLL_VDD Supply for PLL Analog Section. This pin should be connected to AVDD. 44 PLL_GND Ground for PLL Analog Section. This pin should be connected to AGND. 45 PLL_LF1 Loop Filter for PLL1. 46 PLL_LF2 Loop Filter for PLL2. 47 ADGND Analog Ground (Mixed Signal). This pin should be connected to AGND. 48 ADVDD Analog Voltage Supply (Mixed Signal). This pin should be connected to AVDD. 49 VOUTR O Right Channel Analog Output. 50 NC No Connect. 51 VOUTL O Left Channel Analog Output. 52 NC No Connect. 53 AVDD Analog Voltage Supply. 54 AGND Analog Ground. 55 FILTD Output DAC Reference Decoupling. 56 AGND Analog Ground. 57 VREF Voltage Reference Voltage. 58 AGND Analog Ground. 59 AVDD Analog Voltage Supply. 60 CAPRN ADC Modulator Input Filter Capacitor (Right Channel, Negative). 61 CAPRP ADC Modulator Input Filter Capacitor (Right Channel, Positive). 62 AGND Analog Ground. 63 CAPLP ADC Modulator Input Filter Capacitor (Left Channel, Positive). 64 CAPLN ADC Modulator Input Filter Capacitor (Left Channel, Negative).

Rev. A | Page 10 of 60

ADAV803

TYPICAL PERFORMANCE CHARACTERISTICS

–50

MAGNITUDE ( dB)

–100

–150

0 0.5 1.0 1.5 2.0

FREQUENCY (Normalized to fS)

Figure 3. ADC Composite Filter Response

–5

–10

–15

MAGNITUDE (d B)

–20

–25

–30

0 5 10 15 20

Figure 4. ADC High-Pass Filter Response, f

FREQUENCY (Hz)

= 48 kHz

–50

MAGNITUDE (dB)

–100

04756-003

–150

0 96 192 288 384

FREQUENCY (kHz )

04756-006

Figure 6. DAC Composite Filter Response, 48 kHz

–50

MAGNITUDE (dB)

–100

04756-004

–150

02412 36 48

FREQUENCY (kHz)

Figure 7. DAC Pass-Band Filter Response, 48 kHz

04756-007

–5

–10

–15

MAGNITUDE (d B)

–20

–25

–30

0 5 10 15 20

Figure 5. ADC High-Pass Filter Response, f

FREQUENCY (Hz)

= 96 kHz

04756-005

Rev. A | Page 11 of 60

0.06

0.04

0.02

MAGNITUDE (d B)

–0.02

–0.04

–0.06

0816

FREQUENCY ( kHz)

Figure 8. DAC Filter Ripple, 48 kHz

04756-008

ADAV803

–50

–100

MAGNITUDE (dB)

–100

–150

0 192 384 576 768

FREQUENCY (kHz)

Figure 9. DAC Composite Filter Response, 96 kHz

–50

MAGNITUDE (dB)

–100

–150

0 2448729

FREQUENCY ( kHz)

Figure 10. DAC Pass-Band Filter Response, 96 kHz

04756-009

04756-010

MAGNITUDE (dB)

–150

–200

0 384 768 1152 1536

FREQUENCY (kHz)

Figure 12. DAC Composite Filter Response, 192 kHz

–2

–4

–6

MAGNITUDE (dB)

–8

–10

48 64 80 96

FREQUENCY (kHz)

Figure 13. DAC Pass-Band Filter Response, 192 kHz

04756-012

04756-013

0.10

0.05

MAGNITUDE (dB)

–0.05

–0.10

0 2448729

FREQUENCY ( kHz)

Figure 11. DAC Filter Ripple, 96 kHz

04756-011

Rev. A | Page 12 of 60

0.50

0.40

0.30

0.20

0.10

–0.10

MAGNITUDE (dB)

–0.20

–0.30

–0.40

–0.50

0 8 16 32 64

FREQUENC Y (kHz)

Figure 14. DAC Filter Ripple, 192 kHz

04756-014

ADAV803

–20

DNR = 102dB

(A-WEIGHTED)

–20

THD+N = 95dB

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 2 4 6 8 1012 141618 20

Figure 15. DAC Dynamic Range, f

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

02468101214161820

Figure 16. DAC THD + N, f

FREQUENCY (kHz)

= 48 kHz

THD+N = 96dB

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

04756-015

04756-016

–160

0 5 10 15 20 25 30 35 40 45 48

Figure 18. DAC THD + N, f

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20

Figure 19. ADC Dynamic Range, f

FREQUENCY (kHz)

= 96 kHz

FREQUENCY (kHz)

= 48 kHz

DNR = 102dB

(A-WEIGHTED)

04756-018

04756-019

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20 25 30 35 40 45 48

Figure 17. DAC Dynamic Range, f

FREQUENCY (kHz)

= 96 kHz

DNR = 102dB

(A-WEIGHTED)

04756-017

Rev. A | Page 13 of 60

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20

Figure 20. DAC THD + N, f

FREQUENCY (kHz)

= 48 kHz

THD+N = 92dB

= –3dB)

04756-020

ADAV803

–20

DNR = 102dB

(A-WEIGHTED)

–20

THD+N = 92dB

= –3dB)

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 8 16 24 32 40 48

Figure 21. ADC Dynamic Range, f

FREQUENCY (kHz)

= 96 kHz

04756-021

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 8 16 24 32 40 48

Figure 22. ADC THD + N, f

FREQUENCY (kHz)

= 96 kHz

04756-022

Rev. A | Page 14 of 60

ADAV803

FUNCTIONAL DESCRIPTION

ADC SECTION

The ADAV803’s ADC section is implemented using a secondorder multibit (5 bits) Σ-Δ modulator. The modulator is sampled at either half of the ADC MCLK rate (modulator clock = 128 × f clock = 64 × f followed by a cascade of three half-band FIR filters. The Sinc decimates by a factor of 16 at 48 kHz and by a factor of 8 at 96 kHz. Each of the half-band filters decimates by a factor of 2.

Figure 23 shows the details of the ADC section. By default, the ADC assumes that the MCLK rate is 256 times the sample rate. The ADC can be clocked by a number of different clock sources to control the sample rate. MCLK selection for the ADC is set by Internal Clocking Control Register 1 (Address 0x76). The ADC provides an output word of up to 24 bits of resolution in twos complement format. The output word can be routed to the output ports, the sample rate converter, or the S/PDIF digital transmitter.

) or one-quarter of the ADC MCLK rate (modulator

). The digital decimator consists of a Sinc^5 filter

)

PLL2 INTE RNAL

PLL1 INTE RNAL

MCLKI

DIR PLL(256 × f

DIR PLL(512 × f

ADC MCLK

DIVIDER

ADC

MCLK

ADC

XIN

REG 0x76 BITS[4:2]

REG 0x6F BITS[1:0]

Programmable Gain Amplifier (PGA)

The input of the record channel features a PGA that converts the single-ended signal to a differential signal, which is applied to the analog Σ-Δ modulator of the ADC. The PGA can be programmed to amplify a signal by up to 24 dB in 0.5 dB increments.

VREF

Figure 24 shows the structure of the PGA circuit.

4kΩ TO 64k Ω

EXTERNAL

4kΩ

8kΩ

CAPACITOR

8kΩ

(1nF NPO)

125Ω

EXTERNAL

CAPACITOR

(1nF NPO)

CAPxN

EXTERNAL

CAPACITOR

(1nF NPO)

CAPxP

Figure 24. PGA Block Diagram

MODULATOR

04756-024

Analog Σ-Δ Modulator

The ADC features a second-order, multibit, Σ-Δ modulator. The input features two integrators in cascade followed by a flash converter. This multibit output is directed to a scrambler, followed by a DAC for loop feedback. The flash ADC output is also converted from thermometer coding to binary coding for input as a 5-bit word to the decimator.

Figure 25 shows the

ADC block diagram.

The ADC also features independent digital volume control for the left and right channels. The volume control consists of 256 linear steps, with each step reducing the digital output codes by 0.39%. Each channel also has a peak detector that records the peak level of the input signal. The peak detector register is cleared by reading it.

Figure 23. Clock Path Control on the ADC

MULTIBIT

Σ-Δ

MODULATOR

ADC MCLK

AMC

(REG 0x6E

BIT 7)

÷2

÷4

MODULATOR

CLOCK

(6.144MHz MAX)

04756-023

SINC^5

DECIMATOR

384kHz

768kHz

HALF-BAND

FILTER

VOLUME

CONTROL

192kHz

384kHz

Figure 25. ADC Block Diagram

Rev. A | Page 15 of 60

HPF

SINC

COMPENSATION

96kHz

192kHz

PEAK

DETECT

HALF-BAND

FILTER

48kHz

96kHz

04756-025

ADAV803

Automatic Level Control (ALC)

The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and automatically reduces the gain, if the signal at the input pins causes the ADC output to exceed a preset limit. This function can be useful to maximize the signal dynamic range when the input level is not well defined. The PGA can be used to amplify the unknown signal, and the ALC reduces the gain until the ADC output is within the preset limits. This results in maximum front end gain.

Because the ALC block monitors the output of the ADC, the volume control function should not be used. The ADC volume control scales the results from the ADC, and any distortion caused by the input signal exceeding the input range of the ADC is still present at the output of the ADC, but scaled by a value determined by the volume control register.

The ALC block has two functions, attack mode and recovery mode. Recovery mode consists of three settings: no recovery, normal recovery, and limited recovery. These modes are discussed in the following sections. of the ALC block. When the ALC has been enabled, any changes made to the PGA or ALC settings are ignored. To change the functionality of the ALC, it must first be disabled. The settings can then be changed and the ALC re-enabled.

Figure 26 is a flow diagram

Attack Mode

When the absolute value of the ADC output exceeds the level set by the attack threshold bits in ALC Control Register 2, attack mode is initiated. The PGA gain for both channels is reduced by one step (0.5 dB). The ALC then waits for a time determined by the attack timer bits before sampling the ADC output value again. If the ADC output is still above the threshold, the PGA gain is reduced by a further step. This procedure continues until the ADC output is below the limit set by the attack threshold bits. The initial gains of the PGAs are defined by the ADC left PGA gain register and the ADC right PGA gain register, and they can have different values. The ALC subtracts a common gain offset to these values. The ALC preserves any gain difference in dB as defined by these registers. At no time do the PGA gains exceed their initial values. The initial gain setting, therefore, also serves as a maximum value.

The limit detection mode bit in ALC Control Register 1 determines how the ALC responds to an ADC output that exceeds the set limits. If this bit is a 1, both channels must exceed the threshold before the gain is reduced. This mode can be used to prevent unnecessary gain reduction due to spurious noise on a single channel. If the limit detection mode bit is a 0, the gain is reduced when either channel exceeds the threshold.

No Recovery Mode

By default, there is no gain recovery. Once the gain has been reduced, it is not recovered until the ALC is reset, either by toggling the ALCEN bit in ALC Control Register 1 or by writing any value to ALC Control Register 3. The latter option is more efficient because it requires only one write operation to reset the ALC function. No recovery mode prevents volume modulation of the signal caused by adjusting the gain, which can create undesirable artifacts in the signal. The gain can be reduced but not recovered. Therefore, care should be taken that spurious signals do not interfere with the input signal because these might trigger a gain reduction unnecessarily.

Normal Recovery Mode

Normal recovery mode allows for the PGA gain to be recovered, provided that the input signal meets certain criteria. First, the ALC must not be in attack mode, that is, the PGA gain has been reduced sufficiently such that the input signal is below the level set by the attack threshold bits. Second, the output result from the ADC must be below the level set by the recovery threshold bits in the ALC control register. If both of these criteria are met, the gain is recovered by one step (0.5 dB). The gain is incrementally restored to its original value, assuming that the ADC output level is below the recovery threshold at intervals determined by the recovery time bits.

If the ADC output level exceeds the recovery threshold while the PGA gain is being restored, the PGA gain value is held and does not continue restoration until the ADC output level is again below the recovery threshold. Once the PGA gain is restored to its original value, it is not changed again unless the ADC output value exceeds the attack threshold and the ALC then enters attack mode. Care should be taken when using this mode to choose values for the attack and recovery thresholds that prevent excessive volume modulation caused by continuous gain adjustments.

Limited Recovery Mode

Limited recovery mode offers a compromise between no recovery and normal recovery modes. If the output level of the ADC exceeds the attack threshold, attack mode is initiated. When attack mode has reduced the PGA gain to suitable levels, the ALC attempts to recover the gain to its original level. If the ADC output level exceeds the level set by the recovery threshold bits, a counter is incremented (GAINCNTR). This counter is incremented at intervals equal to the recovery time selection, if the ADC has any excursion above the recovery threshold. If the counter reaches its maximum value, determined by the GAINCNTR bits in ALC Control Register 1, the PGA gain is deemed suitable and no further gain recovery is attempted. Whenever the ADC output level exceeds the attack threshold, attack mode is reinitiated and the counter is reset.

Rev. A | Page 16 of 60

ADAV803

ATTA

Selecting a Sample Rate

The output sample rate of the ADC is always ADC MCLK/256, as shown in

Figure 23. By default, the ADC modulator runs at ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz, the ADC modulator should be set to run at ADC MCLK/4. This is achieved by setting the AMC (ADC Modulator Clock) bit in the ADC Control Register 1. To compensate for the reduced modulator clock speed, a different set of filters is used in the decimator section, ensuring that the sample rate remains the same.

The AMC bit can also be used to boost the THD + N performance of the ADC at the expense of dynamic range. The improvement is typically 0.5 dB to 1.0 dB and works because

IS A RECOV ERY

MODE ENABL ED?

selecting the lower modulator rate reduces the amount of digital noise, improving THD + N, but also reduces the oversampling ratio, therefore reducing the dynamic range by a corresponding amount.

For best performance of the ADC, avoid using similar frequency clocks from separate sources in the ADAV803. For example, running the ADC from a 12.288 MHz clock connected to MCLKI and using the PLL to generate a separate 12.288 MHz clock for the DAC can reduce the performance of the ADC. This is due to the interaction of the clocks, which generate beat frequencies that can affect the charge on the switch capacitors of the analog inputs.

CK MODE

WAIT FOR SAMPLE

IS SAMPLE

GREATER THAN ATTACK

THRESHOL D?

YES

INCREASE GAIN BY 0.5dB

HAS GAIN BEEN

FULLY RESTORED?

YES

DECREASE GAIN BY 0.5dB

AND WAIT ATTACK TIME

LIMITED RECOVERY

WAIT FOR SAMPLE WAIT FOR SAMPLE

IS SAMPLE

ABOVE ATTACK

THRESHOLD?

HAS RECOVERY

TIME BEEN REACHED?

YES

ARE ALL

SAMPLES BELOW

RECOVERY

THRESHOLD?

YES NO

NO NO

INCREMENT

GAINCNTR

IS GAINCNTR

AT MAXIMUM?

YES

NORMAL RECO VERY

IS SAMPLE

ABOVE ATTACK

THRESHOL D?

NONO

HAS RECOVE RY

TIME BEEN REACHED?

YES

ARE ALL

SAMPLES BELOW

RECOVERY

THRESHOL D?

YES

INCREASE GAIN BY 0.5dB

WAIT RECOVERY TIME

HAS GAIN BEEN

FULLY RESTORED?

YESNO

04756-026

Figure 26. ALC Flow Diagram

Rev. A | Page 17 of 60

ADAV803

)

DAC SECTION

The ADAV803 has two DAC channels arranged as a stereo pair with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375 dB per step. The DAC can receive data from the playback or auxiliary input ports, the SRC, the ADC, or the DIR. Each analog output pin sits at a dc level of VREF, and swings 1.0 V rms for a 0 dB digital input signal. A single op amp third-order external low-pass filter is recommended to remove high frequency noise present on the output pins. Note that the use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band. Care should be taken in selecting these components.

The FILTD and VREF pins should be bypassed by external capacitors to AGND. The FILTD pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. The voltage at the VREF pin can be used to bias external op amps used to filter the output signals. For applications in which the VREF is required to drive external op amps, which might draw more than 50 μA or have dynamic load changes, extra buffering should be used to preserve the quality of the ADAV803 reference.

The digital input data source for the DAC can be selected from a number of available sources by programming the appropriate bits in the datapath control register. digital data source and the MCLK source for the DAC are selected. Each DAC has an independent volume register giving 256 steps of control, with each step giving approximately

0.375 dB of attenuation. Note that the DACs are muted by default to prevent unwanted pops, clicks, and other noises from appearing on the outputs while the ADAV803 is being configured. Each DAC also has a peak-level register that records the peak value of the digital audio data. Reading the register clears the peak.

Figure 27 shows how the

Selecting a Sample Rate

Correct operation of the DAC is dependent upon the data rate provided to the DAC, the master clock applied to the DAC, and the selected interpolation rate. By default, the DAC assumes that the MCLK rate is 256 times the sample rate, which requires an 8× oversampling rate. This combination is suitable for sample rates of up to 48 kHz.

For a 96 kHz data rate that has a 24.576 MHz MCLK (256 × f

)

associated with it, the DAC MCLK divider should be set to divide the MCLK by 2. This prevents the DAC engine from running too fast. To compensate for the reduced MCLK rate, the interpolator should be selected to operate in 4 × (DAC MCLK = 128 × f

). Similar combinations can be selected for

different sample rates.

PLL2 INTE RNAL

PLL1 INTE RNAL

MCLKI

REG 0x65 BITS[3:2]

DAC

INPUT

XIN

REG 0x76 BITS[7:5]

REG 0x63 BITS[5:3]

AUXILIARY IN

PLAYBACK

DIR

ADC

04756-027

DIR PLL( 256 × f

DIR PLL( 512 × f

MCLK

DIVIDER

DAC

MCLK

DAC

Figure 27. Clock and Datapath Control on the DAC

PEAK

DETECTOR

VOLUME/MUTE

CONTROL

ZERO DETECT

FROM DAC DATA PATH MULTIPLEXER

04756-028

ANALOG

OUTPUT

DAC

MULTI-BIT

Σ-Δ

MODULATOR

TO CONT ROL

REGISTERS

INTERPOLATOR

TO ZERO FLAG PINS

Figure 28. DAC Block Diagram

Rev. A | Page 18 of 60

ADAV803

SAMPLE RATE CONVERTER (SRC) FUNCTIONAL OVERVIEW

During asynchronous sample rate conversion, data can be converted at the same sample rate or at different sample rates. The simplest approach to an asynchronous sample rate conversion is to use a zero-order hold between the two samplers, as shown in is never equal to T1, nor is the ratio between T2 and T1 rational. As a result, samples at f producing an error in the resampling process.

The frequency domain shows the wide side lobes that result from this error when the sampling of f the attenuated images from the sin(x)/x nature of the zero-order hold. The images at f hold are infinitely attenuated. Because the ratio of T2 to T1 is an irrational number, the error resulting from the resampling at f

can never be eliminated. The error can be significantly

S_OUT

reduced, however, through interpolation of the input data at f

. Therefore, the sample rate converter in the ADAV803 is

S_IN

conceptually interpolated by a factor of 2

=1/T1

S_IN

SPECTRUM OF Z ERO-ORDER HO LD OUTPUT

Figure 29. In an asynchronous system, T2

are repeated or dropped,

S_OUT

is convolved with

S_OUT

(dc signal images) of the zero-order

S_IN

ZERO-ORDER

HOLD

S_OUT

ORIGINAL SIGNAL

SAMPLED AT

SIN(X)/X O F ZERO-ORDER HOLD

S_IN

OUT

= 1/T2

In the frequency domain shown in Figure 31, the interpolation expands the frequency axis of the zero-order hold. The images from the interpolation can be sufficiently attenuated by a good low-pass filter. The images from the zero-order hold are now pushed by a factor of 2 of the zero-order hold, which is f zero-order hold are the determining factor for the fidelity of the output at f

INTERPOLATE

BY N

S_IN

TIME DOMAIN OF

TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER

TIME DOMAIN OF

TIME DOMAIN OF THE ZERO-ORDER HO LD OUTPUT

LOW-PASS

FILTER

SAMPLES

S_IN

RESAMPLING

S_OUT

Figure 30. SRC Time Domain

closer to the infinite attenuation point

× 220. The images at the

S_IN

S_OUT

S_IN

INTERPOLATE

BY N

LOW-PASS

FILTER

ZERO-ORDER

HOLD

ZERO-ORDER

HOLD

S_OUT

OUT

04756-030

SPECTRUM OF

S_OUT

FREQUENCY RESPONSE OF WITH ZERO -ORDER HOLD SPECTRUM

S_OUT

Figure 29. Zero-Order Hold Used by f

SAMPLING

S_OUT

CONVOLVED

to Resample Data from f

S_ OUT

2 ×

S_OUT

S_IN

04756-029

Conceptual High Interpolation Model

Interpolation of the input data by a factor of 2

− 1) samples between each f

sample. Figure 30 shows

S_IN

involves placing

both the time domain and the frequency domain of interpolation by a factor of 2 steps of zero-stuffing (2 f

sample and convolving this interpolated signal with a

S_IN

. Conceptually, interpolation by 220 involves the

− 1) number of samples between each

digital low-pass filter to suppress the images. In the time domain, it can be seen that f sample from the zero-order hold, as opposed to the nearest f

selects the closest f

S_OUT

S_IN

× 220

S_IN

sample in the case of no interpolation. This significantly reduces the resampling error.

Rev. A | Page 19 of 60

FREQUENCY DO MAIN OF SAMPLES AT

FREQUENCY DO MAIN OF T HE INTERPO LATION

SIN(X)/X O F ZERO-ORDER HOLD

FREQUENCY DO MAIN OF

FREQUENCY DO MAIN AFTER RESAMPL ING

S_OUT

S_IN

RESAMPLING

220 ×

S_IN

220 ×

S_IN

04756-031

Figure 31. Frequency Domain of the Interpolation and Resampling

ADAV803

The worst-case images can be computed from the zero-order hold frequency response:

Maximum Image = sin(π × F/f

S_INTERP

)/(π × F/f

S_INTERP

)

where: F is the frequency of the worst-case image that would be

× f

± f

S_IN

/2.

S_IN

× 220.

equal to

S_IN

= f

S_INTERP

The following worst-case images would appear for f 192 kHz:

Image at f

− 96 kHz = −125.1 dB

S_INTERP

+ 96 kHz = −125.1 dB

S_INTERP

Hardware Model

The output rate of the low-pass filter in Figure 30 is the interpolation rate:

× 192,000 kHz = 201.3 GHz

Sampling at a rate of 201.3 GHz is clearly impractical, in addition to the number of taps required to calculate each

sample,

S_IN

interpolated sample. However, because interpolation by 2 involves zero-stuffing 2

− 1 samples between each f most of the multiplies in the low-pass FIR filter are by zero. A further reduction can be realized because only one interpolated sample is taken at the output at the f convolution needs to be performed per f

convolutions. A 64-tap FIR filter for each f

rate, so only one

S_OUT

period instead of

S_OUT

sample is

sufficient to suppress the images caused by the interpolation.

One difficulty with the preceding approach is that the correct interpolated sample must be selected upon the arrival of f Because there are 2 arrival of the f 1/201.3 GHz = 4.96 ps. Measuring the f

possible convolutions per f

clock must be measured with an accuracy of

S_OUT

period with a clock

S_OUT

period, the

of 201.3 GHz frequency is clearly impossible; instead, several coarse measurements of the f

clock period are made and

S_OUT

averaged over time.

Another difficulty with the preceding approach is the number of coefficients required. Because there are 2 tions with a 64-tap FIR filter, there must be 2 coefficients for each tap, which requires a total of 2

possible convolu-

polyphase

coefficients. To reduce the number of coefficients in ROM, the SRC stores a small subset of coefficients and performs a high order interpolation between the stored coefficients.

> f

The preceding approach works when f when the output sample rate, f rate, f

, the ROM starting address, input data, and length of

S_IN

, is less than the input sample

S_OUT

. However,

S_IN

the convolution must be scaled. As the input sample rate rises over the output sample rate, the antialiasing filter’s cutoff frequency must be lowered because the Nyquist frequency of the output samples is less than the Nyquist frequency of the input samples. To move the cutoff frequency of the antialiasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of (f

S_IN/fS_OUT

This technique is supported by the Fourier transform property that, if f(t) is F(ω), then f(k × t) is F(ω/k). Thus, the range of decimation is limited by the size of the RAM.

SRC Architecture

The architecture of the sample rate converter is shown in Figure 32. The sample rate converter’s FIFO block adjusts the left and right input samples and stores them for the FIR filter’s convolution cycle. The f

counter provides the write address

S_IN

to the FIFO block and the ramp input to the digital servo loop. The ROM stores the coefficients for the FIR filter convolution and performs a high order interpolation between the stored coefficients. The sample rate ratio block measures the sample rate for dynamically altering the ROM coefficients and scaling of the FIR filter length as well as the input data. The digital servo loop automatically tracks the f

S_IN

and f

sample rates

S_OUT

and provides the RAM and ROM start addresses for the start of the FIR filter convolution.

RIGHT DATA IN

LEFT DATA IN

S_IN

COUNTER

S_IN

S_OUT

Figure 32. Architecture of the Sample Rate Converter

FIFO

DIGITAL

SERVO LOOP

SAMPLE RATE RATIO

SAMPLE

RATE RATIO

ROM A

ROM B

ROM C

ROM D

FIR FILTER

EXTERNAL

RATIO

HIGH ORDER INTERP

L/R DATA OUT

04756-032

The FIFO receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the RAM. The input data is scaled by the sample rate ratio because, as the FIR filter length of the convolution increases, so does the amplitude of the convolution output. To keep the output of the FIR filter from saturating, the input data is scaled down by multiplying it by (f

S_OUT/fS_IN

) when f

S_OUT

< f

. The FIFO also scales the input

S_IN

data for muting and unmuting of the SRC.

The RAM in the FIFO is 512 words deep for both left and right channels. An offset to the write address provided by the f

S_IN

counter is added to prevent the RAM read pointer from overlapping the write address. The minimum offset on the SRC is 16 samples. However, the group delay and mute-in register can be used to increase this offset.

The number of input samples added to the write pointer of the FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay register. This feature is useful in varispeed applications to prevent the read pointer to the FIFO from running ahead of the write pointer. When set, Bit 7 of the group delay and mute-in register soft-mutes the sample rate. Increasing the offset of the

Rev. A | Page 20 of 60

ADAV803

write address pointer is useful for applications in which small changes in the sample rate ratio between f

S_IN

and f

S_OUT

are expected. The maximum decimation rate can be calculated from the RAM word depth and the group delay as

(512 − 16)/64 taps = 7.75

for short group delay and

(512 − 64)/64 taps = 7

for long group delay.

The digital servo loop is essentially a ramp filter that provides the initial pointer to the address in RAM and ROM for the start of the FIR convolution. The RAM pointer is the integer output of the ramp filter, and the ROM is the fractional part. The digital servo loop must provide excellent rejection of jitter on the f

and f

S_IN

clock within 4.97 ps. The digital servo loop also divides

S_OUT

the fractional part of the ramp output by the ratio of f to dynamically alter the ROM coefficients when f

REG 0x76

clocks, as well as measure the arrival of the

S_OUT

MCLKI

XIN

BIT[1: 0]

PLLINT2PLLINT1

)

DIR PLL(512 ×

SRC

MCLK

SRC

OUTPUT

)

ICLK2

ICLK1

DIR PLL(256 ×

SRC

INPUT

XIN

PLLINT2PLLINT1

REG 0x77 BIT[4:3]

REG 0x00 BITS[ 1:0]

REG 0x62 BITS[7:6]

MCLKI

AUXILIARY IN

PLAYBACK

DIR

ADC

S_IN

S_IN/fS_OUT

> f

S_OUT

04756-033

Figure 33. Clock and Datapath Control on the SRC

The digital servo loop is implemented with a multirate filter. To settle the digital servo loop filter more quickly upon startup or a change in the sample rate, a fast mode has been added to the filter. When the digital servo loop starts up or the sample rate is changed, the digital servo loop enters fast mode to adjust and settle on the new sample rate. Upon sensing that the digital servo loop is settling down to a reasonable value, the digital servo loop returns to normal (or slow) mode.

During fast mode, the MUTE_IND bit in the s Sample Rate Converter Error register is asserted to let the user know that clicks or pops might be present in the digital audio data. The

output of the SRC can be muted by asserting Bit 7 of the Group Delay and Mute register until the SRC has changed to slow mode. The MUTE_IND bit can be set to generate an interrupt when the SRC changes to slow mode, indicating that the data is being sample rate converted accurately.

The frequency responses of the digital servo loop for fast mode and slow mode are shown in filter when f f

. The FIR filter performs its convolution by loading in the

S_OUT

≥ f

S_IN

Figure 34. The FIR filter is a 64-tap

and is (f

S_IN/fS_OUT

) × 64 taps when f

S_IN

starting address of the RAM address pointer and the ROM address pointer from the digital servo loop at the start of the f

period. The FIR filter then steps through the RAM by

S_OUT

decrementing its address by 1 for each tap, and the ROM pointer increments its address by the (f f

> f

S_IN

S_OUT

or 220 for f

S_OUT

≥ f

. Once the ROM address rolls

S_IN

S_OUT/fS_IN

) × 220 ratio for

over, the convolution is completed.

–20

–40

–60

–80

–100

–120

–140

MAGNITUDE (d B)

–160

–180

–200

–220

0.01 0.1 1 10 100 1k 10k 100k

SLOW MODE

FREQUENCY (Hz)

Figure 34. Frequency Response of the Digital Servo Loop;

is the X-Axis, f

S_IN

= 192 kHz, Master Clock is 30 MHz

S_OUT

FAST M OD E

The convolution is performed for both the left and right channels, and the multiply accumulate circuit used for the convolution is shared between the channels. The f

S_IN/fS_OUT

sample rate ratio circuit is used to dynamically alter the coefficients in the ROM when f calculated by comparing the output of an f output of an f If f

> f

S_IN

by more than two f

counter. If f

S_IN

, the sample rate ratio is updated, if it is different

S_OUT

periods from the previous f

S_OUT

S_IN

> f

. The ratio is

S_OUT

counter to the

S_OUT

> f

, the ratio is held at one.

S_IN

S_OUT

to f

S_IN

comparison. This is done to provide some hysteresis to prevent the filter length from oscillating and causing distortion.

Figure 33 shows the detail of the SRC section. The SRC master clock is expected to be equal to 256 times the output sample rate. This master clock can be provided by four different clock sources. The selection is set by the SRC and Clock Control register (Address 0x00), and the selected clock source can be divided using the same register.

04756-034

Rev. A | Page 21 of 60

ADAV803

PLL SECTION

The ADAV803 features a dual PLL configuration to generate independent system clocks for asynchronous operation. Figure 37 shows the block diagram of the PLL section. The PLL generates the internal and system clocks from a 27 MHz clock. This clock is generated either by a crystal connected between XIN and XOUT, as shown in clock source connected directly to XIN. A 54 MHz clock can also be used, if the internal clock divider is used.

Figure 35. Crystal Connection

Both PLLs (PLL1 and PLL2) can be programmed independently and can accommodate a range of sampling rates (32 kHz /44.1 kHz/48 kHz) with selectable system clock oversampling rates of 256 and 384. Higher oversampling rates can also be selected by enabling the doubling of the sampling rate to give 512 or 768 × f

ratios. Note that this option also allows

oversampling ratios of 256 or 384 at double sample rates of 64 kHz /88.2 kHz/96 kHz.

The PLL outputs can be routed internally to act as clock sources for the other component blocks such as the ADC and DAC. The outputs of the PLLs are also available on the three SYSCLK pins. Figure 38 shows how the PLLs can be configured to provide the sampling clocks.

Figure 35, or from an external

XTAL

XIN

XOUT

04756-035

Table 7. PLL Frequency Selection Options

MCLK Selection

Double fS

512/768 × f

256/384 × f

512/768 × fS

256/384 × f

PLL

Sample Rate, f (kHz)

Normal f

1 32/44.1/48 256/384 × f

64/88.2/96

2A 32/44.1/48 256/384 × f

64/88.2/96 Same as f

for PLL 2A

selected

256/512 × f

The PLLs require some external components to operate correctly. These components, shown in

Figure 36, form a loop filter that integrates the current pulses from a charge pump and produces a voltage that is used to tune the VCO. Good quality capacitors, such as PPS film, are recommended.

Figure 37 shows a block diagram of the PLL section, including the master clock selection.

Figure 38 shows how the clock frequencies at the clock output pins, SYSCLK1 to SYSCLK3, and the internal PLL clock values, PLL1 and PLL2, are selected.

The clock nodes, PLL1 and PLL2, can be used as master clocks for the other blocks in the ADAV803, such as the DAC or ADC. The PLL has separate supply and ground pins, which should be as clean as possible to prevent electrical noise from being converted into clock jitter by coupling onto the loop filter pins.

PLL_LF1

10n

732Ω

1.2µF

Figure 36. PLL Loop Filter

PLL BLOCK

PLL_LFx

04756-036

XIN

XOUT

MCLKO

MCLKI

REG 0x74

BIT 5

÷2

REG 0x74

BIT 4

REG 0x78

BIT 6

REG 0x78

BIT 7

PHASE DETECTOR AND LOOP

FILTER

PHASE DETECTOR AND LOOP

FILTER

Figure 37. PLL Section Block Diagram

Rev. A | Page 22 of 60

PLL_LF2

VCO

÷N

VCO

÷N

OUTPUT

SCALER N1

PLL1

OUTPUT

SCALER N2

PLL2

OUTPUT

SCALER N3

SYSCLK1

SYSCLK2

SYSCLK3

04756-037

ADAV803

48kHz 32kHz

44.1kHz

256 384

48kHz 32kHz

44.1kHz

256 512

PLL1 MCLK

PLL2 MCLK

REG 0x75 BITS[3:2]

REG 0x75 BIT 1

REG 0x75 BIT 5

REG 0x75 BITS[7:6]

REG 0x74 BIT 0

REG 0x75

BIT 0

×2

REG 0x75

BIT 4

×2

Figure 38. PLL Clocking Scheme

S/PDIF TRANSMITTER AND RECEIVER

The ADAV803 contains an integrated S/PDIF transmitter and receiver. The transmitter consists of a single output pin, DITOUT, on which the biphase encoded data appears. The S/PDIF transmitter source can be selected from the different blocks making up the ADAV803. Additionally, the clock source for the S/PDIF transmitter can be selected from the various clock sources available in the ADAV803.

The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts the S/PDIF input data stream. The DIRIN pin can be configured to accept a digital input level, as defined in the section, or an input signal with a peak-to-peak level of 200 mV minimum, as defined by the IEC 60958-3 specification. DIR_LF is a loop filter pin, required by the internal PLL, which is used to recover the clock from the S/PDIF data stream.

The components shown in

Figure 42 form a loop filter, which integrates the current pulses from a charge pump and produces a voltage that is used to tune the VCO of the clock recovery PLL. The recovered audio data and audio clock can be routed to the different blocks of the ADAV803, as required. shows a conceptual diagram of the DIRIN block.

REG 0x7A BIT 4

DIRIN

SPDIF

Specifications

SPDIF

RECEIVER

Figure 39

FS3

FS1

REG 0x77

BIT 0

÷2

FS2

REG 0x77

BITS[2:1]

÷2

CHANNEL STATUS

AND USER BITS

PLL1

SYSCLK1

PLLINT1

PLL2

SYSCLK2

PLLINT2

ADC

DIR

PLAYBACK

AUXILIARY IN

SRC

SYSCLK3

REG 0x63

BITS[2:0]

DIT INPUT

04756-038

DIT

Figure 40. Digital Output Transmitter Block Diagram

DIRIN

DIR

AUDIO DATA

RECOVERED CLOCK

CHANNEL STATUS/ USER BITS

Figure 41. Digital Input Receiver Block Diagram

.8n

3.3kΩ

100nF

DIR BLOCK

DIR_LF

Figure 42. DIR Loop Filter Components

DITOUT

04756-041

04756-042

04756-040

COMPARATOR

LEVEL

*EXTERNAL CAPACITOR I S ONLY REQUIRED

FOR VARIABLE LEVEL SPDIF INPUTS.

04756-039

Figure 39. DIRIN Block

Rev. A | Page 23 of 60

ADAV803

(

Serial Digital Audio Transmission Standards

The ADAV803 can receive and transmit S/PDIF, AES/EBU, and IEC-958 serial streams. S/PDIF is a consumer audio standard, and AES/EBU is a professional audio standard. IEC-958 has both consumer and professional definitions. This data sheet is not intended to fully define or to provide a tutorial for these standards. Contact the international standards-setting bodies for the full specifications.

All these digital audio communication schemes encode audio data and audio control information using the biphase-mark method. This encoding method minimizes the dc content of the transmitted signal. As can be seen from

Figure 43, 1s in the original data end up with midcell transitions in the biphasemark encoded data, while 0s in the original data do not. Note that the biphase-mark encoded data always has a transition between bit boundaries.

2 TIMES BIT RATE )

CLOC

DATA

BIPHASE-MARK

DATA

011100

04756-043

Figure 43. Biphase-Mark Encoding

Digital audio-communication schemes use preambles to distinguish among channels (called subframes) and among longer-term control information blocks (called frames). Preambles are particular biphase-mark patterns, which contain encoding violations that allow the receiver to uniquely recognize them. These patterns and their relationship to frames and subframes are shown in

Tabl e 8 and Figure 44.

Table 8. Biphase-Mark Encode Preamble

Biphase Patterns Channel

X 11100010 or 00011101 Left Y 11100100 or 00011011 Right Z 11101000 or 00010111 Left and CS block start

PREAMBLES

LEFT CH

XY ZY XY

RIGHT CH LEFT CH RI GHT CH LEFT CH RIG HT CH

SUBFRAME SUBFRAME

FRAME 191 FRAME 0 FRAME 1

Figure 44. Preambles, Frames, and Subframes

The biphase-mark encoding violations are shown in Figure 45. Note that all three preambles include encoding violations.

04756-044

Ordinarily, the biphase-mark encoding method results in a polarity transition between bit boundaries.

11100010

PREAMBLE X

11100100

PREAMBLE Y

11101000

PREAMBLE Z

04756-045

Figure 45. Preambles

The serial digital audio communication scheme is organized using a frame and subframe construction. There are two subframes per frame (ordinarily the left and right channel). Each subframe includes the appropriate 4-bit preamble, up to 24 bits of audio data, a validity (V) bit, a user (U) bit, a channel status (C) bit, and an even parity (P) bit. The channel status bits and the user bits accumulate over many frames to convey control information. The channel status bits accumulate over a 192 frame period (called a channel status block). The user bits accumulate over 1176 frames when the interconnect is implementing the so-called subcode scheme (EIAJ CP-2401). The organization of the channel status block, frames, and subframes is shown in

Tabl e 9 and Ta bl e 10 . Note that the ADAV803 supports the professional audio standard from a software point of view only. The digital interface supports only consumer mode.

Table 9. Consumer Audio Standard

Data Bits Address17 6 5 4 3 2 1 0

Channel

Status

Emphasis

NonAudio

Pro/ Con

= 0 N + 1 Category Code N + 2 Channel Number Source Number N + 3 Reserved

Clock

Sampling Frequency

Accuracy N + 4 Reserved Word Length N + 5 to

Reserved

(N + 23)

N = 0x20 for receiver channel status buffer.

N = 0x38 for transmitter channel status buffer.

Rev. A | Page 24 of 60

ADAV803

Table 10. Professional Audio Standard

Data Bits Address1 7 6 5 4 3 2 1 0

N Sample

Frequency

Lock Emphasis Non-

Audio

Pro/Con

= 1 N + 1 User Bit Management Channel Mode N + 2 Alignment

Level

Source Word

Length

Use of Auxiliary Mode

Sample Bits N + 3 Channel Identification N + 4 fS

Scaling

Sample

Frequency (f

Reserved Digital Audio

)

Reference

Signal N + 5 Reserved N + 6 Alphanumeric Channel Origin Data—First Character N + 7 Alphanumeric Channel Origin Data N + 8 Alphanumeric Channel Origin Data N + 9 Alphanumeric Channel Origin Data—Last Character N + 10 Alphanumeric Channel Destination Data—First Character N + 11 Alphanumeric Channel Destination Data N + 12 Alphanumeric Channel Destination Data N + 13 Alphanumeric Channel Destination Data—Last Character N + 14 Local Sample Address Code—LSW N + 15 Local Sample Address Code N + 16 Local Sample Address Code N + 17 Local Sample Address Code—MSW N + 18 Time of Day Code—LSW N + 19 Time of Day Code N + 20 Time of Day Code N + 21 Time of Day Code—MSW N + 22 Reliability Flags Reserved N + 23 Cyclic Redundancy Check Character (CRCC)

N = 0x20 for receiver channel status buffer.

N = 0x38 for transmitter channel status buffer

The standards allow the channel status bits in each subframe to be independent, but ordinarily the channel status bits in the two subframes of each frame are the same. The channel status bits are defined differently for the consumer audio standards and the professional audio standards. The 192 channel status bits are organized into 24 bytes and have the interpretations shown in Tabl e 9 and Ta b le 1 0 .

The S/PDIF transmitter and receiver have a comprehensive register set. The registers give the user full access to the functions of the S/PDIF block, such as detecting nonaudio and validity bits, Q subcodes, and preambles. The channel status bits as defined by the IEC60958 and AES3 specifications are stored in register buffers for ease of use. An autobuffering function allows channel status bits and user bits read by the receiver to be copied directly to the transmitter block, removing the need for user intervention.

Receiver Section

The ADAV803 uses a double-buffering scheme to handle reading channel status and user bit information. The channel status

bits are available as a memory buffer, taking up 24 consecutive register locations. The user bits are read using an indirect memory addressing scheme, where the receiver user bit indirect-address register is programmed with an offset to the user bit buffer, and the receiver user bit data register can be read to determine the user bits at that location. Reading the receiver user bit data register automatically updates the indirect address register to the next location in the buffer. Typically, the receiver user bit indirect-address register is programmed to zero (the start of the buffer), and the receiver user bit data register is read repeatedly until all the buffer’s data has been read. and

Figure 47 show how receiving the channel status bits and

Figure 46

user bits is implemented.

DIRIN

S/PDIF

RECEIVE

BUFFER

FIRST BUFFER

Figure 46. Channel Status Buffer

CHANNEL STATUS A

(24 × 8 BITS )

CHANNEL STATUS B

(24 × 8 BITS )

SECOND BUFFER

RECEIVE

CS BUFFER

(0x20 TO 0x37)

RxCSSWITCH

04756-046

S/PDIF

0.....7

8.....15

16.....23

FIRST

BUFFER

0.....7

8.....15

16.....23

USER-BIT

BUFFER

Figure 47. Receiver User Bit Buffer

ADDRESS = 0x50

RECEIVER USER BIT INDIRECT ADDRESS

ADDRESS = 0x51

RECEIVER USER BIT

DATA REGISTER

04756-047

The S/PDIF receive buffer is updated continuously by the incoming S/PDIF stream. Once all the channel status bits for the block (192 for Channel A and 192 for Channel B) are received, the bits are copied into the receiver channel status buffer. This buffer stores all 384 bits of channel status information, and the RxCSSWITCH bit in the channel status switch buffer register determines whether the Channel A or the Channel B status bits are required to be read. The receive channel status bit buffer is 24 bytes long and spans the address range from 0x20 to 0x37.

Because the channel status bits of an S/PDIF stream rarely change, a software interrupt/flag bit, RxCSBINT, is provided to notify the host control either that a new block of channel status bits is available or that the first five bytes of channel status information have changed from a previous block. The function of the RxCSBINT is controlled by the RxBCONF3 bit in the Receiver Buffer Configuration register.

Rev. A | Page 25 of 60

ADAV803

The size of the user bit buffer can be set by programming the RxBCONF0 bit in the receiver buffer configuration register, as shown in

Tabl e 1 1 .

Table 11. RxBCONF3 Functionality

RxBCONF0 Receiver User Bit Buffer Size

0 384 bits with Preamble Z as the start of the block. 1 768 bits with Preamble Z as the start of the block.

The updating of the user bit buffer is controlled by Bits RxBCONF[2:1] and Bit 7 to Bit 4 of the channel status register, as shown in

Tabl e 1 2 and Tabl e 1 3 .

Table 12. RxBCONF[2:1] Functionality

RxBCONF

Bit 2 Bit 1 Receiver User Bit Buffer Configuration

0 0 User bits are ignored. 0 1 Update second buffer when first buffer is full. 1 0

Format according to Byte 1, Bit 4 to Bit 7, if PRO bit is set. Format according to IEC60958-3, if PRO bit is clear.

Table 13. Automatic User Bit Configuration

Bits

7 6 5 4

Automatic Receiver User Bit Buffer Configuration

0 0 0 0 User bits are ignored. 0 1 0 0

AES-18 format: the user bit buffer is treated in the same way as when RxBCONF[2:1] = 0b01.

1 0 0 0

User bit buffer is updated in the same way as when RxBCONF[2:1] = 0b01 and RxBCONF0 = 0b00.

1 1 0 0

User-defined format: the user bit buffer is treated in the same way as when RxBCONF[2:1] = 0b01.

When the user bit buffer has been filled, the RxUBINT interrupt bit in the interrupt status register is set, provided that the RxUBINT mask bit is set, to indicate that the buffer has new information and can be read.

For the special case when the user data is formatted according to the IEC 60958-3 standard into messages made of information units, called IUs, the zeros stuffed between each IU and each message are removed and only the IUs are stored. Once the end of the message is sensed by more that eight zeros between IUs, the user bit buffer is updated with the complete message and the first buffer begins looking for the start of the next message.

Each IU is stored as a byte consisting of 1, Q, R, S, T, U, V, and W bits (see the IEC 60958-3 specification for more information). When 96 IUs are received, the Q subcode of the IUs is stored in the Q subcode buffer, consisting of 10 bytes. The Q subcode is the Q bits taken from each of the 96 IUs. The first 10 bytes (80 bits) of the Q subcode contain information sent by CD, MD, and DAT systems. The last 16 bits of the Q subcode are used to perform a CRC check of the Q subcode. If an error occurs in the CRC check of the Q subcode, the QCRCERROR

bit is set. This is a sticky bit that remains high until the register is read.

Transmitter Operation

The S/PDIF transmitter has a similar buffer structure to the receive section. The transmitter channel status buffer occupies 24 bytes of the register map. This buffer is long enough to store the 192 bits required for one channel of channel status information. Setting the TxCSSWITCH bit determines if the data loaded to the transmitter channel status buffer is intended for Channel A or Channel B. In most cases, the channel status bits for Channel A and Channel B are the same, in which case setting the Tx_A/B_Same bit reads the data from the transmitter channel status buffer and transmits it on both channels.

Because the channel status information is rarely changed during transmission, the information contained in the buffer is transmitted repeatedly. The Disable_Tx_Copy bit can be used to prevent the channel status bits from being copied from the transmitter CS buffer into the S/PDIF transmitter buffer until the user has finished loading the buffers. This feature is typically used, if the Channel A data and Channel B data are different. Setting the bit prevents the data from being copied. Clearing the bit allows the data to be copied and then transmitted.

Figure 48 shows how the buffers are organized.

DITOUT

CHANNEL

TRANSMIT

CS BUFFER

(0x38 TO 0x4F )

TxCSSWITCH

Figure 48. Transmitter Channel Status Buffer

STATUS A

(24 × 8 BITS)

CHANNEL STATUS B

(24 × 8 BITS)

S/PDIF

TRANSMIT

BUFFER

04756-048

As with the receiver section, the transmitted user bits are also double-buffered. This is required because, unlike the channel status bits, the user bits do not necessarily repeat themselves. The user bits can be buffered in various configurations, as listed in

Tabl e 1 4 . Transmission of the user bits is determined by the state of the BCONF3 bit. If the bit is 0, the user bits begin transmitting right away without alignment to the Z preamble. If this bit is 1, the user bits do not start transmitting until a Z preamble occurs when the TxBCONF[2:1] bits are 01.

Table 14. Transmitter User Bit Buffer Configurations

TxBCONF2-1

Bit 2 Bit 1 Transmitter User Bit Buffer Configuration

0 0 Zeros are transmitted for the user bits. 0 1 Host writes user bits to the buffer until it is full. 1 0

Writes the user bits to the buffer in IUs specified by IEC60958-3 and transmits them according to the standard.

1 1

First 10 bytes of the user-bit buffer are configured to store a Q subcode.

Rev. A | Page 26 of 60

ADAV803

Table 15. Transmitter User Bit Buffer Size

TxBCONF0 Buffer Size

0 384 bits with Preamble Z as the start of the block. 1 768 bits with Preamble Z as the start of the block.

By using sticky bits and interrupts, the transmit buffers can notify the host or microcontroller about their status. The sticky bit, TxUBINT, is set when the transmit user bit buffer has been updated and the second transmit user bit buffer is empty and ready to accept new user bits. This bit is located in the interrupt status register. When the host reads the interrupt status register, this bit is cleared. Interrupts for the TxUBINT sticky bit can be enabled by setting the TxUBINT Mask bit in the interrupt status mask register

S/PDIF 0

ADDRESS = 0x52

TRANSMITT ER USER BIT

INDIRECT ADDRESS

ADDRESS = 0x53

TRANSMITT ER USER BIT

DATA REGISTER

Figure 49. Transmitter User Bit Buffer

0.....7

8.....15

16.....23

USER-BIT

BUFFER

0.....7

8.....15

16.....23

SECOND BUFFER

04756-049

Autobuffering

The ADAV803 S/PDIF receiver and transmitter sections have an autobuffering mode allowing the channel status and user bits to be copied automatically from the receiver to the transmitter without user intervention. The channel status and user bits can be independently selected for autobuffering using the Auto_CSBits and Auto_UBits bits, respectively, in the Autobuffer register. When the receiver and transmitter are running at the same sample rate, the transmitted channel status and user bits are the same as the received channel-status and user bits.

In many systems, however, it is likely that the receiver and transmitter are not running at the same frequency. When the transmitter sample rate is higher than the receiver sample rate, the channel status and user bit blocks are sometimes repeated. When the transmitter sample rate is lower than the receiver sample rate, the channel status and user bit blocks might be dropped. Because the first five bytes of the channel status are typically constant, they can be repeated or dropped with no information loss. However, if the PRO bit in the channel status is set and the local sample address code and time-of-day code bytes contain information, these bytes might be repeated or dropped, in which case information can be lost. It is up to the user to determine how to handle this case.

When the user bits are transmitted according to the IEC 60958-3 format, the messages contained in the user bits can still be sent without dropping or repeating messages. Because zero-stuffing is allowed between IUs and messages, zeros can be added or subtracted to preserve the messages. When the transmitter sample rate is greater than the receiver sample rate, extra zeros are stuffed between the messages. When the sample rate of the transmitter is less than the sample rate of the receiver, the zeros stuffed between the messages are subtracted. If there are not enough zeros between the messages to be subtracted, the zeros between IUs are subtracted as well. The Zero_Stuff_IU bit in the Autobuffer register enables the adding or subtracting of zeros between messages.

Interrupts

The ADAV803 provides interrupt bits to indicate the presence of certain conditions that require attention. Reading the interrupt status register (Register 0x1C) allows the user to determine if any of the interrupts have been asserted. The bits of the Interrupt Status register remain high, if set, until the register is read. Two bits, SRCError and RxError, indicate interrupt conditions in the sample rate converter and an S/PDIF receiver error, respectively. Both these conditions require a read of the appropriate error register (Register 0x1A and Register 0x18, respectively) to determine the exact cause of the interrupt.

Each interrupt in the interrupt status register has an associated mask bit in the interrupt status mask register. The interrupt mask bit must be set for the corresponding interrupt to be generated. This feature allows the user to determine which functions should be responded to.

The dual function pin ZEROL/INT can be set to indicate the presence of no audio data on the left channel or the presence of an interrupt set in the interrupt status register. As shown in Tabl e 1 6 , the function of this pin is selected by the INTRPT bit in DAC Control Register 4.

Table 16. ZEROL/INT Pin Functionality

INTRPT Pin Functionality

0 Pin functions as a ZEROL flag pin. 1 Pin functions as an interrupt pin.

SERIAL DATA PORTS

The ADAV803 contains four flexible serial ports (SPORTs) to allow data transfer to and from the codec. All four SPORTs are independent and can be configured as master or slave ports. In slave mode, the xLRCLK and xBCLK signals are inputs to the serial ports. In master mode, the serial port generates the xLRCLK and xBCLK signals. The master clock for the SPORT can be selected from a number of sources, as shown in Figure 50.

Rev. A | Page 27 of 60

ADAV803

Care should be taken to ensure that the clock rate is appropriate for whatever block is connected to the serial port. For example, if the ADC is running from the MCLKI input at 256 × f

, then

the master clock for the SPORT should also run from the MCLKI input to ensure that the ADC and serial port are synchronized.

The SPORTs can be set to transmit or receive data in I2S, leftjustified or right-justified formats with different word lengths by programming the appropriate bits in the playback register, auxiliary input port register, record register, and auxiliary output port-control register.

Figure 51 is a timing diagram of

the serial data port formats.

Clocking Scheme

The ADAV803 provides a flexible choice of on-chip and offchip clocking sources. The on-chip oscillator with dual PLLs is intended to offer complete system clocking requirements for use with available MPEG encoders, decoders, or a combination of codecs. The oscillator function is designed for generation of a 27 MHz video clock from a 27 MHz crystal connected between the XIN and XOUT pins. Capacitors must also be connected between these pins and DGND, as shown in

Figure 35. The capacitor values should be specified by the crystal manufacturer. A square wave version of the crystal clock is output on the MCLKO pin. If the system has a 27 MHz clock available, this clock can be connected directly to the XIN pin.

DIR PLL(512 × DIR PLL(256 ×

PLLINT1 PLLINT2

MCLKI

DIR PLL(512 × DIR PLL(256 ×

PLLINT1 PLLINT2

MCLKI

PLLINT1 PLLINT2

MCLKI

PLLINT1 PLLINT2

REG 0x76

BITS[4:2]

)

XIN

REG 0x76

BITS[7:5]

)

XIN

REG 0x77

BITS[4:3]

XIN

REG 0x76

BITS[1:0]

ADC

MCLK

ICLK1 ICLK2

PLL CLOCK

DAC

MCLK

ICLK1 ICLK2

PLL CLOCK

REG 0x00

BITS[3:2]

DIVIDE R DIR PLL(512 × DIR PLL(256 ×

DIVIDE R

REG 0x00

BITS[4:5]

REG 0x00

BITS[ 1:0]

ICLK1

)

ICLK2

Figure 50. SPORT Clocking Scheme

OUTPUT

PORT

REG 0x06 BITS[5:4]

INPUT

PORT

REG 0x04 BITS[4:3]

MCLK

DIVIDER

REG 0x00

BITS[7:6]

SRC

OLRCLK OBCLK OSDATA

ILRCLK IBCLK ISDATA

04756-050

LRCL

BCLK

SDATA

LRCL

BCLK

SDATA

LRCL

BCLK

SDATA

LEFT CHANNEL RIGHT CHANNEL

MSB MSB

LEFT CHANNEL

MSB

LEFT CHANNEL RIGHT CHANNEL

MSB MSB

LSB LSB

LEFT-JUSTIFI ED MODE — 16 BIT S TO 24 BITS PER CHANNEL

LSB

I2S MODE — 16 BITS TO 24 BITS PER CHANNE L

LSB LSB

RIGHT-JUSTIFI ED MODE — SE LECT NUMBER OF BITS PER CHANNEL

Figure 51. Serial Data Modes

MSB

RIGHT CHANNE L

LSB

04756-051

Rev. A | Page 28 of 60

ADAV803

Datapath

The ADAV803 features a digital input/output switching/ multiplexing matrix that gives flexibility to the range of possible input and output connections. Digital input ports include playback and auxiliary input (both 3-wire digital), and S/PDIF (single-wire to the on-chip receiver). Output ports include the record and auxiliary output ports (both 3-wire digital) and the S/PDIF port (single-wire from the on-chip transmitter). Internally, the DIR and DIT are interfaced via 3-wire interfaces. The datapath for each input and output port is selected by programming Datapath Control Register 1 and Datapath Control Register 2.

Figure 52 shows the internal datapath

structure of the ADAV803.

PLL

ADC

REFERENCE

DAC

CONTROL

REGISTERS

OSCILLATOR

SRC

PLAYBACK

DATA

INPUT

Figure 52. Datapath

DATA

INPUT

RECORD

DATA

OUTPUT

AUX

DATA

OUTPUT

DIT

DIRAUX

04756-052

Rev. A | Page 29 of 60

ADAV803

INTERFACE CONTROL

The ADAV803 has a dedicated control port to allow the internal registers of the ADAV803 to be accessed. Each of the internal registers is eight bits wide. Where bits are described as reserved (RES), these bits should be programmed as zero.

I2C INTERFACE

The I2C interface of the ADAV803 is a 2-wire interface consisting of a clock line, SCL, and a data line, SDA. SDA is bidirectional; the ADAV803 drives SDA to either acknowledge the master, ACK, or send data during a read operation. The SDA pin for the I a 1 kΩ pull-up resistor. A write or read access occurs when the SDA line is pulled low while the SCL line is high, indicated by START in the timing diagrams. SDA is allowed to change only when SCL is low, except when a start or stop condition occurs, as shown in both standard (100 kbps) and fast (400 kbps) modes as defined

by the I

C standards.

The first eight bits of the access consist of the device address and the R/W bit. The device address consists of an internal built-in address (0b00100) and two address pins, AD1 and AD0. The two address pins allow up to four ADAV803s to be used in a system.

C port is an open-drain collector that requires

Figure 53 and Figure 54. The I2C interface supports

Initiating a write operation to the ADAV803 involves sending a start condition and then sending the device address with the R/W set low. The ADAV803 responds by issuing an ACK to indicate that it has been addressed. The user then sends a second frame telling the ADAV803 which register is required to be written to. The 7-bit register address is left-shifted to make the eight bits that the frame requires. Another ACK is issued by the ADAV803. Finally, the user can send another frame with the eight data bits required to be written to the register. A third ACK is issued by the ADAV803, after which the user can send a stop condition to complete the data transfer.

A read operation requires that the user first write to the ADAV803 to point to the correct register and then read the data. This is achieved by sending a start condition followed by the device address frame, with R/W low, and then the register address frame. Following the ACK from the ADAV803, the user must issue a repeated start condition. This is identical to a start condition. The next frame is the device address with R/W set high. On the next frame, the ADAV803 outputs the register data on the SDA line. A stop condition completes the read operation. Figure 53 and Figure 54 show examples of writing to and reading from the DAC left volume register (Address 0b1101000).

SCK

SDA AD1 AD0 R/W

START BY

MASTER

0100 1

FRAME 1

CHIP ADDRESS BYTE

SCK

(CONTINUED)

SDA

(CONTINUED)

Figure 53. Writing to the DAC Left Volume Register in I

ACK. BY ADAV803

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE TO

ADAV803

FRAME 2

ACK. BY

ADAV803

ACK. BY

ADAV803

STOP BY

MASTER

04756-053

Rev. A | Page 30 of 60

ADAV803

SCL

0100AD1AD0 1

FRAME 1

CHIP ADDRESS BYTE

00100

FRAME 3

CHIP ADDRESS BYTE

SCL

(CONTINUED)

SDA

(CONTINUED)

SDA

START BY

MASTER

REPEATED START

BY MASTER

Figure 54. Reading from the DAC Left Volume Register in I

BLOCK READS AND WRITES

The ADAV803 provides the user with the ability to write to or read from a block of registers in one continuous operation. To use this feature, the user has to continue providing data frames before the stop condition. For a write operation, the register address is automatically incremented with each additional frame and the register data is written to that register address. For a read operation, the register address is automatically incremented with each additional frame, and the register data is clocked out on that frame.

R/W

ACK. BY

ADAV803

D7AD1 AD0 D6 D5 D4 D3 D2 D1 D0

ACK. BY

ADAV803

FRAME 4

FRAME 2

ACK. BY ADAV803

ACK. BY

ADAV803

STOP BY MASTER

Care should be exercised when using the block read or block write modes. For most cases, block reading or writing to a register automatically increments the register address to point to the next register. The exceptions to this case are the indirect memory address registers, transmitter user bit and receiver user bit data buffers. Using a block read or write to access these registers does not update the absolute register address, but instead updates the buffer address to provide the next value in the buffer.

04756-054

Rev. A | Page 31 of 60

ADAV803

REGISTER DESCRIPTIONS

SRC and Clock Control—Address 0000000 (0x00)

Table 17. SRC and Clock Control Register Bit Map

7 6 5 4 3 2 1 0

SRCDIV1 SRCDIV0 CLK2DIV1 CLK2DIV0 CLK1DIV1 CLK1DIV0 MCLKSEL1 MCLKSEL0

Table 18. SRC and Clock Control Register Bit Descriptions

Bit Name Description

SRCDIV[1:0] Divides the SRC master clock. 00 = SRC master clock is not divided. 01 = SRC master clock is divided by 1.5. 10 = SRC master clock is divided by 2. 11 = SRC master clock is divided by 3. CLK2DIV[1:0] Clock divider for Internal Clock 2 (ICLK2). 00 = Divide by 1. 01 = Divide by 1.5. 10 = Divide by 2. 11 = Divide by 3. CLK1DIV[1:0] Clock divider for Internal Clock 1 (ICLK1). 00 = Divide by 1. 01 = Divide by 1.5. 10 = Divide by 2. 11 = Divide by 3. MCLKSEL[1:0] Clock selection for the SRC master clock. 00 = Internal Clock 1. 01 = Internal Clock 2. 10 = PLL recovered clock (512 × fS). 11 = PLL recovered clock (256 × fS).

S/PDIF Loopback Control—Address 0000011 (0x03)

Table 19. S/PDIF Loopback Control Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved TxMUX

Table 20. S/PDIF Loopback Control Register Bit Descriptions

Bit Name Description

TxMUX Selects the source for S/PDIF output (DITOUT). 0 = S/PDIF transmitter, normal mode. 1 = DIRIN, loopback mode.

Rev. A | Page 32 of 60

ADAV803

Playback Port Control—Address 0000100 (0x04)

Table 21. Playback Port Control Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved Reserved CLKSRC1 CLKSRC0 SPMODE2 SPMODE1 SPMODE0

Table 22. Playback Port Control Register Bit Descriptions

Bit Name Description

CLKSRC[1:0] Selects the clock source for generating the ILRCLK and IBCLK. 00 = Input port is a slave. 01 = Recovered PLL clock. 10 = Internal Clock 1. 11 = Internal Clock 2. SPMODE[2:0] Selects the serial format of the playback port. 000 = Left-justified. 001 = I2S. 100 = 24-bit, right-justified. 101 = 20-bit, right-justified. 110 = 18-bit, right-justified. 111 = 16-bit, right-justified.

Auxiliary Input Port—Address 0000101 (0x05)

Table 23. Auxiliary Input Port Register Bit Map

7 6 5 4 3 2 1 0 Reserved Reserved Reserved CLKSRC1 CLKSRC0 SPMODE2 SPMODE1 SPMODE0

Table 24. Auxiliary Input Port Register Bit Descriptions

Bit Name Description

CLKSRC[1:0] Selects the clock source for generating the IAUXLRCLK and IAUXBCLK. 00 = Input port is a slave. 01 = Recovered PLL cock. 10 = Internal Clock 1. 11 = Internal Clock 2. SPMODE[2:0] Selects the serial format of auxiliary input port. 000 = Left-justified. 001 = I2S. 100 = 24-bit, right-justified. 101 = 20-bit, right-justified. 110 = 18-bit, right-justified. 111 = 16-bit, right-justified.

Rev. A | Page 33 of 60

ADAV803

Record Port Control—Address 0000110 (0x06)

Table 25. Record Port Control Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved CLKSRC1 CLKSRC0 WLEN1 WLEN0 SPMODE1 SPMODE0

Table 26. Record Port Control Register Bit Descriptions

Bit Name Description

CLKSRC[1:0] Selects the clock source for generating the OLRCLK and OBCLK. 00 = Record port is a slave. 01 = Recovered PLL clock. 10 = Internal Clock 1. 11 = Internal Clock 2. WLEN[1:0] Selects the serial output word length. 00 = 24 bits. 01 = 20 bits. 10 = 18 bits. 11 = 16 bits. SPMODE[1:0] Selects the serial format of the record port. 00 = Left-justified. 01 = I2S. 10 = Reserved. 11 = Right-justified.

Auxiliary Output Port—Address 0000111 (0x07)

Table 27. Auxiliary Output Port Register Bit Map

7 6 5 4 3 2 1 0 Reserved Reserved CLKSRC1 CLKSRC0 WLEN1 WLEN0 SPMODE1 SPMODE0

Table 28. Auxiliary Output Port Register Bit Descriptions

Bit Name Description

CLKSRC[1:0] Selects the clock source for generating the OAUXLRCLK and OAUXBCLK. 00 = Auxiliary record port is a slave. 01 = Recovered PLL clock. 10 = Internal Clock 1. 11 = Internal Clock 2. WLEN[1:0] Selects the serial output word length. 00 = 24 bits. 01 = 20 bits. 10 = 18 bits. 11 = 16 bits. SPMODE[1:0] Selects the serial format of the auxiliary record port. 00 = Left-justified. 01 = I2S. 10 = Reserved. 11 = Right-justified.

Rev. A | Page 34 of 60

ADAV803

Group Delay and Mute—Address 0001000 (0x08)

Table 29. Group Delay and Mute Register Bit Map

7 6 5 4 3 2 1 0

MUTE_SRC GRPDLY6 GRPDLY5 GRPDLY4 GRPDLY3 GRPDLY2 GRPDLY1 GRPDLY0

Table 30. Group Delay and Mute Register Bit Descriptions

Bit Name Description

MUTE_SRC Soft-mutes the output of the sample rate converter. 0 = No mute. 1 = Soft mute. GRPDLY[6:0] Adds delay to the sample rate converter FIR filter by GRPDLY[6:0] input samples. 0000000 = No delay. 0000001 = 1 sample delay. 0000010 = 2 sample delay. 1111110 = 126 sample delay. 1111111 = 127 sample delay.

Receiver Configuration 1—Address 0001001 (0x09)

Table 31. Receiver Configuration 1 Register Bit Map

7 6 5 4 3 2 1 0

NOCLOCK RxCLK1 RxCLK0 AUTO_DEEMPH ERR1 ERR0 LOCK1 LOCK0

Table 32. Receiver Configuration 1 Register Bit Descriptions

Bit Name Description

NOCLOCK Selects the source of the receiver clock when the PLL is not locked. 0 = Recovered PLL clock is used. 1 = ICLK1 is used. RxCLK[1:0] Determines the oversampling ratio of the recovered receiver clock. 00 = RxCLK is a 128 × fS recovered clock. 01 = RxCLK is a 256 × fS recovered clock. 10 = RxCLK is a 512 × fS recovered clock. 11 = Reserved. AUTO_DEEMPH Automatically de-emphasizes the data from the receiver based on the channel status information. 0 = Automatic de-emphasis is disabled. 1 = Automatic de-emphasis is enabled. ERR[1:0] Defines what action the receiver should take, if the receiver detects a parity or biphase error. 00 = No action is taken. 01 = Last valid sample is held. 10 = Invalid sample is replaced with zeros. 11 = Reserved. LOCK[1:0] Defines what action the receiver should take, if the PLL loses lock. 00 = No action is taken. 01 = Last valid sample is held. 10 = Zeros are sent out after the last valid sample. 11 = Soft-mute of the last valid audio sample.

Rev. A | Page 35 of 60

ADAV803

Receiver Configuration 2—Address 0001010 (0x0A)

Table 33. Receiver Configuration 2 Register Bit Map

7 6 5 4 3 2 1 0

RxMUTE SP_PLL SP_PLL_ SEL1 SP_PLL_ SEL0 Reserved Reserved NO NONAUDIO NO_VALIDITY

Table 34. Receiver Configuration 2 Register Bit Descriptions

Bit Name Description

RxMUTE Hard-mutes the audio output for the AES3/S/PDIF receiver. 0 = AES3/S/PDIF receiver is not muted. 1 = AES3/S/PDIF receiver is muted. SP_PLL AES3/S/PDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock. 0 = Left/right clock generated from the AES3/S/PDIF preambles is the reference clock to the PLL. 1 = Left/right clock from one of the serial ports is the reference clock to the PLL. SP_PLL_SEL[1:0] Selects one of the four serial ports as the reference clock to the PLL when SP_PLL is set. 00 = Playback port is selected. 01 = Auxiliary input port is selected. 10 = Record port is selected. 11 = Auxiliary output port is selected. NO NONAUDIO

0 = AES3/S/PDIF receiver data is sent to the SRC. 1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO NONAUDIO bit is set. NO_VALIDITY When the NO_VALIDITY bit is set, data from the AES3/S/PDIF receiver is not allowed into the SRC. 0 = AES3/S/PDIF receiver data is sent to the SRC. 1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO_VALIDITY bit is set.

When the NO NONAUDIO bit is set, data from the AES3/S/PDIF receiver is not allowed into the sample rate converter (SRC). If the NO NONAUDIO data is due to DTS, AAC, and so on, as defined by the IEC61937 standard, then the data from the AES3/S/PDIF receiver is not allowed into the SRC regardless of the state of this bit.

Rev. A | Page 36 of 60

ADAV803

Receiver Buffer Configuration—Address 0001011 (0x0B)

Table 35. Receiver Buffer Configuration Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved RxBCONF5 RxBCONF4 RxBCONF3 RxBCONF2 RxBCONF1 RxBCONF0

Table 36. Receiver Buffer Configuration Register Bit Descriptions

Bit Name Description

RxBCONF5

0 = User bit interrupt is enabled in normal mode. 1 = If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit. RxBCONF4

0 = User bits are stored together. 1 = User bits are stored separately. RxBCONF3 Defines the function of RxCSBINT. 0 = RxCSBINT are set when a new block of receiver channel status is read, which is 192 audio frames.

RxBCONF[2:1] Defines the user bit buffer. 00 = User bits are ignored. 01 = Updates the second user bit buffer when the first user bit buffer is full.

11 = Reserved. RxBCONF0 Defines the user bit buffer size, if RxBCONF[2:1] = 01. 0 = 384 bits with Preamble Z as the start of the buffer. 1 = 768 bits with Preamble Z as the start of the buffer.

If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit interrupt is enabled only when there is a change in the start (ID) bit.

This bit determines whether Channel A and Channel B user bits are stored in the buffer together or separated between A and B.

1 = RxCSBINT is set only if the first five bytes of the receiver channel status block changes from the previous channel status block.

10 = Formats the received user bits according to Byte 1, Bit 4 to Bit 7, of the channel status, if the PRO bit is set. If the PRO bit is not set, formats the user bits according to the IEC60958-3 standard.

Transmitter Control—Address 0001100 (0x0C)

Table 37. Transmitter Control Register Bit Map

7 6 5 4 3 2 1 0

Reserved TxVALIDITY TxRATIO2 TxRATIO1 TxRATIO0 TxCLKSEL1 TxCLKSEL0 TxENABLE

Table 38. Transmitter Control Register Bit Descriptions

Bit Name Description

TxVALIDITY This bit is used to set or clear the VALIDITY bit in the AES3/S/PDIF transmit stream. 0 = Audio is suitable for digital-to-analog conversion. 1 = Audio is not suitable for digital-to-analog conversion. TxRATIO[2:0] Determines the AES3/S/PDIF transmitter to AES3/S/PDIF receiver ratio. 000 = Transmitter to receiver ratio is 1:1. 001 = Transmitter to receiver ratio is 1:2. 010 = Transmitter to receiver ratio is 1:4. 101 = Transmitter to receiver ratio is 2:1. 110 = Transmitter to receiver ratio is 4:1. TxCLKSEL[1:0] Selects the clock source for the AES3/S/PDIF transmitter. 00 = Internal Clock 1 is the clock source for the transmitter. 01 = Internal Clock 2 is the clock source for the transmitter. 10 = Recovered PLL clock is the clock source for the transmitter. 11 = Reserved. TxENABLE Enables the AES3/S/PDIF transmitter. 0 = AES3/S/PDIF transmitter is disabled. 1 = AES3/S/PDIF transmitter is enabled.

Rev. A | Page 37 of 60

ADAV803

Transmitter Buffer Configuration—Address 0001101 (0x0D)

Table 39. Transmitter Buffer Configuration Register Bit Map

7 6 5 4 3 2 1 0

IU_Zeros3 IU_Zeros2 IU_Zeros1 IU_Zeros0 TxBCONF3 TxBCONF2 TxBCONF1 TxBCONF0

Table 40. Transmitter Buffer Configuration Register Bit Descriptions

Bit Name Description

IU_Zeros[3:0] Determines the number of zeros to be stuffed between IUs in a message up to a maximum of 8. 0000 = 0. 0001 = 1. … 0111 = 7. 1000 = 8. TxBCONF3 Transmitter user bits can be stored in separate buffers or stored together. 0 = User bits are stored together. 1 = User bits are stored separately. TxBCONF[2:1] Configures the transmitter user bit buffer. 00 = Zeros are transmitted for the user bits. 01 = Transmitter user bit buffer size is configured according to TxBCONF0. 10 = User bits are written to the transmit buffer in IUs specified by the IEC60958-3 standard. 11 = Reserved. TxBCONF0 Determines the buffer size of the transmitter user bits when TxBCONF[2:1] is 01. 0 = 384 bits with Preamble Z as the start of the buffer. 1 = 768 bits with Preamble Z as the start of the buffer.

Channel Status Switch Buffer and Transmitter—Address 0001110 (0x0E)

Table 41. Channel Status Switch Buffer and Transmitter Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved Tx_A/B_Same Disable_Tx_Copy Reserved Reserved TxCSSWITCH RxCSSWITCH

Table 42. Channel Status Switch Buffer and Transmitter Register Bit Description

Bit Name Description

Tx_A/B_Same

0 = Channel status for A and B are separate. 1 = Channel status for A and B are the same. Disable_Tx_Copy

0 = Copying transmitter channel status is enabled. 1 = Copying transmitter channel status is disabled. TxCSSWITCH Toggle switch for the transmit channel status buffer. 0 = 24-byte Transmitter Channel Status A buffer can be accessed at address locations 0x38 through 0x4F. 1 = 24-byte Transmitter Channel Status B buffer can be accessed at address locations 0x38 through 0x4F. RxCSSWITCH Toggle switch for the receive channel status buffer. 0 = 24-byte Receiver Channel Status A buffer can be accessed at address locations 0x20 through 0x37. 1 = 24-byte Receiver Channel Status B buffer can be accessed at address locations 0x20 through 0x37.

Transmitter Channel Status A and B are the same. The transmitter reads only from the Channel Status A buffer and places the data into the Channel Status B buffer.

Disables the copying of the channel status bits from the transmitter channel status buffer to the S/PDIF transmitter buffer.

Rev. A | Page 38 of 60

ADAV803

Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F)

Table 43. Transmitter Message Zeros Most Significant Byte Register Bit Map

7 6 5 4 3 2 1 0

MSBZeros7 MSBZeros6 MSBZeros5 MSBZeros4 MSBZeros3 MSBZeros2 MSBZeros1 MSBZeros0

Table 44. Transmitter Message Zeros Most Significant Byte Register Bit Description

Bit Name Description

MSBZeros[7:0]

Transmitter Message Zeros Least Significant Byte—Address 0010000 (0x10)

Table 45. Transmitter Message Zeros Least Significant Byte Register Bit Map

7 6 5 4 3 2 1 0

LSBZeros7 LSBZeros6 LSBZeros5 LSBZeros4 LSBZeros3 LSBZeros2 LSBZeros1 LSBZeros0

Table 46. Transmitter Message Zeros Least Significant Byte Register Bit Descriptions

Bit Name Description

LSBZeros[7:0] Least significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x09.

Autobuffer—Address 0010001 (0x11)

Most significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x00.

Table 47. Autobuffer Register Bit Map

7 6 5 4 3 2 1 0

Reserved Zero_Stuff_IU Auto_UBits Auto_CSBits IU_Zeros3 IU_Zeros2 IU_Zeros1 IU_Zeros0

Table 48. Autobuffer Register Bit Descriptions

Bit Name Description

Zero_Stuff_IU Enables the addition or subtraction of zeros between IUs during autobuffering of the user bits in IEC60958-3 format. 0 = No zeros added or subtracted. 1 = Zeros can be added or subtracted between IUs. Auto_UBits Enables the user bits to be autobuffered between the AES3/S/PDIF receiver and transmitter. 0 = User bits are not autobuffered. 1 = User bits are autobuffered. Auto_CSBits Enables the channel status bits to be autobuffered between the AES3/S/PDIF receiver and transmitter. 0 = Channel status bits are not autobuffered. 1 = Channel status bits are autobuffered. IU_Zeros[3:0] Sets the maximum number of zero-stuffing to be added between IUs while autobuffering up to a maximum of 8. 0000 = 0. 0001 = 1. … 0111 = 7. 1000 = 8.

Sample Rate Ratio MSB—Address 0010010 (0x12)

Table 49. Sample Rate Ratio MSB Register (Read-Only) Bit Map

7 6 5 4 3 2 1 0

Reserved SRCRATIO14 SRCRATIO13 SRCRATIO12 SRCRATIO11 SRCRATIO10 SRCRATIO09 SRCRATIO08

Table 50. Sample Rate Ratio MSB Register (Read-Only) Bit Descriptions

Bit Name Description

SRCRATIO[14:8] Seven most significant bits of the15-bit sample rate ratio.

Rev. A | Page 39 of 60

ADAV803

Sample Rate Ratio LSB—Address 0010011 (0x13)

Table 51. Sample Rate Ratio LSB Register (Read-Only) Bit Map

7 6 5 4 3 2 1 0

SRCRATIO07 SRCRATIO06 SRCRATIO05 SRCRATIO04 SRCRATIO03 SRCRATIO02 SRCRATIO01 SRCRATIO00

Table 52. Sample Rate Ratio LSB Register (Read-Only) Bit Descriptions

Bit Name Description

SRCRATIO[7:0] Eight least significant bits of the15-bit sample rate ratio.

Preamble-C MSB—Address 0010100 (0x14)

Table 53. Preamble-C MSB Register (Read-Only) Bit Map

7 6 5 4 3 2 1 0

PRE_C15 PRE_C14 PRE_C13 PRE_C12 PRE_C11 PRE_C10 PRE_C9 PRE_C8

Table 54. Preamble-C MSB Register (Read-Only) Bit Descriptions

Bit Name Description

PRE_C[15:8]

Preamble-C LSB—Address 0010101 (0x15)

Table 55. Preamble-C LSB Register (Read-Only) Bit Map

7 6 5 4 3 2 1 0

PRE_C07 PRE_C06 PRE_C05 PRE_C04 PRE_C03 PRE_C02 PRE_C01 PRE_C00

Eight most significant bits of the 16-bit Preamble-C, when nonaudio data is detected according to the IEC60937 standard; otherwise, bits show zeros.

Table 56. Preamble-C LSB Register (Read-Only) Bit Descriptions

Bit Name Description

PRE_C[7:0]

Eight least significant bits of the 16-bit Preamble-C, when nonaudio data is detected according to the IEC60937 standard; otherwise, bits show zeros.

Preamble-D MSB—Address 0010110 (0x16)

Table 57. Preamble-D MSB Register (Read-Only) Bit Map

7 6 5 4 3 2 1 0

PRE_D15 PRE_D14 PRE_D13 PRE_D12 PRE_D11 PRE_D10 PRE_D9 PRE_D8

Table 58. Preamble-D MSB Register (Read-Only) Bit Descriptions

Bit Name Description

PRE_D[15:8]

Eight most significant bits of the 16-bit Preamble-D, when nonaudio data is detected according to the IEC60937 standard; otherwise, bits show zeros. When subframe nonaudio is used, this becomes the eight most significant bits of the 16-bit Preamble-C of Channel B.

Preamble-D LSB—Address 0010111 (0x17)

Table 59. Preamble-D LSB Register (Read-Only) Bit Map

7 6 5 4 3 2 1 0

PRE_D07 PRE_D06 PRE_D05 PRE_D04 PRE_D03 PRE_D02 PRE_D01 PRE_D00

Table 60. Preamble-D LSB Register (Read-Only) Bit Descriptions

Bit Name Description

PRE_D[7:0]

Eight least significant bits of the 16-bit Preamble-D, when nonaudio data is detected according to the IEC60937 standard; otherwise, bits show zeros. When subframe nonaudio is used, this becomes the eight most significant bits of the 16-bit Preamble-C of Channel B.

Rev. A | Page 40 of 60

ADAV803

Receiver Error—Address 0011000 (0x18)

Table 61. Receiver Error Register (Read-Only) Bit Map

7 6 5 4 3 2 1 0

RxValidity Emphasis NonAudio NonAudio Preamble CRCError NoStream BiPhase/Parity Lock

Table 62. Receiver Error Register (Read-Only) Bit Descriptions

Bit Name Description

RxValidity This is the VALIDITY bit in the AES3 received stream. Emphasis

NonAudio

NonAudio Preamble

CRCError This bit is the error flag for the channel status CRCError check. This bit does not clear until the receiver error register is read. NoStream

BiPhase/Parity This bit is set if a biphase or parity error occurred in the AES3/S/PDIF stream. This bit is not cleared until the register is read. Lock

This bit is set if the audio data is pre-emphasized. Once it has been read, it remains high and does not generate an interrupt unless it changes state.

This bit is set when Channel Status Bit 1 (nonaudio) is set. Once it has been read, it does not generate another interrupt unless the data becomes audio or the type of nonaudio data changes.

This bit is set if the audio data is nonaudio due to the detection of a preamble. The nonaudio preamble type register indicates what type of preamble was detected. Once read, it remains in its state and does not generate an interrupt unless it changes state.

This bit is set if there is no AES3/S/PDIF stream present at the AES3/S/PDIF receiver. Once read, it remains high and does not generate an interrupt unless it changes state.

This bit is set if the PLL has locked or cleared when the PLL loses lock. Once read, it remains in its state and does not generate an interrupt unless it changes state.

Receiver Error Mask—Address 0011001 (0x19)

Table 63. Receiver Error Mask Register Bit Map

7 6 5 4 3 2 1 0

RxValidity Mask

Emphasis Mask

NonAudio Mask

NonAudio Preamble Mask

CRCError Mask

NoStream Mask

BiPhase/Parity Mask

Lock Mask

Table 64. Receiver Error Mask Register Bit Descriptions

Bit Name Description

RxValidity Mask Masks the RxValidity bit from generating an interrupt. 0 = RxValidity bit does not generate an interrupt. 1 = RxValidity bit generates an interrupt. Emphasis Mask Masks the Emphasis bit from generating an interrupt. 0 = Emphasis bit does not generate an interrupt. 1 = Emphasis bit generates an interrupt. NonAudio Mask Masks the NonAudio bit from generating an interrupt. 0 = NonAudio bit does not generate an interrupt. 1 = NonAudio bit generates an interrupt. NonAudio Preamble Mask Masks the NonAudio preamble bit from generating an interrupt. 0 = NonAudio preamble bit does not generate an interrupt. 1 = NonAudio preamble bit generates an interrupt. CRCError Mask Masks the CRCError bit from generating an interrupt. 0 = CRCError bit does not generate an interrupt. 1 = CRCError bit generates an interrupt. NoStream Mask Masks the NoStream bit from generating an interrupt. 0 = NoStream bit does not generate an interrupt. 1 = NoStream bit generates an interrupt. BiPhase/Parity Mask Masks the BiPhase/Parity bit from generating an interrupt. 0 = BiPhase/Parity bit does not generate an interrupt. 1 = BiPhase/Parity bit generates an interrupt. Lock Mask Masks the Lock bit from generating an interrupt. 0 = Lock bit does not generate an interrupt. 1 = Lock bit generates an interrupt.

Rev. A | Page 41 of 60

ADAV803

Sample Rate Converter Error—Address 0011010 (0x1A)

Table 65. Sample Rate Converter Error Register (Read-Only) Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved TOO_SLOW OVRL OVRR MUTE_IND

Table 66. Sample Rate Converter Error Register (Read-Only) Bit Descriptions

Bit Name Description

TOO_SLOW

OVRL

OVRR

MUTE_IND

Sample Rate Converter Error Mask—Address 0011011 (0x1B)

Table 67. Sample Rate Converter Error Mask Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Reserved OVRL Mask OVRR Mask MUTE_IND MASK

This bit is set when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the internal convolution.

This bit is set when the left output data of the sample rate converter has gone over the full-scale range and has been clipped. This bit is not cleared until the register is read.

This bit is set when the right output data of the sample rate converter has gone over the full-scale range and has been clipped. This bit is not cleared until the register is read.

Mute indicated. This bit is set when the SRC is in fast mode and clicks or pops can be heard in the SRC output data. The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state and does not generate an interrupt until it has changed state.

Table 68. Sample Rate Converter Error Mask Register Bit Descriptions

Bit Name Description

OVRL Mask Masks the OVRL from generating an interrupt. 0 = OVRL bit does not generate an interrupt. 1 = OVRL bit generates an interrupt. OVRR Mask Masks the OVRR from generating an interrupt. 0 = OVRR bit does not generate an interrupt. 1 = OVRR bit generates an interrupt. Reserved. MUTE_IND MASK Masks the MUTE_IND from generating an interrupt. 0 = MUTE_IND bit does not generate an interrupt. 1 = MUTE_IND bit generates an interrupt.

Rev. A | Page 42 of 60

ADAV803

Interrupt Status—Address 0011100 (0x1C)

Table 69. Interrupt Status Register Bit Map

7 6 5 4 3 2 1 0

SRCError TxCSTINT TxUBINT TxCSBINT RxCSDIFF RxUBINT RxCSBINT RxERROR

Table 70. Interrupt Status Register Bit Descriptions

Bit Name Description

SRCError

TxCSTINT

TxUBINT This bit is set if the S/PDIF transmit buffer is empty. This bit remains high until the interrupt status register is read. TxCSBINT

RxCSDIFF

RxUBINT

RxCSBINT

RxERROR

This bit is set if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample rate converter error register. This bit remains high until the interrupt status register is read.

This bit is set if a write to the transmitter channel status buffer was made while transmitter channel status bits were being copied from the transmitter CS buffer to the S/PDIF transmit buffer.

This bit is set if the transmitter channel status bit buffer has transmitted its block of channel status. This bit remains high until the interrupt status register is read.

This bit is set if the receiver Channel Status A block is different from the receiver Channel Status B clock. This bit remains high until read, but does not generate an interrupt.

This bit is set if the receiver user bit buffer has a new block or message. This bit remains high until the interrupt status register is read.

This bit is set if a new block of channel status is read when RxBCONF3 = 0, or if the channel status has changed when RxBCONF3 = 1. This bit remains high until the interrupt status register is read.

This bit is set if one of the AES3/S/PDIF receiver interrupts is asserted, and the host should immediately read the receiver error register. This bit remains high until the interrupt status register is read.

Interrupt Status Mask—Address 0011101 (0x1D)

Table 71. Interrupt Status Mask Register Bit Map

7 6 5 4 3 2 1 0

SRCError Mask TxCSTINT Mask TxUBINT Mask TxCSBINT Mask Reserved RxUBINT Mask RxCSBINT Mask RxError Mask

Table 72. Interrupt Status Mask Register Bit Descriptions

Bit Name Description

SRCError Mask Masks the SRCError bit from generating an interrupt. 0 = SRCError bit does not generate an interrupt. 1 = SRCError bit generates an interrupt. TxCSTINT Mask Masks the TxCSTINT bit from generating an interrupt. 0 = TxCSTINT bit does not generate an interrupt. 1 = TxCSTINT bit generates an interrupt. TxUBINT Mask Masks the TxUBINT bit from generating an interrupt. 0 = TxUBINT bit does not generate an interrupt. 1 = TxUBINT bit generates an interrupt. TxCSBINT Mask Masks the TxCSBINT bit from generating an interrupt. 0 = TxCSBINT bit does not generate an interrupt. 1 = TxCSBINT bit generates an interrupt. RxUBINT Mask Masks the RxUBINT bit from generating an interrupt. 0 = RxUBINT bit does not generate an interrupt. 1 = RxUBINT bit generates an interrupt. RxCSBINT Mask Masks the RxCSBINT bit from generating an interrupt. 0 = RxCSBINT bit does not generate an interrupt. 1 = RxCSBINT bit generates an interrupt. RxError Mask Masks the RxError bit from generating an interrupt. 0 = RxError bit does not generate an interrupt. 1 = RxError bit generates an interrupt.

Rev. A | Page 43 of 60

ADAV803

Mute and De-Emphasis—Address 0011110 (0x1E)

Table 73. Mute and De-Emphasis Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved TxMUTE Reserved Reserved SRC_DEEM1 SRC_DEEM0 Reserved

Table 74. Mute and De-Emphasis Register Bit Descriptions

Bit Name Description

TxMUTE Mutes the AES3/S/PDIF transmitter. 0 = Transmitter is not muted. 1 = Transmitter is muted. SRC_DEEM[1:0] Selects the de-emphasis filter for the input data to the sample rate converter. 00 = No de-emphasis. 01 = 32 kHz de-emphasis. 10 = 44.1 kHz de-emphasis. 11 = 48 kHz de-emphasis.

NonAudio Preamble Type—Address 0011111 (0x1F)

Table 75. NonAudio Preamble Type Register (Read-Only) Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved

DTS-CD Preamble

NonAudio Frame

NonAudio Subframe_A

NonAudio Subframe_B

Table 76. NonAudio Preamble Type Register (Read-Only) Bit Descriptions

Bit Name Description

DTS-CD Preamble This bit is set if the DTS-CD preamble is detected. NonAudio Frame

NonAudio Subframe_A

NonAudio Subframe_B

This bit is set if the data received through the AES3/S/PDIF receiver is nonaudio data according to the IEC61937

standard or nonaudio data according to SMPTE337M.

This bit is set if the data received through Channel A of the AES3/S/PDIF receiver is subframe nonaudio data

according to SMPTE337M.

This bit is set if the data received through Channel B of the AES3/S/PDIF receiver is subframe nonaudio data

according to SMPTE337M.

Receiver Channel Status Buffer—Address 0100000 to Address 0110111 (0x20 to 0x37)

Table 77. Receiver Channel Status Buffer Register Bit Map

7 6 5 4 3 2 1 0

RCSB7 RCSB6 RCSB5 RCSB4 RCSB3 RCSB2 RCSB1 RCSB0

Table 78. Receiver Channel Status Buffer Register Bit Descriptions

Bit Name Description

RCSB[7:0]

The 24-byte receiver channel status buffer. The PRO bit is stored at address location 0x20, Bit 0. This buffer is readonly if the channel status is not autobuffered between the receiver and transmitter.

Transmitter Channel Status Buffer—Address 0111000 to Address 1001111 (0x38 to 0x4F)

Table 79. Transmitter Channel Status Buffer Register Bit Map

7 6 5 4 3 2 1 0

TCSB7 TCSB6 TCSB5 TCSB4 TCSB3 TCSB2 TCSB1 TCSB0

Table 80. Transmitter Channel Status Buffer Register Bit Descriptions

Bit Name Description

TCSB[7:0]

The 24-byte transmitter channel status buffer. The PRO bit is stored at address location 0x38, Bit 0. This buffer is disabled when autobuffering between the receiver and transmitter is enabled.

Rev. A | Page 44 of 60

ADAV803

Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50)

Table 81. Receiver User Bit Buffer Indirect Address Register Bit Map

7 6 5 4 3 2 1 0

RxUBADDR7 RxUBADDR6 RxUBADDR5 RxUBADDR4 RxUBADDR3 RxUBADDR2 RxUBADDR1 RxUBADDR0

Table 82. Receiver User Bit Buffer Indirect Address Register Bit Descriptions

Bit Name Description

RxUBADDR[7:0] Indirect address pointing to the address location in the receiver user bit buffer.

Receiver User Bit Buffer Data—Address 1010001 (0x51)

Table 83. Receiver User Bit Buffer Data Register Bit Map

7 6 5 4 3 2 1 0

RxUBDATA7 RxUBDATA6 RxUBDATA5 RxUBDATA4 RxUBDATA3 RxUBDATA2 RxUBDATA1 RxUBDATA0

Table 84. Receiver User Bit Buffer Data Register Bit Descriptions

Bit Name Description

RxUBDATA[7:0]

Transmitter User Bit Buffer Indirect Address—Address 1010010 (0x52)

Table 85. Transmitter User Bit Buffer Indirect Address Register Bit Map

7 6 5 4 3 2 1 0

TxUBADDR7 TxUBADDR6 TxUBADDR5 TxUBADDR4 TxUBADDR3 TxUBADDR2 TxUBADDR1 TxUBADDR0

A read from this register reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR0[7:0]. This buffer can be written to when autobuffering of the user bits is enabled; otherwise, it is a read-only buffer.

Table 86. Transmitter User Bit Buffer Indirect Address Register Bit Descriptions

Bit Name Description

TxUBADDR[7:0] Indirect address pointing to the address location in the transmitter user bit buffer.

Transmitter User Bit Buffer Data—Address 1010011 (0x53)

Table 87. Transmitter User Bit Buffer Data Register Bit Map

7 6 5 4 3 2 1 0

TxUBDATA7 TxUBDATA6 TxUBDATA5 TxUBDATA4 TxUBDATA3 TxUBDATA2 TxUBDATA1 TxUBDATA0

Table 88. Transmitter User Bit Buffer Data Register Bit Descriptions

Bit Name Description

TxUBDATA[7:0]

A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR0[7:0]. When user bit autobuffering is enabled, this buffer is disabled.

Q Subcode CRCError Status—Address 1010100 (0x54)

Table 89. Q Subcode CRCError Status Register (Read-Only) Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Reserved Reserved QCRCERROR QSUB

Table 90. Q Subcode CRCError Status Register (Read-Only) Bit Descriptions

Bit Name Description

QCRCERROR

QSUB This bit is set if a Q subcode has been read into the Q subcode buffer (see Table 91).

This bit is set if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This bit is cleared once the register is read.

Rev. A | Page 45 of 60

ADAV803

Q Subcode Buffer—Address 0x55 to Address 0x5E

Table 91. Q Subcode Buffer Bit Map

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x55 Address Address Address Address Control Control Control Control 0x56

0x57 Index Index Index Index Index Index Index Index 0x58 Minute Minute Minute Minute Minute Minute Minute Minute 0x59 Second Second Second Second Second Second Second Second 0x5A Frame Frame Frame Frame Frame Frame Frame Frame 0x5B Zero Zero Zero Zero Zero Zero Zero Zero 0x5C

0x5D

0x5E

Datapath Control Register 1—Address 1100010 (0x62)

Table 92. Datapath Control Register 1 Bit Map

7 6 5 4 3 2 1 0

SRC1 SRC0 REC2 REC1 REC0 AUXO2 AUXO1 AUXO0

Track number

Absolute minute

Absolute second

Absolute frame

Track number

Absolute minute

Absolute second

Absolute frame

Track number

Absolute minute

Absolute second

Absolute frame

Track number

Absolute minute

Absolute second

Absolute frame

Track number

Absolute minute

Absolute second

Absolute frame

Track number

Absolute minute

Absolute second

Absolute frame

Track number

Absolute minute

Absolute second

Absolute frame

Track number

Absolute minute

Absolute second

Absolute frame

Table 93. Datapath Control Register 1 Bit Descriptions

Bit Name Description

SRC[1:0] Datapath source select for sample rate converter (SRC). 00 = ADC. 01 = DIR. 10 = Playback. 11 = Auxiliary in. REC[2:0] Datapath source select for record output port. 000 = ADC. 001 = DIR. 010 = Playback. 011 = Auxiliary in. 100 = SRC. AUXO[2:0] Datapath source select for auxiliary output port. 000 = ADC. 001 = DIR. 010 = Playback. 011 = Auxiliary in. 100 = SRC.

Rev. A | Page 46 of 60

ADAV803

Datapath Control Register 2—Address 1100011 (0x63)

Table 94. Datapath Control Register 2 Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved DAC2 DAC1 DAC0 DIT2 DIT1 DIT0

Table 95. Datapath Control Register 2 Bit Descriptions

Bit Name Description

DAC[2:0] Datapath source select for DAC. 00 = ADC. 01 = DIR. 10 = Playback. 11 = Auxiliary in. 100 = SRC. DIT[2:0] Datapath source select for DIT. 000 = ADC. 001 = DIR. 010 = Playback. 011 = Auxiliary in. 100 = SRC.

DAC Control Register 1—Address 1100100 (0x64)

Table 96. DAC Control Register 1 Bit Map

7 6 5 4 3 2 1 0

DR_ALL DR_DIG CHSEL1 CHSEL0 POL1 POL0 MUTER MUTEL

Table 97. DAC Control Register 1 Bit Descriptions

Bit Name Description

DR_ALL Hard reset and power-down. 0 = Normal, output pins go to V 1 = Hard reset and low power, output pins go to AGND. DR_DIG DAC digital reset. 0 = Normal. 1 = Reset all except registers. CHSEL[1:0] DAC channel select. 00 = Normal, left-right. 01 = Both right. 10 = Both left. 11 = Swapped, right-left. POL[1:0] DAC channel polarity. 00 = Both positive. 01 = Left negative. 10 = Right negative. 11 = Both negative. MUTER Mute right channel. 0 = Mute. 1 = Normal. MUTEL Mute left channel. 0 = Mute. 1 = Normal.

REF

level.

Rev. A | Page 47 of 60

ADAV803

DAC Control Register 2—Address 1100101 (0x65)

Table 98. DAC Control Register 2 Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved DMCLK1 DMCLK0 DFS1 DFS0 DEEM1 DEEM0

Table 99. DAC Control Register 2 Bit Descriptions

Bit Name Description

DMCLK[1:0] DAC MCLK divider. 00 = MCLK. 01 = MCLK/1.5. 10 = MCLK/2. 11 = MCLK/3. DFS[1:0] DAC interpolator select. 00 = 8 × (MCLK = 256 × fS). 01 = 4 × (MCLK = 128 × fS). 10 = 2 × (MCLK = 64 × fS). 11 = Reserved. DEEM[1:0] DAC de-emphasis select. 00 = None. 01 = 44.1 kHz. 10 = 32 kHz. 11 = 48 kHz.

DAC Control Register 3—Address 1100110 (0x66)

Table 100. DAC Control Register 3 Bit Map

7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved ZFVOL ZFDATA ZFPOL

Table 101. DAC Control Register 3 Bit Descriptions

Bit Name Description

ZFVOL DAC zero flag on mute and zero volume. 0 = Enabled. 1 = Disabled. ZFDATA DAC zero flag on zero data disable. 0 = Enabled. 1 = Disabled. ZFPOL DAC zero flag polarity. 0 = Active low. 1 = Active high.

Rev. A | Page 48 of 60

ADAV803

DAC Control Register 4—Address 1100111 (0x67)

Table 102. DAC Control Register 4 Bit Map

7 6 5 4 3 2 1 0 Reserved INTRPT ZEROSEL1 ZEROSEL0 Reserved Reserved Reserved Reserved

Table 103. DAC Control Register 4 Bit Descriptions

Bit Name Description

INTRPT This bit selects the functionality of the ZEROL/INT pin. 0 = Pin functions as a ZEROL flag pin. 1 = Pin functions as an interrupt pin. ZEROSEL[1:0] These bits control the functionality of the ZEROR pin when the ZEROL/INT pin is used as an interrupt. 00 = Pin functions as a ZEROR flag pin. 01 = Pin functions as a ZEROL flag pin. 10 = Pin is asserted when either the left or right channel is zero. 11 = Pin is asserted when both the left and right channels are zero.

DAC Left Volume—Address 1101000 (0x68)

Table 104. DAC Left Volume Register Bit Map

7 6 5 4 3 2 1 0

DVOLL7 DVOLL6 DVOLL5 DVOLL4 DVOLL3 DVOLL2 DVOLL1 DVOLL0

Table 105. DAC Left Volume Register Bit Descriptions

Bit Name Description

DVOLL[7:0] DAC left channel volume control.

1111111 = 0 dBFS. 1111110 = −0.375 dBFS. 0000000 = −95.625 dBFS.

DAC Right Volume—Address 1101001 (0x69)

Table 106. DAC Right Volume Register Bit Map

7 6 5 4 3 2 1 0

DVOLR7 DVOLR6 DVOLR5 DVOLR4 DVOLR3 DVOLR2 DVOLR1 DVOLR0

Table 107. DAC Right Volume Register Bit Descriptions

Bit Name Description

DVOLR[7:0] DAC right channel volume control. 1111111 = 0 dBFS. 1111110 = −0.375 dBFS. 0000000 = −95.625 dBFS.

DAC Left Peak Volume—Address 1101010 (0x6A)

Table 108. DAC Left Peak Volume Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved DLP5 DLP4 DLP3 DLP2 DLP1 DLP0

Table 109. DAC Left Peak Volume Register Bit Descriptions

Bit Name Description

DLP[5:0] DAC left channel peak volume detection. 000000 = 0 dBFS. 000001 = −1 dBFS. 111111 = −63 dBFS.

Rev. A | Page 49 of 60

ADAV803

DAC Right Peak Volume—Address 1101011 (0x6B)

Table 110. DAC Right Peak Volume Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved DRP5 DRP4 DRP3 DRP2 DRP1 DRP0

Table 111. DAC Right Peak Volume Register Bit Descriptions

Bit Name Description

DRP[5:0] DAC right channel peak volume detection. 000000 = 0 dBFS. 000001 = −1 dBFS. 111111 = −63 dBFS.

ADC Left Channel PGA Gain—Address 1101100 (0x6C)

Table 112. ADC Left Channel PGA Gain Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved AGL5 AGL4 AGL3 AGL2 AGL1 AGL0

Table 113. ADC Left Channel PGA Gain Register Bit Descriptions

Bit Name Description

AGL[5:0] PGA left channel gain control. 000000 = 0 dB. 000001 = 0.5 dB. … 101111 = 23.5 dB. 110000 = 24 dB. … 111111 = 24 dB.

ADC Right Channel PGA Gain—Address 1101101 (0x6D)

Table 114. ADC Right Channel PGA Gain Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved AGR5 AGR4 AGR3 AGR2 AGR1 AGR0

Table 115. ADC Right Channel PGA Gain Register Bit Descriptions

Bit Name Description

AGR[5:0] PGA right channel gain control. 000000 = 0 dB. 000001 = 0.5 dB. … 101111 = 23.5 dB. 110000 = 24 dB. … 111111 = 24 dB.

Rev. A | Page 50 of 60

ADAV803

ADC Control Register 1—Address 1101110 (0x6E)

Table 116. ADC Control Register 1 Bit Map

7 6 5 4 3 2 1 0

AMC HPF PWRDWN ANA_PD MUTER MUTEL PLPD PRPD

Table 117. ADC Control Register 1 Bit Descriptions

Bit Name Description

AMC ADC modulator clock. 0 = ADC MCLK/2 (128 × fS). 1 = ADC MCLK/4 (64 × fS). HPF High-pass filter enable. 0 = Normal. 1 = HPF enabled. PWRDWN ADC power-down. 0 = Normal. 1 = Power-down. ANA_PD ADC analog section power-down. 0 = Normal. 1 = Power-down. MUTER Mute ADC right channel. 0 = Normal. 1 = Muted. MUTEL Mute ADC left channel. 0 = Normal. 1 = Muted. PLPD PGA left power-down. 0 = Normal. 1 = Power-down. PRPD PGA right power-down. 0 = Normal. 1 = Power-down.

ADC Control Register 2—Address 1101111 (0x6F)

Table 118. ADC Control Register 2 Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved Reserved BUF_PD Reserved Reserved MCD1 MCD0

Table 119. ADC Control Register 2 Bit Descriptions

Bit Name Description

BUF_PD Reference buffer power-down control. 0 = Normal. 1 = Power-down. MCD[1:0] ADC master clock divider. 00 = Divide by 1. 01 = Divide by 2. 10 = Divide by 3. 11 = Divide by 1.

Rev. A | Page 51 of 60

ADAV803

ADC Left Volume—Address 1110000 (0x70)

Table 120. ADC Left Volume Register Bit Map

7 6 5 4 3 2 1 0

AVOLL7 AVOLL6 AVOLL5 AVOLL4 AVOLL3 AVOLL2 AVOLL1 AVOLL0

Table 121. ADC Left Volume Register Bit Descriptions

Bit Name Description

AVOLL[7:0] ADC left channel volume control. 1111111 = 1.0 (0 dBFS). 1111110 = 0.996 (−0.00348 dBFS). 1000000 = 0.5 (−6 dBFS). 0111111 = 0.496 (−6.09 dBFS). 0000000 = 0.0039 (−48.18 dBFS).

ADC Right Volume—Address 1110001 (0x71)

Table 122. ADC Right Volume Register Bit Map

7 6 5 4 3 2 1 0

AVOLR7 AVOLR6 AVOLR5 AVOLR4 AVOLR3 AVOLR2 AVOLR1 AVOLR0

Table 123. ADC Right Volume Register Bit Descriptions

Bit Name Description

AVOLR[7:0] ADC right channel volume control. 1111111 = 1.0 (0 dBFS). 1111110 = 0.996 (−0.00348 dBFS). 1000000 = 0.5 (−6 dBFS). 0111111 = 0.496 (−6.09 dBFS). 0000000 = 0.0039 (−48.18 dBFS).

ADC Left Peak Volume—Address 1110010 (0x72)

Table 124. ADC Left Peak Volume Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved ALP5 ALP4 ALP3 ALP2 ALP1 ALP0

Table 125. ADC Left Peak Volume Register Bit Descriptions

Bit Name Description

ALP[5:0] ADC left channel peak volume detection. 000000 = 0 dBFS. 000001 = −1 dBFS. 111111 = −63 dBFS.

ADC Right Peak Volume—Address 1110011 (0x73)

Table 126. ADC Right Peak Volume Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved ARP5 ARP4 ARP3 ARP2 ARP1 ARP0

Table 127. ADC Right Peak Volume Register Bit Descriptions

Bit Name Description

ARP[5:0] ADC right channel peak volume detection. 000000 = 0 dBFS. 000001 = −1 dBFS. 111111 = −63 dBFS.

Rev. A | Page 52 of 60

ADAV803

PLL Control Register 1—Address 1110100 (0x74)

Table 128. PLL Control Register 1 Bit Map

7 6 5 4 3 2 1 0

DIRIN_CLK1 DIRIN_CLK0 MCLKODIV PLLDIV PLL2PD PLL1PD XTLPD SYSCLK3

Table 129. PLL Control Register 1 Bit Descriptions

Bit Name Description

DIRIN_CLK[1:0] Recovered S/PDIF clock sent to SYSCLK3.

11 = SYSCLK3 is the recovered S/PDIF clock from DIRIN. MCLKODIV Divide input MCLK by 2 to generate MCLKO. 0 = Disabled. 1 = Enabled. PLLDIV Divide XIN by 2 to generate the PLL master clock. 0 = Disabled. 1 = Enabled. PLL2PD Power-down PLL2. 0 = Normal. 1 = Power-down. PLL1PD Power-down PLL1. 0 = Normal. 1 = Power-down. XTLPD Power-down XTAL oscillator. 0 = Normal. 1 = Power-down. SYSCLK3 Clock output for SYSCLK3. 0 = 512 × fS. 1 = 256 × fS.

00 = SYSCLK3 comes from PLL block. 01 = Reserved. 10 = Reserved.

Rev. A | Page 53 of 60

ADAV803

PLL Control Register 2—Address 1110101 (0x75)

Table 130. PLL Control Register 2 Bit Map

7 6 5 4 3 2 1 0

FS2_1 FS2_0 SEL2 DOUB2 FS1 FS0 SEL1 DOUB1

Table 131. PLL Control Register 2 Bit Descriptions

Bit Name Description

FS2_[1:0] Sample rate select for PLL2. 00 = 48 kHz. 01 = Reserved. 10 = 32 kHz. 11 = 44.1 kHz. SEL2 Oversample ratio select for PLL2. 0 = 256 × fS. 1 = 384 × fS. DOUB2 Double-selected sample rate on PLL2. 0 = Disabled. 1 = Enabled. FS[1:0] Sample rate select for PLL1. 00 = 48 kHz. 01 = Reserved. 10 = 32 kHz. 11 = 44.1 kHz. SEL1 Oversample ratio select for PLL1. 0 = 256 × fS. 1 = 384 × fS. DOUB1 Double-selected sample rate on PLL1. 0 = Disabled. 1 = Enabled.

Rev. A | Page 54 of 60

ADAV803

Internal Clocking Control Register 1—Address 1110110 (0x76)

Table 132. Internal Clocking Control Register 1 Bit Map

7 6 5 4 3 2 1 0

DCLK2 DCLK1 DCLK0 ACLK2 ACLK1 ACLK0 ICLK2_1 ICLK2_0

Table 133. Internal Clocking Control Register 1 Bit Descriptions

Bit Name Description

DCLK[2:0] DAC clock source select. 000 = XIN. 001 = MCLKI. 010 = PLLINT1. 011 = PLLINT2. 100 = DIR PLL (512 × fS). 101 = DIR PLL (256 × fS). 110 = XIN. 111 = XIN. ACLK[2:0] ADC clock source select. 000 = XIN. 001 = MCLKI. 010 = PLLINT1. 011 = PLLINT2. 100 = DIR PLL (512 × fS). 101 = DIR PLL (256 × fS). 110 = XIN. 111 = XIN. ICLK2_[1:0] Source selector for internal clock ICLK2.

00 = XIN. 01 = MCLKI. 10 = PLLINT1. 11 = PLLINT2.

Internal Clocking Control Register 2—Address 1110111 (0x77)

Table 134. Internal Clocking Control Register 2 Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved Reserved ICLK1_1 ICLK1_0 PLL2INT1 PLL2INT0 PLL1INT

Table 135. Internal Clocking Control Register 2 Bit Descriptions

Bit Name Description

ICLK1_[1:0] Source selector for internal clock ICLK1. 00 = XIN. 01 = MCLKI. 10 = PLLINT1. 11 = PLLINT2. PLL2INT[1:0] PLL2 internal selector (see Figure 38). 00 = FS2. 01 = FS2/2. 10 = FS3. 11 = FS3/2. PLL1INT PLL1 internal selector. 0 = FS1. 1 = FS1/2.

Rev. A | Page 55 of 60

ADAV803

PLL Clock Source Register—Address 1111000 (0x78)

Table 136. PLL Clock Source Register Bit Map

7 6 5 4 3 2 1 0

PLL2_Source PLL1_Source Reserved Reserved Reserved Reserved Reserved Reserved

Table 137. PLL Clock Source Register Bit Descriptions

Bit Name Description

PLL2_Source Selects the clock source for PLL2. 0 = XIN. 1 = MCLKI. PLL1_Source Selects the clock source for PLL1.

PLL Output Enable—Address 1111010 (0x7A)

Table 138. PLL Output Enable Register Bit Map

7 6 5 4 3 2 1 0

Reserved Reserved DIRINPD DIRIN_PIN Reserved SYSCLK1 SYSCLK2 SYSCLK3

Table 139. PLL Output Enable Register Bit Descriptions

Bit Name Description

DIRINPD This bit powers down the S/PDIF receiver. 0 = Normal. 1 = Power-down. DIRIN_PIN This bit determines the input levels of the DIRIN pin. 0 = DIRIN accepts input signals down to 200 mV according to AES3 requirements. 1 = DIRIN accepts input signals as defined in the Specifications section. SYSCLK1 Enables the SYSCLK1 output. 0 = Enabled. 1 = Disabled. SYSCLK2 Enables the SYSCLK2 output. 0 = Enabled. 1 = Disabled. SYSCLK3 Enables the SYSCLK3 output. 0 = Enabled. 1 = Disabled.

0 = XIN. 1 = MCLKI

Rev. A | Page 56 of 60

ADAV803

ALC Control Register 1—Address 1111011 (0x7B)

Table 140. ALC Control Register 1 Bit Map

7 6 5 4 3 2 1 0

FSSEL1 FSSEL0 GAINCNTR1 GAINCNTR0 RECMODE1 RECMODE0 LIMDET ALCEN

Table 141. ALC Control Register 1 Bit Descriptions

Bit Name Description

FSSEL[1:0] These bits should equal the sample rate of the ADC. 00 = 96 kHz. 01 = 48 kHz. 10 = 32 kHz. 11 = Reserved. GAINCNTR[1:0] These bits determine the limit of the counter used in limited recovery mode. 00 = 3. 01 = 7. 10 = 15. 11 = 31. RECMODE[1:0] These bits determine which recovery mode is used by the ALC section. 00 = No recovery. 01 = Normal recovery. 10 = Limited recovery. 11 = Reserved. LIMDET These bits limit detect mode. 0 = ALC is used when either channel exceeds the set limit. 1 = ALC is used only when both channels exceed the set limit. ALCEN These bits enable ALC. 0 = Disable ALC. 1 = Enable ALC.

Rev. A | Page 57 of 60

ADAV803

ALC Control Register 2— Address = 1111100 (0x7C)

Table 142. ALC Control Register 2 Bit Map

7 6 5 4 3 2 1 0

Reserved RECTH1 RECTH0 ATKTH1 ATKTH0 RECTIME1 RECTIME0 ATKTIME

Table 143. ALC Control Register 2 Bit Descriptions

Bit Name Description

RECTH[1:0] Recovery threshold. 00 = −2 dB. 01 = −3 dB. 10 = −4 dB. 11 = −6 dB. ATKTH[1:0] Attack threshold. 00 = 0 dB. 01 = −1 dB. 10 = −2 dB. 11 = −4 dB. RECTIME[1:0] Recovery time selection. 00 = 32 ms. 01 = 64 ms. 10 = 128 ms. 11 = 256 ms. ATKTIME Attack timer selection. 0 = 1 ms. 1 = 4 ms.

ALC Control Register 3—Address 1111101 (0x7D)

Table 144. ALC Control Register 3 Bit Map

7 6 5 4 3 2 1 0

ALC RESET ALC RESET ALC RESET ALC RESET ALC RESET ALC RESET ALC RESET ALC RESET

Table 145. ALC Control Register 3 Bit Description

Bit Name Description

ALC RESET

A write to this register restarts the ALC operation. The value written to this register is irrelevant. A read from this register gives the gain reduction factor.

Rev. A | Page 58 of 60

ADAV803

LAYOUT CONSIDERATIONS

Getting the best performance from the ADAV803 requires a careful layout of the printed circuit board (PCB). Using separate analog and digital ground planes is recommended, because these give the currents a low resistance path back to the power supplies. The ground planes should be connected in only one place, usually under the ADAV803, to prevent ground loops.

The analog and digital supply pins should be decoupled to their respective ground pins with a 10 μF to 47 μF tantalum capacitor and a 0.1 μF ceramic capacitor. These capacitors should be placed as close as possible to the supply pins.

ADC

The ADC uses a switch capacitor input stage and is, therefore, particularly sensitive to digital noise. Sources of noise, such as PLLs or clocks, should not be routed close to the ADC section. The CAPxN and CAPxP pins form a charge reservoir for the switched capacitor section of the ADC, so keeping these nodes electrically quiet is a key factor in ensuring good performance. The capacitors connected to these pins should be of good quality, either NPO or COG, and should be placed as close as possible to CAPxN and CAPxP.

DAC

The DAC requires an analog filter to filter out-of-band noise from the analog output. A third-order Bessel filter is recommended, although the filter to use depends on the requirements of the application.

PLL

The PLL can be used to generate digital clocks, either for use internally or to clock external circuitry. Because every clock is a potential source of noise, care should be taken when using the PLL. The ADAV803’s PLL outputs can be enabled or disabled, as required. If the PLL clocks are not required by external circuitry, it is recommended that the outputs be disabled. To reduce cross-coupling between clocks, a digital ground trace can be routed on either side of the PLL clock signal, if required.

The PLL has its own power supply pins. To get the best performance from the PLL and from the rest of the ADAV803, it is recommended that a separate analog supply be used. Where this is not possible, the user must decide whether to connect the PLL supply to the analog (AVDD) or digital (DVDD) supply. Connecting the PLL supply to AVDD gives the best jitter performance, but can degrade the performance of the ADC and DAC sections slightly due to the increased digital noise created on the AVDD by the PLL. Connecting the PLL supply to DVDD keeps digital noise away from the analog supply, but the jitter specifications might be reduced depending on the quality of the digital supply. Using the layout recommendations described in this section helps to reduce these effects.

RESET AND POWER-DOWN CONSIDERATIONS

When the ADAV803 is held in reset by bringing the pin low, a number of circuit blocks remain powered up. For example, the crystal oscillator circuit based around the XIN and XOUT pins is still active, so that a stable clock source is available when the ADAV803 is taken out of reset. In addition, the VCO associated with the S/PDIF receiver is active so that the receiver locks to the incoming S/PDIF stream in the shortest possible time. Where power consumption is a concern, the individual blocks of the ADAV803 can be powered down via the control registers to gain significant power savings. shows typical power savings when using the power-down bits in the control registers.

Table 146. Typical Power Requirements

Operating Mode

Normal 50 25 5 5 280.5 Reset low 30 4 2.5 1 123.75 Power-

down bits

AV (mA)

12 0.1 1.3 0.7 46.53

DV (mA)

ODV (mA)

DIR_V (mA)

RESET

Table 1 46

Power (mW)

Rev. A | Page 59 of 60

ADAV803

OUTLINE DIMENSIONS

12.20

PIN 1

12.00 SQ

11. 80

4964

0.75

0.60

0.45

1.60 MAX

10.20

10.00 SQ

9.80

051706-A

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.20

0.09

7°

3.5° 0°

0.08 COPLANARIT Y

COMPLIANT TO JEDEC STANDARDS MS-026-BCD

VIEW A

LEAD PITCH

0.50

BSC

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

Figure 55. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Model

ADAV803ASTZ

Range

−40°C to +85°C I2C Single-Ended 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 ADAV803ASTZ-REEL1−40°C to +85°C I2C Single-Ended 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 EVAL-ADAV803EBZ

Z = RoHS Compliant Part.

Evaluation Board

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C

Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

Control Interface

DAC Outputs Package Description

Package Option

Rev. A | Page 60 of 60

Datasheet ADAV803 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TEST CONDITIONS

ADAV803 SPECIFICATIONS

TIMING SPECIFICATIONS

TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

ADC SECTION

Programmable Gain Amplifier (PGA)

Analog Σ-Δ Modulator

Automatic Level Control (ALC)

Attack Mode

No Recovery Mode

Normal Recovery Mode

Limited Recovery Mode

Selecting a Sample Rate

DAC SECTION

Selecting a Sample Rate

SAMPLE RATE CONVERTER (SRC) FUNCTIONAL OVERVIEW

Conceptual High Interpolation Model

Hardware Model

SRC Architecture

PLL SECTION

S/PDIF TRANSMITTER AND RECEIVER

Serial Digital Audio Transmission Standards

Receiver Section

Transmitter Operation

Autobuffering

Interrupts

SERIAL DATA PORTS

Clocking Scheme

Datapath

INTERFACE CONTROL

I2C INTERFACE

BLOCK READS AND WRITES

REGISTER DESCRIPTIONS

SRC and Clock Control—Address 0000000 (0x00)

S/PDIF Loopback Control—Address 0000011 (0x03)

Playback Port Control—Address 0000100 (0x04)

Auxiliary Input Port—Address 0000101 (0x05)

Record Port Control—Address 0000110 (0x06)

Auxiliary Output Port—Address 0000111 (0x07)

Group Delay and Mute—Address 0001000 (0x08)

Receiver Configuration 1—Address 0001001 (0x09)

Receiver Configuration 2—Address 0001010 (0x0A)

Receiver Buffer Configuration—Address 0001011 (0x0B)

Transmitter Control—Address 0001100 (0x0C)

Transmitter Buffer Configuration—Address 0001101 (0x0D)

Channel Status Switch Buffer and Transmitter—Address 0001110 (0x0E)

Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F)

Transmitter Message Zeros Least Significant Byte—Address 0010000 (0x10)

Autobuffer—Address 0010001 (0x11)

Sample Rate Ratio MSB—Address 0010010 (0x12)

Sample Rate Ratio LSB—Address 0010011 (0x13)

Preamble-C MSB—Address 0010100 (0x14)

Preamble-C LSB—Address 0010101 (0x15)

Preamble-D MSB—Address 0010110 (0x16)

Preamble-D LSB—Address 0010111 (0x17)

Receiver Error—Address 0011000 (0x18)

Receiver Error Mask—Address 0011001 (0x19)

Sample Rate Converter Error—Address 0011010 (0x1A)

Sample Rate Converter Error Mask—Address 0011011 (0x1B)

Interrupt Status—Address 0011100 (0x1C)

Interrupt Status Mask—Address 0011101 (0x1D)

Mute and De-Emphasis—Address 0011110 (0x1E)

NonAudio Preamble Type—Address 0011111 (0x1F)

Receiver Channel Status Buffer—Address 0100000 to Address 0110111 (0x20 to 0x37)