Datasheet ADAV801 Datasheet (Analog Devices)

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Audio Codec for Recordable DVD

FEATURES

Stereo analog-to-digital converter (ADC)

Supports 48/96 kHz sample rates 102 dB dynamic range Single-ended input Automatic level control

Stereo digital-to-analog converter (DAC)

Supports 32/44.1/48/96/192 kHz sample rates 101 dB dynamic range

Single-ended output Asynchronous operation of ADC and DAC Stereo sample rate converter (SRC)

Input/output range: 8 kHz to 192 kHz

140 dB dynamic range Digital interfaces

Record

Playback

Auxiliary record

Auxiliary playback S/PDIF (IEC60958) input and output

Digital interface receiver (DIR)

Digital interface transmitter (DIT) PLL-based audio MCLK generators Generates required DVDR system MCLKs Device control via SPI®-compatible serial port 64-lead LQFP package

PRODUCT OVERVIEW

The ADAV801 is a stereo audio codec intended for applications such as DVD or CD recorders that require high performance and flexible, cost-effective playback and record functionality. The ADAV801 features Analog Devices’ proprietary, high performance converter cores to provide record (ADC), playback (DAC), and format conversion (SRC) on a single chip. The ADAV801 record channel features variable input gain to allow for adjustment of recorded input levels and automatic level control, followed by a high performance stereo ADC whose digital output is sent to the record interface. The record channel also features level detectors that can be used in feedback loops to adjust input levels for optimum recording. The playback channel features a high performance stereo DAC with independent digital volume control.

ADAV801

FUNCTIONAL BLOCK DIAGRAM

COUT

CIN

CCLK

CONTROL

REGISTERS

RECORD

DATA

OUTPUT

AUX DATA

OUTPUT

CLATCH

OLRCLK OBCLK

OSDATA

OAUXLRCLK OAUXBCLK OAUXSDATA

DIT

DITOUT

ZEROL/INT ZEROR

MCLKO

SYSCLK1

PLL

PLAYBACK

DATA INPUT

IBCLK

ILRCLK

DIGITAL

INPUT/OUTPUT

SWITCHING MATRIX

(DATAPATH)

AUX DATA

INPUT

ISDATA

IAUXBCLK

IAUXSDATA

IAUXLRCLK

DIR

DIRIN

VINL VINR

VREF

VOUTL

VOUTR

FILTD

MCLKI

XOUT

XIN

ANALOG-TO-DIGITAL

CONVERTER

REFERENCE SRC

DIGITAL-TO-ANALOG

CONVERTER

ADAV801

SYSCLK3

SYSCLK2

Figure 1.

APPLICATIONS

DVD-recordable All formats CD-R/W

The sample rate converter (SRC) provides high performance sample rate conversion to allow inputs and outputs that require different sample rates to be matched. The SRC input can be selected from playback, auxiliary, DIR, or ADC (record). The SRC output can be applied to the playback DAC, both main and auxiliary record channels, and a DIT.

Operation of the ADAV801 is controlled via an SPI-compatible serial interface, which allows the programming of individual control register settings. The ADAV801 operates from a single analog 3.3 V power supply and a digital power supply of 3.3 V with optional digital interface range of 3.0 V to 3.6 V.

The part is housed in a 64-lead LQFP package and is characterized for operation over the commercial temperature range of

−40°C to +85°C.

04577-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

ADAV801

TABLE OF CONTENTS

Specifications..................................................................................... 3

PLL Section ................................................................................. 22

Test Conditions............................................................................. 3

ADAV801 Specifications ............................................................. 3

Timing Specifications .................................................................. 6

Temperature Range ...................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Functional Description ..................................................................15

ADC Section ............................................................................... 15

DAC Section................................................................................ 18

Sample Rate Converter (SRC) Functional Overview ............ 19

REVISION HISTORY

7/04—Revision 0: Initial Version

SPDIF Transmitter and Receiver.............................................. 23

Serial Data Ports ......................................................................... 27

Interface Control ............................................................................ 30

SPI Interface ................................................................................ 30

Block Reads and Writes ............................................................. 30

Layout Considerations................................................................... 54

ADC ............................................................................................. 54

DAC.............................................................................................. 54

PLL ............................................................................................... 54

Reset and Power-Down Considerations ................................. 54

Outline Dimensions....................................................................... 55

Ordering Guide .......................................................................... 55

Rev. 0 | Page 2 of 56

ADAV801

SPECIFICATIONS

TEST CONDITIONS

Test conditions, unless otherwise noted.

Table 1.

Test Parameter Condition

Supply Voltage

Analog 3.3 V

Digital 3.3 V Ambient Temperature 25°C Master Clock (XIN) 12.288 MHz Measurement Bandwidth 20 Hz to 20 kHz Word Width (All Converters) 24 bits Load Capacitance on Digital Outputs 100 pF ADC Input Frequency 1007.8125 Hz at −1 dBFS DAC Output Frequency 960.9673 Hz at 0 dBFS Digital Input Slave Mode, I2S Justified Format Digital Output Slave Mode, I2S Justified Format

ADAV801 SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Comments

PGA SECTION

Input Impedance 4 kΩ

Minimum Gain 0 dB

Maximum Gain 24 dB

Gain Step 0.5 dB REFERENCE SECTION

Absolute Voltage, V

Temperature Coefficient 80 ppm/°C

REF

ADC SECTION

Number of Channels 2

Resolution 24 Bits

Dynamic Range −60 dB input

Unweighted 99 dB fS = 48 kHz 98 dB fS = 96 kHz A-Weighted 98 102 dB fS = 48 kHz 101 dB fS = 96 kHz

Total Harmonic Distortion plus Noise

−88 dB fS = 48 kHz

−87 dB fS = 96 kHz

Analog Input

Input Range (± Full Scale) 1.0 V rms

DC Accuracy

Gain Error −1.5 −0.8 dB Interchannel Gain Mismatch 0.05 dB Gain Drift 1 mdB/°C

Offset −10 mV Crosstalk (EIAJ Method) −110 dB Volume Control Step Size (256 Steps) 0.39

REF

1.5 V

Input = −1.0 dBFS

% per step

Rev. 0 | Page 3 of 56

ADAV801

Parameter Min Typ Max Unit Comments

Maximum Volume Attenuation −48 dB Mute Attenuation

∞

Group Delay

fS = 48 kHz 910 µs fS = 96 kHz 460 µs

ADC LOW-PASS DIGITAL DECIMATION FILTER CHARACTERISTICS1

Pass-Band Frequency 22 kHz Sample rate: 48 kHz 44 kHz Sample rate: 96 kHz Stop-Band Frequency 26 kHz Sample rate: 48 kHz

52 kHz Sample rate: 96 kHz

Stop-Band Attenuation 120 dB Sample rate: 48 kHz

120 dB Sample rate: 96 kHz

Pass-Band Ripple ±0.01 dB Sample rate: 48 kHz ±0.01 dB Sample rate: 96 kHz ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS

Cutoff Frequency 0.9 Hz fS = 48 kHz SRC SECTION

Resolution 24 Bits

Sample Rate 8 192 kHz XIN = 27 MHz

SRC MCLK 138 × f

33 MHz

S-MAX

Maximum Sample Rate Ratios

Upsampling 1:8 Downsampling 7.75:1

Dynamic Range 140

Total Harmonic Distortion plus Noise 120 dB

DAC SECTION

Number of Channels 2

Resolution 24

Dynamic Range 20 Hz to 20 kHz, −60 dB input

Unweighted 99

A-Weighted 97 101

100

Total Harmonic Distorton plus Noise

−91

−90

Analog Outputs

Output Range (± Full Scale) 1.0 Output Resistance 60 Common-Mode Output Voltage 1.5

DC Accuracy

Gain Error −2 −0.8 Interchannel Gain Mismatch 0.05 Gain Drift 1

DC Offset −30 Crosstalk (EIAJ Method) −110 Phase Deviation 0.05 Mute Attenuation −95.625

dB ADC outputs all zero codes

is the greater of the input

S-MAX

or output sample rate

/2, 1 kHz,

= 48 kHz

/2, 1 kHz,

= 48 kHz

= 44.1 kHz,

+30

20 Hz to f

−60 dBFS input, f f

OUT

20 Hz to f 0 dBFS input, f f

OUT

Bits

dB fS = 48 kHz dB fS = 96 kHz dB fS = 48 kHz dB fS = 96 kHz Referenced to 1 V rms dB fS = 48 kHz dB fS = 96 kHz

V rms Ω V

dB dB mdB/°C mV dB Degrees dB

Rev. 0 | Page 4 of 56

ADAV801

Parameter Min Typ Max Unit Comments

Volume Control Step Size (256 Steps) 0.375 Group Delay

48 kHz 630 96 kHz 155 192 kHz 66

DAC LOW-PASS DIGITAL INTERPOLATION FILTER CHARACTERISTICS

Pass-Band Frequency 20 kHz Sample rate: 44.1 kHz 22 kHz Sample rate: 48 kHz 42 kHz Sample rate: 96 kHz Stop-Band Frequency 24 kHz Sample rate: 44.1 kHz 26 kHz Sample rate: 48 kHz 60 kHz Sample rate: 96 kHz Stop-Band Attenuation 70 dB Sample rate: 44.1 kHz 70 dB Sample rate: 48 kHz 70 dB Sample rate: 96 kHz

Pass-Band Ripple ±0.002 dB Sample rate: 44.1 kHz ±0.002 dB Sample rate: 48 kHz ±0.005 dB Sample rate: 96 kHz PLL SECTION

Master Clock Input Frequency 27/54 MHz

Generated System Clocks

MCLKO 27/54 MHz SYSCLK1 256 768 × f

SYSCLK2 256 768 × f

SYSCLK3 256 512 × f

Jitter

SYSCLK1 65 ps rms SYSCLK2 75 ps rms SYSCLK3 75 ps rms

DIR SECTION

Input Sample Frequency 27.2 200 kHz

Differential Input Voltage 200 mV DIT SECTION Output Sample Frequency 27.2 DIGITAL I/O

Input Voltage High, V

Input Voltage Low, V

Input Leakage, IIH @ VIH = 3.3 V

Input Leakage, IIL @ VIL = 0 V

2.0

Output Voltage High, VOH @ IOH = 0.4 mA 2.4 V

Output Voltage Low, VOL @ IOL = −2 mA

Input Capacitance POWER

Supplies

Voltage, AVDD 3.0 3.3 3.6 V Voltage, DVDD 3.0 3.3 3.6 V Voltage, ODVDD 3.0 3.3 3.6 V

µs µs µs

256/384/512/768 × 32/44.1/ 48 kHz

256/512 × 32/44.1/48 kHz

200 kHz

DVDD V

0.8 V 10 µA 10 µA

0.4 V 15 pF

Rev. 0 | Page 5 of 56

ADAV801

Parameter Min Typ Max Unit Comments

Operating Current All supplies at 3.3 V

Analog Current 60 mA Digital Current 38 mA Digital Interface Current 13 mA DIRIN/DIROUT Current 5 mA PLL Current 18 mA

Power-Down Current

Analog Current 18 mA Digital Current 2.5 mA Digital Interface Current 700 µA DIRIN/DIROUT Current 3.5 mA PLL Current 900 µA

Power Supply Rejection

Signal at Analog Supply Pins −70 dB 1 kHz, 300 mV p-p

−70 dB 20 kHz, 300 mV p-p

Guaranteed by design.

TIMING SPECIFICATIONS

Timing specifications are guaranteed over the full temperature and supply range.

Table 3.

Parameter Min Typ Max Unit Comments

MASTER CLOCK AND RESET

MCLK

XIN

RESET

SPI PORT

CCH

CCL

CIS

CIH

CLS

CLH

COE

COD

COTS

SERIAL PORTS

Slave Mode

SBH

SBL

SBF

SLS

SLH

SDS

SDH

SDD

MCLKI Frequency 12.288 54 MHz XIN Frequency 27.0 54 MHz RESET Low

20 ns

CCLK High 40 ns CCLK Low 40 ns CIN Setup 10 ns To CCLK rising edge CIN Hold 10 ns From CCLK rising edge CLATCH Setup 10 ns To CCLK rising edge CLATCH Hold 10 ns From CCLK rising edge COUT Enable 15 ns From CLATCH falling edge COUT Delay 20 ns From CCLK falling edge COUT Three-State 25 ns From CLATCH rising edge

xBCLK High 40 ns xBCLK Low 40 ns xBCLK Frequency 64 × fS xLRCLK Setup 10 ns To xBCLK rising edge xLRCLK Hold 10 ns From xBCLK rising edge xSDATA Setup 10 ns To xBCLK rising edge xSDATA Hold 10 ns From xBCLK rising edge xSDATA Delay 10 ns From xBCLK falling edge

RESET low, no MCLK

Rev. 0 | Page 6 of 56

ADAV801

Parameter Min Typ Max Unit Comments

Master Mode

MLD

MDD

MDS

MDH

The prefix x refers to I-, O-, IAUX-, or OAUX- for the full pin name.

TEMPERATURE RANGE

Table 4.

Min Typ Max Unit

Specifications Guaranteed 25 °C Functionality Guaranteed −40 +85 °C Storage −65 +150 °C

xLRCLK Delay 5 ns From xBCLK falling edge xSDATA Delay 10 ns From xBCLK falling edge xSDATA Setup 10 ns From xBCLK rising edge xSDATA Hold 10 ns From xBCLK rising edge

Rev. 0 | Page 7 of 56

ADAV801

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

DVDD to DGND and ODVDD to

DGND AVDD to AGND 0 V to 4.6 V Digital Inputs DGND − 0.3 V to DVDD + 0.3 V Analog Inputs AGND − 0.3 V to AVDD + 0.3 V AGND to DGND −0.3 V to +0.3 V Reference Voltage Indefinite short circuit to ground Soldering (10 s) 300°C

0 V to 4.6 V

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. 0 | Page 8 of 56

ADAV801

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

AVDD

VOUTLNCVOUTR

ADVDD

ADGND

PLL_LF2

PLL_LF1

PLL_GND

PLL_VDD

DGND

SYSCLK1

SYSCLK2

SYSCLK3

XIN

XOUT

MCLKO

MCLKI

DVDD

DGND

VINR

VINL AGND AVDD

DIR_LF DIR_GND DIR_VDD

RESET

CLATCH

CIN CCLK COUT

EROL/INT

ZEROR

DVDD DGND

CAPLN

CAPLP

AGND

PIN 1 INDICATOR

CAPRP

64 63 62 61 60 59 58

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24

CAPRN

AVDD

AGND

VREF

AGND

FILTD

57 56 55 54 53 52 51 50 49

ADAV801

TOP VIEW

(Not to Scale)

25 26 27 31302928 32

OBCLK

OLRCLK

OSDATA

DIRIN

ODVDD

ODGND

DITOUT

OAUXLRCLK

OAUXBCLK

OAUXSDATA

IAUXBCLK

IAUXLRCLK

IAUXSDATA

04577-0-002

NC = NO CONNECT

IBCLK

ILRCLK

ISDATA

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 VINR I Analog Audio Input, Right Channel. 2 VINL I Analog Audio Input, Left Channel. 3 AGND Analog Ground. 4 AVDD Analog Voltage Supply. 5 DIR_LF DIR Phase-Locked Loop (PLL) Filter Pin. 6 DIR_GND Supply Ground for DIR Analog Section. This pin should be connected to AGND. 7 DIR_VDD Supply for DIR Analog Section. This pin should be connected to AVDD. 8

RESET

I Asychronous Reset Input (Active Low). 9 CLATCH I Chip Select (Control Latch) Pin of SPI-Compatible Control Interface. 10 CIN I Data Input of SPI-Compatible Control Interface. 11 CCLK I Clock Input of SPI-Compatible Control Interface. 12 COUT O Data Output of SPI-Compatible Control Interface. 13 ZEROL/INT O

Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined

by the INTRPT pin in DAC Control Register 4. 14 ZEROR O Right Channel (Output) Zero Flag. 15 DVDD Digital Voltage Supply. 16 DGND Digital Ground. 17 ILRCLK I/O Sampling Clock (LRCLK) of Playback Digital Input Port. 18 IBCLK I/O Serial Clock (BCLK) of Playback Digital Input Port. 19 ISDATA I Data Input of Playback Digital Input Port. 20 OLRCLK I/O Sampling Clock (LRCLK) of Record Digital Output Port. 21 OBCLK I/O Serial Clock (BCLK) of Record Digital Output Port. 22 OSDATA O Data Output of Record Digital Output Port. 23 DIRIN I Input to Digital Input Receiver (S/PDIF). 24 ODVDD Interface Digital Voltage Supply. 25 ODGND Interface Digital Ground. 26 DITOUT O S/PDIF Output from DIT. 27 OAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Output Port.

Rev. 0 | Page 9 of 56

ADAV801

Pin No. Mnemonic I/O Description

28 OAUXBCLK I/O Serial Clock (BCLK) of Auxiliary Digital Output Port. 29 OAUXSDATA O Data Output of Auxiliary Digital Output Port. 30 IAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Input Port. 31 IAUXBCLK I/O Serial (BCLK) of Auxiliary Digital Input Port. 32 IAUXSDATA I Data Input of Auxiliary Digital Input Port. 33 DGND Digital Ground. 34 DVDD Digital Supply Voltage. 35 MCLKI I External MCLK Input. 36 MCLKO O Oscillator Output. 37 XOUT I Crystal Input. 38 XIN I Crystal or External MCLK Input. 39 SYSCLK3 O System Clock 3 (from PLL2). 40 SYSCLK2 O System Clock 2 (from PLL2). 41 SYSCLK1 O System Clock 1 (from PLL1). 42 DGND Digital Ground. 43 PLL_VDD Supply for PLL Analog Section. This pin should be connected to AVDD. 44 PLL_GND Ground for PLL Analog Section. This pin should be connected to AGND. 45 PLL_LF1 Loop Filter for PLL1. 46 PLL_LF2 Loop Filter for PLL2. 47 ADGND Analog Ground (Mixed Signal). This pin should be connected to AGND. 48 ADVDD Analog Voltage Supply (Mixed Signal). This pin should be connected to AVDD. 49 VOUTR O Right Channel Analog Output. 50 NC No Connect. 51 VOUTL O Left Channel Analog Output. 52 NC No Connect. 53 AVDD Analog Voltage Supply. 54 AGND Analog Ground. 55 FILTD Output DAC Reference Decoupling. 56 AGND Analog Ground. 57 VREF Voltage Reference Voltage. 58 AGND Analog Ground. 59 AVDD Analog Voltage Supply. 60 CAPRN ADC Modulator Input Filter Capacitor (Right Channel, Negative). 61 CAPRP ADC Modulator Input Filter Capacitor (Right Channel, Positive). 62 AGND Analog Ground. 63 CAPLP ADC Modulator Input Filter Capacitor (Left Channel, Positive). 64 CAPLN ADC Modulator Input Filter Capacitor (Left Channel, Negative).

Rev. 0 | Page 10 of 56

ADAV801

TYPICAL PERFORMANCE CHARACTERISTICS

–50

MAGNITUDE (dB)

–100

–150

0 0.5 1.0 1.5 2.0

FREQUENCY (Normalized to fS)

Figure 3. ADC Composite Filter Response

–5

–10

–15

MAGNITUDE (dB)

–20

–25

–30

0 5 10 15 20

FREQUENCY (Hz)

Figure 4. ADC High-Pass Filter Response, fS = 48 kHz

04577-0-037

04577-0-038

–50

MAGNITUDE (dB)

–100

–150

0 96 192 288 384

FREQUENCY (kHz)

Figure 6. DAC Composite Filter Response, 48 kHz

–50

MAGNITUDE (dB)

–100

–150

02412 36 48

FREQUENCY (kHz)

Figure 7. DAC Pass-Band Filter Response, 48 kHz

0.06

04577-0-040

04577-0-041

–5

–10

–15

MAGNITUDE (dB)

–20

–25

–30

0 5 10 15 20

Figure 5. ADC High-Pass Filter Response, f

FREQUENCY (Hz)

= 96 kHz

04577-0-039

Rev. 0 | Page 11 of 56

0.04

0.02

0.00

MAGNITUDE (dB)

–0.02

–0.04

–0.06

0 8 16 24

FREQUENCY (kHz)

Figure 8. DAC Filter Ripple, 48 kHz

04577-0-042

ADAV801

–50

–100

MAGNITUDE (dB)

–100

–150

0 192 384 576 768

FREQUENCY (kHz)

Figure 9. DAC Composite Filter Response, 96 kHz

–50

MAGNITUDE (dB)

–100

–150

0 2448729

FREQUENCY (kHz)

Figure 10. DAC Pass-Band Filter Response, 96 kHz

0.10

0.05

0.00

MAGNITUDE (dB)

–0.05

–0.10

0 2448729

FREQUENCY (kHz)

Figure 11. DAC Filter Ripple, 96 kHz

04577-0-043

04577-0-044

04577-0-045

MAGNITUDE (dB)

–150

–200

0 384 768 1152 1536

FREQUENCY (kHz)

Figure 12. DAC Composite Filter Response, 192 kHz

–2

–4

–6

MAGNITUDE (dB)

–8

–10

48 64 80 96

Figure 2 kHz

13. DAC Pass-Band Filter Response, 19

FREQUENCY (kHz)

0.50

0.40

0.30

0.20

0.10

0.00

–0.10

MAGNITUDE (dB)

–0.20 –0.30

–0.40

–0.50

0 8 16 32 64

FREQUENCY (kHz)

Figure 14. DAC Fil r Ripple, 192 kHz te

04577-0-046

04577-0-047

04577-0-048

Rev. 0 | Page 12 of 56

ADAV801

–20

–40

DNR = 102dB (A-Weighted)

–20

–40

THD+N = 95dB

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 2 4 6 8 101214161820

Fig

ure 15. DAC Dynamic Range, f

FREQUENCY (kHz)

= 48 k

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

02468101214161820

FREQUENCY (kHz)

Figure 16. DAC THD + N, f

THD+N = 96dB

= 48 kHz

–20

–40

DNR = 102dB (A-Weighted)

04577-0-049

04577-0-050

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20 25 30 35 40 45 48

Figure 18. DAC THD + N, f

FREQUENCY (kHz)

= 96 kHz

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20

Figure 19. ADC Dynam c Range, f

FREQUENCY (kHz)

DNR = 102dB (A-Weighted)

= 48 kHz

–20

–40

THD+N = 92dB

= –3dB)

04577-0-052

04577-0-053

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20 25 30 35 40 45 48

Figure 17. DAC Dynamic Range, f

FREQUENCY (kHz)

= 96 kHz

04577-0-051

Rev. 0 | Page 13 of 56

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20

Figure 20. DAC THD + N, f

FREQUENCY (kHz)

= 48 kHz

04577-0-054

ADAV801

–20

–40

DNR = 102dB (A-Weighted)

–20

–40

TH(VD+N = 92dB

= –3dB)

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 8 16 24 32 40 48

Figure 21. ADC Dynamic Range, f

FREQUENCY (kHz)

= 96 kHz

04577-0-055

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 8 16 24 32 40 48

Figure 22. ADC THD + N, f

FREQUENCY (kHz)

= 96 kHz

04577-0-056

Rev. 0 | Page 14 of 56

ADAV801

Ω

FUNCTIONAL DESCRIP

TION

ADC SECTION

The ADAV801’s ADC section is implemented using a secondorder multibit (5 bits) Σ-∆ modulator. The modulator is sampled at either half of the ADC MCLK rate (modulator clo = 128 × f clock = 64 × f followed by a cascade of three half-band FIR filters. The Sin decimates by a factor of 16 at 48 kHz 96 kHz. Each of the half-band filters decimates by a factor of 2.

Figure 23 shows the details of the ADC section. The ADC can be clocked by a number of different clock sources to control t sample rate. MCLK selection for the ADC is set by Internal Clocking Control Register 1 (Address 0x76). The ADC provide an output word of up to 24 bits in resolution in twos complement format. The output word can be routed to ei output ports, the sample rate converter, or the SPDIF digital transmitter.

) or one-quarter of the ADC MCLK rate (modulator

). The digital decimator consists of a Sinc^5 filter

and by a factor of 8 at

ther the

)

PLL2 INTERNAL

PLL1 INTERNAL

MCLKI

DIR PLL (256 × f

DIR PLL (512 × f

XIN

REG 0x76 BITS 4–2

Programmable Gain Amplifier (PGA)

The input of the record channel features a PGA that converts the single-ended signal to a differential signal, which is applied to the analog Σ-Δ modulator of the ADC. The PGA can be programmed to amplify a signal by up to 24 dB in 0.5 dB

increments. Figure 24 shows the structure of the PGA circuit.

4kΩ TO 64k

EXTERNAL

4kΩ

VREF

8kΩ

CAPACITOR

8kΩ

(1nF NPO)

125Ω

EXTERNAL

CAPACITOR

(1nF NPO)

CAPxN

EXTERNAL

CAPACITOR

(1nF NPO)

CAPxP

Figure 24. PGA Block Diagram

MODULATOR

04577-0-004

Analog Σ-∆ Modulator

The ADC features a second-order, multibit, Σ-Δ modulator. The input features two integrators in cascade followed by a flash converter. This multibit output is directed to a scrambler, followed by a DAC for loop feedback. The flash ADC outp also converted from thermometer coding to binary codin input as a 5-bit word to the decimator. F

igure 25 shows the

ut is

g for

ADC block diagram.

ADC MCLK

DIVIDER

MCLK

ADC

REG 0x6F BITS 1–0

04577-0-003

Figure 23. Clock Path Control on the ADC

MULTIBIT

Σ–∆

MODULATOR

DC MCL

AMC

(REG 0X63

BIT-7)

÷2 ÷4

MODULATOR

CLOCK

(6.144MHz MAX)

SINC^5

DECIMATOR

384kHz 768kHz

HALF-BAND

FILTER

The ADC also features independent digital volume control for the left and right channels. The volume control consists of 256 linear steps, with each step reducing the digital output codes by 0.39%. Each channel also has a peak detector that records the peak level of the input signal. The peak detector register is cleared by reading it.

PEAK

DETECT

HALF-BAND

FILTER

48kHz 96kHz

04577-0-005

VOLUME

ONTROL

192kHz 384kHz

Diagram Figure 25. A DC Block

HPF

SINC

COMPENSATION

96kHz

192kHz

Rev. 0 | Page 15 of 56

ADAV801

Automatic Level Control (

The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and automatically reduces the gain, if the signal the input pins causes the ADC output to exceed a preset limit. This function can be useful to maximize the signal dynamic range when the input level is not well defined. The PGA can b used to amplify the unknown signal, and the ALC reduces the gain until the ADC output is within the preset limits. This results in m

Because the ALC block monitors the output of the ADC, the volume control function should not be used. The ADC v control scales the results from the ADC, and any distortion caused by the input signal exceeding the input range of the ADC is still present at the output of the ADC, but scaled by a value determined by the volume control register.

The ALC block has two functions, attack mode and recover mode. Recovery mode consists of three settings: no recovery, normal recovery, and limited recovery. These modes are discussed in the following sections. Figure 26 is a flow diagram of the ALC block. When the ALC has been enabled, any changes made to the PGA or ALC settings are ignored. To change the functionality of the ALC, it must first be disabled. The settings can then be changed and the ALC re-enabled.

aximum front end gain.

Attack Mode

When the absolute value of the ADC output exceeds the level set by the attack threshold bits in ALC Control Register 2, attack mode is initiated. The PGA gain for both channels is reduced by one step (0.5 dB). The ALC then waits for a time determined by the attack timer bits before sampling the ADC output value again. If the ADC output is still above the threshold, the PGA gain is reduced by a further step. This procedure continues until the ADC output is below the limit set by the attack threshold bits. The initial gains of the PGAs are defined by the ADC left PGA gain register and the ADC right PGA gain register, and they can have different values. The ALC subtracts a common gain offset to these values. The ALC preserves any gain difference in dB as defined by these registers. At no time do the PGA gains exceed their initial values. The initial gain setting, therefore, also serves as a maximum value.

The limit detection mode bit in ALC Control Register 1 determines how the ALC responds to an ADC output that exceeds the set limits. If this bit is a 1, then both channels must exceed the threshold before the gain is reduced. This mode can be used to prevent unnecessary gain reduction due to spurious noise on a single channel. If the limit detection mode bit is a 0, the gain is reduced when either channel exceeds the threshold.

ALC)

olume

No Recovery Mode

By default, there is no gain recovery. Once the gain has bee reduced, it by toggling the ALCEN bit in ALC Control Register 1 o writing any value to ALC Control Register 3. The latter option more efficient, because it requires only one write operation to reset the ALC function. No recovery mode prevents volume modulation of the signal caused by adjusting the gain, which can create undesirable artifacts in the signal. The gain can be reduced but not recovered. Therefore, care should be taken that spurious signals do not interfere with the input signal, because these might trigger a ga

ormal Recovery Mode

Normal recovery mode allows for the PGA gain to be recovered, provided that the input signal meets certain criteria. First, the ALC must not be in attack mode, that is, the PGA gain has been reduced set by the attack threshold bits. Second, the output result from the ADC must be below the level set by the recovery threshold bits in the ALC control register. If both of these criteria are met, the gain is recovered by one step (0.5 dB). The gain is incrementally restored to its original value, assuming that the ADC output level is below the recovery threshold at intervals determined by the recovery time bits.

If the ADC output level exceeds the recovery threshold while the PGA gain is being restored, the PGA gain value is held and does not continue restoration until the ADC output level is again below the recovery threshold. Once the PGA gain is restored to its original value, it is not changed again unless the ADC output value exceeds the attack threshold and the ALC then enters attack mode. Care should be taken when using this mode to choose values for the attack and recovery thresholds that prevent excessive volume modulation caused by continuous gain adjustments.

is not recovered until the ALC has been reset, either

in reduction unnecessarily.

sufficiently such that the input signal is below the level

r by

Limited Recovery Mode

Limited recovery mode offers a compromise between no recovery and normal recovery modes. If the output level of the ADC exceeds the attack threshold, then attack mode is initiated. When attack mode has reduced the PGA gain to suitable levels, the ALC attempts to recover the gain to its original level. If the ADC output level exceeds the level set by the recovery threshold bits, a counter is incremented (GAINCNTR). This counter is incremented at intervals equal to the recovery time selection, if the ADC has any excursion above the recovery threshold. If the counter reaches its maximum value, determined by the GAINCNTR bits in ALC Control Register 1, the PGA gain is deemed suitable and no further gain recovery is attempted. Whenever the ADC output level exceeds the attack threshold, attack mode is reinitiated and the counter is reset.

Rev. 0 | Page 16 of 56

ADAV801

Selecting a Samp

le Rate

The output sample rate of the ADC is always ADC MCLK/256, as shown in Figure 23. By default, the ADC modulator runs at ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz, the ADC modulator should be set to run at ADC MCLK/4. This is achieved by setting the AMC (ADC Modulator Clock) bit in the ADC Control Register 1. To compensate for the reduced modulator clock speed, a different set of filters are used in the decimator section ensuring that the sample rate remains the same.

The AMC bit can also be used to boost the THD + N perform

ance of the ADC at the expense of dynamic range. The improvement is typically 0.5 dB to 1.0 dB and works, b selecting the lower modulator rate reduces the amount of dig

ecause

IS A RECOVERY

MODE ENABLED?

ital

noise, improving THD + N, b therefore reducing the dynamic range by a corresponding amount.

For best performance of the ADC, avoid using similar frequency clocks from separate sources in the ADAV801. For example, running the ADC from a 12.288 MHz clock conne to MCLKI and using the PLL t clock for the DAC can reduce the performance of the ADC. This is due to the interaction of the clocks, which generate b frequencies that can affect the charge on the switch capacitors of the analog inputs.

ATTACK MODE

WAIT FOR SAMPLE

IS SAMPLE

GREATER THAN ATTACK

THRESHOLD?

ut reduces the oversampling ratio,

cted

o generate a separate 12.288 MHz

eat

YES

INCREASE GAIN BY 0.5dB

HAS GAIN BEEN

FULLY RESTORED?

YES

YESYES

DECREASE GAIN BY 0.5dB

AND WAIT ATTACK TIME

LIMITED RECOVERY

WAIT FOR SAMPLE WAIT FOR SAMPLE

IS SAMPLE

ABOVE ATTACK

THRESHOLD?

HAS RECOVERY

TIME BEEN

REACHED?

YES

ARE ALL

SAMPLES BELOW

RECOVERY

THRESHOLD?

YES NO

NO NO

INCREMENT

GAINCNTR

IS GAINCNTR

AT MAXIMUM?

NORMAL RECOVERY

SAMPLE

ABO

VE ATTACK

THRESHOLD?

NONO

HAS RECOVERY

TIME BEEN REACHED?

YES

ARE ALL

SAMPLES BELOW

RECOVERY

THRESHOLD?

YES

INCREASE GAIN BY 0.5dB

WAIT RECOVERY TIME

HAS GAIN BEEN

FULLY RESTORED?

YESNO

Figure 26. ALC Flow Diagram

Rev. 0 | Page 17 of 56

04577-0-006

ADAV801

DAC SECTION

The ADAV801 has two DAC channels arranged as a stereo with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 1 of 0.375 dB per step. The DAC can receive data from the playback or auxiliary input ports, the SRC, the ADC, or the DIR. Each analog output pin sits at a dc level of VREF, and swings

1.0 V rms for a 0 dB digital input signal. A single op amp thirdorder external low-pass filter is recommen

ded to remove high frequency noise present on the output pins. Note that the use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band. Care should be taken in selecting these components.

The FILTD and FILTR pins should be bypassed by external capacitors to AGND. The FILTD pin is used to reduce th of the internal DAC bias circuitry, thereby reducing the DAC output noise. The voltage at the VREF pin, FILTR, can be use to bias external op amps used to filter the output signals. For applications in which the FILTR is required to drive exter op amps, which might draw more than 50 µA or have dynamic load changes, extra buffering should be used to preserve the quality of the ADAV801 reference.

The digital input data source for the DAC can be selected from a number of available sources by programming the appropriate bits in the datapath control register. Figure 27 shows how the digital data source and the MCLK source for the DAC are selected. Each DAC has an independent volume register giving 256 steps of control, with each step giving approximately 0.375 dB of attenuation. Note that the DACs are muted by default to prevent unwanted pops, clicks, and other noises from appearing on the outputs while the ADAV801 is being configured. Each DAC also has a peak-level register that records the peak value of the digital audio data. Reading the register clears the peak.

pair

28 steps

e noise

nal

electing a Sample Rate

Correct operation of pon the data rate provided to the DAC, the master clock applied to the DAC, and the selected interpolation rate. By default, the DAC assumes that

the DAC is dependent u

the MCLK rate is 256 times the sample rate, which requires an 8-times oversampling rate. This combination is suitable for sample rates of up to 48 kHz.

For a 96 kHz data rate that has a 24.576 MHz MCLK (256 × f

)

associated with it, the DAC MCLK divider should be set to divide the MCLK

by 2. This prevents the DAC engine from running too fast. To compensate for the reduced MCLK rate, the interpolator should be selected to operate in 4 × (DAC MCLK =

). Similar combinations can be selected for different

128 × f

sample rates.

)

PLL2 INTERNAL

PLL1 INTERNAL

MCLKI

DAC

INPUT

XIN

REG 0x76 BITS 7–5

REG 0x65 BITS 3–2

REG 0x63 BITS 5–3

AUXILIARY IN PLAYBACK DIR

ADC

04577-0-007

DIR PLL (256 × f

DIR PLL (512 × f

MCLK

DIVIDER

DAC

MCLK

DAC

Figure 27. Clock and Datapath Control on the DAC

PEAK

DETECTOR

VOLUME/MUTE

CONTROL

ZERO DETECT

FROM DAC DATAPATH MULTIPLEXER

04577-0-008

ANALOG

OUTPUT

DAC

MULTIBIT

Σ-∆

MODULATOR

TO CONTROL

REGISTERS

INTERPOLATOR

TO ZERO FLAG PINS

Figure 28. DAC Block Diagram

Rev. 0 | Page 18 of 56

ADAV801

SAMPLE RATE CONVERTER (SRC) FUNCTIONAL O

During asynchronous samp conv or at t sam rates.

erted at the same sample rate differen ple The sim conversi

plest approach to an asynchronous sample rate

on is to use a zero-order hold between the two samplers, as shown in Figure 29. In an asynchronous syste is never equal to T1, nor is the ratio between T2 and T1 ra As a result, samples

at f

an error in the resam

le rate conversion, data can be

are repeated or dropped, producing

S_OUT

pling process.

VERVIEW

m, T2

tional.

S_IN

INTERPOLATE

BY N

TIME DOMAIN OF

LOW-PASS

FILTER

SAMPLES

S_IN

ZERO-ORDER

HOLD

S_OUT

OUT

The frequency domain shows the wide side lobes tha esult from this error when the sampling of f the attenu orde order h nfinite he ratio of T2 to T1 i rom the resampling at f

ated images from the SIN(x)/x nature of the zero-

r hold. The images at f

(dc signal imag

S_IN

old are i ly attenuated. Because t

s an irrational number, the error resulting f

n never be eliminated. The error can be

S_OUT

is convolved with

S_OUT

significantly reduced, however, through interpolation of t input data at f ADAV801 is concep

. Therefore, the sample rate converter in t

S_IN

tually interpolated by a factor of 2

ZERO-ORDER

HOLD

= 1/T1

S_IN

ORIGINAL SIGNAL

SAMPLED AT

SIN(X)/X OF ZERO-ORDER HOLD

SPECTRUM OF ZERO-ORDER HOLD OUTPUT

SPECTRUM OF

S_OUT

S_IN

SAMPLING

S_OUT

= 1/T2

t r

es) of the zero-

OUT

TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER

TIME DOMAIN OF

TIME DOMAIN OF THE ZERO-ORDER HOLD OUTPUT

S_OUT

RESAMPLING

Figure 30. SRC Time Domain

In the frequency domain shown in Figure 31, the interpolation expands the frequency axis of the zero-order hold. The images from the interpolation can be su ficiently attenuated by a good

low-pass filter. The images from the zero-order hold are now

pushed by

a factor of 2

closer to the infinite attenuatio

of the zero-order hold, which is f

× 220. The images at the

S_IN

n point

zero-order hold are the determining factor for the fidelity of t output at f

S_IN

S_OUT

INTERPOLATE

BY N

LOW-PASS

FILTER

ZERO-ORDER

HOLD

S_OUT

OUT

04577-0-010

S_OUT

FREQUENCY RESPONSE OF WITH ZERO-ORDER HOLD SPECTRUM

Figure 29. Zero-Order Hold Used by f

S_OUT

CONVOLVED

to Resample Data from f

S_ OUT

Conceptual High Interpolation Model

Interpolation of the input data by a factor of 2

− 1) samples between each f

sample. Figure 30 shows

S_IN

involves placin

both the time domain and the frequency domain of

interpolation by a factor of 2

involves the steps of zero-stuffing (220 − 1) number of samples between each f interpolated signal with a digital low-pass filter images. In the time domain, it can be een at f closest f the nearest f

× 220 sample from the zero-order hold, as opposed to

S_IN

sample in the case of no interpolation. This

S_IN

. Conceptually, interpolation b

sample and convolving this

S_IN

s th

to suppress the

S_OUT

significantly reduces the resampling error.

2×

S_OUT

S_IN

selects the

04577-0-009

Rev. 0 | Page 19 of 56

FREQUENCY DOMAIN OF SAMPLES AT

FREQUENCY DOMAIN OF THE INTERPOLATION

SIN(X)/X OF ZERO-ORDER HOLD

FREQUENCY DOMAIN OF

FREQUENCY DOMAIN AFTER RESAMPLING

S_OUT

S_IN

RESAMPLING

220×

S_IN

220×

S_IN

Figure 31. Frequency Domain of the Interpolation and Resampling

04577-0-011

ADAV801

The mputed from the zero-order

worst-case images can be co

hold frequency response:

maximum image = sin (

× F/f

S_INTERP

)/(× F/f

where:

F is the frequency of the worst-case image that would be

× f

± f

S_IN

/2.

S_IN

× 220.

S_INTERP

S_IN

is f

The following worst-case images would appear for f 192 kHz:

Image at f

− 96 kHz = −125.1 dB

S_INTERP

+ 96 kHz = −125.1 dB

S_INTERP

Hardware Model

The output rate of the low-pass filter in Figure 30 is the interpolation rate:

× 192,000 kHz = 201.3 GHz

Sampling at a rate of 201.3 GHz is clearly impractical, not to mention the number of taps required to calculate each interpolated sample. However, because interpolation by 2

involves zero-stuffing 2

−1 samples between each f most of the multiplies in the low-pass FIR filter are by zero. A further reduction can be realized, because only one interpolated sample is taken at the output at the f convolution needs to be performed per f

convolutions. A 64-tap FIR filter for each f

rate, so only one

S_OUT

period instead of

S_OUT

sufficient to suppress the images caused by the interpolation.

One difficulty with the above approach is that the correct interpolated sample must be selected upon the arrival of

Because th

ere are 2 arrival of the f 1/201.3 GHz = 4.96 ps. Measuring the f

possible convolutions per f

clock must be measured with an accuracy of

S_OUT

period with a clock

S_OUT

of 201.3 GHz frequency is clearly impossible; instead, several coarse measurements of the f

clock period are made and

S_OUT

averaged over time.

Another difficulty with the above approach is the number of

coefficients required. Because there are 2 tions with a 64-tap FIR filter, there must be 2

possible convolu-

coefficients for each tap, which requires a total of 2 cients. To reduce the number of coefficients in ROM, the SRC stores a small subset of coefficients and performs a high order interpolation between the stored coefficients.

> f

The above approach works when f the output sample rate, f

, the ROM starting address, input data, and length of th

S_IN

convolution must be sc

S_OUT

aled. As the input sample rate rises over

S_OUT

, is less than the input sample rate

. However, when

S_IN

the output sample rate, the antialiasing filter’s cutoff frequency

S_INTERP

S_OUT

)

equal to

S_IN

sample,

S_IN

sample is

eriod, the

lyphase

coeffi-

S_O

must be lowered, because the Nyquist frequency of the output samples is less than the Nyquist frequency of the input samples. To move the cutoff frequency of the antialiasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of (f

S_IN/fS_OUT

This technique is supported by the Fourier transform propert

y that, if f(t) is F(ω), then f(k × t) is F(ω/k). Thus, the range of decimation is limited by the size of the RAM.

SRC Architecture

The architecture of the sample rate converter is shown in Figure 32. The sample rate converter left and right input samples and ores them for the FIR filter’s c

onvolution cycle. The f

to the FIFO blo l servo loop.

ck and the ramp input to the digita

counter provides the write address

S_IN

The ROM stores the coefficients for the FIR filter convolu and performs a high order interpolation between the stored

’s FIFO block adjusts the

tion

coefficients. The sample rate ratio block measures the sample rate for dynamically altering the ROM coefficients and sc of the FIR filter length as well as the input data. The digi servo loop automatically tracks the f

S_IN

and f

sample rates

S_OUT

aling

tal

and provides the RAM and ROM start addresses for the start of the FIR filter convolution.

RIGHT DATA IN

LEFT DATA IN

S_IN

COUNTER

SAMPLE RATE RATIO

S_IN

S_OUT

Figure 32. Architecture of the Sample Rate Converter

FIFO

DIGITAL

SERVO LOOP

SAMPLE

RATE RATIO

ROM A ROM B ROM C ROM D

FIR FILTER

EXTERNAL

RATIO

HIGH ORDER INTERP

L/R DATA OUT

04577-0-012

The FIFO receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the RAM. The input data is scaled by the sample rate ratio, because, as the FIR filter length of the convolution increases, so does the amplitude of the convolution output. To keep the output of the FIR filter from saturating, the input data is scaled down by multiplying it by (f

S_OUT/fS_IN

) when f

S_OUT

< f

. The FIFO also scales the input

S_IN

data for muting and unmuting of the SRC.

The RAM in the FIFO is 512 words deep for both left and right channels. An offset to the write address provided by the f

S_IN

counter is added to prevent the RAM read pointer from overlapping the write address. The minimum offset on the SRC is 16 samples. However, the group delay and mute-in register can be used to increase this offset.

Rev. 0 | Page 20 of 56

ADAV801

The number of inp FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay register. This feature is useful in varispeed applications to prevent the read pointer to the FIFO from running ahead of the write pointer. When set, Bit 7 of the group delay and mute-in register soft-mutes the sample rate. Increasing the offset of the write address pointer is useful for applications in which small changes in the sample rate ratio between f expected. The maximum decimation rate can be calculated from the RAM word depth and the group delay as

(512 − 16)/64 taps = 7.75

for short group delay and

(512 − 64)/64 taps = 7

for long group delay.

The digital servo loop is essentially a ramp filter that provides the initial pointer to the address in RAM and ROM for the start of the FIR convolution. The RAM pointer is the integer output of the ramp filter, and the ROM is the fractional part. The digital servo loop must provide excellent rejection of jitter on

and f

the f

S_IN

clock within 4.97 ps. The digital servo loop also divides

S_OUT

the fractional part of the ramp output by the rati to dynamically alter the ROM coefficients when f

REG 0x76

BIT 1

ut samples added to the write pointer of the

and f

S_IN

clocks, as well as measure the arrival of the

S_OUT

o of f

S_IN

MCLKI

PLLINT2

PLLINT1

XIN

REG 0x76

)

DIR PLL (512 ×

BIT 0

DIR PLL (256 ×

ICLK2

ICLK1

REG 0x00 BITS 1–0

S_OUT

S_IN/fS_OUT

> f

are

S_OUT

servo loop is settling down to a r

easonable value, the digital

servo loop returns to normal (or slow) mode.

During fast mode, the MUTE_OUT bi e error

e he u at clicks ght

regist r is asserted to let t ser know th or pops mi

pres l audio tput of

be ent in the digita data. The ou the SRC can

e mu Bit 7 of he group delay and r

b ted by asserting t mute registe

l t ged to he MU

unti he SRC has chan slow mode. T TE_OUT bit

an be n inter when the SRC

c set to generate a rupt changes to

m h ing sample rate

slow ode, indicating that t e data is be

onve ly.

c rted accurate

The frequency responses of the digital servo loop for fast mod

t in the sample rat

and slow mode are shown in Figure 34. The FIR filter is a 64-tap

≥ f

filter when f f

S_OUT

. The FIR filter performs its convolution by loading in the

and is (f

S_IN

S_IN/fS_OUT

) × 64 taps when f

S_IN

starting address of the RAM address pointer and the ROM address pointer from the digital servo loop at the start of the

period. The FIR filter then steps through the RAM by

S_OUT

decrementing its address by 1 for each tap, and the ROM

pointer increments its address by the (f f

S_IN

> f

S_OUT

or 220 for f

S_OUT

≥ f

. Once the ROM address rolls

S_IN

S_OUT

) × 220 ratio for

S_IN

over, the convolution is completed.

–20 –40 –60

–80 –100 –120 –140

MAGNITUDE (dB)

–160 –180 –200

–220

0.01 0.1 1 10 100 1k 10k 100k

SLOW MODE

FREQUENCY (Hz)

Figure 34. Frequency Response of the Digital Servo Loop. f

= 192 KHz, Master Clock is 30 MHz

S_OUT

FAST MODE

S_IN

is the X-Axis,

04577-0-014

SRC

MCLK

SRC

OUTPUT

SRC

INPUT

REG 0x62 BITS 7–6

AUXILIARY IN PLAYBACK DIR

ADC

04577-0-013

Figure 33. Clock and Datapath Control on the SCR

The digital servo loop is implemented with a multirate filter. To

ttle the digital servo loop filter more quickly upon startup or a

se change in the sample rate, a fast mode has been filter. When the digital servo loop starts up or the s

added to the

ample rate is changed, the digital servo loop enters fast mode to adjust and settle on the new sample rate. Upon sensing that the digital

Rev. 0 | Page 21 of 56

The convolution is performed for both the left and right channels, and the multiply accumulate circuit used for the

S_OUT

to f

S_IN

convolution is shared between the channels. The f sample rate ratio circuit is used to dynam cally alter the coefficients

in the ROM when f

S_IN

> f

S_OUT

calculated by comparing the output of an f output of an f

> f

If f

S_IN

counter. If f

S_IN

, the sample rate ratio is updated, if it is different

S_O

by more than two f

periods from the previous f

S_OUT

> f

, the ratio is held at one.

S_IN

S_IN/fS_OUT

. The ratio is

counter to the

S_OUT

comparison. This is done to provide some hysteresis to prevent the filter length from oscillating and causing distortion.

ADAV801

PLL SECTION

The ADAV801 features a dual PLL configuration to generate independent system clocks for asynchronous operation. Figure 37 shows the block diagram of the PLL section. The PLL generates the internal and system clocks from a 27 MHz clock. This clock is generated either by a crystal connected between XIN and XOUT, as shown in Figure 35, or from clock source connected directly to XIN. A 54 MHz clock can also be used, if the internal clock divider is used.

XTA

XIN

XOUT

Figure 35. Crystal Connection

Both PLLs (PLL1 and PLL2) can be programmed independently and can accommodate a range of sampling rates (32/44.1/48 kHz) with selectable system clock oversampling rates of 256 and

384. Higher oversampling rates can also be selected by enabling the doubling of the sampling rate to give 512 or 768 × f Note that this option also allows oversampling ratios of 256 or 384 at double sample r z.

ates of 64/88.2/96 kH

The PLL outputs can be routed internally to act as clock sources for the oth , and so

er component blocks such as the ADC, DAC on. The outputs of the PLLs are also available on the three SYSCLK pins. Figure 38 shows how the PLLs can be configured to provide the sampling clocks.

an external

04577-0-015

ratios.

Table 7. PLL Frequency Selection Options

MCLK Selection

PLL Sample Rate (fS)

1 32/44.1/48 kHz 256/384 × f

64/88.2/96 kHz

2A 32/44.1/48 kHz 256/384 × f

64/88.2/96 kHz 2B Same as fS selected 512 × f For PLL 2A 512 × f

Normal f

Double f

512/768 × f 256/384 × f 512/768 × f 256/384 × f

The PLLs require some external components to operate correctly. These c 6, form a loop filter that integrates the current pulses from a charge pum produces a voltage that is used to tune the VCO. Good quali capacitors, such as PPS film, are recommended. Figure 37 sh

omponents, shown in Figure 3

p and

ows a block diagram of the PLL section, including master clock selection. Figure 38 shows how the clock frequencies at the clock output pins, SYSCLK1 to SYSCLK 3, and the internal PLL clock values, PLL1 and PLL2, are sele cted.

The clock nodes, PLL1 and PLL2, can be use

r t e ADAV801 e DAC or ADC.

fo he other blocks in th such as th

e nd gro pins, which should be

Th PLL has separate supply a und

l t electri se from being

as c ean as possible to preven cal noi

nv ouplin ns.

co erted into clock jitter by c g onto the loop filter pi

AVDD

PLL_LF1

6.8nF

100nF

3.3kΩ

Figure 36. PLL Loo p Filter

PLL BLOCK

PLL_LFx

d as master clocks

04577-0-016

XIN

XOUT

MCLKO

MCLKI

REG 0x74

BIT 5

÷2

G 0x74

BIT 4

REG 0x78

BIT 6

REG 0x

BIT

Figure 37. PLL

Rev. 0 | Page 22 of 56

PHASE DETECTOR AND LOOP

FILTER

PHASE DETECTOR AND LOOP

FILTER

PLL_LF2

Section Block Diagram

VCO

÷N

VCO

÷N

OUTPUT

SCALER N1

PLL1

OUTPUT

SCALER N2

PLL2

OUTPUT

SCALER N3

SYSCLK1

SYSCLK2

SYSCLK3

04577-0-017

ADAV801

48kHz 32kHz

44.1kHz

256 384

48kHz 32kHz

44.1kHz

256 512

PLL1 MCLK PLL2 MCLK

REG 0x75 BITS 3–2

REG 0x75 BIT 1

REG 0x75 BIT 5

REG 0

7–6

BITS

REG 0x74 BIT 0

REG

BIT 0

×2

REG 0x75

BIT 4

×2

Figure 38. PLL Clocking Scheme

SPDIF TRANSMITTER AND RECEIVER

The ADAV801 contains an integrated SPDIF transmitter and receiver. The transmitter consists of a single output pin, DITOUT, on which the biphase encoded data appears. The SPDIF transmitter source can be selected from the different blocks making up the ADAV801. Additionally, the clock source for the SPDIF transmitter can be selected from the various clock sources available in the ADAV801.

The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts the SPDIF input data stream. The DIRIN pin can be configured to accept a digital input level, as defined in the Specifications section, or an input signal with a peak-to-peak level of 200 mV minimum, as defined by the IEC60958-3 specification. DIR_LF is a loop filter pin, required by the internal PLL, which is used to recover the clock from the SPDIF data stream.

The components shown in Figure 42 form a loop filter, which integrates the current pulses from a charge pump and produces a voltage that is used to tune the VCO of the clock recovery PLL. The recovered audio data and audio clock can be routed to the different blocks of the ADAV801, as required. Figure 39 shows a conceptual diagram of the DIRIN block.

0x75

FS3

FS1

REG 0x77

BIT 0

÷2

FS2

REG 0x77

BITS 2–1

÷2

CHANNEL STATUS

PLL1

SYSCLK1

PLLINT1

PLL2

SYSCLK2

PLLINT2

SPDIF

SYSCLK3

REG 0x74 BIT 4

DIRIN

LEVEL

* EXTERNAL CAPACITOR IS REQUIRED ONLY

FOR VARIABLE LEVEL SPDIF INPUTS.

04577-0-018

COMPARATOR

SPDIF

RECEIVER

Figure 39. DIRIN Block

AND USER BITS

ADC

DIR

PLAYBACK

AUXILIARY IN

SRC

REG 0x63

BITS 2–0

DIT INPUT

DIT

Figure 40. Digital Output Transmitter Block Diagram

DIRIN

DIR

AUDIO DATA

RECOVERED CLOCK

CHANNEL STATUS/ USER BITS

Figure 41. Digital Input Receiver Block Diagram

DITOUT

04577-0-021

04577-0-019

04577-0-020

Rev. 0 | Page 23 of 56

ADAV801

(

l Dig udio tand

Seria ital A Transmission S ards

ADAV801 can receive and tra PDIF, AES/EBU

The nsmit S , and

958 serial str d,

IEC- eams. SPDIF is a consumer audio standar and AES ssional audio standard. IECboth con fessional definitions. This da

tended to f e

not in ully define or to provide a tutorial for thes

rds. Con

standa tact the international standards-setting bodies

e full specification

for th s.

e digita

All thes l audio communication schemes encode audio data and rmation using the biphas

d. This encoding me content of the

metho thod minimizes the dc

itted signal. As c in the

transm an be seen from Figure 43, 1s

al data end up with m e biphase-

origin idcell transitions in th

encoded data, while 0s in ta do not. Note

mark the original da

e biphase-mark encod a transition

that th ed s data always ha

en bit bounda

betwe ries.

2 TIMES BIT RATE)

BIPHASE-MARK

AVDD

100nF

6.8nF

Figure 42. one

3kΩ

DIR Loop Filter Comp nts

DIR BLOCK

DIR_LF

04577-0-022

/EBU is a profe 958 has

sumer and pro ta sheet is

audio control info e-mark

CLOCK

011100

DATA

Figure 43. Biphase-Mark Encoding

Digital audio-communication schemes use preambles to distinguish among channels (called subframes) and among longer-term control information blocks (called frames). Preambles are particular biphase-mark patterns, which contain encoding violations that allow the receiver to uniquely recognize them. These patterns and their relationship to frames and subframes are shown in Table 8 and Figure 44.

Table 8. Biphase-Mark Encode Preamble

Biphase Patterns Channel

X 11100010 or 00011101 Left Y 11100100 or 00011011 Right Z 11101000 or 00010111 Left and CS block start

04577-0-023

PREAMBLES

XY ZY XY

LEFT CH

RIGHT CH LEFT CH RIGHT CH LEFT CH RIGHT CH

SUB-

FRAME

FRAME 191 FRAME 0 FRAME 1

Figure 44. Preambles, Fra mes, and Su bframes

SUB-

FRAME

04577- 024

The biphase-mark encoding violations are shown in Figure 45. Note that all three preambles include encoding violations. Ordinarily, the biphase-mark en ding method results in a polarity transitionco between bit boundaries.

11100010

PREAMBLE X

11100100

PREAMBLE Y

11101000

PREAMBLE Z

04577-0-025

Figure 45. Preambles

The serial digital a rganized

udio communication scheme is o using a frame and subframe construction. There are two subframes per frame (ordinarily the left and right channel). Each subframe includes the appropriate 4-bit preamble, up to 24 bits of audio data, a validity (V) bit, a user (U) bit, a channel status (C) bit, and an even parity (P) bit. The channel status bits and the user bits accumulate over many frames to convey control information. The channel status bits accumulate over a 192 frame period (called a channel status block). The user bits accumulate over 1,176 frames when the interconnect is implementing the so-called subcode scheme (EIAJ CP-2401). Th organization of the channel status block, frames, and subframes

is shown in Table 9 and Table 10. Note that the ADAV801 supports the professional audio standard from a software point of view only. The digital interface supports only consumer mode.

Table 9. Consumer Audio Standard

Data

Address 7 6 5 4 3 2 1 0

N + 1 Category Code N + 2 Channel Number Source Number

N + 3 Reserved

N + 4 Reserved Word Length N + 5 to

(N + 23) N = 0x20 for receiver channel status buffer.

N = 0x38 for transmitter channel status buffer.

Channel

Status

Emphasis

Clock

Accuracy

Bits

Pro

Copy- Non-

right Audio

Sampling Frequency

Reserved

= 0

Rev. 0 | Page 24 of 56

ADAV801

Table 10. Professional Audio Standard

Address 7 6 5 4 3 2 1 0

N + 1 User Bit Management Channel Mode

N + 2

N + 3 Channel Identification

N + 4

N + 5 Reserved N + 6 Alphanumeric Channel Origin Data—First Character N + 7 Alphanumeric Channel Origin Data N + 8 Alphanumeric Channel Origin Data N + 9 el Origin Data—Last Character Alphanumeric Chann N + 1 lp ion Data—First Character 0 A hanumeric Channel Destinat N + 11 Alphanumeric Channel Destination Data N + 12 Alphanumeric Channel Destination Data N + 1 Al3 phanumeric Channel Destination Data—Last Character N + 14 Local Sample Address Code—LSW N + 15 Local Sample Address Code N + 16 Local Sample Address Code N + 17 Local Sample Address Code—MSW N + 18 Time of Day Code—LSW N + 19 Time of Day Code N + 20 Time of Day Code N + 21 Time of Day Code—MSW N + 22 Reliability Flags Reserved N + 23 Cyclic Redundancy Check Character (CRCC) N = 0x20 for receiver channel status buffer.

N = 0x38 for transmitter channel status buffer.

Sample

Frequency

Alignm

Level

Scal-

ing

Lock Emphasis

Source Word Length

Sample Frequency (f

Data Bits

Pro/

Non-

Con

Audio

Use of Auxiliary Mode ent

Sample Bits

)

Reserved

= 1

Digital Audio

Reference

Signal

The standards allow the channel status bits in each subframe to be independent, but ordinarily the channel status bit in the two subframes of each frame are the same. The channel status bits are defined differently for the consumer audio standards and the professional audio standards. The 192 channel status bits

are organized into 24 bytes and have the interpretations shown in Table 9 and Table 10.

The SPDIF transmitter and receiver have a comprehensive register set. The registers give the user full access to the functions of the SPDIF block, such as detecting nonaudio an

d validity bits, Q subcodes, preambles, and so on. The channel status bits as defined by the IEC60958 and AES3 specifications are stored in register buffers for ease of use. An autobuffering function allows channel status bits and user bits read by the receiver to be copied directly to the transmitter block, removing the need for user intervention.

Receiver Section

The ADAV801 uses a double-buffering scheme to handle reading channel status and user bit information. The channel status bits are available as a memory buffer, taking up 24 consecutive register locations. The user bits are read using an indirect memory addressing scheme, where the receiver user- bit indirect-address register is programmed with an offset to the

user bit buffer, and the rece to determine the user bits at that location. Reading the receiv user bit data register automatically updates the indirect address register to the next location in the buffer. Typically, the receiver user bit indirect-address register is programmed to zero (the start of the buffer), and the receiver user bit data register is repeatedly until all the buffer’s data has been read. Figure 46 an Figure 47 show how receiving the channel status bits and user bits is implemented.

DIRIN

SPDIF

RECEIVE

BUFFER

FIRST BUFFER

Figure 46. Channel Status Buffer

SPDIFIN

0...7

8...15

16...23

FIRST

BUFFER

Figure 47. Receiver User Bit Buffer

The SPDIF receive buffer is updated continuously by the incoming SPDIF stream. Once all the channel status bits f block (192 for Channel A and 192 for Channel B) are recei the bits are copied into the receiver channel status buffer. buffer stores all 384 bits of channel status information, an RxCSSWITCH t i determ es wh er the Channel A or the Channel B status bits

equi to be fer is

are r red read. The receive channel status bit buf

bytes g and

24 lon spans the address range from 0x20 to 0x37.

Because the chan change, a software T, is provided to

tify th ost co tatus

no e h ntrol that either a new block of channel s bits is available or status

formation have changed from a previous block. The function

bi n the channel status switch buffer register

in eth

nel status bits of an SPDIF stream rarely

interrupt/flag bit, RxCSBIN

that the first five bytes of channel

of the RxCSBINT is controlled by the RxBCONF3 bit in the receiver buffer configuration register.

The size of the user bit buffer can be set by programming the RxBCONF0 bit in the receiver buffer configuration register, as shown in Table 11.

iver user bit data register can be read

CHANNEL STATUS A

(24 × 8 BITS)

CHANNEL STATUS B

(24 × 8 BITS)

0...7

8...15

16...23

USER-BIT

BUFFER

SECONDBUFFER

RECEIVE CS BUFFER (0x20–0x37)

RxCSSWITCH

ADDRESS = 0x50

RECEIVER USER BIT INDIRECT ADDRESS

ADDRESS = 0x51

RECEIVER USER BIT

DATA REGISTER

04577-0-026

or the

This

d the

read

04577-0-027

ved,

Rev. 0 | Page 25 of 56

ADAV801

Table 11. RxBCONF3 Functionality

RxBCONF0 Receiver Us

0 384 bits with Preamble Z as the start of the block. 1 768 bits with Preamble Z as the start of the block.

The updating of the user bit buffer is controlled by Bits RxBCONF2–1 and Bit 7 to Bit 4 of the channel status register, as shown in Table 12 and Table 13.

Table 12. RxBCONF2–1 Functionality

RxBCONF Bit 2 Bit 1 Receiver User Bit Buffer Configuration

0 0 User bits are ignored. 0 1 Update second buffer when first buffer is full. 1 0

Format according to Byte 1, Bit 4 to Bit 7, if PRO bit is set. Format according to IEC60958-3, if PRO bit is clear.

Table 13. Automatic User Bit Configuration

Bits 7 6 5 4

Automatic Receiver User Bit Buffer Configuration

0 0 0 0 User bits are ignored. 0 1 0 0

AES-18 format: the user bit buffer is treated in the same way as when RxBCONF2–1 = 0b01.

1 0 0 0

User bit buffer is updated in the same way as when RxBCONF2–1 = 0b01 and RxBCONF0 = 0b00.

1 1 0 0

User-defined format: the user bit buffer is treated in the same way as when RxBCONF2–1 = 0b01.

When the user bit buffer has been filled, the RxUBINT interrupt bit in the interrupt status register is set, provided that the RxUBINT mask bit is set, to indicate that the buffer has new information and can

For the special ca

se when the user data is formatted according to the IEC60958-3 standard into messages made of information units, called IUs, the zeros stuffed between each IU and each message are removed and only the IUs are stored. Once the end of the message is sensed by more that eight zeros between IUs, the user bit buffer is updated with the complete messag first buffer begins looking for the start of the next message.

Each IU is stored as a byte consisting of 1, Q, R, S, T, U, V, and W bits (see the IEC60958-3 specification for more information). When 96 IUs are received, the Q subcode of the IUs is stor the Q subcode buffer, consisting of 10 bytes. The Q subcode is the Q bits taken from each of the 96 IUs. The first 10 bytes (80 bits) of the Q subcode contain information sent by CD, MD and DAT systems. The last 16 bits of the Q subcode are used to perform a CRC check of the Q subcode. If an error occurs in the CRC check of the Q subcode, the QCRCERROR bit is set. This is a sticky bit that remains high until the register is read.

er Bit Buffer Size

be read.

e and the

ed in

Transmitter Operation

The SPDIF transmitter has a similar buffer structure to th receive section. The transmitter chan

nel status buffer occupies

24 bytes of the register map. This buffer is long enough to store the 192 bits required for one channel of channel status information. Setting the TxCSSWITCH bit determines if the data loaded to the transmitter channel status buffer is intended for Channel A or Channel B. In most cases, the channel status bi

ts for Channel A and Channel B are the same, in which case setting the Tx_A/B_Same bit reads the data from the transmitter channel status buffer and transmits it on both channels.

Because the channel status information is rarely changed dur

ing transmission, the information contained in the buffer is transmitted repeatedly. The Disable_Tx_Copy bit can be used to prevent the channel status bits from being copied from the transmitter CS buffe the user has

r into the SPDIF transmitter buffer until

finished loading the buffers. This feature is typically used, if the Channel A data and Channel B data are different. Setting the bit prevents the data from being copied. Clearing th bit allows the data to be copied and then transmitted. Figure 48

shows how the buffers are organized.

DITOUT

CHANNEL

STATUS A

TRANSMIT CS BUFFER (0x38–0x4F)

TxCSSWITCH

Figure 48. Transmitter Channel Status Buffer

(24 × 8 BITS)

CHANNEL STATUS B

(24 × 8 BITS)

SPDIF

TRANSMIT

BUFFER

04577-0-028

As with the receiver section, the transmitted user bits are als double-buffered. This is required, beo cause, unlike the channel status bits, the user bits do not necessarily repeat themselves. The user bits can be buffered in various configurations, as listed in Table 14. Transmission of the user bits is determined by th

e state of the BCONF3 bit. If the bit is 0, the user bits begin transmitting right away with this bit is 1, the user bits do not start transm Z preamble occurs when the TxBCONF2–1

ble 14. Tr urations

Ta ansmitter User Bit Buffer Config

BCONF2-1

out alignment to the Z preamble. If

itting until a

bits are 01.

Bit 2 Bit 1 Transmitter User Bit Buffer Configuration

0 0 Zeros are transmitted for the user bits. 0 1 Host writes user bits to the buffer until it is full.

1 0

Writes the user bits to the buffer in IUs specified by IEC60958-3 and transmits them according to the standard.

1 1

First 10 bytes of the user-bit buffer are configured to store a Q subcode.

Rev. 0 | Page 26 of 56

ADAV801

Table 15. Transmitter User Bit Buffer Size

TxBCONF0 Buffer Size

0 384 bits with Preamble Z as the start of the block. 1 768 bits with Preamble Z as the start of the block.

By using sticky bits and interrupts, the transmit buffers can notify the host or microcontroller when the first user bit buffer has been updated and when the second transmit user bit buffer is full. The sticky bit, TxUBINT, is set when the transmit user bit buffer has been updated and the second transmit user bit buffer is ready to accept new user bits. The sticky bit, TxFBINT, is set whenever the second transmit user bit buffer is full. Any new writes to this buffer are ignored until the first transmit buffer is updated. These two bits are located in the interrupt status register. When the host reads the interrupt status register, these bits are cleared. Interrupts for the TxUBINT and TxFBINT sticky bits can be enabled by setting the TxUBMASK and TxFBMASK bits, respectively, in the interrupt status mask register.

SPDIF 0

0...7

8...15

16...23

SECOND BUFFER

04577-0-029

ADDRESS = 0x52

TRANSMITTER USER BIT

INDIRECT ADDRESS

ADDRESS = 0x53

TRANSMITTER USER BIT

DATA REGISTER

Figure 49. Transmitter User Bit Buffer

0...7

8...15

16...23

USER-BIT

BUFFER

Autobuffering

The ADAV801 SPDIF receiver and transmitter sections have an autobuffering mode allowing the channel status and user bits to be copied automatically from the receiver to the transmitter without user intervention. The channel status and user bits can be independently selected for autobuffering using the Auto_CSBits and Auto_UBits bits, respectively, in the autobuffer register. When the receiver and transmitter are running at the same sample rate, the transmitted channel status and user bits are the same as the received channel-status and user bits.

In many systems, however, it is likely that the receiver and transmitter are not running at the same frequency. When the transmitter sample rate is higher than receiver sample rate, the channel status and user bit block is sometimes repeated.

When

the transmitter sample rate is lower than the receiver sample

te, the channel status and user bit blocks might be dropped.

ecause the first five bytes of the channel status are typically

B constant, they can be repeated or dropped with no information loss. However, if the PRO bit in the channel status is set and the local sample address code and time-of-day code bytes contain

information, these bytes might be repeated or dropped, in which case information can be lost. It is up to the user to determine how to handle this case.

When the user bits are transmitted according to the IEC60 format, the messages contained in the user bits can still be without dropping

or repeating messages. Because zero-stuffing

958-3

sent

is allowed between IUs and messages, zeros can be added or subtracted to preserve the messages. When the transmitter sample rate is greater than the receiver sample rate, extra zeros are stuffed between the messages. When the sample rate of the transmitter is less than the sample rate of the receiver, the zero

stuffed between the messages are subtracted. If there are not

en the menough zeros betwe

between IUs are subt

essages to be subtracted, the zeros

racted as well. The Zero_Stuff_IU bit in the autobuffer register enables the adding or subtracting of zeros between messages.

Interrupts

The ADAV801 provides interrupt bits to indicate the presence of certain conditions that require attention. Reading the interrupt status register allows the user to determine if any of the interrupts have been asserted. The bits of the interrupt status register remain high, if set, until the register is read. Two bits, SRCError and RxError, indicate interrupt conditions in the sample rate converter and an SPDIF receiver error, respectivel

y. Both these conditions require a read of the appropriate error register to determine the exact cause of the inter

ach interrupt in the interrupt status register has an associated

rupt.

mask bit in the interrupt status mask register. The interrupt mask bit must be set for the corresponding interrupt to be generated. This feature allows the user to determine which functions should be responded to.

The dual function pin ZEROL/INT can be set to indicate the presence of no audio data on the left channel or the presence of an interrupt set in the interrupt status register. As shown in Table 16, the function of this pin is selected by the INTRPT bit in DAC Control Register 4.

Table 16. ZEROL/INT Pin Functionality

INTRPT Pin Functionality

0 Pin functions as a ZEROL flag pin. 1 Pin functions as an interrupt pin.

SERIAL DATA PORTS

The ADAV801 contains four flexible serial ports (SPORTs) to allow da independent and can be configured as master or slave ports. In slave mode, the xLRCLK and xBCLK signals are inputs to the serial ports. In master mode, the serial port generates the xLRCLK and xBCLK signals. The master clock for the SPORT can be selected from a number of sources, as shown in Figure 50.

ta transfer to and from the codec. All four SPORTs are

Rev. 0 | Page 27 of 56

ADAV801

DIR PLL (512 ×

DIR PLL (256 ×

DIR PLL (512 × DIR PLL (256 ×

REG 0x76

PLLINT1 PLLINT2

MCLKI

XIN

PLLINT1 PLLINT2

MCLKI

XIN

MCLKI

XIN PLLINT1 PLLINT2

MCLKI

XIN PLLINT1 PLLINT2

BITS 4–2

)

REG 0x76

BITS 7–5

)

REG 0x77

BITS 4–3

REG 0x76

BITS 1–0

ADC

MCLK

ICLK1 ICLK2

PLL CLOCK

DAC

MCLK

ICLK1 ICLK2

PLL CLOCK

REG 0x00

BITS 3–2

DIVIDER DIR PLL (512 × DIR PLL (256 ×

DIVIDER

REG 0x00

BITS 4–5

Figure 50. SPORT Clocking Scheme

REG 0x00

BITS 1–0 ICLK1

)

ICLK2

OUTPUT

PORT

REG 0x06 BITS 4–3

INPUT

PORT

REG 0x04 BITS 4-3

MCLK

DIVIDER

REG 0x00

BITS 1-0

SRC

OLRCLK

LKOBC

OSDATA

ILRCLK IBCLK ISDATA

04577-0-031

Care should be taken to ensure that the clock rate is appropriate

, then

le,

for whatever block is connected to the serial port. For examp if the ADC is running from the MCLKI input at 256 × f the master clock for the SPORT should also run from the MCLKI input to ensure that the C and serial port are

synchronized.

The SPORTs can be set ive data in I

to transmit or rece

S, leftjustified or right-justified formats with different word lengths by programming the appropriate bits in the playback register, auxiliary input port register, record register, and auxiliary output port-control register. Figure 51 is a timing diagram of the serial data port formats.

Clocking Scheme

The ADAV801 provides a flexible choice of on-chip and offchip clocking sources. The on-chip oscillator with dual PLLs is intended to offer complete system clocking requirements for use with available MPEG encoders, decoders, or a combination of codecs. The oscillator function is designed for generation of a 27 MHz video clock from a 27 MHz crystal connected between the XIN and XOUT pins. Capacitors must also be connected between these pins and DGND, as shown in Figure 35. The capacitor values should be specified by the crystal manufacturer. A square wave version of the crystal clock is output on the MCLKO pin. If the system has a 27 MHz clock available, this clock can be connected directly to the XIN pin.

LRCL

BCLK

SDATA

LRCL

BCLK

SDATA

LRCL

BCLK

SDATA

MSB MSB

MSB

LEFT CHANNEL RIGHT CHANNEL

LSB LSB

LEFT-JUSTIFIED MODE — 16 BITS TO 24 BITS PER CHANNEL

LEFT CHANNEL

LSB

I2S MODE — 16 BITS TO 24 BITS PER CHANNEL

LEFT CHANNEL RIGHT CHANNEL

MSB MSB

RIGHT-JUSTIFIED MODE — SELECT NUMBER OF BITS PER CHANNEL

LSB LSB

MSB

RIGHT CHANNEL

Figure 51. Serial Data Modes

LSB

04577-0-030

Rev. 0 | Page 28 of 56

ADAV801

Datapath

The ADAV801 features a digital in

put/output switching/ multiplexing matrix that gives flexibility to the range of possib input and output connections. Digital input ports include playback and auxiliary input (both 3-wire digital), and S/PDIF (single-wire to the on-chip receiver). Output port record and auxiliary

output ports (both 3-wire digital) and the

s include the

S/PDIF port (single-wire from the on-chip transmitter). Internally, the DIR and DIT are interfaced via 3-wire interfaces The datapath for each input and output port is selected by programming Datapath Control Registers 1 and 2. Figure 52 shows the internal datapath structure of the ADAV801.

PLL

ADC

REFERENCE

DAC

REGISTERS

CONTROL

OSCILLATOR

SRC

PLAYBACK

DATA

INPUT

Figure 52. Datapath

DATA

INPUT

RECORD

DATA

OUTPUT

AUX

DATA

OUTPUT

DIT

DIRAUX

04577-0-032

Rev. 0 | Page 29 of 56

ADAV801

INTERFACE CONTROL

ADAV801 has a d cated contro ort to allow access to

The edi l p the internal registers of the AD registers is ei ide. Where bits are described a (RES), d be programmed as zero.

SPI INTERF

ontrol of the ADAV8 .

C 01 is via an SPI-compatible serial port The SPI contro a 4-wire serial control port with one

ycle of data transfer c s. Figure 53 shows the

c onsisting of 16 bit

rmat of an SPI write The transfer of

fo /read of the ADAV801.

ata is initiated on the ATCH. The data

d falling edge of CL

resented on the first s ents the register

p even CCLKs repres address read/w If this bit is low, the following eight bits

f data are loaded to th provided. If this bit is

o e register address

h, a read operation is indicated. The contents of the register

hig

ess are clocked ou n on the following eight

addr t on the COUT pi

CLKs. For a read ope ts after the read/write

C ration, the data bi bits are ignored.

ght bits w s reserved

these bits shoul

ACE

l port is

rite bit.

AV801. Each of the internal

BLOCK EADS AN

R D WRITES

The ADAV801 provides the user with the ability to write to or read from a block of registers in one continuous operation. In SPI mode, the CLATCH line should be held low for longer than the 16 CCLK periods to use the block read/write mode. For a write operation, once the LSB has been clocked into the ADAV801 on the 16th CCLK, the register address as specified by the first seven bits of the write operation is incremented and the next eight bits are clocked into the next register address.

The read operation is similar. Once the LSB of a read register operation has been clocked out, the register address is incremented and the data from the next register is clocked out on the following eight CCLKs. Figure 55 and Figure 56 show the timing diagrams for the block write and read operations.

CLATCH

CCLK

CIN

COUT

CLATCH

CIN

CLATCH

D14

D15

CIN

ADDRESS [6:0] DATA [7:0]

14131211109876543210

8 BITS

R/W = 1

D8 D0

Figure 53.

SPI Serial Port Timing Diagram

R/W

re 54. SPI C orm

Figu ontrol Word F at

8 BITS 8 BITS

Figure 55. SPI Block Write Operation

DON’T CARE

8 BITS

04577-0-036

04577-0-034

04577-0-033

OUT

8 BITS 8 BITS 8 BITS 8 BITS

Figure 56. SPI Block Read Operation

Rev. 0 | Page 30 of 56

04577-0-035

ADAV801

Table 17. SRC and Clock Control Registe

SRCD SRCD CLK2 CLK2DIV0 CLK1DIV1 CLK1DIV0 MCLKSEL1 MCLKSEL0

7 6 5 4 3 2 1 0

ADDRESS = 0000000 (0x00) SRCDIV1–0

00 = SRC master clock is not divided. 01 = SRC master clock is di 10 = SRC master clock 11= SRC master clock

CLK2DIV1–0

00 = Divide by 1. 01 = Divid 10 = Divide by 2. 11 = Divide by 3.

CLK1DIV1–0

00 = Divide by 1.

11 = Divide by 3.

MCLKSEL1–0

00 loc 01 = Int 10 = PLL recovered clock (512 × f 11 = PLL recovered clock (25

IV1 IV0 DIV1

Divides the SRC master clock.

Clock divider for Internal Clock 2 (ICLK2).

e by 1.5.

Clock divider for Internal Clo

01 = Divide by 1.5. 10 = Divide by 2.

Clock for th aster clock.

selection e SRC m

= Internal C k 1.

ernal Clock 2.

Table 18. SPDIF Loop

RES RES

7 6 5 4 3 2 1 0

ADDRESS = 0000011 (0x03) TxMUX

0 = SPDIF transmitter, normal mode. 1 = DIRIN, loopback mode.

back Control Register

Selects the source for SPDIF output (DITOUT).

Table 19. Playback Port Control Register

7 6 5 4 3 2 1 0

ADDRESS = 0000100 (0x04) CLKSRC1–0

00 = Input port is a slave. 01 = Recovered PLL clock. 10 = Internal Clock 1. 11 = Internal Clock 2.

SPMODE2–0

000 = Left-justified. 001 = I 100 = 24-bit, right-justified. 101 = 20-bit, right-justified. 110 = 18-bit, right-justified. 111 = 16-bit, right-justified.

Selects the clock source for generating the ILRCLK and IBCLK.

Selects the serial format of the playback port.

vided by 1.5.

is divided by 2.

is divided by 3.

ck 1 (ICLK1).

6 × f

RES RES RES RES RES TxMUX

CLKSRC0 SPMODE2 SPMODE1 SPMODE0 RES RES RES CLKSRC1

Rev. 0 | Page 31 of 56

ADAV801

Table 20. Auxiliary Input Port Register

RES RES RES CLKSRC1 CLKSRC0 SPMODE SPMODE1 SPMODE0

7 6 5 4 3 2 1 0

ADDRESS = 0000101 (0x05) CLKSRC1–0

00 = Input port is a slave. 01 = Recovered PLL cock. 10 = Internal Clock 1. 11 = Internal Clock 2.

SPMODE2–0

000 = Left-jus 001 = I 100 = 24-bit, 101 = 20-bit, 110 = 18-bit, right-justified. 111 = 16-bit, right-j

Selects the clock source for generating the IAUXLRCLK and IAUXBCLK.

Selects the serial format of auxiliary inp

tified.

right-justified. right-justified.

ustified.

ut port.

Table 21. Record Por

RES RES CLKSRC1 CLKSRC0 WLEN1 WLEN0 SPMODE1 SPMODE0

7 6 5 4 3 2 1 0

ADDRESS = 0000110 (0x06) CLKSRC1–0

00 = Record port is a slave. 01 = Re 10 = Internal Clock 1. 11 = Internal C

WLEN1–0

00 = 24 bits. 01 = 20 bits. 10 = 18 bits. 11 = 16 bits.

SPMODE1–0

00 = Left-justified.

10 = Reserved. 11 = Right-justified.

t Control Register

Selects the clock source for gen RCLK and OBCLK. erating the OL

covered PLL clock.

lock 2.

Selects the seria

Selects the serial format of the

01 = I

l output word length.

record port.

Rev. 0 | Page 32 of 56

ADAV801

Table 22. Auxiliary Output Port Register

RES CLKSR KSRC0 WLEN WLEN DE1 SP

7 6 5 4 3 2 1 0

ADDRESS = 0000111 (0x07) CLKSRC1–0

WLEN1–0

01 = 20 bits. 10 = 18 bits. 11 = 16 bits.

SPMODE1–0

01 = I 10 = Reserved. 11 = Right-justified.

Selects the clock source for generating the OAUXLRCLK and OAUXB 00 = Auxiliary record port is a slave. 01 = Recovered PLL clock. 10 = Internal Clock 1. 11 = Internal Clock 2. Selects the serial output word length. 00 = 24 bits.

Selects the serial format of the auxiliary r 00 = Left-justified.

Table 23. Group Dela

MUTE_SRC

7 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0001000 (0x08) MUTE_SRC

0 = No mute. 1 = Soft-mute. GRPDLY6–0 Adds dela t sam 00 lay 000000 0000010 = 2 sample delay. 1111110 = 126 sample delay. 1111111 = 127 sample delay.

y and Mute Register

Soft-mutes the output of the sample rate converter.

00000 = No de .

RES C1 CL 1 0 SPMO MODE0

CLK.

ecord port.

GRPDLY6–0

y to the sample rate converter FIR filter by GRPDLY6–0 inpu ples.

1 = 1 sample delay.

Rev. 0 | Page 33 of 56

ADAV801

Table 24. Receiver Configuration 1 Register

NOCL 0 TO_ DEEMPH ERR1–0 LOCK1–0

7 6, 5 4 3, 2 1, 0

ADDRESS = 0001001 (0x09) NOCLOCK

1 = ICLK1 is used.

RxCLK1–0

00 = RxCLK is a 128 × f

11 = Reserved.

AUTO_DEEM

0 = Automatic de-emphasis is disabled. 1 = Automatic de-emphasis is enabled.

ERR1–0

OCK1–0

00 = No action is taken. 01 = Last valid sample is held. 10 = Zeros are sent out after the last valid sample. 11 = Soft-mute of the last valid audio sample.

Table 25. Receiver Co ration 2 Register

RxMUTE L 1–0

7 6 5, 4 3 2 1 0

ADDRESS = 0001010 (0x0A) RxMUTE

0 = AES3/SPDIF receiver is not muted. 1 = AES3/SPDIF receiver is muted.

SP_PLL

0 = Left/right clock generated from the A 1 = Left/right clock from one of the serial

SP_PLL_SEL1–0

00 = Playback port is selected. 01 = Auxiliary input port is selected. 10 = Record port is selected.

NONAUDIO

0 = AES3/SPDIF receiver data is sent to

NO_VALIDITY

1 = Data from the AES3/SPDIF receiver is not allowed into the SRC, if the VALIDITY bit is set.

OCK RxCLK1– AU

Selects the source of the receiver clock when the PLL is not locked. 0 = Recovered PLL clock is used.

Determines the oversampling ratio of the recovered receiver clock.

recovered clock.

01 = RxCLK is a 256 10 = RxCLK is a 512 × f

Automatically de-emphasizes the d

Defines what action the receiver 00 = No action is taken. 01 = Last valid sample is held. 10 = Invalid sample is replaced with zeros. 11 = Reserved. Defines what ac

× f

recovered clock.

recovered

tion the receiver should take, if the PLL loses lock.

clock.

ata from the receiver based on the channel status information.

should take, if the receiver detects a parity or biphase error.

nfigu

SP_PL SP_PLL_ SEL RES RES NO NONAUDIO NO_VALIDITY

Hard-mutes the audio output for the AES3/SPDIF receiver.

AES3/SPDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock.

ES3/SPDIF preambles is the reference clock to the PLL.

ports is the reference clock to the PLL.

Selects one of the four serial ports as the

11 = Auxiliary output port is selected. When the NONAUDIO bit is set, data from the AES3/SPDIF receiv

(SRC). If the NO the AES3/SPDIF

1 = Data from the AES3/SPDIF receiver i When the VALIDITY bit is set, data from 0 = AES3/SPDIF receiver data is sent to the SRC.

NAUDIO data is due to DTS, AAC, and so on, as d

receiver is not allowed into the SRC regardless of the state of this bit.

reference clock to the PLL when SP_PLL is set.

er is not allowed into the sample rate converter

efined by the IEC61937 standard, then the data from

the SRC.

s not allowed into the SRC, if the NONAUDIO bit is set.

the AES3/SPDIF receiver is not allowed into the SRC.

Rev. 0 | Page 34 of 56

ADAV801

Table 26. Receiver Buffer Configuration Register

RES RxBCON RxBCO CONF2–1

7 6 5 4 3 2, 1 0

ADDRESS = 0001011 (0x0B) RxBCONF5

0 = User bit interrupt is enabled in normal mode. 1 =

RxBCONF4

0 = User bits are stored together. 1 = User bits are stored separately.

RxBCONF3

0 = RxCSBINT are set when a new block of r

RxBCONF2–1

00 = User bits ar

11 = Reserved.

xBCONF0

0 = 384 bits with Preamble Z as the sta 1 = 76 its wit eamble Z as the rt of the buffer.

If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit interrupt is

If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit.

This bit de between A

Defines the function of RxCSBINT.

1 = RxCSBINT is set only if the first five bytes status block.

Defines the user bit buffer.

01 = Updates the second user bit buffer when the first user bit buffer is full. 10 = Formats the received user bits according to Byte 1, Bit 4 to Bit 7, of the channel status, if the PRO bit is set. If the

PRO bit is not set, formats the user bits according to the

Defines the user bit buffer size, if RxBCONF2–1 = 01.

8 b h Pr st

Table 27. Transmitter Control Register

RES TxVALIDITY TxRATIO2–0 TxCLKSEL1–0 TxENABLE

7 6 5, 4, 3 2, 1 0

ADDRESS = 0001100 (0x0C) TxVALIDITY

0 = Audio is suitable for D/A conversion. 1 = Audio is not suitable for D/A conversion.

TxRATIO2–0

000 = Transmitter to receiver ratio is 1:1. 001 = Transmitter to receiver ratio is 1:2. 010 = Transmitter to receiver ratio is 1:4. 101 = Transmitter to receiver ratio is 2:1. 110 = Transmitter to receiver ratio is 4:1.

TxCLKSEL1–0

10 = Recovered PLL clock is the clock sour 11 = Reserved.

TxENABLE

0 = AES 1 = AES3/SPDIF transmitter is enabled.

This bit is used to set or clear the VALIDITY bit in the AES3/SPDIF transmit stream.

Determines the AES3/SPDIF transmitter to AES3/SPDIF receiver ratio.

Selects the clock source for the AES3/SPDIF transmitter. 00 = Internal Clock 1 is the cl 01 = Internal Clock 2 is the clock source for the transmitter.

Enables the AES3/SPDIF transmitter.

3/SPDIF transmitter is disabled.

RES F5 RxBCONF4 NF3 RxB RxBCONF0

enabled only when there is a change in the start (ID) bit.

termines whether Channel A and Channel B user bits are stored in the buffer together or separated

and B.

eceiver channel status is read, which is 192 audio frames.

of the receiver channel status block changes from the previous channel

e ignored.

IEC60958-3 standard.

rt of the buffer.

ock source for the transmitter.

ce for the transmitter.

Rev. 0 | Page 35 of 56

ADAV801

Table 28. Transmitter Buffer Configuration Register

IU_Zeros3–0

7, 6, 5, 4 3 2, 1 0

ADDRESS = 0001101 (0x0D) IU_Zeros3–0

0000 = 0. 0001 = 1. … 01 1000 =

TxBCONF3

0 = User bits are stored together. 1 = User bits are stored separately.

TxBCONF2–1

00 = Zeros are transmitted for the u 01 = Transmitter user bit buffer 10 = User bits are written to the transmit buffer in IUs specified by the IEC60958-3 standard. 11 = Reserved. TxBCONF0 Determines the buffer size of the transmit 0 = 384 bits with Preamble Z as the start of the buffer. 1 = 768 bit

Determines the number of zeros to be stuffed between IUs in a message up to a maximum of 8.

11 = 7.

Transmitter user bits can be stored in separate buffers or stored together.

Configures the transmitter user bit buffer.

s with Preamble Z as the start of the buffer.

Table 29. Channel Status Switch Buffer and Transmitter

7 6 5 4 3 2 1 0

ADDRESS = 0001110 (0x0E) Tx_A/B_Same

Disable_Tx_Copy

TxCSSWITCH

RxCSSWITCH

0 = 24-byte Receiver Channel Status A buffer can be accessed at address locations 0x20 through 0x37.

Transmitter Channel Status A and B a

s the data into t

place he Channel Status B buffer. 0 = Channel status for A and B are separate.

nnel status for A and B are the same.

1 = Cha Disables the copying of the channel status bits from the tra

buffer. 0 = Copying transmitter channel status is enabled. 1 = Copying transmitter channel sta Toggle switch for the transmit 0 = 24-byte Transm 1 = 24-b Toggle switch for the receive channel status buffer.

1 = 24-byte Receiver Channel Status B buffer can be accessed at address locations 0x20 through 0x37.

yte Transmitter Channel Status B buffer can be accessed at address locations 0x38 through 0x4F.

itter Channel Status A buffer can be accessed at address locations 0x38 through 0x4F.

Table 30. Transmitte t Significant Byte r Message Zeros M

MSBZe

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0001111 (0x0F) MSBZeros7–0

ros7–0

Most significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x00.

TxBCONF3 TxBCONF2–1 TxBCONF0

ser bits.

size is configured according to TxBCONF0.

ter user bits when TxBCONF2–1 is 01.

Disable_Tx_Copy RES RES TxCSSWITCH RxCSSWITCH RES RES Tx_A/B_Same

re the same. The transmitter reads only from the Channel Status A buffer and

nsmitter channel status buffer to the SPDIF transmitter

tus is disabled.

channel status buffer.

Rev. 0 | Page 36 of 56

ADAV801

icant Byte Table 31. Transmitter Message Zeros Least Signif

LSBZeros7–0

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010000 (0x10) LSBZeros7–0

able 32. Autobuffer Register

RES Zero_

7 6 5 4 3, 2, 1, 0

ADDRESS = 0010001 (0x11) Zero_Stuff_IU

Auto_UBits

Auto_CSBits

0 = Channel status bit 1 = Channel status

IU_Zeros3–0

0000 = 0.

1000 = 8.

Table e Ratio MSB egister (Re Only)

33. Sample Rat R ad

RES

7 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010010 (0x12) SRCRATIO14–08

Table 34. Sam

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010011 (0x13) SRCRATIO07–00

ple Rate Ratio LSB Register (Read Only)

Table 35. Preamble-C

PRE_C15–PRE_C08

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010100 (0x14) PRE_C15–08

Least significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x09.

Stuff_IU Auto_UBits Auto_CSBits IU_Zeros3–0

Enables the addition or subtract 0 = No zeros added or subtracted. 1 = Zeros can be added or subtracted between IUs. Enables the user bits to be autobuffered 0 = User bits are not autobuffered. 1 = User bits are autobuffered. Enables the channel status bi

s are not autobuffered.

bits are autobuffered.

maximum number of zero-stuffing to be added between IUs while autobuffering up to a maximum of 8.

Sets the

0001 = 1. … 0111 = 7.

SRCRATIO14–SRCRATIO08

Seven most significant bits of the15-bit sample rate ratio.

SRCRATIO07–SRCRATIO00

Eight least significant bits of the15-bit sample rate ratio.

ion of zeros between IUs during autobuffering of the user bits in IEC60958-3 format.

between the AES3/SPDIF receiver and transmitter.

ts to be autobuffered between the AES3/SPDIF receiver and transmitter.

MSB Register (Read Only)

Eight most significant bits of the 16-bit Preamble-C, when nonaudio data is detected according to the IEC60937 standard; otherwise, bits show zeros.

Rev. 0 | Page 37 of 56

ADAV801

Table 36. Preamble-C LSB Register (Rea

PRE_C07–PRE_C00

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010101 (0x15) PRE_C07–00

Eight least signif nt bits of th -bit Preamb -C, when nonaudio data is detected according to the IEC60937

d; otherwise, bits show zeros.

standar

Table 37. Preamble-D MPRSB Register (Read Only)

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010110 (0x16) PRE_D15–08

E_D15–PRE_D08

Ei nonaudio data is detected according to the IEC60937

ght most significant bits of the 16-bit Preamble-D, when

st nonaudio is used, this becomes the eight most significant bits

andard; otherwise, bits show zeros. When subframe

the 16-bit Preamble-C of Channel B.

Table 38. Preamble-D LSB Register (Read Only)

PRE_D07–PRE_D00

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010111 (0x17)

Ei mble-D, when nonaudio data is detected according to the IEC60937

PRE_D07–00

ght least significant bits of the 16-bit Prea standard; otherwise, bits becomes the eight most significant bits of

the 16-bit Preamble-C of Channel B.

Table 39. Receiver Erro

Validity Emphasis NonAudio

7 3 2 1 0 6 5 4

ADDRESS = 0011000 (0x18) RxValidity Emphasis

NonAudio

nAudio

No Preamble

CRCError

NoStream

BiPhase/Parity

Lock

r Register (Read Only)

is is the VALIDITY bit in the AES3 rece

Th ived stream. This bit is set, if the audio data is pre-emphasized. Once it has been read, it remains high and does not generate an

interrupt unless it changes state. This bit is set, when Channel Status Bit 1 (n

upt unle data bec audio or pe of no ha

interr ss the omes the ty naudio data c nges.

is bit is set, e audio da s nonaudio due to the det ion of a pream . The nonau preamble type register

Th if th ta i ect ble dio indicate unless it changes state.

This bit is the error flag for the channel status CRCError check. This bit does not clear until the receiver error regi is read.

This bit is set, if there is no AES3/SPDIF stream present at the AES3/SPDIF receiver. Once read, it remains high and does not generate an interrupt unless it changes state.

This bit is set, if a biphase or parity error occurred in the AES3/SPDIF stream. This bit is not cleared until the register is read.

This bit is set, if the PLL has locked or cleared when the PLL loses lock. Once read, it remains in its state and does not generate an interrupt unless it changes state.

s what type of preamble was detected. Once read, it remains in its state and does not generate an interrupt

d Only)

ica e 16 le

show zeros. When subframe nonaudio is used, this

NonAudio Pre

onaudio) is set. Once it has been read, it does not generate another

amble

CRCError NoStream BiPhase/ Parity Lock

ster

Rev. 0 | Page 38 of 56

ADAV801

Table 40. Receiver Error Mask Register

N udio

onA

RxValid Emphasis

Mask

7 6 5 4 3 2 1 0

ADDRESS = 0011001 (0x19) RxValidity Mask

0 = RxValidity bit does not generate an interrupt. 1 = RxValidity bit generates an interrupt.

Emphasis Mask

0 = Emphasis bit does not generate an interrupt. 1 = Emphasis bit generates an interrupt.

NonAudio Mas

NonAudio Preamble Mask

rat pt. 1 = N

CRCError M

1 = CRCError bit generates an interrupt.

NoStream Mask

0 = NoStream bit does not generate an interrupt. 1 = NoStream bit generates an interrupt.

BiPhase/Parity Mask

0 = BiPhase/Parity bit does not generate an interrupt.

Lock Mask

ask

Masks the RxValidity bit from gene

Masks the emphasis bit from generating an in

Masks the NonAudio bit from generating 0 = NonAudio bit does not generate an interrupt. 1 = NonAudio bit generates an interrupt. Masks the No

0 = NonAudio preamble bit does not gene e an interru

Masks the CRCError bit from generating an interrupt. 0 = CRCError bit does not generate an interrupt.

Masks the NoStream bit from generating an interrupt.

Masks the BiPhase/Parity bit from generating

1 = BiPhase/Parity bit generates an interrupt. Masks the Lock bit from generating an interrupt. 0 = Lock bit does not generate an interrupt. 1 = Lock bit generates an interrupt.

ity No

Mask

nAudio preamble bit from generating an interrupt.

onAudio preamble bit generates an interrupt.

nAudio

Mask

rating an interrupt.

an interrupt.

Preamble Mask

terrupt.

an interrupt.

CRCError Mask

Stream

Mask

Table 41. Sample Rate Co

7 6 5 4 3 2 1 0

ADDRESS = 0011010 (0x1A) TOO_SLOW

OVRL

OVRR

MUTE_IND

nverter Error Register (Read Only)

RES RES RES RES TOO_SLOW OVRL OVRR MUTE_IND

This bit is set, when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the internal convolution.

This bit is set, when the left output data of the sample rate converter has gone over the full-scale range and has been clipped. This bit is not cleared until the register is read.

This bit is set, when the right output data of the sample rate converter has gone over the full-scale range and has been clipped. This bit is not cleared until the register is read.

Mute indicated. This bit is set, when the SRC is in fast mode and clicks or pops can be heard in the SRC output data. The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state and does not generate an interrupt until it has changed state.

BiPhas Parity Mask Lock Mask

Rev. 0 | Page 39 of 56

ADAV801

Table 42. Sample Rate Converter Error Ma

RES RES RES RES OVRL Mask sk E_

7 6 3 2 0 5 4 1

ADDRESS = 0011011 (0x1B) OVRL Mask

0 = OVRL bit does not generate an interrupt. 1 = OVRL bit generates an interrupt.

OVRR Mask

0 = OVRR bit does not generate an interrupt. 1 = OVRR bit generates an interrupt. Reserved.

MUTE_IND M

0 = MUTE_IND bit does not generate an interrupt. 1 = MUTE_IND bit generates an interrupt.

ASK

RES OVRR Ma MUT IND MASK

he OVRL from generating an interrupt.

Masks t

Masks the OVRR from generating an interrupt.

Masks the MUTE_IND from generating an

Table 43. Interrupt St

SRCError TxCSTINT TxUBINT

7 6 5 4 3 2 1 0

ADDRESS = 0011100 (0x1C) SRCError

TxCSTINT

TxUBINT TxCSINT

RxCSDIFF

RxUBINT

RxCSBIN

RxERROR

atus Register

This bit is set, if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample rate converter error register. This bit remains hi

This bit is set, if a write to the transmitter channel status buffer was made while transmitter channel status bits were being copied from the transmitter CS buf

This bit is set, if the SPDIF transmit buffer is empty. T This bit is set, if the transmitter channel status b

high until the interrupt status register is read. This bit is set, if the receiver Channel Status A block is different from the re

remains high until read, but does not generate an interrupt. This bit is set, if the rec

status register is read.

it is set, if block of c tus is rea O 0, or if the s when

This b a new hannel sta d when RxBC NF3 = channel status ha changed

BCONF3 = 1. is bit remains gh until the interrupt status register is read.

Rx Th hi

is set, if one of the AES3/SPDIF receiver interrupts is asserted, and the host should immediately read the

This bit receiver error register. This bit rema

sk Register

interrupt.

TxCSINT RxCSDIFF RxUBINT RxCSBINT RxERROR

gh until the interrupt status register is read.

fer to the SPDIF transmit buffer.

his bit remains high until the interrupt status register is read.

it buffer has transmitted its block of channel status. This bit remains

ceiver Channel Status B clock. This bit

eiver user bit buffer has a new block or message. This bit remains high until the interrupt

ins high until the interrupt status register is read.

Rev. 0 | Page 40 of 56

ADAV801

Table 44. Interrupt Status Mask Register

SRCError T

7 6 5 4 3 2 1 0

ADDRESS = 0011101 (0x1D) SRCError Mask

0 = SRCError bit does not generate an interrupt. 1 = SRCError bit generates

TxCSTINT Mas

0 = TxCSTINT bit d 1 = TxCSTINT bit generates a

TxUBINT M

TxCSBINT Mask

RxUBINT Mask

0 = RxU 1 = RxUBINT bit generates an interrupt.

xCSBINT Mask

0 = RxCSBINT bit does not ge 1 = RxCSBINT bit generates an

RxError Mask

0 = RxError bit doe 1 = RxE

ask

Mask Ma

Masks the SRCError bit from generating an interrupt.

Masks the TxCST

Masks the TxUBINT bit from generating an interrupt. 0 = TxUBINT bit does not generate an interrupt. 1 = TxUBINT bit generates an interrupt. Masks the TxCSBINT bit from generating an inte 0 = TxCSBINT bit does not generate an inte 1 = TxCSBINT bit generates an i Masks the RxUBIN

BINT bit does not generate an interrupt.

Masks the RxCSBINT bit from generating an interrupt.

Masks the RxError bit from gene

rror bit generates an interrupt.

xCSTINT

INT bit from generating an interrupt.

oes not generate an interrupt.

T bit from generating an interrupt.

s not generate an interrupt.

able 45. Mute and De-Emphasis Register

RES RES TxMUTE

7 6 5 4 3 2, 1 0

ADDRESS = 0011110 (0x1E) TxMUTE

SRC_DEEM1–0

00 = No de-emphasis. 01 = 32 kHz de-emphasis. 10 = 44.1 kHz de-e 11 = 48

Mutes the AES3 0 = Transmitter is not muted. 1 = Transmitter is muted. Selects the de-emphasis filter for the input data to the sample rate converter.

kHz de-emphasis.

/SPDIF transmitter.

mphasis.

Table 46. NonAudio Preambl

RES RES RES

7 6 5 4 3 2 1 0

ADDRESS = 0011111 (0x1F) DTS-CD Preamble NonAudio Frame

NonAu

dio

Subfra

me_A

onAudio

Subframe_B

e Type Register (Read Only)

bit is set, if the DTS-CD preamble is detected.

This This bit is set, if the data received through the AES3/SPDIF receiver is nonaudio data according to the IEC61937

standard or nonaudio data according to SMPTE337M. This bit is set, if the data received through Channel A of the AES3/SPDIF receiver is

according to SMPTE337M. This bit is set, if the data received through Channel B of the AES3/SPDIF receiver is subframe nonaudio data

according to SMPTE337M.

TxUBINT Mask

an interrupt.

n interrupt.

nterrupt.

nerate an interrupt.

nterrupt.

rating an interrupt.

TxCSBINT Mask RES

rrupt.

RES RES SRC_DEEM1–0 RES

DTS-CD

RES

Preamble

RxUBINT Mask

NonAudio Frame

RxCSBINT Mask

NonAudio Subframe_A

subframe nonaudio data

RxError Mask

NonAudio Subframe_B

Rev. 0 | Page 41 of 56

ADAV801

Table 47. Receiver Channel S

B7–RC

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS 000 to 01 (0x20 to= 0100 10111 0x37) RCSB7–0

Table 48. T ter Ch tus Bu

B7–TCS

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS to 10 38 to= 0111000 01111 (0x 0x4F) TCSB7–0

ransmit annel Sta ffer

Table 49. Receiver User Bit Buffer Indire ess Regi

ADDRESS = 1010000 (0x50) RxUBADDR07–00

RxUBADDR07–RxUBADDR00

7, 6, 5, 4, 3, 2, 1, 0

Indirect address pointi e addre tion in t iver use ffer.

Table 50. Receiver Us

ADDRESS = 1010001 (0x51) RxUBDATA07–00

Table 51. Transmitte Indirect Address Register

TxUBADDR07–TxU

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 1010010 (0x52) TxUBADDR07–00

r User Bit Buffer

Table 52. Transmitter User Bit Buffer

ADDRESS = 1010011 (0x53) TxUBDATA07–00

Table 53. Q Subcode CRCError Status Register (Read-Only)

RES RES RES RES RES RES QCRCERROR QSUB

7 6 5 4 3 2 1 0

ADDRESS = 1010100 (0x54) QCRCERROR

QSUB

tatus Buffer

RCS SB0

The 24-byte receiver channel status buffer. The PRO b d at ad tion 0 This bu d only if the channel status is not autob betwee ceiver an mitter.

TCS B0

The 24-byte transmi el stat The PR tored a location 0x38, Bit 0. This buffer is disa autob etwee iver and transmitter is

bled when uffering b n the rece enabled.

tter chann us buffer. O bit is s t address

uffered n the re d trans

it is store dress loca x20, Bit 0. ffer is rea

ct Addr ster

ng to th ss loca he rece r bit bu

er Bit Buffer Data Register

RxUBDATA

7, 6, 5, 4, 3, 2, 1, 0

A read from this r

00. This buffer can be written to when autobuff

Indirect add

07–RxUBDATA00

egister reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR07–

ering of the user bits is enabled; otherwise, it is a read-only buffer.

BADDR00

ress pointing to the address location in the transmitter user bit buffer.

Data Register

TxUBDATA

7, 6, 5, 4, 3, 2, 1, 0

A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR07–00. When user bit autobuffering is enabled, this buffer is disabled.

This bit is set, if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This bit is cleared once the register is read.

This bit is set, if a Q subcode has been read into the Q subcode buffer (see Table 54).

07–TxUB

DATA00

Rev. 0 | Page 42 of 56

ADAV801

Table 54. Q Subcode Buffer

s Bit 7 it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bi

Addres B 1 t 0

0x55 Address Address Address ss Control Control Control Control Addre 0x56

0x57 Index Index Index Index Index Index Index Index 0x58 Minute te Minute Minute Minute Minute Minute Minute Minu 0x59 Second Second Second Second Second Second Second Second 0x5A Frame Frame Frame Frame Frame Frame Frame Frame 0x5B Zero Zero Zero Zero Zero Zero Zero Zero 0x5C

0x5D

0x5E

Table 55. Datapath Control Register 1

SRC1 SRC0 REC2 REC1 REC0 AUXO2 AUXO1 AUXO0

7 6 5 4 3 2 1 0

ADDRESS = 1100010 (0x62) SRC1–0

REC2–0

AUXO2–0

000 = ADC. 001 = DIR. 010 = Playback. 011 = Auxiliary in. 100 = SRC.

Track Tra number

Absolute minute minute

Absolute second

Absolute frame

ck Track Track

Absolute Absolute minute

te Absolute

Absolu

second Absolute

frame

auxiliary output port.

second Absolute

frame

Datapath source select for sample rate converter (SRC). 00 = ADC. 01 = DIR. 10 = Playback. 11 = Auxiliary in. Datapath source select for record output port. 000 = ADC. 001 = DIR. 010 = Playback. 011 = Auxiliary in 100 = SRC. Datapath source select for

number

Absolute minute

Absolute second

Absolute frame

Track number

Absolute minute

Absolute second

Absolute frame

Track number

Absolute minute

Absolute second

Absolute frame

Track number

Absolute minute

Absolute second

Absolute frame

Track number number number

Absolute minute

Absolute second

Absolute frame

Rev. 0 | Page 43 of 56

ADAV801

Table 56. Datapath Control Registe

RES RES DAC2 DAC1

7 6 5 4 3 2 1 0

ADDRESS = 1100011 (0x63) DAC2–0

DIT2–0

000 = ADC. 001 = DIR. 010 = Playback. 011 = Auxiliary in. 100 = SRC.

Datapath source select for DAC. 00 = ADC. 01 = DIR. 10 = Playback. 11 = Auxiliary in. 100 = SRC. Datapath source select for D

Table 57. DAC Contr

DR_ALL

7 6 5 4 3 2 1 0

ADDRESS = 1100100 (0x64) DR_ALL

0 = Normal, output pins go to V

DR_DIG

CHSEL1–0

00 = Norma 01 = Both ri 10 = Both left. 11 = Swapped,

POL1–0

01 = Left nega 10 gative. 11 = Both negative.

MUTER

0 = Normal. 1 = Mute.

MUTEL

0 = Normal. 1 = Mute.

ol Register 1

Hard reset a wer-downnd po .

1 = Har

DAC digital reset. 0 = Normal. 1 = Reset all DAC channel select.

DAC channel 00 = Both positive.

= Right ne

Mute rig

Mute left channel.

r 2

DAC0 DIT2 DIT1 DIT0

IT.

DR_DIG CHSEL1 CHSEL0 POL1 POL0 MUTER MUTEL

level.

REF

d reset and low power, output pins go to AGND.

except registers.

l, left-right.

ght.

right-left.

polarity.

tive.

ht channel.

Rev. 0 | Page 44 of 56

ADAV801

Table 58. DAC Control Register 2

RES RES DMCLK1 DMCLK0 DFS1 DFS0 DEEM1 DEEM0

7 6 5 4 3 2 1 0

ADDRESS = 1100101 (0x65) DMCLK1–0

DAC MCLK divider. 00 = MCLK. 01 = MCLK/1.5. 10 = MCLK/2. 11 = MCLK/3.

CLK

elect.

DFS1–0

DAC interpolator s 00 = 8 × (M = 256 × f 01 =

EEM1–0

= 4 × (MCLK 128 × f

(MCLK = 64 × f

10 = 2 ×

11 = Reserved.

DAC de-emphasis s

00 = None.

01 = 44.1 kHz.

10 = 32 kHz.

11 = 48 kHz.

Table 59. DAC Contr Register 3

RES

RES RES RES RES ZFVOL ZFDATA ZFPOL

7 4 3 2 1 0 6 5

ADDRESS = 1100110 (0x66) ZFVOL

ZFDATA

ZFPOL

DAC zero flag on mute and zero volume. 0

= Enabled. 1 = Disabled. DAC zero flag on zero data

disable. 0 = Enabled. 1 = Disabled. DAC zero f

= Active high.

= Active low.

lag polarity.

Table 60. DAC Contr

ol Register 4

RES INTRPT ZEROSEL1 ZEROSEL0 RES RES RES RES

7 6 5 4 3 2 1 0

ADDRESS = 1100111 (0x67) INTRPT

This bit selects th unctionality the ZEROL/ pin. e f of INT 0 = Pin functions as a ZEROL flag pin. = Pin functions as an interrupt p

ZEROSEL1–0

0 = Pin is asserted w 1 = Pin is asserted when both the left and

1 in.

T lity of the ZEROR pin when the ZEROL/INT pin is used as an interrupt.

hese bits control the functiona 00 = Pin functions as a ZEROR flag pin. 01 = Pin functions as a ZEROL flag pin. 1 hen either the left or right channel is zero. 1 right channels are zero.

Rev. 0 | Page 45 of 56

ADAV801

Table 61. DAC Left Volume Register

DVO DVOLL6 DVOLL DVOLL DVOLL DVOLL DVOLL DVOLL

7 6 5 4 3 2 1 0

ADDRESS = 1101000 (0x68) DVOLL7–0

Table 62. DAC Right Volume Register

7 6 5 4 3 2 1 0

ADDRESS = 1101001 (0x69) DVOLR7–0

1111111 = 0 dBFS. 1111110 = −0.375 dBFS. 0000000 = −95.625 dBFS.

Table 63. DAC Left P

RES RES

7 6 5 4 3 2 1 0

ADDRESS = 1101010 (0x6A) DLP5–0

000000 = 0 dBFS. 000001 = −1 dBFS. 111111 = −63 dBFS

Table 64. DAC Right Peak Volume Register

7 6 5 4 3 2 1 0

ADDRESS = 1101011 (0x6B) DRP5–0

000000 = 0 dBFS.

Table 65. ADC Left Chan ter

RES RES

7 6 5 4 3 2 1 0

ADDRESS = 1101100 (0x6C) AGL5–0

000000 = 0 dB. 000001 = 0.5 dB. … 101111 = 23.5 dB. 110000 = 24 dB. … 111111 = 24 dB.

LL7 5 4 3 2 1 0

DAC left channel volume control 1111111 = 0 dBFS. 1111110 = −0.375 dBFS.

0000 = −95.625 dBFS.

000

LR7 DVOLR6 DVOLR5 DVOLR4 DVOLR3 DVOLR2 DVOLR1 DVOLR0 DVO

DAC right cha

nnel volume control.

eak Volume Register

DLP5 DLP4 DLP3 DLP2 DLP1 DLP0

DAC left channel peak volume detection.

DRP5 DRP4 DRP3 DRP2 DRP1 DRP0 RES RES

DAC right channel peak volume detection.

000001 = −1 dBFS. 111111 = −6

3 dBFS.

nel PGA Gain Regis

AGL5 AGL4 AGL3 AGL2 AGL1 AGL0

PGA left channel gain control.

Rev. 0 | Page 46 of 56

ADAV801

Table 66. ADC Right Channel PGA

RES RES AGR5 AGR4 AGR3 AGR2 AGR1 AGR0

7 6 5 4 3 2 1 0

ADDRESS = 1101101 (0x6D) AGR5–0

000000 = 0 dB. 000001 = 0.5 dB. … 101111 = 23.5 dB. 110000 = 24 dB. … 111111 = 24 dB.

PGA right channel gain control.

Table 67. ADC Control Register 1

AMC HPF PWRDWN ANA_PD MUTER MUTEL PLPD PRPD

7 6 5 4 3 2 1 0

ADDRESS = 1101110 (0x6E) AMC

0 = ADC MCLK/2 (128 × fS). 1 = ADC MCLK/4 (64 × f

HPF

0 = Normal.

PWRDWN

0 = Norma ow

ANA_PD

UTER

MUTEL

1 = Muted.

PLPD

0 = N 1 = w

PRPD

0 = Normal. 1 = Power-down.

ADC modulator clock.

High-pass filter enable.

1 = HPF enabled. ADC power-down.

1 = Power-d n. ADC analog sect 0 = Normal. 1 = Power-down. Mute ADC right channel. 0 = Normal. 1 = Muted. Mute ADC left channel. 0 = Normal.

PGA left power-down.

ormal.

Po er-dow

PGA rig

Gain Register

ion po

ht power-down.

wer-down.

Rev. 0 | Page 47 of 56

ADAV801

Table 68. ADC Control Register 2

RES RES ES UF_PD RES RES MCD1 MCD0

7 6 5 4 3 2 1 0

ADDRESS = 1101111 (0x6F) BUF_PD

0 = Normal. n.

MCD1–0

00 = Divide by 1. 01 = Divide by 2. 10 = Divide by 11 = Divide b

Reference buffer power-down control.

1 = Power-dow ADC master clo

Table 69. ADC Left V er

AVOLL7

7 6 5 4 3 2 1 0

ADDRESS = 1110000 (0x70) AVOLL7–0

1111111 = 1.0 (0 dBFS). 1111110 = 0. 1000000 = 0.5 (−6 0111111 = 0.496 (−6.09 dBFS). 0000000 = 0.

olume Regist

ADC left channel v

Table 70. ADC Right

AVOLR7

7 6 5 4 3 2 1 0

ADDRESS = 1110001 (0x71) AVOLR7–0

11111 1 = 1.0 BFS). 111111 1000000 = 0.5 (−6 dBFS). 0111111 = 0.4 0000000 = 0.0039 (−48.18 dBFS

Volume Register

ADC right chan me conel volu ntrol.

Table 71. ADC Left P gister

RES RES ALP

7 6 5 4 3 2 1 0

ADDRESS = 1110010 (0x72) ALP5–0

000000 = 0 dBFS. 000001 = −1 d 111111 = −63 dBFS.

eak Volume Re

ADC left channel peak volume detection.

Table 72. ADC Right egister

RES

7 6 5 4 3 2 1 0

ADDRESS = 1110011 (0x73) ARP5–0

000000 = 0 dBFS.

Peak Volume R

ADC right channel peak volume detection.

000001 = −1 dBFS. 111111 = −63

ck divider.

y 1.

AVOLL6 AVOLL5 AVOLL4 AVOLL3 AVOLL2 AVOLL1 AVOLL0

olume control.

996 (−0.00348 dBFS).

dBFS).

0039 (−48.18 dBFS).

AVOLR6 AVOLR5 AVOLR4 AVOLR3 AVOLR2 AVOLR1 AVOLR0

(0 d

0 = 0.996 (−0.00348 dBFS).

96 (−6.09 dBFS).

BFS.

RES ARP5 ARP4 ARP3 ARP2 ARP1 ARP0

dBFS.

R B

5 ALP4 ALP3 ALP2 ALP1 ALP0

Rev. 0 | Page 48 of 56

ADAV801

Table 73. PLL Control Register 1

DIRIN_C DIRIN_C MCLKO PLLDIV PLL2PD PLL1PD XTLPD SYSCLK3

7 6 5 4 3 2 1 0

ADDRESS = 1110100 (0x74) DIRIN_CLK1-0

Recovered SPDIF clock se 00 = SYSCLK3 comes from PLL block. 01 = Reserved 10 = Reserved.

11 = SYSCLK3 is

CLKODIV

Divide input MCLK by 2 to 0 = Disabled. 1 = Enabled

PLLDIV

Divide XIN b 0 = Disabled. 1 = Enabled

PLL2PD

Power-down P 0 = Normal. 1 = Power-down.

PLL1PD

Power-down PLL1. 0 = Normal. 1 = Power-d

XTLPD

Power-dow 0 = Normal. 1 = Power-

SYSCLK3

Clock output 0 = 512 × f 1 = 256 × fS.

Table 74. PLL Control Register 2

7 6 5 4 3 2 1 0

ADDRESS = 1110101 (0x75) FS2_1–0

Sampl rate se t for PLL2. e lec 00 = 48 kHz. 01 = Reserved. 10 = 32 kH 11 = 44.1 kHz

SEL2

Oversample rat 0 = 256 × f 1 = 384 × fS.

UB2

Double-se 0 = Disabled. 1 = Enable

FS1–0

Sample rate 00 = 48 kHz. 01 = Rese 10 = 32 kHz

SEL1

11 = 44.1 kHz.

Oversample ratio select for PLL1. 0 = 256 × f 1 = 384 × fS.

DOUB1

Double-selected sample rate on PLL1. 0 = Disabled. 1 = Enabled.

LK1 LK0 DIV

nt to SYSCLK3.

the recovered SPDIF clock from DIRIN.

generate MCLKO.

y 2 to generate the PLL master clock.

LL2.

own.

n XTAL oscillator.

down.

for SYSCLK3.

SEL2 DOUB2 FS1 FS0 SEL1 DOUB1 FS2_1 FS2_0

io select for PLL2.

lected sample rate on PLL2.

select for PLL1.

rved.

Rev. 0 | Page 49 of 56

ADAV801

Table 75. Internal Clocking Control R

DCLK2 CLK1 D LK0 LK2 CLK2 ICLK2

7 6 5 4 3 2 1 0

ADDRESS = 1110110 (0x76) DCLK2–0

ACLK2–0

ICLK2_1–0

DAC clock source select. 000 = XIN. 001 = MCLK 010 = PLLINT1. 011 = PL

LINT2. 100 = DIR P 101 = DIR PLL (256 × f 110 = XIN.

XIN.

111 =

C clock source select.

IN.

000 = X 001 = MCLKI. 010 = PLLINT 011 = PLLINT2. 100 = DIR PLL (512 × f 101 = DIR PLL (256 × f 110 = XIN. 111 = XIN. Source selecto 00 = XIN. 01 = MCLKI. 10 = PLLINT1. 11 = PLLINT2.

Table

76. Internal Clo l Register 2

cking Contro

RES RES

7 6 5 4 3 2 1 0

ADDRESS = 1110111 (0x77) ICLK1_1–0

PLL2INT1–0

PLL1INT

Source selector for internal clock ICLK1. 00 = XIN. 01 = MCLKI. 10 = PLLINT1. 11 = PLLINT2. PLL2 internal selector (see Figure 38). 00 = FS2. 01 = FS2/2. 10 = FS3. 11 = FS3/2. PLL1 internal selector. 0 = FS1. 1 = FS1/2.

egister 1

D C AC ACLK1 ACLK0 I _1 _0

LL (512 × f

r for internal clock ICLK2.

RES ICLK1_1 ICLK1_0 PLL2INT1 PLL2INT0 PLL1INT

Rev. 0 | Page 50 of 56

ADAV801

Table 77. PLL Clock Source Regist

PLL1_Sour RES RES R RES

7 6 5 4 3 2 1 0

ADDRESS = 1111000 (0x78) PLL1_Source

PLL2_Source

Table 78. PLL Output Register

Selects the clock source for PLL1. 0 = XIN. 1 = MCLKI. Selects the clo 0 = XIN. 1 = MCLKI.

Enable

RES

7 6 5 4 3 2 1 0

ADDRESS = 1111010 (0x7A) DIRINPD

DIRIN_PIN

YSCLK1

YSCLK2

YSCLK3

This bit powers down the SPDIF receiver. 0 = Normal. 1 = Power-down. This bit determines the input levels of the DIRIN pin. 0 = DIRIN accepts input signals 1 = DIRIN accepts input signals as defined in the Specificati Enables the SYSCLK1 output. 0 = Enabled. 1 = Disabled. Enables the SYSC 0 = Enabled. 1 = Disabled. Enabl tput. 0 =

Enabled.

1 = Disa

ce PLL2_Source ES RES RES

ck source for PLL2.

RES DIRINPD DIRIN_PIN RES SYSCLK1 SYSCLK2 SYSCLK3

down to 200 mV according to AES3 requirements.

ons section.

LK2 output.

es the SYSCLK3 ou

bled.

Rev. 0 | Page 51 of 56

ADAV801

Table 79. ALC Control Register 1

FSSEL1–0

7, 6 5, 4 3, 2 1 0

ADDRESS = 1111011 (0x7B) FSSEL1–0

GAINCNTR1–0

RECMODE1–0

LIMDET

ALCEN

These bits should equal the sample rate of the ADC. 00 = 96 kHz. 01 = 48 kHz. 10 = 32 kHz. 11 = Reserved. These bits determine the limit of the counter used in limited recovery mode. 00 = 3. 01 = 7. 10 = 15. 11 = 31. These bits determine which recovery mode is used by the ALC section. 00 = No recovery. 01 = Normal recovery. 10 = Limited recovery. 11 = Reserved. These bits limit detect mode. 0 = ALC is used when either channel exceeds the set limit. 1 = ALC is used only when both channels exceed the set limit. These bits enable ALC. 0 = Disable ALC. 1 = Enable ALC.

Table 80. ALC Control Register 2

RES RECTH1–0 ATKTH1–0 RECTIME1–0 ATKTIME

7 6, 5 4, 3 2, 1 0

ADDRESS = 1111100 (0x7C) RECTH1–0

ATKTH1–0

RECTIME1–0

ATKTIME

Recovery threshold. 00 = −2 dB. 01 = −3 dB. 10 = −4 dB. 11 = −6 dB. Attack threshold. 00 = 0 dB. 01 = −1 dB. 10 = −2 dB. 11 = −4 dB. Recovery time selection. 00 = 32 ms. 01 = 64 ms. 10 = 128 ms. 11 = 256 ms. Attack timer selection. 0 = 1 ms. 1 = 4 ms.

GAINCNTR1–0 RECMODE1–0 LIMDET ALCEN

Rev. 0 | Page 52 of 56

ADAV801

Table 81. ALC Control Register 3

ALC RESET

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 1111101 (0x7D) ALC RESET

A write to this register restarts the ALC operation. The value written to this register is irrelevant. A read from this register gives the gain reduction factor.

Rev. 0 | Page 53 of 56

ADAV801

LAYOUT CONSIDERATIONS

Getting the best performance from the ADAV801 requires a careful layout of the printed circuit board (PCB). Using separate analog and digital ground planes is recommended, because these give the currents a low resistance path back to the power supplies. The ground planes should be connected in only one place, usually under the ADAV801, to prevent ground loops.

The analog and digital supply pins should be decoupled to their respective ground pins with a 10 µF to 47 µF tantalum capacitor and a 0.1 µF ceramic capacitor. These capacitors should be placed as close as possible to the supply pins.

ADC

The ADC uses a switch capacitor input stage and is, therefore, particularly sensitive to digital noise. Sources of noise, such as PLLs or clocks, should not be routed close to the ADC section. The CAPxN and CAPxP pins form a charge reservoir for the switched capacitor section of the ADC, so keeping these nodes electrically quiet is a key factor in ensuring good performance. The capacitors connected to these pins should be of good quality, either NPO or COG, and should be placed as close as possible to CAPxN and CAPxP.

DAC

The DAC requires an analog filter to filter out-of-band noise from the analog output. A third-order Bessel filter is recommended, although the filter to use depends on the requirements o

PLL

The PLL can be used to generate digital clocks, either for use internally or to clock external circuitry. Because every clock is a potential source of noise, care should be taken when using the PLL. The ADAV801’s PLL outputs can be enabled or disabled, as required. If the PLL clocks are not required by external circuitry, it is recommended that the outputs be disabled. To reduce cross-coupling between clocks, a digital ground trace can be routed on either side of the PLL clock signal, if required.

f the application.

The PLL has its own power supply pins. To get the best performance from the PLL and from the rest of the ADAV801, it is recommended that a separate analog supply be used. Where this is not possible, the user must decide whether to connect the PLL supply to the analog (AV Connecting the PLL supply to AV

) or digital (DVDD) supply.

gives the best jitter

performance, but can degrade the performance of the ADC and DAC sections slightly due to the increased digital noise created on the AV

by the PLL. Connecting the PLL supply to DVDD

keeps digital noise away from the analog supply, but the jitter specifications might be reduced depending on the quality of the digital supply. Using the layout recommendations described in this section helps to reduce these effects.

RESET AND POWER-DOWN CONSIDERATIONS

When the ADAV801 is held in reset by bringing the

pin low, a number of circuit blocks remain powered up. For example, the crystal oscillator circuit based around the XIN and XOUT pins is still active, so that a stable clock source is available when the ADAV801 is taken out of reset. Also, the VCO associated with the SPDIF receiver is active so that the receiver locks to the incoming SPDIF stream in the shortest possible time. Where power consumption is a concern, the individual blocks of the ADAV801 can be powered down via the control registers to gain significant power savings. Table 82 shows typical power savings when using the power-down bits in the control registers.

Table 82. Typical Power Requirements

Operating Mode

Normal 50 25 5 5 280.5 Reset low 30 4 2.5 1 123.75 Power-down

bits

AV (mA)

12 0.1 1.3 0.7 46.53

DV (mA)

ODV (mA)

DIR_V (mA)

RESET

Power (mW)

Rev. 0 | Page 54 of 56

ADAV801

OUTLINE DIMENSIONS

0.75

0.60

0.45

SEATING

PLANE

1.60 MAX

PIN 1

12.00

BSC SQ

4964

10.00

BSC SQ

1.45

1.40

1.35

0.15

0.05

ROTATED 90° CCW

10°

SEATING PLANE

VIEW A

6° 2°

0.08 MAX COPLANARITY

0.20

0.09

7°

3.5° 0°

COMPLIANT TO JEDEC STANDARDS MS-026BCD

VIEW A

0.50

BSC

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

Figure 57. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Model

ADAV801ASTZ

Range

−40°C to +85°C SPI Single-Ended 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

ADAV801ASTZ-REEL1 −40°C to +85°C SPI Single-Ended 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

Z = Pb free part.

Control Interface DAC Outputs Package Description

Package Option

Rev. 0 | Page 55 of 56

ADAV801

NOTES

D04577–0–7/04(0)

Rev. 0 | Page 56 of 56

Datasheet ADAV801 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

PRODUCT OVERVIEW

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

SPECIFICATIONS

TEST CONDITIONS

ADAV801 SPECIFICATIONS

TIMING SPECIFICATIONS

TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

ADC SECTION

Programmable Gain Amplifier (PGA)

Attack Mode

No Recovery Mode

Limited Recovery Mode

DAC SECTION

Conceptual High Interpolation Model

Hardware Model

SRC Architecture

PLL SECTION

SPDIF TRANSMITTER AND RECEIVER

Receiver Section

Transmitter Operation

Autobuffering

Interrupts

SERIAL DATA PORTS

Clocking Scheme

Datapath

INTERFACE CONTROL

LAYOUT CONSIDERATIONS

RESET AND POWER-DOWN CONSIDERATIONS

OUTLINE DIMENSIONS

ORDERING GUIDE