Datasheet ADATE302-02 Datasheet (ANALOG DEVICES)

500 MHz Dual Integrated DCL with Differential

www.BDTIC.com/ADI

Drive/Receive, Level Setting DACs, and Per Pin PMU

FEATURES

Driver

3-level driver with high-Z mode and built-in clamps Precision trimmed output resistance Low leakage mode (typically <10 nA) Voltage range: −2.0 V to +6.0 V

1.0 ns minimum pulse width, 1 V terminated

Comparator

Window and differential comparator >1 GHz input equivalent bandwidth

Load

±12 mA maximum current capability

Per pin PMU

Force voltage range: −2.0 V to +6.0 V 5 current ranges: 25 mA, 2 mA, 200 μA, 20 μA, and 2 μA

Levels

14-bit DAC for DCL levels Typically <±5 mV INL (calibrated) 16-bit DAC for PMU levels Typically <±1.5 mV INL (calibrated) linearity in FV mode

HVOUT output buffer

0 V to 13.5 V output range

84-ball, 9 mm × 9 mm, flip-chip BGA package

1.7 W per channel with no load

APPLICATIONS

Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment

ADATE302-02

GENERAL DESCRIPTION

The ADATE302-02 is a complete, single-chip solution that performs the pin electronic functions of the driver, the comparator, and the active load (DCL), per pin PMU, and dc levels for ATE applications. The device also contains an HVOUT driver with a VHH buffer capable of generating up to 13.5 V.

The driver features three active states: data high mode, data low mode, and term mode, as well as an inhibit state. The inhibit state, in conjunction with the integrated dynamic clamp, facilitates the implementation of a high speed active termination. The output voltage range is −2.0 V to +6.0 V to accommodate a wide variety of test devices.

The ADATE302-02 can be used as either a dual single-ended drive/receive channel or a single differential drive/receive channel. Each channel of the ADATE302-02 features a high speed window comparator per pin for functional testing as well as a per pin PMU with FV or FI and MV or MI functions. All necessary dc levels for DCL functions are generated by on-chip 14-bit DACs. The per pin PMU features an on-chip 16-bit DAC for high accuracy and contains integrated range resistors to minimize external component counts.

The ADATE302-02 uses a serial bus to program all functional blocks and has an on-board temperature sensor for monitoring the device temperature.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

6/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 52

ADATE302-02

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FUNCTIONAL BLOCK DIAGRAM

DAC16_MON

MEASOUT01

PMUS_CH0

DATA0P

DATA0N

RCV0P

RCV0N

COMP_VTT0

COMP_Q H0P

COMP_QH0N

COMP_QL0P

COMP_QL0N

MUX

*

CH1

100

16-BIT DAC

MUX

50

PMU_FLAG

PMU

*

CH1

VCH

VCL

VH

VT VL

DRV

MUX

VCH VCL

R

(TRIMMED)

OUT

SENSE

OVD

FORCE

OVD_CH0

DUT0

*

WINDOW

DIFF.

*

VHH

*

G

C

VOH

VOL

OTHER CHANNEL DUT1

HVOUT

SDIN

RST

SCLK

CS

SDOUT

*

SPI

*

ONE PER DEVICE.

IOL

VCOM

14-BIT DAC

IOH

Figure 1. Functional Block Diagram with One of Two Channels Shown

ADATE302-02

TEMPERATURE

SENSOR

*

TEMPSENSE

07278-001

Rev. 0 | Page 3 of 52

ADATE302-02

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SPECIFICATIONS

VDD = 10.0 V, VCC = 3.3 V, VSS = −5.75 V, V defined in Ta b le 3 7. All specified values are at T Temperature coefficients are measured at T analyses, and/or limited bench evaluations. Typical values are not tested or guaranteed. Test levels are specified in the Explanation of Test Levels section.

TOTAL FUNCTION

Table 1.

Parameter Min Typ Max Unit

TOTAL FUNCTION

Output Leakage Current

PE Disable, Range E −20.0 +6.0 +20.0 nA P −2.0 V < V

PE Disable, Range A, B, C, D 7.5 nA CT −2.0 V < V

High-Z Mode −400 +15 +400 nA P −2.0 V < V

Output Capacitance 4 pF S VTERM mode operation DUT Pin Range −2.0 +6.0 V D

POWER SUPPLIES

Total Supply Range, V VPLUS Supply, V Positive Supply, VDD 9.5 10.0 10.5 V D Defines PSRR conditions Negative Supply, VSS −6.0 −5.75 −5.5 V D Defines PSRR conditions Logic Supply, VCC 3.1 3.3 3.5 V D Defines PSRR conditions Comparator Termination, V V

Supply Current, I

PLUS

V

Supply Current, I

PLUS

Logic Supply Current, ICC 1.0 2.7 10.0 mA P Quiescent (SPI is static) Comparator Termination Current,

I

COMP_VTTx

Positive Supply Current, IDD 140.0 190 256.0 mA P Load power down (IOH = IOL = 0 mA)

170.0 231 311.0 mA P Load active off (IOH = IOL = 12 mA) Negative Supply Current, ISS 200.0 272 406.0 mA P Load power down (IOH = IOL = 0 mA)

230.0 311 461.0 mA P Load active off (IOH = IOL = 12 mA) Total Power Dissipation 2.5 3.55 4.0 W P Load power down (IOH = IOL = 0 mA)

3.0 4.2 5.5 W P Load active off (IOH = IOL = 12 mA)

TEMPERATURE MONITORS

Temperature Sensor Gain 10 mV/K CT Temperature Sensor Accuracy Without

Calibration over 25°C to 100°C

VREF INPUT

Reference Input Voltage Range for

DACs (VREF Pin)

Input Bias Current 0.08 100 A P Tested with 5 V applied

to VSS 22.5 23.25 V D Defines PSRR conditions

PLUS

16.25 16.75 17.25 V D Defines PSRR conditions

PLUS

1 1.5 3.3 V D

COMP_VTTx

−1.0 +1.3 +4.0 mA P HVOUT disabled

PLUS

4.0 12.7 17.0 mA P HVOUT enabled, RCVx pins active, no load, VHH = 12 V

PLUS

= 16.75 V, V

PLUS

= 80°C, where TJ corresponds to the internal temperature sensor, unless otherwise noted.

J

= 80°C ± 20°C, unless otherwise noted. Typical values are based on design, simulation

J

COMP_VTTx

= 1.5 V, V

= 5.0 V, V

REF

= 0.0 V. All default test conditions are as

REF_GND

Test Level Conditions/Comments

< +6.0 V; PMU and PE disabled via SPI;

DUTx

VCH = 7.0 V, VCL = −2.5 V

< +6.0 V; PMU and PE disabled via SPI;

DUTx

VCH = 7.0 V, VCL = −2.5 V

< +6.0 V; PMU disabled and PE enabled via

DUTx

SPI; RCVx pins active, VCH = 7.0 V, VCL = −2.5V

40.0 46 70.0 mA P

6 °C CT Temperature voltage available on Pin A1 at all times and

on Pin K1 when selected (see Table 24 and Table 36)

4.95 5 5.05 V D Referenced to V

; not referenced to V

REF_GND

DUTGND

Rev. 0 | Page 4 of 52

ADATE302-02

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DRIVER

VH − VL ≥ 200 mV (to meet dc/ac specifications).

Table 2.

Parameter Min Typ Max Unit

DC SPECIFICATIONS

High-Speed Differential Logic Input

Characteristics (DATAx, RCVx) Input Termination Resistance 92 100 108 Ω P Push 6 mA into xP pins, force 1.3 V on xN pins; measure

Input Voltage Differential 0.2 1.0 V PF Common-Mode Voltage 0.85 2.35 V PF Input Bias Current −20.0 +4.0 +20.0 A P Each pin tested at 2.85 V and 0.35 V, while other high speed

Pin Output Characteristics

Output High Range, VH −1.9 +6.0 V D Output Low Range, VL −2.0 +5.9 V D Output Term Range, VT −2.0 +6.0 V D Functional Amplitude (VH − VL) 0.0 8.0 V D Amplitude can be programmed to VH = VL, accuracy

DC Output Current Limit Source 75 100 120 mA P Driver high, VH = 6.0 V, short DUTx pin to −2.0 V, measure

DC Output Current Limit Sink −120 −100 −75 mA P Driver low, VL = −2.0 V, short DUTx pin to 6.0 V, measure current Output Resistance, ±50 mA 45.0 48.5 51.0 Ω P Source: driver high, VH = 3.0 V, I

ABSOLUTE ACCURACY VH tests done with VL = −2.5 V and VT = −2.5 V;

VH, VL, VT Uncalibrated Accuracy −300 ±75 +300 mV P Error measured at calibration points of 0 V and 5 V VH, VL, VT Offset Tempco ±450 V/°C CT Measured at calibration points VH, VL, VT DNL ±1 mV CT After two-point gain/offset calibration VH, VL, VT INL −10 ±2.5 +10 mV P After two-point gain/offset calibration; measured over driver

VH, VL, VT Resolution 0.6 1 mV PF After two-point gain/offset calibration; range/number of DAC

DUTGND Voltage Accuracy −7 ±1.3 +7 mV P Over ±0.1 V range; measured at end points of VH, VL, and VT

VH, VL, VT Crosstalk ±2 mV CT

Overall Voltage Accuracy ±10 mV CT Sum of INL, crosstalk, DUTGND, and tempco over ±5°C,

VH, VL, VT DC PSRR ±15 mV/V CT Measured at calibration points

AC SPECIFICATIONS

Rise/Fall Times Toggle DATAx pins

0.2 V Programmed Swing 683 ps CB VH = 0.2 V, VL = 0.0 V, terminated; 20% to 80%

1.0 V Programmed Swing 521 ps CB VH = 1.0 V, VL = 0.0 V, terminated; 20% to 80%

1.8 V Programmed Swing 430 524 630 ps P/CB VH = 1.8 V, VL = 0.0 V, terminated; 20% to 80%

2.0 V Programmed Swing 531 ps CB VH = 2.0 V, VL = 0.0 V, terminated; 20% to 80%

3.0 V Programmed Swing 589 ps CB VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80%

3.0 V Programmed Swing 811 ps CB VH = 3.0 V, VL = 0.0 V, unterminated; 10% to 90%

5.0 V Programmed Swing 1105 ps CB VH = 5.0 V, VL = 0.0 V, unterminated; 10% to 90% Rise to Fall Matching 6 ps CB VH = 1.0 V, VL = 0.0 V, terminated; rise to fall within one channel

Test Level

Conditions/Comments

voltage from xP to xN, calculate resistance (V/I)

pin left open

specifications apply when VH − VL ≥ 200 mV

current

= 1 mA and 50 mA;

DUTx

sink: driver low, VL = 0.0 V, I

VL tests done with VH = 7.5 V and VT = 7.5 V; VT tests done with VL = −2.5 V and VH = 7.5 V; unless otherwise specified

output ranges

bits as measured at calibration points of 0 V and 5 V

functional range VL = −2.0 V: VH = −1.9 V → 6.0 V, VT = −2.0 V → 6.0 V;

VH = 6.0 V: VL = −2.0 V → 5.9 V, VT = −2.0 V → 6.0 V; VT = 1.5 V: VL = −2.0 V → 5.9 V, VH = −1.9 V → 6.0 V; dc crosstalk on VL, VH, VT output level when other driver DACs are varied

after gain/offset calibration

= −1 mA and −50 mA; ∆V

DUTx

/∆I

DUTx

Rev. 0 | Page 5 of 52

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Parameter Min Typ Max Unit

Minimum Pulse Width Toggle DATAx pins

2.0 V Programmed Swing 1.2 ns CB VH = 2.0 V, VL = 0.0 V, terminated; timing error ±27 ps

1.2 ns CB VH = 2.0 V, VL = 0.0 V, terminated; less than 10% amplitude

1.0 ns CB VH = 2.0 V, VL = 0.0 V, terminated; less than 20% amplitude

Maximum Toggle Rate 500 MHz CB VH = 2.0 V, VH = 0.0 V, terminated, 18% amplitude degradation

Dynamic Performance, Drive

(VH to VL and VL to VH) Propagation Delay Time 2.1 ns CB VH = 2.0 V, VL = 0.0 V, terminated Propagation Delay Tempco 4.5 ps/°C CT VH = 2.0 V, VL = 0.0 V, terminated Delay Matching VH = 2.0 V, VL = 0.0 V, terminated

Edge to Edge 41 ps CB Rising vs. falling

Channel to Channel ±15 ps CB Rising vs. rising, falling vs. falling Delay Change vs. Duty Cycle ±30 ps CB VH = 3.0 V, VL = 0.0 V, terminated; 5% to 95% duty cycle; 1 MHz Overshoot and Undershoot 48 mV CB VH = 3.0 V, VL = 0.0 V, terminated Settling Time (VH to VL) Toggle DATAx pins

To Within 3% of Final Value 1.2 ns CB VH = 3.0 V, VL = 0.0 V, terminated

To Within 1% of Final Value 14 ns CB VH = 3.0 V, VL = 0.0 V, terminated

Dynamic Performance, VTERM

(VH or VL to VT and VT to VH or VL)

Propagation Delay Time 2.7 ns CB VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated Delay Matching, Edge to Edge 59 ps CB VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; rising vs. falling Propagation Delay Tempco 5.5 ps/°C CT VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated Transition Time, Active to VT,

VT to Active

Dynamic Performance,

Inhibit (VH or VL to/from Inhibit) Propagation Delay Time VH = +1.0 V, VL = −1.0 V, terminated

Active to Inhibit 2.7 ns CB

Inhibit to Active 3.7 ns CB Transition Time VH = +1.0 V, VL = −1.0 V, terminated; 20% to 80%

Active to Inhibit 1.3 ns CB

Inhibit to Active 0.4 ns CB I/O Spike 157 mV CB VH = 0.0 V, VL = 0.0 V, terminated

Toggle DATAx pins

Toggle RCVx pins

0.614 ns CB VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; 20% to 80%

Toggle RCVx pins

Test Level Conditions/Comments

degradation

REFLECTION CLAMP

Clamp accuracy specifications apply when VCH > VCL.

Table 3.

Parameter Min Typ Max Unit

VCH

Range −1.0 +6.0 V D Uncalibrated Accuracy −200 ±45 +200 mV P Driver high-Z, sinking 1 mA; VCH error measured at

Resolution 0.6 0.75 mV PF Driver high-Z, sinking 1 mA; after two-point gain/offset

DNL ±1 mV CT Driver high-Z, sinking 1 mA; after two-point gain/offset

INL −40 ±2 +40 mV P Driver high-Z, sinking 1 mA; after two-point gain/offset

Tempco −0.5 mV/°C CT Measured at calibration points

Rev. 0 | Page 6 of 52

Test Level

Conditions/Comments

calibration points of 0 V and 5 V

calibration; range/number of DAC bits as measured at calibration points of 0 V and 5 V

calibration

calibration; measured over VCH range of −1 V to +6 V

ADATE302-02

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Parameter Min Typ Max Unit

VCL

Range −2 +5.0 V D

Uncalibrated Accuracy −200 ±70 +200 mV P Driver high-Z, sourcing 1 mA; VCL error measured at

Resolution 0.6 0.75 mV PF Driver high-Z, sourcing 1 mA; after two-point gain/offset

DNL ±1 mV CT Driver high-Z, sourcing 1 mA; after two-point gain/offset

INL −40 ±2 +40 mV P Driver high-Z, sourcing 1 mA; after two-point gain/offset

Tempco 0.6 mV/°C CT Measured at calibration points

DC CLAMP CURRENT LIMIT

VCH −120 −83 −60 mA P Driver high-Z, VCH = 0 V, VCL = −2.0 V, V

VCL 60 86 120 mA P Driver high-Z, VCH = 6.0 V, VCL = 5.0 V, V

DUTGND VOLTAGE ACCURACY −7 ±1 +7 mV P Over ±0.1 V range; measured at the end points of VCH

NORMAL WINDOW COMPARATOR

VOH tests done with VOL = −2.0 V, VOL tests done with VOH = 6.0 V, unless other wise specified.

Test Level Conditions/Comments

calibration points of 0 V and 5 V

calibration; range/number of DAC bits as measured at calibration points of 0 V and 5 V

calibration

calibration; measured over VCL range of −2 V to +5 V

and VCL functional range

DUTx

= 5 V

= 0.0 V

Table 4.

Parameter Min Typ Max Unit

DC SPECIFICATIONS

Input Voltage Range −2.0 +6.0 V D

Differential Voltage Range ±0.1 ±8.0 V D

Comparator Input Offset Voltage

Accuracy, Uncalibrated

Comparator Threshold Resolution 0.61 1 mV PF After two-point gain/offset calibration; range/

Comparator Threshold DNL ±1 mV CT After two-point gain/offset calibration

Comparator Threshold INL −7 ±1.2 +7 mV P After two-point gain/offset calibration; measured

Comparator Input Offset Voltage

Tempco

DUTGND Voltage Accuracy −7 ±0.5 +7 mV P Over ±0.1 V range; measured at end points of VOH

Comparator Uncertainty Range 5.3 mV CB V

DC Hysteresis 0.5 mV CB V

DC PSRR ±5 mV/V CT Measured at calibration points

Digital Output Characteristics

Internal Pull-Up Resistance to

Comparator, COMP_VTTx Pin

V Common-Mode Voltage V

V

Differential Voltage 250 mV CT Measured with 100 Ω differential termination 450 500 550 mV P Measured with no external termination Rise/Fall Time, 20% to 80% 222 ps CB Measured with each comparator leg terminated

Range 1 1.5 3.3 V D

COMP_VTTx

−150 ±30 +150 mV P Offset measured at calibration points of 0 V and 5 V

±200 µV/°C CT Measured at calibration points

46 50 54 Ω P Pull 1 mA and 10 mA from Logic 1 leg and measure

V CT Measured with 100 Ω differential termination

V P Measured with no external termination

COMP_VTTx

− 0.5

COMP_VTTx

− 0.3 V

Test Level

Conditions/Comments

number of DAC bits as measured at calibration points of 0 V and 5 V

over VOH, VOL range of −2.0 V to +6.0 V

and VOL functional range

= 0 V, sweep comparator threshold to

DUTx

determine uncertainty region

= 0 V

DUTx

∆V to calculate resistance; measured ∆V/9 mA; done for both comparator logic states

50 Ω to GND

Rev. 0 | Page 7 of 52

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Parameter Min Typ Max Unit

AC SPECIFICATIONS Input transition time = 600 ps, 10% to 90%;

Propagation Delay, Input to Output 1.4 ns CB V

Propagation Delay Tempco 4 ps/°C CT V

Propagation Delay Matching V

High Transition to Low Transition 39 ps CB High to Low Comparator ±30 ps CB

Propagation Delay Change with

Respect to Slew Rate, 600 ps and 1 ns

(10% to 90%)

Overdrive, 250 mV and 1.0 V 65 ps CB For 250 mV: V

Pulse Width, 1 ns, 5 ns, 10 ns, and

15 ns

Duty Cycle, 5% to 95% 11.8 ps CB V

Minimum Pulse Width 1 ns CB V

Input Equivalent Bandwidth,

Terminated

ERT High-Z Mode, 3 V, 20% to 80% 0.9 ns CB V

19 ps CB V

27 ps CB V

1000 MHz CB V

Test Level Conditions/Comments

measured with each comparator leg terminated 50 Ω to GND; unless otherwise specified

= 0 V to 1.0 V swing, driver VTERM mode,

DUTx

VT = 0.0 V; high-side measurement: VOH = 0.5 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.5 V

= 0 V to 1.0 V swing, driver VTERM mode,

DUTx

VT = 0.0 V; high-side measurement: VOH = 0.5 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.5 V

= 0 V to 1.0 V swing, driver VTERM mode,

DUTx

VT = 0.0 V; high-side measurement: VOH = 0.5 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.5 V

= 0 V to 0.5 V swing, driver VTERM mode,

DUTx

VT = 0.0 V; high-side measurement: VOH = 0.25 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.25 V

= 0 V to 0.5 V swing; for 1.0 V: V 0 V to 1.25 V swing; driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.25 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.25 V; input transition time = 400 ps (10%/90%)

= 0 V to 1.0 V swing @ 32.0 MHz, driver VTERM

DUTx

mode, VT = 0.0 V; high-side measurement: VOH = 0.5 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.5 V; input transition time = 400 ps (10%/90%)

= 0 V to 1.0 V swing @ 1.0 MHz, driver VTERM

DUTx

mode, VT = 0.0 V; high-side measurement: VOH = 0.5 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.5 V; input transition time = 400 ps (10%/90%)

= 0 V to 1.0 V swing, driver VTERM mode,

DUTx

VT = 0.0 V; less than 10% amplitude degradation measured by shmoo; input transition time = 400 ps (10%/90%)

= 0 V to 1.0 V swing, driver VTERM mode,

DUTx

VT = 0.0 V; as measured by shmoo; input transition time = 400 ps (10%/90%)

= 0 V to 3.0 V swing, driver high-Z; as measured

DUTx

by shmoo

DUTx

=

DIFFERENTIAL COMPARATOR

VOH tests done with VOL = −1.1 V, VOL tests done with VOH = 1.1 V, unless other wise specified.

Table 5.

Parameter Min Typ Max Unit

DC SPECIFICATIONS

Input Voltage Range −1.5 +4.5 V D Operational Differential Voltage

Range Maximum Differential Voltage Range ±8 V D Comparator Input Offset Voltage

Accuracy, Uncalibrated

±0.05 ±1.1 V D

−150 ±25 +150 mV P Offset measured at differential calibration points of

Rev. 0 | Page 8 of 52

Test Level

Conditions/Comments

+1 V and −1 V, with common mode = 0 V

ADATE302-02

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Parameter Min Typ Max Unit

VOH, VOL Resolution 0.61 1 mV PF After two-point gain/offset calibration; range/number of

VOH, VOL DNL ±1 mV CT After two-point gain/offset calibration; common mode =

VOH, VOL INL −7 ±1.0 +7 mV P After two-point gain/offset calibration; measured over

VOH, VOL Offset Voltage Tempco ±200 µV/°C CT Measured at calibration points Comparator Uncertainty Range 18 mV CB V

DC Hysteresis 0.5 mV CB V CMRR 1 mV/V P Offset measured at common-mode voltage points of

DC PSRR ±15 mV/V CT Measured at calibration points

AC SPECIFICATIONS Input transition time = 600 ps, 10% to 90%, measured

Propagation Delay, Input to Output 1.4 ns CB V

Propagation Delay Tempco 4 ps/°C CT V

Propagation Delay Matching V

High Transition to Low Transition 27 ps CB High to Low Comparator ±32 ps CB

Propagation Delay Change with

V

Respect to

Slew Rate, 400 ps and 1 ns

25 ps CB V

(10% to 90%)

Overdrive, 250 mV and 750 mV 79 ps CB V

Pulse Width, 1 ns, 5 ns, 10 ns, and

56 ps CB V

15 ns

Duty Cycle, 5% to 95% 16 ps CB V

Minimum Pulse Width 1 ns CB V

Input Equivalent Bandwidth,

500 MHz CB V

Terminated

Test Level Conditions/Comments

DAC bits as measured at differential calibration points of +1 V and −1 V, with common mode = 0 V

0 V

VOH, VOL range of −1.1 V to +1.1 V, common mode = 0 V

= 0 V, sweep comparator threshold to determine

DUTx

uncertainty region

= 0 V

DUTx

−1.5 V and +4.5 V, with differential voltage = 0 V

with each comparator leg terminated 50 Ω to GND

DUT0

= 0 V, V

= −0.5 V to +0.5 V swing, driver VTERM

DUT1

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel

DUT0

= 0 V, V

= −0.5 V to +0.5 V swing, driver VTERM

DUT1

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel

DUT0

= 0 V, V

= −0.5 V to +0.5 V swing, driver VTERM

DUT1

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel

DUT0

= 0 V, V

= −0.5 V to +0.5 V swing, driver VTERM

DUT1

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel

DUT0

= 0 V, V

= −0.5 V to +0.5 V swing, driver VTERM

DUT1

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel

= 0 V, for 250 mV: V

DUT0

for 750 mV: V

= 0 V to 1.0 V swing, driver VTERM mode,

DUT1

VT = 0.0 V; VOH = −0.25 V; repeat for other DUT channel with comparator threshold = 0.25 V

DUT0

= 0 V, V

= −0.5 V to +0.5 V swing @ 32 MHz,

DUT1

driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel

DUT0

= 0 V, V

= −0.5 V to +0.5 V swing @ 32 MHz, driver

DUT1

VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel

DUT0

= 0 V, V

= −0.5 V to +0.5 V swing, driver VTERM

DUT1

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; less than 10% amplitude degradation measured by shmoo; repeat for other DUT channel

DUT0

= 0 V, V

= −0.5 V to +0.5 V swing, driver VTERM

DUT1

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; less than 22% amplitude degradation measured by shmoo; repeat for other DUT channel

= 0 V to 0.5 V swing;

Rev. 0 | Page 9 of 52

ADATE302-02

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ACTIVE LOAD

See Tab le 2 9 for load control information.

Table 6.

Parameter Min Typ Max Unit

DC SPECIFICATIONS Load active on, RCVx pins active, unless otherwise noted

Input Characteristics

VCOM Voltage Range −1.75 +5.75 V D

V

Range −2.0 +6.0 V D

DUTx

VCOM Accuracy, Uncalibrated −200 ±25 +200 mV P IOH = IOL = 6 mA, VCOM error measured at calibration

VCOM Resolution 0.61 1 mV PF IOH = IOL = 6 mA, after two-point gain/offset

VCOM DNL ±1 mV CT IOH = IOL = 6 mA, after two-point gain/offset calibration

VCOM INL −7 ±2 +7 mV P IOH = IOL = 6 mA, after two-point gain/offset

DUTGND Voltage Accuracy −7 ±1 +7 mV P Over ±0.1 V range; measured at end points of VCOM

Output Characteristics

IOL

Maximum Source Current 12 mA D Uncalibrated Offset −600.0 ±100 +600.0 µA P IOH = 0 mA, VCOM = 1.5 V, V

Uncalibrated Gain −12 ±1 +12 % P IOH = 0 mA, VCOM = 1.5 V, V

Resolution 1.5 2 µA PF IOH = 0 mA, VCOM = 1.5 V, V

DNL ±3.0 µA CT IOH = 0 mA, VCOM = 1.5 V, V

INL −70 ±20 +70 µA P IOH = 0 mA, VCOM = 1.5 V, V

90% Commutation Voltage 0.25 V P IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOL

IOH

Maximum Sink Current 12 mA D Uncalibrated Offset −600.0 ±100 +600.0 µA P IOL = 0 mA, VCOM = 1.5 V, V

Uncalibrated Gain −12 ±1 +12 % P IOL = 0 mA, VCOM = 1.5 V, V

Resolution 1.5 2 µA PF IOL = 0 mA, VCOM = 1.5 V, V

DNL ±3.0 µA CT IOL = 0 mA, VCOM = 1.5V, V

INL −70 ±20 +70 µA P IOL = 0 mA, VCOM = 1.5V, V

90% Commutation Voltage 0.25 V P IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOH

Output Current Tempco ±1.5 µA/°C CT Measured at calibration points

Test Level

Conditions/Comments

points of 0 V and 5 V

calibration; range/number of DAC bits as measured at calibration points of 0 V and 5 V

calibration; measured over VCOM range of −1.75 V to +5.75 V

functional range

= 0.0 V, IOL offset

DUTx

calculated from calibration points of 1 mA and 11 mA

= 0.0 V, IOL gain

DUTx

calculated from calibration points of 1 mA and 11 mA

= 0.0 V, after two-point

DUTx

gain/offset calibration; range/number of DAC bits as measured at calibration points of 1 mA and 11 mA

= 0.0 V, after two-

DUTx

point gain/offset calibration

= 0.0 V, after two-

DUTx

point gain/offset calibration; measured over IOL range of 0 mA to 12 mA

reference at V

= 1.75 V, ensure >90% of reference current

V

DUTx

= −1.0 V, measure IOL current at

DUTx

= 3.0 V, IOH offset

DUTx

calculated from calibration points of 1 mA and 11 mA

= 3.0 V, IOH gain

DUTx

calculated from calibration points of 1 mA and 11 mA

= 3.0 V, after two-point

DUTx

gain/offset calibration; range/number of DAC bits as measured at calibration points of 1 mA and 11 mA

= 3.0 V, after two-point

DUTx

gain/offset calibration

= 3.0 V, after two-point

DUTx

gain/offset calibration; measured over IOH range of 0 mA to 12 mA

reference at V

= 2.25 V, ensure >90% of reference current

V

DUTx

= 5.0 V, measure IOH current at

DUTx

Rev. 0 | Page 10 of 52

ADATE302-02

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Parameter Min Typ Max Unit

AC SPECIFICATIONS Load active on, unless otherwise noted

Dynamic Performance Propagation Delay, Load Active On

to Load Active Off; 50%, 90%

Propagation Delay, Load Active Off

to Load Active On; 50%, 90%

Propagation Delay Matching 6.9 ns CB Toggle RCVx pins, DUTx terminated 50 Ω to GND,

Load Spike 156 mV CB Toggle RCVx pins, DUTx terminated 50 Ω to GND,

Settling Time to 90% 1.6 ns CB Toggle RCVx pins, DUTx terminated 50 Ω to GND,

4.1 ns CB Toggle RCVx pins, DUTx terminated 50 Ω to GND,

11 ns CB Toggle RCVx pins, DUTx terminated 50 Ω to GND,

Test Level Conditions/Comments

IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH; measured from 50% point of RCVxP − RCVxN to 90% point of final output, repeat for drive low and high

IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH; active on vs. active off, repeat for drive low and high

IOH = IOL = 0 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH; repeat for drive low and high

IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM= −1.25 V for IOH; measured at 90% of final value

PMU

FV = force voltage, MV = measure voltage, FI = force current, MI = measure current, FN = force nothing.

Table 7.

Parameter Min Typ Max Unit

FORCE VOLTAGE (FV)

Current Range A ±25 mA D Current Range B ±2 mA D Current Range C ±200 µA D Current Range D ±20 µA D Current Range E ±2 µA D Force Input Voltage Range at

Output For All Ranges

Force Voltage Uncalibrated

Accuracy for Range C

Force Voltage Uncalibrated

Accuracy for All Ranges

Force Voltage Offset Tempco

for All Ranges

Force Voltage Gain Tempco

for All Ranges

Forced Voltage INL −7 ±2 +7 mV P PMU enabled, FV, Range C, PE disabled, after two-point gain/

Force Voltage Compliance vs.

Current Load

Range A ±4 mV CT Range B to Range E ±1 mV CT

−2.0 +6.0 V D

−100 ±25 +100 mV P PMU enabled, FV, PE disabled, error measured at calibration

±25 mV CT PMU enabled, FV, PE disabled, error measured at calibration

±25 µV/°C CT Measured at calibration points for each PMU current range

±75 ppm/°C CT Measured at calibration points for each PMU current range

PMU enabled, FV, PE disabled, force −2.0 V, measure voltage

Test Level

Conditions/Comments

points of 0 V and 5 V

points of 0 V and 5 V; repeat for each PMU current range

offset calibration; measured over output range of −2.0 V to +6.0 V

while PMU sinking zero- and full-scale current; measure V; force 6.0 V, measure voltage while PMU sourcing zero- and fullscale current; measure V; repeat for each PMU current range

Rev. 0 | Page 11 of 52

ADATE302-02

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Parameter Min Typ Max Unit

Current Limit, Source and Sink

Range A 108 135 180 % FS P PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx

Range B to Range E 120 140 180 % FS P PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to

DUTGND Voltage Accuracy −7 ±1 +7 mV P Over ±0.1 V range; measured at end points of FV functional

MEASURE CURRENT (MI) V

Measure Current, Pin DUTx

−2.0 +6.0 V D

Voltage Range for All Ranges Measure Current Uncalibrated

Accuracy

Range A ±650 µA CT PMU enabled, FIMI, PE disabled, error at calibration points of

Range B −400 ±20 +400 µA P PMU enabled, FIMI, PE disabled, error at calibration points of

Range C ± 2.00 µA CT PMU enabled, FIMI, PE disabled, error at calibration points of

Range D ±0.20 µA CT PMU enabled, FIMI, PE disabled, error at calibration points of

Range E ±0.02 µA CT PMU enabled, FIMI, PE disabled, error at calibration points of

Measure Current Offset Tempco

Range A ±2.5 µA/°C CT Measured at calibration points

Range B ±125 nA/°C CT Measured at calibration points

Range C ±20 nA/°C CT Measured at calibration points

Range D and Range E ±4 nA/°C CT Measured at calibration points Measure Current Gain Error,

Nominal Gain = 1

Range A −3.5 % CT PMU enabled, FIMI, PE disabled, gain error from calibration

Range B −20 ±2 +20 % P PMU enabled, FIMI, PE disabled, gain error from calibration

Range C to Range E ±2 % CT PMU enabled, FIMI, PE disabled, gain error from calibration

Measure Current Gain Tempco Measured at calibration points

Range A ±300 ppm/°C CT

Range B to Range E ±50 ppm/°C CT Measure Current INL

Range A ±0.05 % FSR CT PMU enabled, FIMI, PE disabled, after two-point gain/offset

Range B −0.02 ±0.005 0.02 % FSR P PMU enabled, FIMI, PE disabled, after two-point gain/

Range B to Range E ±0.005 % FSR CT PMU enabled, FIMI, PE disabled, after two-point gain/offset

FVMI DUT Pin Voltage Rejection −0.01 0.01 % FSR/V P PMU enabled, FVMI, PE disabled, force −1 V and +5 V into load

DUTGND Voltage Accuracy ±2.5 mV CT Over ±0.1 V range; measured at end points of MI functional

Test Level Conditions/Comments

to 6.0 V; source: force 2.5 V, short DUTx to −1.0 V; Range A FS = 25 mA, 108% FS = 27 mA, 180% FS = 45 mA

6.0 V; source: force 2.5 V, short DUTx to −1.0 V; repeat for each PMU current range; example: Range B FS = 2 mA, 120% FS = 2.4 mA, 180% FS = 3.6 mA

range

externally forced to 0.0 V, unless otherwise specified;

DUTx

ideal MEASOUT transfer functions: V

MEASOUT01

I(V

MEASOUT01

[V] = (I

) [A] = (V

× 5/FSR) + 2.5 + V

MEASOUT01

−20 mA and 20 mA, error = (I(V

−1.6 mA and 1.6 mA, error = (I(V

±80% FS, error = (I(V

MEASOUT01

points of ±80% FS

points of ±1.6 mA

points of ±80% FS

calibration, measured over FSR output of −25 mA to +25 mA

offset calibration measured over FSR output of −2 mA to +2 mA

calibration; measured over FSR output

of 1 mA; measure I reported at MEASOUT01

range

− V

DUTGND

) − I

MEASOUT01

DUTx

DUTGND

− 2.5) × FSR/5

) − I

)

DUTx

) − I

)

DUTx

)

Rev. 0 | Page 12 of 52

ADATE302-02

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Parameter Min Typ Max Unit

FORCE CURRENT (FI) V

Force Current, DUTx Pin Voltage

Range for All Ranges

Force Current Uncalibrated

Accuracy Range A −5.0 ±0.5 +5.0 mA P PMU enabled, FIMI, PE disabled, error at calibration points of

Range B −400 ±40 +400 µA P PMU enabled, FIMI, PE disabled, error at calibration points of

Range C −40 ±4 +40 µA P PMU enabled, FIMI, PE disabled, error at calibration points of

Range D −4 ±0.4 +4 µA P PMU enabled, FIMI, PE disabled, error at calibration points of

Range E −400 ±75 +400 nA P PMU enabled, FIMI, PE disabled, error at calibration points of

Force Current Offset Tempco

Range A ±1 µA/°C CT Measured at calibration points Range B ±80 nA/°C CT Measured at calibration points Range C to Range E ±4 nA/°C CT Measured at calibration points

Forced Current Gain Error,

Nominal Gain = 1

Forced Current Gain Tempco Measured at calibration points

Range A −500 ppm/°C CT Range B to Range E ±75 ppm/°C CT

Force Current INL

Range A −0.3 ±0.05 +0.3 % FSR P PMU enabled, FIMI, PE disabled, after two-point gain/offset

Range B to Range E -0.2 ±0.015 0.2 % FSR P PMU enabled, FIMI, PE disabled, after two-point gain/offset

Force Current Compliance vs.

Voltage Load

Range A to Range D −0.6 ±0.06 +0.6 % FSR P Range E −1.0 +±0.1 +1.0 % FSR P

MEASURE VOLTAGE

Measure Voltage Range −2.0 +6.0 V D Measure Voltage Uncalibrated

Accuracy Measure Voltage Offset Tempco ±10 µV/°C CT Measured at calibration points Measure Voltage Gain Error −2 ±0.01 +2 % P PMU enabled, FVMV, Range B, PE disabled, gain error from

Measure Voltage Gain Tempco 25 ppm/°C CT Measured at calibration points Measure Voltage INL −7 ±1 +7 mV P PMU enabled, FVMV, Range B, PE disabled, after two-point

Rejection of Measure V vs. I

−2.0 +6.0 V D

−20 ±4 +20 % P PMU enabled, FIMI, PE disabled, gain error from calibration

PMU enabled, FIMV, PE disabled; force positive full-scale

−25 ±2.0 +25 mV P PMU enabled, FVMV, Range B, PE disabled, error at calibration

−1.5 ±0.1 +1.5 mV P PMU enabled, FVMV, Range D, PE disabled, force 0 V into load

DUTx

Test Level Conditions/Comments

externally forced to 0.0 V, unless otherwise specified

DUTx

Ideal force current transfer function: I

= (PMUDAC − 2.5) × (FSR/5)

FORCE

−20 mA and +20 mA

−1.6 mA and +1.6 mA

±80% FS

points of ±80% FS

calibration; measured over FSR output of

−25 mA to +25 mA

calibration; measured over FSR output

current driving −2.0 V and +6.0 V, measure I @ DUTx pin; force negative full-scale current driving −2.0 V and +6.0 V, measure I @ DUTx pin

points of 0 V and 5 V, error = (V

calibration points of 0 V and 5 V

gain/offset calibration; measured over output range of −2.0 V to +6.0 V

of −10 µA and +10 µA; measure V reported at MEASOUT01

MEASOUT01

− V

DUTx

)

Rev. 0 | Page 13 of 52

ADATE302-02

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Parameter Min Typ Max Unit

MEASOUT01 DC CHARACTERISTICS

MEASOUT01 Voltage Range −2.0 +6.0 V D DC Output Current 4 mA D MEASOUT01 Pin Output

Impedance

Output Leakage Current When

Tristated

Output Short-Circuit Current −25 +25 mA P PMU enabled, FVMV, PE disabled; source: PMU force 6.0 V,

VOLTAGE CLAMPS

Low Clamp Range (VCL) −2.0 +4.0 V D High Clamp Range (VCH) 0.0 6.0 V D Positive Clamp Voltage Droop −300 +50 +300 mV P PMU enabled, FIMI, Range A, PE disabled, PMU clamps

Negative Clamp Voltage Droop −300 −50 +300 mV P PMU enabled, FIMI, Range A, PE disabled, PMU clamps

Uncalibrated Accuracy −250 ±100 +250 mV P PMU enabled, FIMI, Range B, PE disabled, PMU damps enabled,

INL −70 ±5 +70 mV P PMU enabled, FIMI, Range B, PE disabled, PMU damps enabled,

DUTGND Voltage Accuracy ±1 mV CT Over ±0.1 V range; measured at end points of PMU clamp

SETTLING/SWITCHING TIMES SCAP = 330 pF, FFCAP = 220 pF

Voltage Force Settling Time to

0.1% of Final Value

Range A, 200 pF and

2000 pF Load

Range B, 200 pF and

2000 pF Load

Range C, 200 pF and

2000 pF Load

Range D, 200 pF and

2000 pF Load

Range E, 200 pF and

2000 pF Load

Voltage Force Settling Time to

1.0% of Final Value Range A, 200 pF and

2000 pF Load

Range B, 200 pF and

2000 pF Load

Range C, 200 pF and

2000 pF Load

Range D, 200 pF Load 8.1 µs CB Range D, 2000 pF Load 585 µs CB Range E, 200 pF Load 8.1 µs CB Range E, 2000 pF Load 590 µs CB

25 200 Ω P PMU enabled, FVMV, PE disabled; source resistance: PMU force

−1 +1 µA P Tested at −2.0 V and +6.0 V

PMU enabled, FV, PE disabled, program PMUDAC steps of

15 µs S

20 µs S

124 µs S

1015 µs S

3455 µs S

PMU enabled, FV, PE disabled, start with PMUDAC

8.0 µs CB

Test Level Conditions/Comments

6.0 V and load with 0 mA and 4 mA; sink resistance: PMU force

−2.0 V and load with 0 mA and −4 mA; resistance = V/I at MEASOUT01 pin

short MEASOUT01 to −2.0 V; sink: PMU force −2.0 V, short MEASOUT01 to 6.0 V

enabled, VCH = 5 V, VCL = −1 V, PMU force 1 mA and 25 mA into open; V seen at DUTx pin

enabled, VCH = 5 V, VCL = −1 V, PMU force −1 mA and −25 mA into open; V seen at DUTx pin

PMU force ±1 mA into open; VCH errors at calibration points of 0 V and 5 V; VCL errors at the calibration points of 0 V and 4 V

PMU force ±1 mA into open; after two-point gain/offset calibration; measured over PMU clamp range

functional range

500 mV and 5.0 V; simulation of worst case, 2000 pF load, PMUDAC step of 5.0 V

programmed to 0.0 V, program PMUDAC to 500 mV

Rev. 0 | Page 14 of 52

ADATE302-02

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Parameter Min Typ Max Unit

Voltage Force Settling Time to

1.0% of Final Value

Range A, 200 pF and

2000 pF Load Range B, 200 pF Load 4.4 µs CB Range B, 2000 pF Load 7.6 µs CB Range C, 200 pF Load 6.3 µs CB Range C, 2000 pF Load 8.1 µs CB Range D, 200 pF Load 130 µs CB Range D, 2000 pF Load 280 µs CB Range E, 200 pF Load 390 µs CB Range E, 2000 pF Load 605 µs CB

Current Force Settling Time to

0.1% of Final Value Range A, 200 pF in Parallel

with 120 Ω Range B, 200 pF in Parallel

with 1.5 kΩ Range C, 200 pF in Parallel

with 15.0 kΩ Range D, 200 pF in Parallel

with 150 kΩ Range E, 200 pF in Parallel

with 1.5 MΩ

Current Force Settling Time to

1.0% of Final Value Range A, 200 pF in Parallel

with 120 Ω Range B, 200 pF in Parallel

with 1.5 kΩ Range C, 200 pF in Parallel

with 15.0 kΩ Range D, 200 pF in Parallel

with 150 kΩ Range E, 200 pF in Parallel

with 1.5 MΩ

INTERACTION AND CROSSTALK

Measure Voltage Channel-to-

Channel Crosstalk

Measure Current Channel-to-

Channel Crosstalk

PMU enabled, FV, PE disabled, start with PMUDAC

4.2 µs CB

PMU enabled, FI, PE disabled, start with PMUDAC

8.2 µs S

9.4 µs S

30 µs S

281 µs S

2668 µs S

PMU enabled, FI, PE disabled, start with PMUDAC

3.3 µs CB

4.4 µs CB

8 µs CB

205 µs CB

505 µs CB

±0.125 % FSR CT PMU enabled, FIMV, PE disabled, Range B, forcing 0 mA into

±0.01 % FSR CT PMU enabled, FVMI, PE disabled, Range E, forcing 0 V into

Test Level Conditions/Comments

programmed to 0.0 V, program PMUDAC to 5.0 V

programmed to 0 current, program PMUDAC to FS current

0 V load; other channel: Range A, forcing a step of 0 mA to 25 mA into 0 V load; report V of MEASOUT01 pin under test;

0.125% × 8.0 V = 10 mV

0 mA current load; other channel: Range E, forcing a step of 0 V to 5 V into 0 mA current load; report V of MEASOUT01 pin under test; 0.01% × 5.0 V = 0.5 mV

EXTERNAL SENSE (PMUS_CHx)

Table 8.

Parameter Min Typ Max Unit

Voltage Range −2.0 +6.0 V D Input Leakage Current −20 +20 nA P Tested at −2.0 V and +6.0 V

Rev. 0 | Page 15 of 52

Test Level

Conditions/Comments

ADATE302-02

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DUTGND INPUT

Table 9.

Parameter Min Typ Max Unit

Input Voltage Range, Referenced to GND −0.1 +0.1 V D Input Bias Current 1 100 A P Tested at −100 mV and +100 mV

SERIAL PERIPHERAL INTERFACE

Table 10.

Parameter Min Typ Max Unit

Serial Input Logic High 1.8 VCC V PF Serial Input Logic Low 0 0.7 V PF Input Bias Current −10 +1 +10 A P Tested at 0.0 V and 3.3 V SCLK Clock Rate 50 MHz PF SCLK Pulse Width 9 ns CT SCLK Crosstalk on DUTx Pin 8 mV CB PE disabled, PMU FV enabled and forcing 0 V Serial Output Logic High VCC − 0.4 VCC V PF Sourcing 2 mA Serial Output Logic Low 0 0.8 V PF Sinking 2 mA Update Time 10 s D Maximum delay time required for the part to enter

Test Level

Conditions/Comments

a stable state after a serial bus command is loaded

Conditions/Comments

HVOUT DRIVER

Table 11.

Parameter Min Typ Max Unit

VHH BUFFER VHH = (VT + 1 V) × 2 + DUTGND

Voltage Range 5.9 V

Output High 13.5 V P VHH mode enabled, RCVx pins active, VHH level = full

Output Low 5.9 V P VHH mode enabled, RCVx pins active, VHH level = zero

Accuracy Uncalibrated −500 ±100 +500 mV P VHH mode enabled, RCVx pins active, V

Offset Tempco 1 mV/°C CT Measured at calibration points Resolution 1.21 1.5 mV PF VHH mode enabled, RCVx pins active, after two-point

INL −30 ±15 +30 mV P VHH mode enabled, RCVx pins active, after two-point gain/

DUTGND Voltage Accuracy ±1 mV CT Over ±0.1 V range; measured at end points of VHH

Output Resistance 1 10 Ω P VHH mode enabled, RCVx pins active, source: VHH = 10.0 V,

DC Output Current Limit Source 60 100 mA P VHH mode enabled, RCVx pins active, VHH = 10.0 V, short

DC Output Current Limit Sink −100 −60 mA P VHH mode enabled, RCVx pins active, VHH = 6.5 V, short

Rise Time (From VL or VH to

VHH)

Fall Time (From VHH to VL or VH) 23 ns CB VHH mode enabled, toggle RCVx pins, VHH = 13.5 V, VL =

Preshoot, Overshoot, and

Undershoot

175 ns CB VHH mode enabled, toggle RCVx pins, VHH = 13.5 V, VL =

±100 mV CB VHH mode enabled, toggle RCVx pins, VHH = 13.5 V, VL =

− 3.25 V D V

PLUS

Rev. 0 | Page 16 of 52

Test Level

Conditions/Comments

= 16.75 V nominal; in this condition,

PLUS

maximum = 13.5 V

V

HVOUT

scale, sourcing 15 mA

scale, sinking 15 mA

error

measured at calibration points of 7 V and 12 V

gain/offset calibration; range/number of DAC bits as measured at calibration points of 7 V and 12 V

offset calibration; measured over VHH range of 5.9 V to 13.5 V

functional range

= 0 mA and 15 mA; sink: VHH = 6.5 V, I

I

HVOUT

and −15 mA; V/I

HVOUT pin to 5.9 V, measure current

HVOUT pin to 14.1 V, measure current

VH = 3.0 V; 20% to 80%, for DATAx high and DATAx low

VH = 3.0 V; for DATAx high and DATAx low

HVOUT

= 0 mA

ADATE302-02

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Parameter Min Typ Max Unit

VL/VH BUFFER

Voltage Range −0.1 +6.0 V D Accuracy Uncalibrated −500 ±100 +500 mV P VHH mode enabled, RCVx pins inactive, error measured at

Offset Tempco 1 mV/°C CT Measured at calibration points Resolution 0.61 0.75 mV PF VHH mode enabled, RCVx pins inactive, after two-point

INL −20 ±4 +20 mV P VHH mode enabled, RCVx pins inactive, after two-point

DUTGND Voltage Accuracy ±2 mV CT Over ±0.1 V range; measured at end points of VH and VL,

Output Resistance 46 48 50 Ω P VHH mode enabled, RCVx pins inactive, source: VH = 3.0 V,

DC Output Current Limit Source 60 100 mA P VHH mode enabled, RCVx pins inactive, VH = 6.0 V, short

DC Output Current Limit Sink −100 −60 mA P VHH mode enabled, RCVx pins inactive, VL = −0.1 V, short

Rise Time (VL to VH) 10.0 ns CB VHH mode enabled, RCVx pins inactive, VL = 0.0 V,

Fall Time (VH to VL) 11.3 ns CB VHH mode enabled, RCVx pins inactive, VL = 0.0 V,

Preshoot, Overshoot, and

Undershoot

±54 mV CB VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,

Test Level Conditions/Comments

calibration points of 0 V and 5 V

gain/offset calibration; range/number of DAC bits as measured at calibration points of 0 V and 5 V

gain/offset calibration; measured over range of −0.1 V to +6.0 V

functional range

= 1 mA and 50 mA; sink: VL = 2.0 V, I

I

HVOUT

and −50 mA; V/I

HVOUT pin to −0.1 V, DATAx high, measure current

HVOUT pin to 6.0 V, DATAx low, measure current

VH = 3.0 V, toggle DATAx pins; 20% to 80%

toggle DATAx pins

HVOUT

= −1 mA

OVERVOLTAGE DETECTOR (OVD)

Table 12.

Parameter Min Typ Max Unit

DC CHARACTERISTICS

Programmable Voltage Range −3.0 +7.0 V D Accuracy Uncalibrated −200 +200 mV P OVD offset errors measured at programmed levels of

Hysteresis 112 mV CB

LOGIC OUTPUT CHARACTERISTICS

Off State Leakage 10 1000 nA P Disable OVD alarm, apply 3.3 V to OVD_CHx pin,

Maximum On Voltage @100 A 0.2 0.7 V P Activate alarm, force 100 A into OVD_CHx, measure

Propagation Delay 1.8 s CB For OVD high: DUTx = 0 V to 6 V swing, OVD_CHx high =

Test Level

Conditions/Comments

7.0 V and −3.0 V

measure leakage current

active alarm voltage

3.0 V, OVD_CHx low = −3.0 V; for OVD_CHx low: DUTx = 0 V to 6 V swing, OVD_CHx high = 7.0 V, OVD_CHx low = 3.0 V

16-BIT DAC MONITOR MUX

Table 13.

Parameter Min Typ Max Unit

DC CHARACTERISTICS

Programmable Voltage Range −2.5 +7.5 V D Output Resistance 16 kΩ CT PMUDAC = 0.0 V, FV, I = 0 A, 200 A; V/I

Test Level

Conditions/Comments

Rev. 0 | Page 17 of 52

ADATE302-02

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 14.

Parameter Rating

Supply Voltages

Positive Supply Voltage (VDD to GND) −0.5 V to +11.0 V Positive VCC Supply Voltage (VCC to GND) −0.5 V to +4.0 V Negative Supply Voltage (VSS to GND) −6.25 V to +0.5 V Supply Voltage Difference (VDD to VSS) −1.0 V to +16.5 V Reference Ground (DUTGND to GND) −0.5 V to +0.5 V AGND to DGND −0.5 V to +0.5 V VPLUS Supply Voltage (V

to GND) −0.5 V to +17.5 V

PLUS

Input Voltages

Input Common-Mode Voltage V Short-Circuit Voltage High Speed Input Voltage High Speed Differential Input Voltage

1

2

3

to VDD

SS

−3.0 V to +8.0 V 0 to VCC 0 to VCC

VREF −0.5 V to +5.5 V

DUTx I/O Pin Current

DCL Maximum Short-Circuit Current

4

±140 mA

Temperature

Operating Temperature, Junction 125°C Storage Temperature Range −65°C to +150°C

1

RL = 0 Ω, V

clamp modes).

2

DATAxP, DATAxN, RCVxP, RCVxN, under source R = 0 Ω.

3

DATAxP to DATAxN, RCVxP, RCVxN.

4

RL = 0 Ω, V

condition. ADATE302-02 must current limit and survive continuous short circuit.

continuous short-circuit condition (VH, VL, VT, high-Z, VCOM,

DUTx

= −3 V to +8 V; DCL current limit. Continuous short-circuit

DUTx

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 15. Thermal Resistance

Package Type θJA θ

Unit

JC

84-Ball CSP_BGA 31.1 0.51 °C/W

EXPLANATION OF TEST LEVELS

D Definition

S Design verification simulation

P 100% production tested

P

F

Characterized on tester

C

T

C

Characterized on bench

B

Functionally checked during production test

ESD CAUTION

Rev. 0 | Page 18 of 52

ADATE302-02

G

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1098765432

1

HVOUT PMUS_CH0

A

VPLUS

B

FFCAP_0B

C

OVD_CH0

D

FFCAP_0A VSS

E

AGND AGND

F

COMP_Q L0P

VSSO_0

(DRIVE)

SCAP0

AGND

VDD

COMP_QL0N COMP_VTT0

VSS AGND VDD VDD AGND VSS SCAP1

DATA0N VSS

DATA0P

RCV0N

RCV0P

DUT0

VDDO_0 (DRIVE)

VDD VDD VSS DATA1N AGND FFCAP_1B

VDDO_1 (DRIVE)

DUT1

VSSO_1

(DRIVE)

DATA1P VDD OVD_CH1

RCV1N VSS FFCAP_1A

RCV1P AGND AGND

COMP_VTT 1 COMP_Q L1N CO MP_QL1P

PMUS_CH1 TEMPSENSE

VDD/VDD_

TMPSNS

COMP_QH0P COMP_Q H0N AGND

H

AGND AGND

J

K

VREF_GND VREF AGND VCC SCLK SDOUT CS AGND DUTGND

AGND

VSS VDD VDD VSS AGND COMP_QH1N COMP_QH1P

RST SDIN DGND DAC16_MO N AG ND AGND AGND

Figure 2. Pin Configuration, Bottom Side (BGA Balls Are Visible)

Table 16. Pin Function Descriptions

BGA Designator Mnemonic Description

A1 TEMPSENSE Temperature Sense Output A2 PMUS_CH1 PMU External Sense Path Channel 1 A3 VSSO_1 (Drive) Driver Output Supply −5.75 V Channel 1 A4 DUT1 Device Under Test Channel 1 A5 VDDO_1 (Drive) Driver Output Supply +10.0 V Channel 1 A6 VDDO_0 (Drive) Driver Output Supply +10.0 V Channel 0 A7 DUT0 Device Under Test Channel 0 A8 VSSO_0 (Drive) Driver Output Supply −5.75 V Channel 0 A9 PMUS_CH0 PMU External Sense Path Channel 0 A10 HVOUT High Voltage Driver Output B1 VDD/VDD_TMPSNS Temperature Sense Supply +10.0 V B2 SCAP1 PMU Stability Capacitor Connection Channel 1 (330 pF)

Rev. 0 | Page 19 of 52

MEASOUT01/ TEMPSENSE

07278-002

ADATE302-02

www.BDTIC.com/ADI

BGA Designator Mnemonic Description

B3 VSS Supply −5.75 V B4 AGND Analog Ground B5 VDD Supply +10.0 V B6 VDD Supply +10.0 V B7 AGND Analog Ground B8 VSS Supply −5.75 V B9 SCAP0 PMU Stability Capacitor Connection Channel 0 (330 pF) B10 VPLUS Supply +16.75 V C1 FFCAP_1B PMU Feedforward Capacitor Connection B Channel 1 (220 pF) C2 AGND Analog Ground C3 DATA1N Driver Data Input (Negative) Channel 1 C4 VSS Supply −5.75 V C5 VDD Supply +10.0 V C6 VDD Supply +10.0 V C7 VSS Supply −5.75 V C8 DATA0N Driver Data Input (Negative) Channel 0 C9 AGND Analog Ground C10 FFCAP_0B PMU Feedforward Capacitor Connection B Channel 0 (220 pF) D1 OVD_CH1 Overvoltage Detection Flag Output Channel 1 D2 VDD Supply +10.0 V D3 DATA1P Driver Data Input (Positive) Channel 1 D8 DATA0P Driver Data Input (Positive) Channel 0 D9 VDD Supply +10.0 V D10 OVD_CH0 Overvoltage Detection Flag Output Channel 0 E1 FFCAP_1A PMU Feedforward Capacitor Connection A Channel 1 (220 pF) E2 VSS Supply −5.75 V E3 RCV1N Receive Data Input (Negative) Channel 1 E8 RCV0N Receive Data Input (Negative) Channel 0 E9 VSS Supply −5.75 V E10 FFCAP_0A PMU Feedforward Capacitor Connection A Channel 0 (220 pF) F1 AGND Analog Ground F2 AGND Analog Ground F3 RCV1P Receive Data Input (Positive) Channel 1 F8 RCV0P Receive Data Input (Positive) Channel 0 F9 AGND Analog Ground F10 AGND Analog Ground G1 COMP_QL1P Low-Side Comparator Output (Positive) Channel 1 G2 COMP_QL1N Low-Side Comparator Output (Negative) Channel 1 G3 COMP_VTT1 Comparator Supply Termination Channel 1 G8 COMP_VTT0 Comparator Supply Termination Channel 0 G9 COMP_QL0N Low-Side Comparator Output (Negative) Channel 0 G10 COMP_QL0P Low-Side Comparator Output (Positive) Channel 0 H1 COMP_QH1P High-Side Comparator Output (Positive) Channel 1 H2 COMP_QH1N High-Side Comparator Output (Negative) Channel 1 H3 AGND Analog Ground H4 VSS Supply −5.75 V H5 VDD Supply +10.0 V H6 VDD Supply +10.0 V H7 VSS Supply −5.75 V H8 AGND Analog Ground H9 COMP_QH0N High-Side Comparator Output (Negative) Channel 0 H10 COMP_QH0P High-Side Comparator Output (Positive) Channel 0 J1 AGND Analog Ground

Rev. 0 | Page 20 of 52

ADATE302-02

www.BDTIC.com/ADI

BGA Designator Mnemonic Description

J2 AGND Analog Ground J3 AGND Analog Ground J4 DAC16_MON 16-Bit DAC Monitor Mux Output J5 DGND Digital Ground J6 SDIN Serial Peripheral Interface (SPI) Data In J7 J8 AGND Analog Ground J9 AGND Analog Ground J10 AGND Analog Ground K1 MEASOUT01/TEMPSENSE

K2 DUTGND DUT Ground Reference K3 AGND Analog Ground K4

K5 SDOUT Serial Peripheral Interface (SPI) Data Out K6 SCLK Serial Peripheral Interface (SPI) Clock K7 VCC Supply +3.3 V K8 AGND Analog Ground K9 VREF +5 V DAC Reference Voltage K10 VREF_GND DAC Ground Reference

RST

CS

Serial Peripheral Interface (SPI) Reset

Muxed Output Shared by PMU MEASOUT Channel 0, PMU MEASOUT Channel 1, Temperature Sense and Temperature Sense GND Reference

Serial Peripheral Interface (SPI) Chip Select

Rev. 0 | Page 21 of 52

ADATE302-02

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TYPICAL PERFORMANCE CHARACTERISTICS

0.30

0.5V

0.25

0.20

0.15

VOLTAGE (V)

0.10

0.05

0

024681012141618

0.2V

TIME (ns)

Figure 3. Driver Small Signal Response;

VH = 0.2 V, 0.5 V; VL = 0.0 V; 50 Ω Termination

07278-080

1.8

1.6

1.4

1.2

1.0

0.8

0.6

VOLTAGE (V)

0.4

0.2

0

–0.2

024681012141618

TIME (ns)

Figure 6. 100 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V;

50 Ω Termination

07278-085

1.6

1.4

1.2

1.0

0.8

0.6

VOLTAGE (V)

0.4

0.2

0

–0.2

0 2 4 6 8 10 12 14 16 18

TIME (ns)

Figure 4. Driver Large Signal Response;

VH = 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V; 50 Ω Termination

6

5

4

3

2

VOLTAGE (V)

1

0

1.6

1.4

1.2

1.0

0.8

0.6

VOLTAGE (V)

0.4

0.2

0

–0.2

07278-079

123456789100

TIME (ns)

7278-084

Figure 7. 300 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V;

50 Ω Termination

1.6

1.4

1.2

1.0

0.8

VOLTAGE (V)

0.6

0.4

0.2

–1

024681012141618

TIME (ns)

7278-078

Figure 5. Driver Large Signal Response; VH = 1.0 V, 3.0 V, 5.0 V; VL = 0.0 V;

500 Ω Termination

Rev. 0 | Page 22 of 52

0

0987654321

TIME (ns)

07278-083

Figure 8. 400 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V;

50 Ω Termination

ADATE302-02

www.BDTIC.com/ADI

1.6

1.2

1.4

1.2

1.0

0.8

VOLTAGE (V)

0.6

0.4

0.2

0

0.51.01.52.02.53.03.54.04.55.0

TIME (ns)

07278-081

Figure 9. 500 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V;

50 Ω Termination

1.0

0.9

0.8

0.7

0.6

0.5

0.4

VOLTAGE (V)

0.3

0.2

0.1

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

TIME (ns)

7278-082

Figure 10. 600 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V; VL = 0.0 V;

50 Ω Termination

1.0

0.8

0.6

0.4

VOLTAGE (V)

0.2

0

–0.2

TIME (ns)

Figure 12. Driver Active (VH/VL) to/from VTERM Transition;

VH = 2.0 V; VT = 1.0 V; VL = 0.0 V

1.6

1.4

1.2

1.0

0.8

0.6

VOLTAGE (V)

0.4

0.2

0

–0.2

TIME (ns)

Figure 13. Driver Active (VH/VL) to/from VTERM Transition;

VH = 3.0 V; VT = 1.5 V; VL = 0.0 V

20181614121086420

7278-076

20181614121086420

07278-077

0.6

0.5

0.4

0.3

VOLTAGE (V)

0.2

0.1

0

024681012141618

TIME (ns)

07278-075

Figure 11. Driver Active (VH/VL) to/from VTERM Transition;

VH = 1.0 V; VT = 0.5 V; VL = 0.0 V

Rev. 0 | Page 23 of 52

10

0

–10

–20

–30

TRAILING EDGE ERROR (ps)

–40

–50

11

PULSE WIDTH (ns)

NEGATIVE PULSE

POSITIVE PULSE

0

07278-063

Figure 14. Driver Minimum Pulse Width;

VH = 0.2 V; VL = 0.0 V

ADATE302-02

www.BDTIC.com/ADI

10

0

–10

–20

–30

TRAILING EDGE ERROR (ps)

–40

–50

110

NEGATIVE PULSE

PULSE WIDTH (ns)

POSITIVE PULSE

07278-064

Figure 15. Driver Minimum Pulse Width;

0

–10

–20

–30

TRAILING EDGE ERROR (p s)

–40

–50

110

Figure 18. Driver Minimum Pulse Width;

VH = 0.5 V; VL = 0.0 V

10

0

NEGATIVE PULSE

–10

POSITIVE PULSE

–20

TRAILING EDGE ERROR (ps)

–30

110

PULSE WIDTH (ns)

07278-065

Figure 16. Driver Minimum Pulse Width;

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

LINEARITY ERROR (mV)

–2.0

–2.5

–3.0

–1 0 1 2 3 4 56

–2

Figure 19. Driver VH Linearity Error

VH = 1.0 V; VL = 0.0 V

NEGATIVE PULSE

PULSE WIDTH (ns)

VH = 3.0 V; VL = 0.0 V

DRIVER OUTPUT VOLTAGE (V)

POSITIVE PULSE

07278-067

07278-020

10

0

–10

–20

TRAILING EDGE ERRO R (ps)

–30

110

NEGATIVE PULSE

PULSE WIDTH (ns)

POSITIVE PULSE

07278-066

Figure 17. Driver Minimum Pulse Width;

VH = 2.0 V; VL = 0.0 V

Rev. 0 | Page 24 of 52

2.0

1.5

1.0

0.5

0

–0.5

–1.0

LINEARITY ERROR (mV)

–1.5

–2.0

–2.5

–1 0 1 2 3 4 56

–2

DRIVER OUTPUT VOLTAGE (V)

7278-021

Figure 20. Driver VL Linearity Error

ADATE302-02

www.BDTIC.com/ADI

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

LINEARITY ERROR (mV)

–2.0

–2.5

–3.0

–2–10123456

DRIVER OUTPUT VOLTAGE (V)

Figure 21. Driver VT Linearity Error

7278-022

INTERACTIO N ERROR (mV)

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

0.2

0

–2

–1 0 1 2 3 4 56

PROGRAMMED VH DAC L EVEL (V)

Figure 24. Driver Interaction Error;

VL = −2.0 V; VH Swept from −1.9 V to +6.0 V

7278-025

1.4

1.2

1.0

0.8

0.6

0.4

0.2

INTERACTIO N ERROR (mV)

0

–0.2

–1 0 1 2 3 4 56

–2

PROGRAMMED VL DAC LEVEL (V)

7278-023

Figure 22. Driver Interaction Error;

53

52

51

50

49

48

DRIVER OUTPUT RESISTANCE ( )

47

–60

–40 –20 0 20 40 60

DRIVER OUTPUT CURRENT (mA)

Figure 25. Driver Output Resistance vs. Output Current

07278-026

VH = 6.0 V; VL Swept from −2.0 V to +5.9 V

0.6

0.5

0.4

0.3

0.2

0.1

INTERACTIO N ERROR (mV)

0

120

100

80

60

40

DRIVER OUTPUT CURRENT (mA)

20

–0.1

–2–10123456

PROGRAMMED VH DAC L EVEL (V)

07278-024

Figure 23. Driver Interaction Error;

VT = 1.5 V; VH Swept from −1.9 V to +6.0 V

Rev. 0 | Page 25 of 52

0

–2 –1 0 1 2 3 4 56

V

(V)

DUTx

Figure 26. Driver Output Current Limit;

Driver Programmed to −2.0 V; V

Swept from −2.0 V to +6.0 V

DUTx

07278-027

ADATE302-02

www.BDTIC.com/ADI

0

–10

–20

–30

–40

–50

–60

–70

–80

DRIVER OUTPUT CURRENT (mA)

–90

–100

–2–10123456

Figure 27. Driver Output Current Limit;

Driver Programmed to 6.0 V; V

16

14

12

10

8

VOLTAGE (V)

6

4

2

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

V

(V)

DUTx

Swept from −2.0 V to +6.0 V

DUTx

TIME (µs)

Figure 28. HVOUT VHH Response;

VHH = 13.5 V

6

4

2

0

–2

–4

–6

LINEARITY ERROR (mV)

–8

–10

–12

07278-028

7 8 9 10 11 12 13 14

6

VHH PROGRAMMED VOLTAGE (V)

07278-038

Figure 30. HVOUT VHH Linearity Error

90

80

70

60

50

40

30

20

HVOUT DRIVER CURRENT (mA)

10

0

07278-086

0 1 2 3 4 56

–1

V

(V)

HVOUT

07278-040

Figure 31. HVOUT VH Current Limit;

VH = −0.1 V; V

Swept from −0.1 V to +6.0 V

HVOUT

3

2

1

0

–1

–2

LINEARITY ERROR (mV)

–3

–4

0123456

VL PROGRAMMED VOLT AGE (V)

07278-037

Figure 29. HVOUT VL Linearity Error

Rev. 0 | Page 26 of 52

100

80

60

40

20

0

–20

–40

HVOUT DRIVER CURRENT (mA)

–60

–80

5 6 7 8 9 10 11 12 13 14 15

V

(V)

HVOUT

Figure 32. HVOUT VHH Current Limit;

VHH = 10.0 V; V

Swept from 5.9 V to 14.1 V

HVOUT

07278-041

ADATE302-02

www.BDTIC.com/ADI

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

VOLTAGE (V)

0.3

0.2

0.1

0

–0.1

0 1.2 2.4 3.6 4.8 6.0

INPUT EDGE

TIME (ns)

SHMOO

Figure 33. Comparator Shmoo;

1.0 V Swing; 200 ps (10%/90%)

07278-089

30

INPUT VOLTAGE SWING = 1V COMPARATOR T HRESHOLD = 0. 5V

25

20

INPUT RISING EDGE

15

10

5

PROPAGATI ON DELAY VARI ATION (p s)

0

0.40.60.81.0

INPUT SL EW RATE [ 10%/90%] (n s)

Figure 36.Comparator Slew Rate Dispersion

INPUT FALLING EDGE

07278-087

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

VOLTAGE (V)

0.3

0.2

0.1

0

–0.1

0 1.2 2.4 3.6 4.8 6.0

INPUT EDGE

SHMOO

TIME (ns)

Figure 34. Comparator Shmoo;

7278-090

0.8

0.7

0.6

0.5

0.4

VOLTAGE (V)

0.3

0.2

0.1

0

1.38

2.76

Figure 37. Comparator Output Waveform; COMP_QH0P, COMP_QH0N

1.0 V Swing; 200 ps (10%/90%)

10

0

POSITIVE PUL SE

–10

NEGATIVE PULSE

–20

TRAILING EDGE ERROR (p s)

–30

110

PULSE WIDTH (ns)

07278-091

Figure 35. Comparator Minimum Pulse Width Input;

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

LINEARITY ERROR (mV)

–1.2

–1.4

–1.6

–2–10123456

PROGRAM THRESHOLD VOLTAGE (V)

Figure 38. Comparator Threshold Linearity

1.0 V Swing; 200 ps (10%/90%)

4.14

COMP_QH0P

COMP_QH0N

5.52

6.90

8.28

9.66

TIME (ns)

11.00

12.40

13.80

15.20

16.60

17.90

19.30

07278-088

7278-029

Rev. 0 | Page 27 of 52

ADATE302-02

www.BDTIC.com/ADI

0.2

8

0

–0.2

–0.4

–0.6

–0.8

DIFFERENTIAL COMPARATOR OFFSET (mV)

–1.0

–1 0 1 2 3 45

–2

INPUT COMMON-MODE VOLTAGE (V)

Figure 39. Differential Comparator CMRR

3

DRIVER ACTIVE LOW (VL) TO/FRO M FULL LOAD CURRENT

0

–3

–6

–9

LOAD CURRENT (mA)

–12

FULL LO AD CURRENTTO/ FROM

–15

0 102030405

DRIVER ACTIVE LOW (VL)

TIME (ns)

Figure 40. Active Load Response

7278-030

0

07278-092

6

4

2

0

–2

LINEARITY ERROR (µA)

–4

–6

0

2 4 6 8 10 12

ACTIVE LO AD CURRENT (mA)

Figure 42. Active Load Current Linearity

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

LINEARITY ERROR (mV)

–0.8

–1.0

–1.2

–2–10123456

VCOM VOLTAGE (V)

Figure 43. Active Load VCOM Linearity

7278-032

07278-033

15

10

5

0

–5

LOAD CURRENT (mA)

–10

–15

–2–10123456

V

(V)

DUTx

07278-031

Figure 41. Active Load Commutation Response;

VCOM = 2.0 V; IOH = IOL = 12 mA

Rev. 0 | Page 28 of 52

5.5

5.0

4.5

(nA)

4.0

DUTx

I

3.5

3.0

2.5 –2–10123456

V

(V)

DUTx

Figure 44. DUTx Pin Leakage Current in Low Leakage Mode

07278-034

ADATE302-02

www.BDTIC.com/ADI

6

4

2

(nA)

0

DUTx

I

–2

–4

–6

–2 –1 0 1 2 3 4 56

V

(V)

DUTx

Figure 45. DUTx Pin Leakage Current in High-Z Mode

07278-035

30

20

10

0

–10

–20

–30

–40

LINEARITY ERROR (µA)

–50

–60

–70

–30

–20 –10 0 10 20 30

PMU OUTPUT CURRENT (mA)

Figure 48. PMU Force Current Range A Linearity

07278-043

LINEARITY ERROR (µA)

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–1.5 –1.0 –0. 5 0 0.5 1.0 1.5 2.0

–2.0

PMU OUTPUT CURRENT (mA)

Figure 49. PMU Force Current Range B Linearity

0.04

0.03

0.02

0.01

0

–0.01

–0.02

–0.03

–0.04

–0.05

–0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20

–0.20

PMU OUTPUT CURRENT (mA)

Figure 50. PMU Force Current Range C Linearity

07278-044

07278-045

0.5

0.4

0.3

0.2

0.1

0

ERROR VOLT AGE (mV)

–0.1

–0.2

–0.3

–0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20

–0.20

ERROR (mV)

07278-039

Figure 46. DUTGND Voltage Effects

0.4

0.2

0

–0.2

–0.4

–0.6

LINEARITY ERROR (mV)

–0.8

–1.0

–1.2

–2 –1 0 1 2 3 4 5 67

–3

PMU OUTPUT V OLTAGE (V)

7278-042

Figure 47. PMU Force Voltage Linearity

Rev. 0 | Page 29 of 52

ADATE302-02

www.BDTIC.com/ADI

0.004

0.003

0.002

0.001

0

–0.001

–0.002

LINEARITY ERROR (µA)

–0.003

–0.004

–0.005

–0.020 –0.015 –0. 010 –0.005 0 0.005 0.010 0.015 0.020

PMU OUTPUT CURRENT ( mA)

Figure 51. PMU Force Current Range D Linearity

7278-046

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

PMU VOLTAGE ERROR (mV)

–0.4

–0.5

–0.6

–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0

I

(mA)

DUTx

07278-049

Figure 54. PMU Force Voltage Range B Output Voltage Error at −2.0 V vs.

Output Current

0.0004

0.0002

0

–0.0002

–0.0004

LINEARITY ERROR (µA)

–0.0006

–0.0008

–0.0020 –0.0015 –0.0010 –0.0005 0 0.0005 0.0010 0. 0015 0. 0020

PMU OUTPUT CURRENT (mA)

Figure 52. PMU Force Current Range E Linearity

0.6

0.4

0.2

0

4

3

2

1

0

–1

–2

PMU VOLTAG E ERROR (mV)

–3

–4

–25

–20 –15 –10 –5 0 5 10 15 20 25

I

07278-047

DUTx

(mA)

07278-050

Figure 55. PMU Force Voltage Range A Output Voltage Error at 6.0 V vs.

Output Current

4

3

2

1

0

–0.2

PMU VOLTAGE ERROR (mV)

–0.4

–0.6

–2.0

–1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0

I

(mA)

DUTx

07278-048

Figure 53. PMU Force Voltage Range B Output Voltage Error at 6.0 V vs.

Output Current

Rev. 0 | Page 30 of 52

–1

–2

PMU VOLTAG E ERROR (mV)

–3

–4

–25 –20 –15 –10 –5 0 5 10 15 20 25

I

(mA)

DUTx

Figure 56. PMU Force Voltage Range A Output Voltage Error at −2.0 V vs.

Output Current

07278-051

ADATE302-02

www.BDTIC.com/ADI

2

1.0

0

–2

–4

–6

PMU CURRENT ERROR (µ A)

–8

–10

–2–10123456

V

(V)

DUTx

07278-052

Figure 57. PMU Force Current Range A Output Current Error at −25 mA vs.

Output Voltage

10

0

–10

–20

–30

–40

PMU CURRENT ERROR (µA)

–50

0.8

0.6

0.4

0.2

0

PMU CURRENT ERROR ( µA)

–0.2

–0.4

–2

–1 0 1 2 3 4 56

V

(V)

DUTx

Figure 60. PMU Force Current Range B Output Current Error at 2 mA vs.

Output Voltage; Output Voltage Is Pulled Externally

0.004

0.003

0.002

0.001

0

PMU CURRENT ERROR (µ A)

–0.001

07278-055

–60

–2–10123456

V

(V)

DUTx

Figure 58. PMU Force Current Range A Output Current Error at 25 mA vs.

Output Voltage; Output Voltage Is Pulled Externally

1.0

0.8

0.6

0.4

0.2

0

–0.2

PMU CURRENT ERROR (µA)

–0.4

–0.6

–2–10123456

V

(V)

DUTx

Figure 59. PMU Force Current Range B Output Current Error at −2 mA vs.

Output Voltage; Output Voltage Is Pulled Externally

–0.002

–2–10123456

V

(V)

07278-053

DUTx

07278-056

Figure 61. PMU Force Current Range E Output Current Error at −2 μA vs.

Output Voltage; Output Voltage Is Pulled Externally

0.0035

0.0030

0.0025

0.0020

0.0015

0.0010

0.0005

PMU CURRENT ERROR (µA)

0

–0.0005

–0.0010

–2–10123456

V

(V)

07278-054

DUTx

07278-057

Figure 62. PMU Force Current Range E Output Current Error at 2 μA vs.

Output Voltage; Output Voltage Is Pulled Externally

Rev. 0 | Page 31 of 52

ADATE302-02

V

www.BDTIC.com/ADI

40

0.20

30

20

10

0

–10

PMU CURRENT (mA)

–20

–30

–40

–2–10123456

V

(V)

DUTx

07278-058

Figure 63. PMU Range A Internal Current Limit, Programmed to Force 2.5 V;

Swept from −2.0 V to +6.0 V

V

DUTx

0.003

0.002

0.001

0

–0.001

PMU CURRENT (mA)

–0.002

0.15

0.10

0.05

0

LINEARITY ERROR (µA)

–0.05

–0.10

–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2. 0

I

(mA)

DUTx

Figure 66. PMU Range B Measure Current Linearity

0.7

0.6

0.5

0.4

0.3

0.2

PMU VOLTAG E ERROR (mV)

0.1

07278-061

–0.003

–2–10123456

V

(V)

DUTx

07278-059

Figure 64. PMU Range E Internal Current Limit, Programmed to Force 2.5 V;

V

Swept from −2.0 V to +6.0 V

DUTx

0.05

0.04

0.03

0.02

0.01

0

–0.01

LINEARITY ERROR (mV)

–0.02

–0.03

–0.04

–2–10123456

V

(V)

DUTx

07278-060

Figure 65. PMU Range B Measure Voltage Linearity

0

–2–1012345

V

(V)

DUTx

Figure 67. PMU Measure Current CMRR, Externally Pulling 1 mA, FVMI;

Error of MI vs. External 1 mA

100mV/DI

1ns/DIV

07278-068

Figure 68. Eye Diagram, 200 Mbps, PRBS31;

VH = 1.0 V; VL = 0.0 V

07278-062

Rev. 0 | Page 32 of 52

ADATE302-02

V

V V

V

www.BDTIC.com/ADI

100mV/DI

500ps/DIV

Figure 69. Eye Diagram, 400 Mbps, PRBS31;

VH = 1.0 V; VL = 0.0 V

199.5mV/DI

500ps/DIV

Figure 70. Eye Diagram, 400 Mbps, PRBS31;

VH = 2.0 V; VL = 0.0 V

199.5mV/DI

07278-069

200ps/DIV

07278-072

Figure 72. Eye Diagram, 800 Mbps, PRBS31;

VH = 2.0 V; VL= 0.0 V

100mV/DI

07278-070

200ps/DIV

07278-073

Figure 73. Eye Diagram, 1000 Mbps, PRBS31;

VH = 1.0 V; VL = 0.0 V

100mV/DI

200ps/DIV

07278-071

Figure 71. Eye Diagram, 800 Mbps, PRBS31;

VH = 1.0 V; VL = 0.0 V

Rev. 0 | Page 33 of 52

199.5mV/DI

200ps/DIV

07278-074

Figure 74. Eye Diagram, 1000 Mbps, PRBS31;

VH = 2.0 V; VL = 0.0 V

ADATE302-02

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SERIAL PERIPHERAL INTERFACE DETAILS

t

CH

SCLK

t

CL

t

CSHD

t

CSSD

t

CSW

CS

t

CSHA

t

CSSA

t

DS

DH

SDIN

SDOUT

DO_15

DATA[14]DATA[15]

LAST

DO_14

LAST

CH[1] R/W

DO_13

LAST

t

DO

DO_12

LAST

ADDR[1] ADDR[0]

DO_2

LAST

DO_1

LAST

DO_0

LAST

Figure 75. SPI Timing Diagram

Table 17. Serial Peripheral Interface Timing Requirements

Symbol Parameter Min Max Unit

tCH SCLK minimum high 9.0 ns tCL SCLK minimum low 9.0 ns t

CSHA

t

CSSA

t

CSHD

t

CSSD

t

SDIN hold 3.0 ns

DH

t

SDIN setup 3.0 ns

DS

t

SDOUT Data Out 15.0 ns

DO

t

CSW

t

CSTP

assert hold

CS

assert setup

CS

deassert hold

CS

deassert setup

CS

1

minimum between assertions

CS

minimum directly after a read request

CS Minimum delay after CS

stopped (not shown in ); this allows any internal

is deasserted before SCLK can be

Figure 75

3.0

ns ns ns ns

2 SCLK cycles 3

SCLK cycles

16 SCLK cycles

operations to complete

1

Extra cycle is needed after read request to prime read data into SPI shift register.

07278-003

Rev. 0 | Page 34 of 52

ADATE302-02

5

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DEFINITION OF SPI WORD

The SPI can take variable length words, depending on the operation. At most, the word is 24 bits longs: 16 bits of data, two channel selects, one R/W selector, and a 5-bit address.

Depending on the operation, the data can be smaller (or nonexistent in the case of a read operation).

Example 1

Write 16 bits of data to a register or DAC; unused MSBs are ignored. For example, Bit 15 and Bit 14 are ignored, while Bit 13 through Bit 0 are applied to the 14-bit DAC.

DATA[15:0] CH[1:0] R/W ADDR[4:0]

Figure 76.

07278-004

Example 2

Write 14 bits of data to the DAC.

DATA[13:0] CH[1:0] R/W ADDR[4:0]

Figure 77.

07278-00

Example 3a

Write two bits of data to the 2-bit register.

DATA[1:0] CH[1:0] R/W ADDR[4:0]

Figure 78.

07278-006

Example 3b

Write two bits of data to the 2-bit register. Bit 15 through Bit 2 are ignored, while Bit 1 through Bit 0 are applied to the register.

DATA[15:0] CH[1:0] R/W ADDR[4:0]

Figure 79.

07278-007

Example 4

Read request and follow with a 2nd instruction (could be NOP) to clock out the data.

CH[1:0] R/W = 0 ADDR[4:0]

DATA[15:0] CH[1:0] R/W ADDR[4:0]

Figure 80.

07278-008

Table 18. Channel Selection

Channel 1 Channel 0 Channel Selected

0 0 NOP (no channel selected, no register changes) 0 1 Channel 0 selected 1 0

Channel 1 selected

1 1 Channel 0 and Channel 1 selected

Table 19. R/W Definition

R/W Description

0 Current register specified by address is shifted out of SDOUT on next shift operation 1 Current data is written to register specified by address and channel select

Rev. 0 | Page 35 of 52

ADATE302-02

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WRITE OPERATION

CS

INPUT

SCLK

INPUT

SDIN

INPUT

SDOUT

OUTPUT

R/W = 1

DATA[15] DATA[14] DATA[13]

0 232221201918171615141312 24 25

DATA[2] DATA[1] DATA[0] CH[ 1] C H[0 ]

ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]

X

XR/W

07278-009

Figure 81. 16-Bit SPI Write

CS

INPUT

SCLK

INPUT

SDIN

INPUT

SDOUT

OUTPUT

R/W = 1

DATA[1] DATA[0 ] C H[1 ] CH[ 0] ADDR[4 ] ADDR[3] ADDR[2] ADD R[1] ADDR[0 ]R/W

0 1110987654123

X

Figure 82. 2-Bit SPI Write

X

07278-010

Rev. 0 | Page 36 of 52

ADATE302-02

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READ OPERATION

The read operation is a two-stage operation. First, a word is

CS

shifted in, specifying which register to read. three clock cycles, and then a second word is shifted in to get the readback data. This second word can be either another operation or an NOP address. If another operation is shifted in, it needs to shift in at least eight bits of data to read back the

CS

INPUT

SCLK

INPUT

is deasserted for

previous specified data. The NOP address can be used for this read if there is no need to write/read another register. It is strongly recommended that the NOP address be used for all reads for clarity of operations.

Any register read that is less than 16 bits has zeros filled in the top bits to make it a 16-bit word.

SDIN

INPUT

SDOUT

OUTPUT

X READ DAT A X

XXREAD INSTRUCTI ON NOP

07278-011

Figure 83. SPI Read Overview

CS

INPUT

SCLK

INPUT

SDIN

INPUT

SDOUT

OUTPUT

DATA[15:0], VALUE IS A DON’ T CARE

0 2524232221201918171615141312

CH[1]

X

ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]

R/WCH[ 0]

X

7278-012

Figure 84. SPI Read—Details of Read Request

CS

INPUT

SCLK

INPUT

SDIN

INPUT

SDOUT

OUTPUT

RDATA IS THE REG ISTER VALUE BEING READ.

DATA[15:0], VAL UE IS A DON’T CARE

0 2524232221201918171615141312

RDATA[15]

RDATA[14]

CH[1]

RDATA[2] RDATA[1] RDATA[0]

Figure 85. SPI Read—Details of Read Out

Rev. 0 | Page 37 of 52

CH[0]

R/W = 1

ADDR[4:0] = 0x00 (NOP )

X

07278-013

ADATE302-02

K

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RESET OPERATION

The ADATE302-02 contains an asynchronous reset feature. The ADATE302-02 can be reset to the default values shown in Tab l e 20 by

RST

utilizing the

pin. To initiate the reset operation, deassert the

of two SCLK cycles.

RST

CS

SCL

MINIMUM O F TWO S CLK EDGES AFTER ASSERTI NG RST BEFO RE RESUMING NORMAL OPERATION.

RST

pin for a minimum of 100 ns and deassert the CS pin for a minimum

100ns

MINIMUM

Figure 86. Reset Operation

07278-093

Rev. 0 | Page 38 of 52

ADATE302-02

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REGISTER MAP

The ADDR[4:0] bits determine the destination register of the data being written to the ADATE302-02.

Table 20. Register Selection

DATA[15:0] CH[1:0] R/W ADDR[4:0] Register Selected Reset State

N/A N/A N/A 0x00 NOP N/A DATA[13:0] CH[1:0] R/W 0x01 VH DAC level 4096d DATA[13:0] CH[1:0] R/W 0x02 VL DAC level 4096d DATA[13:0] CH[1:0] R/W 0x03 VT/VCOM DAC level 4096d DATA[13:0] CH[1:0] R/W 0x04 VOL DAC level 4096d DATA[13:0] CH[1:0] R/W 0x05 VOH DAC level 4096d DATA[13:0] CH[1:0] R/W 0x06 VCH DAC level 4096d DATA[13:0] CH[1:0] R/W 0x07 VCL DAC level 4096d DATA[13:0] CH[1:0] R/W 0x08 V(IOH ) DAC level 4096d DATA[13:0] CH[1:0] R/W 0x09 V(IOL ) DAC level 4096d DATA[13:0] CH[1] R/W 0x0A OVD high level 4096d DATA[13:0] CH[0] R/W 0x0A OVD low level 4096d DATA[15:0] CH[1:0] R/W 0x0B PMUDAC level 16384d DATA[2:0] CH[1:0] R/W 0x0C PE/PMU enable 000b DATA[2:0] CH[1:0] R/W 0x0D Channel state 000b DATA[9:0] CH[1:0] R/W 0x0E PMU state 0d DATA[2:0] CH[1:0] R/W 0x0F PMU measure enable 000b DATA[0] CH[1:0] R/W 0x10 Differential comparator enable 0b DATA[1:0] CH[1:0] R/W 0x11 16-bit DAC monitor 00b DATA[1:0] CH[1:0] R/W 0x12 OVD_CHx alarm mask 01b DATA[2:0] CH[1:0] R 0x13 OVD_CHx alarm state N/A N/A N/A N/A 0x14 to 0x1F Reserved N/A

Rev. 0 | Page 39 of 52

ADATE302-02

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DETAILS OF REGISTERS

Table 21. PE/PMU Enable (ADDR[4:0] = 0x0C)

Bit Name Description

DATA[2] PMU enable

DATA[1] Force VT

DATA[0] PE disable

Table 22. Channel State (ADDR[4:0] = 0x0D)

Bit Name Description

DATA[2] HVOUT mode select

DATA[1] Load enable

DATA[0] Driver high-Z/VT

0 = disable PMU force output and clamps, place PMU in MV mode 1 = enable PMU force output When set to 0, the PMU State bits are ignored, except for PMU Sense Path (DATA[7]).

0 = normal driver operation 1 = force driver to VT See Tab le 29 for complete functionality of this bit.

0 = enable driver functions 1 = disable driver (low leakage) See Tab le 29 for complete functionality of this bit.

0 = HVOUT driver in low impedance 1 = enable HVOUT driver

This bit affects Channel 0 only. Ensure that Channel 0 bit in SPI write is active. Channel 1 bit in SPI write is don’t care.

0 = disable load 1 = enable load See Tab le 29 for complete functionality of this bit.

0 = enable driver high-Z function 1 = enable driver VTERM function See Tab le 29 for complete functionality of this bit.

Table 23. PMU State (ADDR[4:0] = 0x0E)

Bit Name Description

DATA[9:8] PMU input selection

DATA[7] PMU sense path

DATA[6] Reserved DATA[5] PMU clamp enable

DATA[4] PMU measure V/I

DATA[3] PMU force V/I

DATA[2:0] PMU range

1

Note that when the ADDR[4:0] = 0x0C PMU enable bit (DATA[2]) = 0, the PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage

mode. DATA[9:8] and DATA[6:0] of the PMU state register are ignored, and only DATA[7], the PMU sense path bit, is valid.

2

X = don’t care.

1, 2

00 = V 01 = 2.5 V + V 1X = PMUDAC

0 = internal sense 1 = external sense

0 = disable clamps 1 = enable clamps

0 = measure voltage mode 1 = measure current mode

0 = force voltage mode 1 = force current mode

0XX = Range E (2 A) 100 = Range D (20 A) 101 = Range C (200 A) 110 = Range B (2 mA) 111 = Range A (25 mA)

(calibrated for 0.0 V voltage reference)

DUTGND

(calibrated for 0.0 A current reference)

DUTGND

Rev. 0 | Page 40 of 52

ADATE302-02

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Table 24. PMU Measure Enable (ADDR[4:0] = 0x0F)1

Bit Name Description

DATA[2:1] MEASOUT01 select

DATA[0] MEASOUT01 output enable

1

This register is written to or read from if either of the CH[1:0] bits is 1.

Table 25. Differential Comparator Enable (ADDR[4:0] = 0x10)1

Bit Name Description

DATA[0] Differential comparator enable

1

This register is written to or read from if either of the CH[1:0] bits is 1.

Table 26. DAC16_MON (16-Bit DAC Monitor) (ADDR[4:0] = 0x11)1

Bit Name Description

DATA[1] 16-bit DAC mux enable 0 = 16-bit DAC mux is tristated

DATA[0] 16-bit DAC mux select

1

This register is written to or read from if either of the CH[1:0] bits is 1.

00 = PMU MEASOUT Channel 0 01 = PMU MEASOUT Channel 1 10 = Temp sensor ground reference 11 = Temp sensor

0 = MEASOUT01 is tristated 1 = MEASOUT01 is enabled

0 = differential comparator is disabled, Channel 0 normal window comparator (NWC) outputs are on Channel 0 1 = differential comparator is enabled, the differential comparator outputs are on Channel 0

1 = 16-bit DAC mux is enabled 0 = 16-bit DAC Channel 0

1 = 16-bit DAC Channel 1

Table 27. OVD_CHx Alarm Mask (ADDR[4:0] = 0x12)

Bit Name Description

DATA[1] PMU mask

DATA[0] OVD mask

0 = disable PMU alarm flag 1 = enable PMU alarm flag

0 = disable OVD alarm flag 1 = enable OVD alarm flag

Table 28. OVD_CHx Alarm State (ADDR[4:0] = 0x13)1

Bit Name Description

DATA[2] PMU clamp flag

DATA[1] OVD high flag

DATA[0] OVD low flag

1

This register is a read-only register.

0 = PMU not clamped 1 = PMU clamped

0 = DUT voltage < OVD high voltage 1 = DUT voltage > OVD high voltage

0 = DUT voltage > OVD low voltage 1 = DUT voltage < OVD low voltage

Rev. 0 | Page 41 of 52

ADATE302-02

www.BDTIC.com/ADI

USER INFORMATION

Table 29. Driver and Load Truth Table1

Registers Signals

PE Disable DATA[0] ADDR[4:0] = 0x0C

1 X X X X X

0 1 X X X X VT Power-down 0 0 0 0 0 0 VL Power-down 0 0 0 0 0 1

0 0 0 0 1 0 VH Power-down 0 0 0 0 1 1

0 0 0 1 0 0 VL Power-down 0 0 0 1 0 1 VT Power-down 0 0 0 1 1 0 VH Power-down 0 0 0 1 1 1 VT Power-down 0 0 1 0 0 0 VL Active off 0 0 1 0 0 1

0 0 1 0 1 0 VH Active off 0 0 1 0 1 1

0 0 1 1 0 0 VL Active on 0 0 1 1 0 1

0 0 1 1 1 0 VH Active on 0 0 1 1 1 1

1

X = don’t care.

Force VT DATA[1] ADDR[4:0] = 0x0C

Load Enable DATA[1] ADDR[4:0] = 0x0D

Driver High-Z/VT DATA[0] ADDR[4:0] = 0x0D

DATAx RCVx

Driver State Load State

High-Z without

Power- down

clamps

High-Z with

Power- down

clamps

High-Z with

Power- down

clamps

High-Z with

Active on

clamps

High-Z with

Active on

clamps

High-Z with

Active on

clamps

High-Z with

Active on

clamps

Table 30. HVOUT Truth Table1

HVOUT Mode Select DATA[2] ADDR[4:0] = 0x0D

Channel 0 RCV

Channel 0 DATA HVOUT Driver Output

1 1 X VHH mode; VHH = (VT + 1 V) × 2 + DUTGND (Channel 0 VT DAC) 1 0 0 VL (Channel 0 VL DAC) 1 0 1 VH (Channel 0 VH DAC) 0 X X Disabled (HVOUT pin set to 0 V low impedance)

1

X = don’t care.

Table 31. Comparator Truth Table

Differential Comparator Enable

DATA[0] ADDR[4:0] = 0x10 COMP_QH0 COMP_QL0 COMP_QH1 COMP_QL1

0 Normal window mode

Logic high: VOH0 < V Logic low: VOH0 > V

DUT0

1 Differential comparator mode

Logic high: VOH0 < V Logic low: VOH0 > V

DUT0

− V

Normal window mode Logic high: VOL0 < V Logic low: VOL0 > V Differential comparator mode Logic high: VOL0 < V

DUT1

Logic low: VOL0 > V

DUT1

Rev. 0 | Page 42 of 52

DUT0

− V

Normal window mode Logic high: VOH1 < V Logic low: VOH1 > V Normal window mode Logic high: VOH1 < V

DUT1

Logic low: VOH1 > V

DUT1

Normal window mode Logic high: VOL1 < V

DUT1

Logic low: VOL1 > V

DUT1

Normal window mode Logic high: VOL1 < V

DUT1

Logic low: VOL1 > V

DUT1

ADATE302-02

www.BDTIC.com/ADI

DETAILS OF DACs vs. LEVELS

There are ten 14-bit DACs per channel. These DACs provide levels for the driver, comparator, load currents, VHH buffer, OVD, and clamp levels. There are three versions of output levels:

• −2.5 V to +7.5 V; tracks DUTGND. Controls VH, VL,

VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels.

• −3.0 V to +7.0 V; tracks DUTGND. Controls OVD levels.

• −2.5 V to +7.5 V; does not track DUTGND. Controls IOH

and IOL levels.

Table 32. Level Transfer Functions

DAC Transfer Function

V

= 2.0 × (V

OUT

Code = [V V

= 4.0 × (V

OUT

Code = [V V

= 2.0 × (V

OUT

Code = [V I

= [2.0 × (V

OUT

Code = [(I V

= 2.0 × (V

OUT

Code = [V I

= [2.0 × (V

OUT

Code = [(I I

= [2.0 × (V

OUT

Code = [(I I

= [2.0 × (V

OUT

Code = [(I I

= [2.0 × (V

OUT

Code = [(I I

= [2.0 × (V

OUT

Code = [(I

− V

REF

− V

OUT

DUTGND

− V

REF

− V

OUT

DUTGND

− V

REF

− V

OUT

DUTGND

− V

REF

× (5.0/0.012)) + 0.5 × (V

OUT

− V

REF

− V

OUT

DUTGND

− V

REF

× (5.0/0.050)) + 2.5 + 0.5 × (V

OUT

− V

REF

× (5.0/0.004)) + 2.5 + 0.5 × (V

OUT

− V

REF

× (5.0/0.0004)) + 2.5 + 0.5 × (V

OUT

− V

REF

× (5.0/0.00004)) + 2.5 + 0.5 × (V

OUT

− V

REF

× (5.0/0.000004)) + 2.5 + 0.5 × (V

OUT

) × (Code/(214)) − 0.5 × (V

REF_GND

+ 0.5 × (V

REF_GND

− V

REF

) × (Code/(214)) − 1.0 × (V

− 2.0 + 1.0 × (V ) × (Code/(214)) − 0.6 × (V

REF_GND

+ 0.6 × (V

) × (Code/(214)) − 0.5 × (V

REF_GND

+ 0.5 × (V

) × (Code/(216)) − 0.5 × (V

REF_GND

) × (Code/(216)) − 0.5 × (V

REF_GND

) × (Code/(216)) − 0.5 × (V

REF_GND

) × (Code/(216)) − 0.5 × (V

REF_GND

) × (Code/(216)) − 0.5 × (V

REF_GND

− V

REF

) × (Code/(216)) − 0.5 × (V

− V

REF

)] × [(214)/(2.0 × (V

REF_GND

− V

REF_GND

)] × [(214)/(2.0 × (V

REF_GND

− V

REF_GND

)] × [(216)/(2.0 × (V

REF_GND

− V

REF

− V

REF

− V

REF

− V

REF

− V

REF

− V

REF

REF_GND

REF

− V

REF

REF_GND

)] × [(214)/(4.0 × (V

− V

REF

REF_GND

REF

− V

REF

REF_GND

)] × [(214)/(2.0 × (V

− V

REF

REF_GND

REF

− V

REF

REF_GND

)] × [(216)/(2.0 × (V

REF_GND

− V

REF

REF_GND

)] × [(216)/(2.0 × (V

REF_GND

− V

REF

REF_GND

)] × [(216)/(2.0 × (V

REF_GND

− V

REF

REF_GND

)] × [(216)/(2.0 × (V

REF_GND

− V

REF

REF_GND

)] × [(216)/(2.0 × (V

REF_GND

) + V

− V

) + 2.0 + V

) + V

− V

)] × (0.012/5.0)

REF

) + V

− V

) − 2.5] × (0.050/5.0)

) − 2.5] × (0.004/5.0)

) − 2.5] × (0.0004/5.0)

) − 2.5] × (0.00004/5.0)

) − 2.5] × (0.000004/5.0)

There is one 16-bit DAC per channel. This DAC provides the levels for the PMU. The output level is:

• −2.5 V to +7.5 V; tracks DUTGND. Controls PMU levels.

Programmable Range

1

(All 0s to All 1s) Levels

DUTGND

REF_GND

− V

REF

DUTGND

REF_GND

))]

DUTGND

REF_GND

))]

−2.5 V to +7.5 V

VH, VL, VT/VCOM, VOL, VOH, VCH, VCL

−3.0 V to +17.0 V VHH

−3.0 V to +7.0 V OVD

−6 mA to +18 mA IOH, IOL

− V

DUTGND

REF_GND

))]

− V

REF

− V

REF

− V

))]

REF_GND

−2.5 V to +7.5 V PMUDAC

−50 mA to +50 mA

))]

−4 mA to +4 mA

))]

−400 A to +400 A

))]

−40 A to +40 A

))]

−4 A to +4 A

))]

PMUDAC (PMU FI Range A)

PMUDAC (PMU FI Range B)

PMUDAC (PMU FI Range C)

PMUDAC (PMU FI Range D)

PMUDAC (PMU FI Range E)

1

Programmable range includes margin outside of specified part performance, allowing for offset/gain calibration.

Table 33. Load Transfer Functions

Load Level Transfer Function

1

IOL V(IOL)/5 V × 12 mA IOH V(IOH)/5 V × 12 mA

1

V(IOH), V(IOL) DAC levels are not referenced to DUTGND.

Table 34. PMU Transfer Functions

PMU Mode Transfer Function

Force Voltage V Measure Voltage V Force Current I Measure Current V

1

R = 20 Ω for Range A; 250 Ω for Range B; 2.5 kΩ for Range C; 25 kΩ for Range D; 250 kΩ for Range E.

= PMUDAC

OUT

= V

MEASOUT01

= [PMUDAC − (V

OUT

= (V

MEASOUT01

(internal sense) or V

DUTx

/2)]/(R1 × 5)

REF

/2) + V

REF

DUTGND

Rev. 0 | Page 43 of 52

+ (I

× 5 × R1)

DUTx

MEASOUT01

= V

(external sense)

PMUS_CH x

ADATE302-02

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Table 35. PMU User Required Capacitors

Capacitor Location

220 pF Across Pin C10 (FFCAP_0B) and Pin E10 (FFCAP_0A) 220 pF Across Pin C1 (FFCAP _1B) and Pin E1 (FFCAP_1A) 330 pF Between GND and Pin B9 (SCAP0) 330 pF Between GND and Pin B2 (SCAP1)

Table 36. Temperature Sensor

Temperature Output

0 K 0 V 300 K 3 V x K (x K) × 10 mV/K

Table 37. Default Test Conditions

Name Default Test Condition

VH DAC Level 2.0 V VL DAC Level 0.0 V VT/VCOM DAC Level 1.0 V VOL DAC Level −2.0 V VOH DAC Level 6.0 V VCH DAC Level 7.5 V VCL DAC Level −2.5 V IOH DAC Level 0.0 A IOL DAC Level 0.0 A OVD Low DAC Level −2.5 V OVD High DAC Level 6.5 V PMUDAC DAC Level 0.0 V PE/PMU Enable 0x0000: PMU disabled, not force VT, PE enabled Channel State 0x0000: HVOUT mode disabled, load disabled, VTERM inactive PMU State 0x0000: input of DUTGND, internal sense, clamps disabled, FVMV, Range E PMU Measure Enable 0x0000: MEASOUT01 pin tristated Differential Comparator Enable 0x0000: normal window comparator mode 16-Bit DAC Monitor 0x0000: DAC16_MON tristated OVD_CHx Alarm Mask 0x0000: disable alarm functions Data Input Logic low Receive Input Logic low DUTx Pin Unterminated Comparator Output Unterminated

Rev. 0 | Page 44 of 52

ADATE302-02

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RECOMMENDED PMU MODE SWITCHING SEQUENCES

To minimize any possible aberrations and voltage spikes on the DUT output, specific mode switching sequences are recommended for the following transitions:

• PMU disable to PMU enable

• PMU force voltage mode to PMU force current mode

• PMU force current mode to PMU force voltage mode.

PMU Disable to PMU Enable

Step 1: See Tab l e 3 8 for state of registers in PMU disabled mode.

Table 38.

Register Bit Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C DATA[2] 0 PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] XX

DATA[7] X DATA[6] X DATA[5] X DATA[4] X DATA[3] X DATA[2:0] XXX

Step 2: Write to Register ADDR[4:0] = 0x0E (see Tabl e 39).

Table 39.

Register Bit Setting Comments

PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] 1X or 00 Set desired input selection

DATA[7] X DATA[6] X DATA[5] X DATA[4] X DATA[3] 0

DATA[2:0] XXX Set desired range

Step 3: Write to Register ADDR[4:0] = 0x0C (see Tab l e 40).

Table 40.

Register Bit Setting Comments

PE/PMU Enable Register, ADDR[4:0] = 0x0C DATA[2] 1 PMU is now enabled in force voltage mode

This bit must be set to force voltage mode to reduce aberrations

Rev. 0 | Page 45 of 52

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PMU Force Voltage Mode to PMU Force Current Mode

Step 1: See Tabl e 41 for state of registers in force voltage mode.

Table 41.

Register Bit Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C DATA[2] 1 PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] XX

DATA[7] X DATA[6] X DATA[5] X DATA[4] X DATA[3] 0 DATA[2:0] XXX

Step 2: Write to Register ADDR[4:0] = 0x0E (see Tab l e 42).

Table 42.

Register Bit Setting Comments

PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] 01 Set 2.5 V + V

DATA[7] X DATA[6] X DATA[5] X DATA[4] X DATA[3] 1 Set to force current mode DATA[2:0] 0XX 2 A range has the minimum offset current

input selection

DUTGND

Step 3: Write to Register ADDR[4:0] = 0x0B (see Tab l e 43).

Table 43.

Register Bit Setting Comments

PMUDAC Level, ADDR[4:0] = 0x0B DATA[15:0] X

Step 4: Write to Register ADDR[4:0] = 0x0E (see Tab l e 44).

Table 44.

Register Bit Setting Comments

PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] 1X PMUDAC input selection

DATA[7] X DATA[6] X DATA[5] X DATA[4] X DATA[3] 1 Set to force current mode DATA[2:0] XXX Set to the desired current range

Update the PMUDAC level register to the desired value

Rev. 0 | Page 46 of 52

ADATE302-02

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Transition from PMU Force Current Mode to PMU Force Voltage Mode

Step 1: See Tab l e 4 5 for state of registers in force current mode.

Table 45.

Register Bits Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C DATA[2] 1 PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] XX

DATA[7] X DATA[6] X DATA[5] X DATA[4] X DATA[3] 1 DATA[2:0] XXX

Step 2: Write to Register ADDR[4:0] = 0x0E (see Tabl e 46).

Table 46.

Register Bits Setting Comments

PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] 00 Set DUTGND input selection

DATA[7] X DATA[6] X DATA[5] X DATA[4] X DATA[3] 0 Set to force voltage mode DATA[2:0] XXX Set to the desired current range

Step 3: Write to Register ADDR[4:0] = 0x0B (see Tab l e 47).

Table 47.

Register Bits Setting Comments

PMUDAC Level, ADDR[4:0] = 0x0B DATA[15:0] X

Step 4: Write to Register ADDR[4:0] = 0x0E (see Tabl e 48).

Table 48.

Register Bits Setting Comments

PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] 1X PMUDAC input selection

DATA[7] X DATA[6] X DATA[5] X DATA[4] X DATA[3] 0 Force voltage mode DATA[2:0] XXX

Update the PMUDAC level register to the desired value

Rev. 0 | Page 47 of 52

ADATE302-02

V

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BLOCK DIAGRAMS

VCL VCH

VH

VL

DATA

VT

DRIVER HIGH-Z /VT DATA[0]

(ADDR[4:0] = 0x0D)

VT BUFFER WHEN 1

HIGH-Z BUFF ER WHEN 0

RCV

FORCE VT DAT A[1] (ADDR[4:0] = 0x0C)

OVERRIDES T HE RCV PIN AND FORCE S

TERM MODE ON THE DRIVER AND LOAD

POWER-DOW N MODE

DRIVER

VCOM

V(IOH)

V(IOL)

LOAD ENABLE DAT A[1] (ADDR[4:0] = 0x0D) FORCES SW ITCHES OPE N AND POWERS DOWN LOAD W HEN 0

Figure 87. Driver and Load Block Diagram

PE DISABLE DAT A[0] (ADDR[4:0] = 0x0C) FORCES SWITCH OPEN WHEN 1

R

= 47

OUT

(TRIMMED)

DUT

07278-014

VHH = (VT + 1V) × 2 + DUTGND

VH

RCV (SHOWN IN

RCV = 0 STATE)

DATA

VL

~5

48

HV MODE SELECT DATA[2] (ADDR [4:0] = 0x0D) DISABLES HV DRIVER AND FORCES 0V ON HVOUT WHEN 0

HVOUT

07278-015

Figure 88. HVOUT Driver Output Stage

Rev. 0 | Page 48 of 52

ADATE302-02

V

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DUT0

DUT1

DIFFERENTIAL

BUFFER

NOTES

1. DIFFE RENTIAL CO MPARATOR ONL Y ON CHANNEL 0.

DUT0 –

DUT0–

DUT1

OH0

VOL0

VOH0

VOL0

–

VOH NWC

+

VOL

NWC

–

VOH DMC

+

VOL

DMC

–

COMP_QH0

2:1

MUX

DIFFERENTIAL COMPARATOR ENABL E DATA[0] (ADDR[4:0] = 0x10)

COMP_QL0

2:1

MUX

07278-016

Figure 89. Comparator Block Diagram

COMP_VTT

COMP_Q P

5050

COMP_Q N

10mA

07278-017

Figure 90. Comparator Output Scheme

Rev. 0 | Page 49 of 52

ADATE302-02

A

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MEASOUT01 SEL ECT DATA[2:1]

(ADDR[4:0] = 0x0F)

MEASURE OUT

MEASOUT01 OUTPUT

ENABLE DATA[0]

(ADDR[4:0] = 0x0F )

ONE PER DEVICE

PMU INPUT SELECTION DATA[9:8]

2.5V + DUTGND

DUTGND

PMU MEASURE V/I DATA[4]

(ADDR[4:0] = 0x0E)

CH[1] PMU V/I TEMP SENSE

GND REF

MUX

(ADDR[4:0] = 0x0E)

VIN

TEMP SENSE

MUX

PMU SENSE P

(ADDR[4:0] = 0x0E)

MEASURE V

MEASURE I

MUX

PMU FORCE V/ I DATA[3]

(ADDR[4:0] = 0x0E)

MUX

PMU CLAMP ENABLE DATA[5]

(ADDR[4:0] = 0x0E)

VCH

TH DATA[7]

MUX

EXTERNAL DUT SENSE PIN

IN-AMP G = 5

REF

2µA 20µA 200µA 2mA

330pF SCAP (EXTERNAL)

2.5 + DUTGND

225k

25mA BUFFER

22.5k 2.25k

10k

DUT

250

FFCAP_A FFCAP_B

CRA = 220pF

20

MV

MEASURE V

(AT OUTPUT OF

SENSE MUX)

NOTES

1. SWITCHES CONNECTED W ITH DOT TED LINES REPRESENT PMU RANGE DATA[2:0] (ADDR[4:0] = 0x0E); WHEN PMU ENABLE D ATA[2] = 0 (ADDR[4:0] = 0x0C), ALL SWITCHES OPEN AND PMU POW ERS DOWN.

2. THE EXTERNAL SENSE PATH MUST CLOS E THE LOOP TO ENABL E THE CLAMPS TO OPERAT E CORRECTL Y.

3. 25mA RANGE HAS IT S OWN OUT PUT BUFFER.

4. 25mA BUFFER WILL BE TRISTATED WHEN NOT I N USE.

VCL

25mA

Figure 91. PMU Block Diagram

07278-018

Rev. 0 | Page 50 of 52

ADATE302-02

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1

DAC (ADDR[4:0] = 0x0A, CH[1] )

OVD HIGH LE VEL

6.5V

DUT

(ADDR[4:0] = 0x12) DAT A[0] OVD MASK ENABLES OVD FLAGS TO ALARM OVD_CHx PIN

SHORT CIRCUIT

CURRENT = 100µ A

OVD_CHx

ADATE302-02

1

PMU

V/I CLAMP

FLAG

–2.5V

(ADDR[4:0] = 0x13)

(ADDR[4:0] = 0x12) DAT A[1] PMU MASK ENABLES P MU V/I FLAG TO ALARM OVD_CHx PIN

2

DATA[2] DATA[1] DATA[0]

07278-019

DAC (ADDR[4:0] = 0x0A, CH[0] )

1

THE OVD HIG H/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THE REFORE, O NLY ONE O VD HIGH/LOW VOL TAGE LEVEL CAN BE SET PER CHIP. THE OVD DACs PRO VIDE A VOL TAGE RANGE OF –3V TO +7V. THE RECOMMENDED HIGH/LO W SETT INGS ARE +6. 5V/–2.5V. (THESE VAL UES NEED TO BE PROGRAMMED BY THE USER UPO N STARTUP/RE SET.)

2

THIS IS A READ ONLY REGI STER THAT AL LOWS T HE USER TO DET ERMINE THE CAUSE OF THE ACTIVE OVD FLAG.

OVD LOW LEVEL

Figure 92. OVD Block Diagram

Rev. 0 | Page 51 of 52

ADATE302-02

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OUTLINE DIMENSIONS

A1 BALL

CORNER

9.10

9.00 SQ

8.90

TOP VIEW

6.731

REF SQ

7.20

BSC SQ

0.80

BSC

0.90 REF

987654 231

10

BOTTOM VIEW

A

B

C

D

E

F

G

H

J

K

A1 BALL CORNER

*

1.20

1.09

1.00

DETAIL A



0.36 REF

0.38

0.33

0.28

SEATING

PLANE

*

COMPLIANT TO JEDEC STANDARDS MO-219 WI TH EXCEPTIO N TO PACKAGE HEIGHT.

0.305 REF

0.53

0.48

0.43

BALL DIAMET ER

0.83

0.76

0.69

COPLANARITY

0.12

022708-A

Figure 93. 84-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-84-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADATE302-02BBCZ

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 84-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-84-2

Rev. 0 | Page 52 of 52

Datasheet ADATE302-02 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

TOTAL FUNCTION

DRIVER

REFLECTION CLAMP

NORMAL WINDOW COMPARATOR

DIFFERENTIAL COMPARATOR

ACTIVE LOAD

EXTERNAL SENSE (PMUS_CHx)

DUTGND INPUT

SERIAL PERIPHERAL INTERFACE

HVOUT DRIVER

OVERVOLTAGE DETECTOR (OVD)

16-BIT DAC MONITOR MUX

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

SERIAL PERIPHERAL INTERFACE DETAILS

DEFINITION OF SPI WORD

Example 1

Example 2

Example 3a

Example 3b

Example 4

WRITE OPERATION

READ OPERATION

RESET OPERATION

REGISTER MAP

DETAILS OF REGISTERS

USER INFORMATION

DETAILS OF DACs vs. LEVELS

RECOMMENDED PMU MODE SWITCHING SEQUENCES

PMU Disable to PMU Enable

PMU Force Voltage Mode to PMU Force Current Mode

Transition from PMU Force Current Mode to PMU Force Voltage Mode

BLOCK DIAGRAMS

OUTLINE DIMENSIONS

ORDERING GUIDE