Datasheet AD9995 Datasheet (Analog Devices)

12-Bit CCD Signal Processor with

AD9995

CDS

VG

A

CLAMP

12-BIT

ADC

12

DCLK

MSHUT

STROBE

CLOCLI

DOUT

VREF

6dB TO

42dB

HORIZONTAL

DRIVERS

V-

H

CONTROL

4

6

5

RG

H1–H4

V1–V6

VSG1–VSG5

VRT VRB

PRECISION

TIMING

GENERATOR

SYNC

GENERATOR

INTERNAL CLOCKS

VSUB SUBCK HD VD SYNC

INTERNAL

REGISTER

S

SL SCK DATA

CCDIN

Precision Timing ™ Generator

AD9995

FEATURES 6-Phase Vertical Transfer Clock Support Correlated Double Sampler (CDS) 6 dB to 42 dB 10-Bit Variable Gain Amplier (VGA) 12-Bit 36 MHz A/D Converter Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core with <600 ps Resolution On-Chip 3 V Horizontal and RG Drivers 2-Phase and 4-Phase H-Clock Modes Electronic and Mechanical Shutter Modes On-Chip Driver for External Crystal On-Chip Sync Generator with External Sync Input 56-Lead LFCSP Package

APPLICATIONS Digital Still Cameras Digital Video Camcorders Industrial Imaging

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD9995 is a highly integrated CCD signal processor for digital still camera and camcorder applications. It includes a complete analog front end with A/D conversion, combined with a full-function programmable timing generator. The timing generator is capable of supporting both 4- and 6-phase vertical clocking. A Precision Timing core allows adjustment of high speed clocks with less than 600 ps resolution at 36 MHz operation.

The AD9995 is specied at pixel rates of up to 36 MHz. The analog front end includes black level clamping, CDS, VGA, and a 12-bit A/D converter. The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. Operation is programmed using a 3-wire serial interface.

Packaged in a space-saving 56-lead LFCSP, the AD9995 is specied over an operating temperature range of –20°C to +85°C.

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9995

In addition to the programmable timing positions, the AD9995 features on-chip output drivers for the RG and H1–H4 outputs. These drivers are powerful enough to directly drive the CCD inputs. The H-driver and RG current can be adjusted for optimum rise/fall time into a particular load by using the DRVCONTROL register (Addr. 0x35). The 3-bit drive setting for each output is adjustable in 4.1 mA increments, with the minimum setting of 0 equal to OFF or three-state, and the maximum setting of 7 equal to 30.1 mA.

As shown in Figures 5, 6, and 7, the H2 and H4 outputs are inverses of H1 and H3, respectively. The H1/H2 crossover voltage is approximately 50% of the output swing. The crossover

Digital Data Outputs

The AD9995 data output and DCLK phases are programmable using the DOUTPHASE register (Addr. 0x37, Bits [5:0]). Any edge from 0 to 47 may be programmed, as shown in Figure 8a. Normally, the DOUT and DCLK signals will track in phase based on the DOUTPHASE register contents. The DCLK output phase can also be held xed with respect to the data outputs by changing the DCLKMODE register high (Addr. 0x37, Bit 6). In this mode, the DCLK output will remain at a xed phase equal to CLO (the inverse of CLI) while the data output phase is still programmable.

There is a xed output delay from the DCLK rising edge to the DOUT transition, called tOD. This delay can be programmed to four values between 0 ns and 12 ns by using the DOUTDELAY register (Addr. 0x037, Bits [8:7]). The default value is 8 ns.

The pipeline delay through the AD9995 is shown in Figure 8b. After the CCD input is sampled by SHD, there is an 11-cycle delay until the data is available.

voltage is not programmable.

Table I. Timing Core Register Parameters for H1, H3, RG, SHP/SHD

Parameter Length Range Description

Polarity 1b High/Low Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion) Positive Edge 6b 0–47 Edge Location Positive Edge Location for H1, H3, and RG Negative Edge 6b 0–47 Edge Location Negative Edge Location for H1, H3, and RG Sampling Location 6b 0–47 Edge Location Sampling Location for Internal SHP and SHD Signals Drive Strength 3b 0–47 Current Steps Drive Current for H1–H4 and RG Outputs (4.1 mA per Step)

Figure 6. 2-Phase H-Clock Operation

Table II. Precision Timing Edge Locations

Quadrant Edge Location (Dec) Register Value (Dec) Register Value (Bin)

I 0 to 11 0 to 11 000000 to 001011 II 12 to 23 16 to 27 010000 to 011011 III 24 to 35 32 to 43 100000 to 101011 IV 36 to 47 48 to 59 110000 to 111011

REV. 0

–11–

P[0]

PIXEL

PERIOD

RG

H1/H3

RGf[12]

P[48] = P[0]

Hf[24]

CCD

SIGNAL

P[24]P[12] P[36]

Hr[0]

RGr[0]

SHD[0]

NOTES ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

POSITION

t

S1

H2/H4

SHP[24]

NOTES DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS

.

OUTPUT DELAY (tOD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.

P[0] P[48] = P[0]

PIXEL

PERIOD

P[12] P[24] P[36]

DOUT

DCLK

t

OD

NOTES DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0, DCLKMODE = 0. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

DCLK

DOUT

CCDIN

CLI

SHD

(INTERNAL)

N N+1

N+2

N+12N+11N+10N+9N+8N+7N+6N+5N+4

N+3

N+13

N–13

N–3N–4N–5N–6N–7N–8N–9N–10N–11

N–12

N–2

N–1

N+1

N

SAMPLE PIXEL N

PIPELINE LATENCY=11 CYCLES

t

CLIDLY

N–1

N+2

AD9995

(3)(2)

(1)

HD

CLPOB

PBLK

. . .

NOTES PROGRAMMABLE SETTINGS:

1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)

2. FIRST TOGGLE POSITION

3. SECOND TOGGLE POSITION

. . .

ACTIVE

ACTIV

E

HORIZONTAL CLAMPING AND BLANKING

The AD9995’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK during the different regions of each eld. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout in order to accommodate different image transfer timing and high speed line shifts.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK, as shown in Figure 9. These two signals are independently programmed using the registers in Table III. SPOL is the start polarity for the signal, and TOG1 and TOG2 are the rst and second toggle positions of the pulse. Both signals are active low and should be programmed accordingly.

A separate pattern for CLPOB and PBLK may be programmed for every 10 V-sequences. As described in the Vertical Timing Generation section, up to 10 separate V-sequences can be created,

each containing a unique pulse pattern for CLPOB and PBLK. Figure 9 shows how the sequence change positions divide the readout eld into different regions. A different V-sequence can be assigned to each region, allowing the CLPOB and PBLK signals to be changed accordingly with each change in the vertical timing.

Individual HBLK Patterns

The HBLK programmable timing shown in Figure 10 is similar to CLPOB and PBLK. However, there is no start polarity control. Only the toggle positions are used to designate the start and stop positions of the blanking period. Additionally, there is a polarity control HBLKMASK that designates the polarity of the horizontal clock signals H1–H4 during the blanking period. Setting HBLKMASK high will set H1 = H3 = low and H2 = H4 = high during the blanking, as shown in Figure 11. As with the CLPOB and PBLK signals, HBLK registers are available in each V-sequence, allowing different blanking signals to be used with different vertical timing sequences.

Figure 9. Clamp and Pre-Blank Pulse Placement

Table III. CLPOB and PBLK Pattern Registers

Register Length Range Description

SPOL 1b High/Low Starting Polarity of CLPOB/PBLK for V-Sequence 0–9 TOG1 12b 0–4095 Pixel Location First Toggle Position within Line for V-Sequence 0–9 TOG2 12b 0–4095 Pixel Location Second Toggle Position within Line for V-Sequence 0–9

Table IV. HBLK Pattern Registers

Register Length Range Description

HBLKMASK 1b High/Low Masking Polarity for H1/H3 (0 = H1/H3 Low, 1 = H1/H3 High) HBLKALT 2b 0–3 Alternation Mode Enables Odd/Even Alternation of HBLK Toggle Positions 0 = Disable Alternation. 1 = TOG1–TOG2 Odd, TOG3–TOG6 Even. 2 = 3 = TOG1–TOG2 Even, TOG3–TOG6 Odd HBLKTOG1 12b 0–4095 Pixel Location First Toggle Position within Line for Each V-Sequence 0–9 HBLKTOG2 12b 0–4095 Pixel Location Second Toggle Position within Line for Each V-Sequence 0–9 HBLKTOG3 12b 0–4095 Pixel Location Third Toggle Position within Line for Each V-Sequence 0–9 HBLKTOG4 12b 0–4095 Pixel Location Fourth Toggle Position within Line for Each V-Sequence 0–9 HBLKTOG5 12b 0–4095 Pixel Location Fifth Toggle Position within Line for Each V-Sequence 0–9 HBLKTOG6 12b 0–4095 Pixel Location Sixth Toggle Position within Line for Each V-Sequence 0–9

REV. 0

–13–

HD

HBLK

PROGRAMMABLE SETTINGS:

1. FIRST TOGGLE POSITION = START OF BLANKING

2. SECOND TOGGLE POSITION = END OF BLANKING

BLANK BLANK

1 2

HD

HBLK

THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).

H1/H3

H2/H4

HBLK

SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS

.

H1/H3

H2/H4

TOG1

TOG2 TOG3

TOG4 TOG5 TOG6

–15

V

H

HORIZONTAL CCD REGISTER

EFFECTIVE IMAGE AREA

48 OB PIXELS

4 OB PIXELS

10 VERTICAL OB LINES

2 VERTICAL OB LINES

VERTICAL SHIFT

VERT SHIF

T

CCDIN

SHP

SHD

H1/H3

H2/H

HBLK

PBLK

CLPOB

OPTICAL BLACK

DUMMY

EFFECTIVE PIXELS

OB

OPTICAL BLACK

HD

–16

vertical CCD timing, and can support multiple CCDs and dif-

V1–V6 are used to shift each line of pixels into the horizontal

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 2: USE V-SEQUENCE 1

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 2: USE V-SEQUENCE 1

REGION 0: USE V-SEQUENCE 2

REGION 1: USE V-SEQUENCE 0

REGION 3: USE V-SEQUENCE 0

REGION 4: USE V-SEQUENCE 2

CREATE THE VERTICAL PATTERN GROUPS (MAXIMUM OF 10 GROUPS).

BUILD THE V-SEQUENCES BY ADDING LINE START POSITION, # OF REPEATS, AND HBLK/CLPOB PULSES (MAXIMUM OF 10 V-SEQUENCES).

V-SEQUENCE 0

(VPAT0, 1 REP)

BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS, AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH (MAXIMUM OF 7 REGIONS IN EACH FIELD

)

(MAXIMUM OF 6 FIELDS).

V1

V2

V5

V6

V1

V2

V3

V4

FIELD 0

FIELD 1

FIELD 2

REGION 2: USE V-SEQUENCE 3

USE THE MODE REGISTER TO CONTROL WHICH FIELDS ARE USED, AND IN WHAT ORDER (MAXIMUM OF 7 FIELDS MAY BE COMBINED IN ANY ORDER).

FIELD 0

FIELD 1 FIELD 2

FIELD 3

FIELD 4

FIELD 5

FIELD 1 FIELD 4

FIELD 2

V4

V3

V5

V6

V-SEQUENCE 1

(VPAT9, 2 REP)

V-SEQUENCE

2

(VPAT9, N REP)

VPAT 0

V1

V2

V5

V6

V4

V3

V1

V2

V5

V6

V4

V3

V1

V2

V5

V6

V4

V3

VPAT 9

VPOL

VTOG1

VTOG2

VTOG3

VTOG4

VPATLEN

VTOG2, VTOG3) are the pixel locations within the line where

vided, allowing the vertical outputs to be interrupted twice in

Vertical Sequence section.

–18

V-pattern groups and adding repeats, start position, and hori-

VPATSEL

VMASK

VPATREPO

VPATREPE

VPATSTART

–19

VPATSECOND register is used to add a second V-pattern group

vidual VSG output. There is a single bit for each VSG output;

VSEQSEL

VDLEN

VPATSECOND

VSG3 [2], VSG4 [3], VSG5 [4].

VSG2 [3:2], VSG3 [5:4], VSG4 [7:6], VSG5 [9:8].

–20

V-pattern group for V1–V6 during the line when the sensor gates

VSG1–VSG5 are active. Figure 20 shows a typical VSG line,

V-

VPATLEN register from the selected VPAT registers. Because

VPAT length, it is not possible to program multiple repetitions

V1

V2

VPATREPO = 2

V6

HD

VPATREPE = 5

VPATREPO =

2

NOTES

1. THE NUMBER OF REPEATS FOR THE V-PATTERN GROUP MAY BE ALTERNATED ON ODD AND EVEN LINES.

2. THE HBLK TOGGLE POSITIONS MAY BE ALTERNATED BETWEEN ODD AND EVEN LINES IN ORDER TO GENERATE DIFFERENT HBLK PATTERNS FOR ODD/EVEN LINES.

HBLK

TOG1 TOG2

TOG3

TOG4

TOG1 TOG2

V1

V2

V6

HD

VSG

2ND VPAT GROUP

START POSITION FOR 2ND VPAT GROUP USES VPATLEN REGISTER

vertical interline CCD registers should be free of all charge. This

vertical resolution of the CCD, up to 2,000 or 3,000 clock cycles

VPATLEN is used differently. Instead of using the pixel counter

VTOG position to allow very long pulses to be generated. To cal-

Multiplier ModeTogglePosition VTOG VPATLEN= ×

VPATLEN = 4, the toggle position accuracy is now reduced

VPATREPE registers should always be programmed to the same

value as the highest toggle position.

VPOL

VTOG1

VTOG2

VTOG3

VPATLEN

VPATREP

VPATREPE/VPATREPO should be set to the same value as TOG2 or 3.

vertical transfer pulses V1–V6 in conjunction with the high speed

VPATLEN

–23

V-pattern group information is programmed into the AD9995

VSEQSEL registers will then assign a particular V-sequence to

vertical shift timing. The timing of this region area will be the

When programming the AD9995 to generate the V1–V6,

VSG1–VSG5, and SUBCK signals, it is important to note that

–25

VD

HD

V1

V2

V5

V6

SUBCK

MSHUT

VSUB

CCD

OUT

EXPOSURE (t

EXP

)

FIRST FIELD READOUT

REGION 1 REGION 2

REGION 0 R

EGION 3

1

4

7

10

13

16

n–5

n–2

CLOSED

2

5

8

11

14

17

20

n–4

n–1

OPEN

V3

V4

OPEN

3

6

9

12

15

18

21

n

REGION 1 REGION 2

REGION 0 REGION 3

REGION 1 REGION 2

REGION 0 REGION 3

SECOND FIELD READOUT

THIRD FIELD READOUT

FIELD 0

FIELD 1

FIELD 2

n– 3

–26

Values section.

very last SUBCK pulse. In this mode, the SUBCK still pulses

VD

SUBCK

SUBCK PROGRAMMABLE SETTINGS:

1. PULSE POLARITY USING THE SUBCKPOL REGISTER.

2. NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER (SUBCKNUM = 3 IN THE ABOVE FIGURE).

3. PIXEL LOCATION OF PULSE WITHIN THE LINE AND PULSEWIDTH PROGRAMMED USING SUBCK1 TOGGLE POSITION REGISTER

.

t

EXP

VSG

HD

t

EXP

VD

SUBCK

NOTES

1. SECOND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE.

2. LOCATION OF 2ND PULSE IS FULLY PROGRAMMABLE USING THE SUBCK2 TOGGLE POSITION REGISTER.

VSG

HD

t

EXP

t

EXP

VDHDOFF

–28

is also available.

When this bit is set high, the VSUB output will remain on (active)

VD

SUBCK

VSUB OPERATION:

1. ACTIVE POLARITY IS POLARITY (ABOVE EXAMPLE IS VSUB ACTIVE HIGH).

2. ON POSITION IS PROGRAMMABLE. MODE 0 TURNS ON AT THE START OF EXPOSURE, MODE 1 TURNS ON AT THE START OF READOUT

.

3. OFF POSITION OCCURS AT END OF READOUT.

4. OPTIONAL VSUB KEEP-ON MODE WILL LEAVE THE VSUB ACTIVE AT THE END OF READOUT.

t

EXP

VSG1

VSUB

3

1

2

READOUT

2

4

MODE 0

MODE 1

TRIGGER

VSUB

VD

SUBCK

MSHUT PROGRAMMABLE SETTINGS:

1. ACTIVE POLARITY.

2. ON POSITION IS VD UPDATED AND MAY BE SWITCHED ON AT ANY TIME.

3. OFF POSITION CAN BE PROGRAMMED ANYWHERE FROM THE FIELD OF LAST SUBCK UNTIL THE FIELD BEFORE READOUT.

t

EXP

VSG

MSHUT

3

1

2

TRIGGER

EXPOSURE

AND MSHUT

–29

While the TRIGGER register can be used to perform a complete

VSUBMODE[0]

VSUB Mode (0 = Mode 0, 1 = Mode 1) (See Figure 29).

VSUBMODE[1]

VSUB Keep-On Mode. VSUB will stay active after readout

VSUBON[11:0]

VSUB On Position. Active starting in any line of  eld.

VSUBON[12]

VSUB Active Polarity.

AD9995

–31–

DRAFT IMAGE

SERIAL

WRITES

VD

VSG

SUBCK

STROBE

MSHUT

MECHANICAL

SHUTTE

R

VSUB

CCD

OUT

1 9

10

8762

t

EXP

4

5

3

OPEN

CLOSED

MODE

0

MODE

1

10

OPEN

STILL IMAGE 3RD FIELDSTILL IMAGE 2ND FIELDSTILL IMAGE 1ST FIELD

DRAFT IMAGE

STILL IMAGE READOUT

REV. 0

EXPOSURE AND READOUT EXAMPLE

Figure 32. Example of Exposure and Still Image Readout Using Shutter Signals and Mode Register

1. Write to the READOUT register (Addr. 0x61) to specify the number of elds to further suppress SUBCK while the CCD data is read out. In this example, READOUT = 3.

Write to the EXPOSURE register (Addr. 0x62) to specify

the number of elds to suppress SUBCK and VSG outputs during exposure. In this example, EXPOSURE = 1.

Write to the TRIGGER register (Addr. 0x60) to enable the

STROBE, MSHUT, and VSUB signals, and to start the exposure/readout operation. To trigger all of these events (as in Figure 32), set the register TRIGGER = 31. Readout will automatically occur after the exposure period is nished.

Write to the MODE register (Addr. 0x1B) to congure the

next ve elds. The rst two elds during exposure are the same as the current draft mode elds, and the following three elds are the still frame readout elds. The registers for the Draft mode eld and the three readout elds have already been programmed.

2. VD/HD falling edge will update the serial writes from 1.

3. If VSUB mode = 0 (Addr. 0x67), VSUB output turns on at the line specied in the VSUBON register (Addr. 0x68).

4. STROBE output turns on and off at the location specied in the STROBEON and OFF registers (Addr. 0x6E to Addr. 0x71).

5. MSHUT output turns off at the location specied in the MSHUTOFF registers (Addr. 0x6B and 0x6C).

6. The next VD falling edge will automatically start the rst readout eld.

7. The next VD falling edge will automatically start the second readout eld.

8. The next VD falling edge will automatically start the third readout eld.

9. Write to the MODE register to recongure the single Draft mode eld timing.

Write to the MSHUTON register (Addr. 0x6A) to open the

mechanical shutter.

10. VD/HD falling edge will update the serial write from 9.

VSG outputs return to Draft mode timing.

SUBCK output resumes operation.

MSHUT output returns to the on position (active or open).

VSUB output returns to the off position (inactive).

–30–

REV. 0

AD9995

6dB–42dB

CCDIN

DIGIT

AL

FILTER

CLPOB

DC RESTORE

OPTICAL BLAC

K

CLAMP

12-BIT

ADC

VG

A

DA

C

CLAMP LEVEL

REGISTER

8

VG

A GAIN

REGISTER

CDS

INTERNAL

V

REF

2V FULL SCALE

12

PRECISION

TIMING

GENERATION

SHP

SHD

1.5V

OUTPUT

DATA

LATCH

REFTREFB

DOUT

PHASE

V-

H

TIMING

GENERATION

SHP

SHD

DOUT

PHASE

CLPOB

PBLK

1.0V 2.0V

DOUT

AD9995

1.0F1.0F

0.1F

Gain dB Code dB

( ) ( )

= × +0 0351 6.

VGA GAIN REGISTER CODE

42

0

VGA GAIN (dB)

127 255 383 511 639 767 895 1023

36

30

24

18

12

6

Figure 33. Analog Front End Functional Block Diagram

ANALOG FRONT END DESCRIPTION AND OPERATION

The AD9995 signal processing chain is shown in Figure 33. Each processing step is essential in achieving a high quality image from the raw CCD pixel data.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 µF series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, to be compatible with the 3 V supply voltage of the AD9995.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract the video information and reject low frequency noise. The timing shown in Figure 7 illustrates how the two internally generated CDS clocks, SHP and SHD, are used to sample the reference level and level of the CCD signal, respectively. The placement of the SHP and SHD sampling edges is determined by the setting of the SAMPCONTROL register located at Addr. 0x63. Placement of these two clock signals is critical in achieving the best performance from the CCD.

Variable Gain Amplier

The VGA stage provides a gain range of 6 dB to 42 dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain of 6 dB is needed to match a 1 V input signal

with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB.

The VGA gain curve follows a linear-in-dB characteristic. The exact VGA gain can be calculated for any gain register value by using the equation

where the code range is 0 to 1023.

Figure 34. VGA Gain Curve

REV. 0

–31–

AD9995

–33–

REV. 0

A/D Converter

The AD9995 uses a high performance ADC architecture op

timized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB. The ADC uses a 2 V input range. See TPC 2 and TPC 3 for typical linearity and noise performance plots for the AD9995.

Optical Black Clamp

The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD’s black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a xed black level reference, selected by the user in the Clamp Level register. The value can be programmed between 0 LSB and 255 LSB in 256 steps. The resulting error signal is ltered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the postprocessing, the AD9995 optical black clamping may be disabled using Bit D2 in the OPRMODE register. When the loop is disabled, the Clamp Level register may still be used to provide programmable offset adjustment.

The CLPOB pulse should be placed during the CCD’s optical black pixels. It is recommended that the CLPOB pulse duration be at least 20 pixels wide to minimize clamp noise. Shorter pulsewidths may be used, but clamp noise may increase, and the ability to track low frequency variations in the black level will be reduced. See the Horizontal Clamping and Blanking section and the Horizontal Timing Sequence Example section for timing examples.

Digital Data Outputs

The AD9995 digital output data is latched using the DOUT PHASE register value, as shown in Figure 33. Output data timing is shown in Figure 8a. It is also possible to leave the output latches transparent so that the data outputs are valid immediately from the A/D converter. Programming the AFE CONTROL register bit D4 to 1 will set the output latches transparent. The data outputs can also be disabled (three-stated) by setting the AFE CONTROL register Bit D3 to 1.

The data output coding is normally straight binary, but the coding my be changed to gray coding by setting the AFE CONTROL register Bit D5 to 1.

–32–

REV. 0

AD9995

t

PWR

2

1

3 4 5 6 7

8

9

10 11

12

t

SYNC

1V

1ST FIELD

1H

CLOCKS ACTIVE WHEN OUT CONTROL REGISTER IS UPDATED AT VD/HD EDGE

H2/H4

H1/H3, RG, DCLK

DIGITAL

OUTPUTS

HD

(OUTPUT)

VD

(OUTPUT)

SYNC

(INPUT)

SERIAL

WRITES

CLI

(INPUT)

VDD

(INPUT)

POWER-UP AND SYNCHRONIZATION Recommended Power-Up Sequence for Master Mode

When the AD9995 is powered up, the following sequence is recommended (refer to Figure 35 for each step). Note that a SYNC signal is required for Master mode operation. If an external SYNC pulse is not available, it is also possible generate an internal SYNC pulse by writing to the SYNCPOL register, as described in the next section.

1. Turn on power supplies for AD9995.

2. Apply the master clock input CLI.

3. Reset the internal AD9995 registers by writing a 1 to the SW_RESET register (Addr. 0x10 in Bank 1).

4. By default, the AD9995 is in Standby3 mode. To place the part into normal power operation, write 0x004 to the AFE OPRMODE register (Addr. 0x00 in Bank 1).

5. Write a 1 to the BANKSELECT register (Addr. 0x7F). This will select Register Bank 2.

6. Load Bank 2 registers with the required VPAT group, V-sequence, and eld timing information.

7. Write a 0 to the BANKSELECT register to select Bank 1.

8. By default, the internal timing core is held in a reset state with TGCORE_RSTB register = 0. Write a 1 to the TGCORE_RSTB register (Addr. 0x15 in Bank 1) to start the internal timing core operation.

9. Load the required registers to congure the high speed timing, horizontal timing, and shutter timing information.

10. Congure the AD9995 for Master mode timing by writing a 1 to the MASTER register (Addr. 0x20 in Bank 1).

11. Write a 1 to the OUT_CONTROL register (Addr. 0x11 in Bank 1). This will allow the outputs to become active after the next SYNC rising edge.

12. Generate a SYNC event: If SYNC is high at power-up, bring the SYNC input low for a minimum of 100 ns. Then bring SYNC back high. This will cause the internal counters to reset and will start VD/HD operation. The rst VD/HD edge allows most Bank 1 register updates to occur, including OUT_CONTROL to enable all outputs.

Table XIII. Power-Up Register Write Sequence

Address Data Description

0x10 0x01 Reset All Registers to Default Values 0x00 0x04 Power Up the AFE and CLO Oscillator 0x7F 0x01 Select Register Bank 2 0x00–0xFF VPAT, V-Sequence, and Field Timing 0x7F 0x00 Select Register Bank 1 0x15 0x01 Reset Internal Timing Core 0x30–71 Horizontal and Shutter Timing 0x20 0x01 Congure for Master Mode 0x11 0x01 Enable All Outputs after SYNC 0x13 0x01 SYNCPOL (for Software SYNC Only)

Generating Software SYNC without External SYNC Signal

If an external SYNC pulse is not available, it is possible to generate an internal SYNC in the AD9995 by writing to the SYNCPOL register (Addr. 0x13). If the software SYNC option is used, the SYNC input (Pin 46) should be tied to ground (VSS).

After power-up, follow the same procedure as before for Steps 1 to 11. Then, for Step 12, instead of using the external SYNC pulse, write a 1 to the SYNCPOL register. This will generate the SYNC internally, and timing operation will begin.

REV. 0

Figure 35. Recommended Power-Up Sequence and Synchronization, Master Mode

–33–

–34

VD

HD

NOTES

1. SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO ZERO.

2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).

3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x14).

4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1–H2, AND RG ARE HELD AT THEIR DEFAULT POLARITIES.

5. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE

.

SUSPEN

D

SYNC

H124, RG, V1–V4,

VSG, SUBCK

0 1 2 3 4 5 6 7 8

H-COUNTER

RESET

VD

NOTES INTERNAL H-COUNTER IS RESET 17 CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDPOL = 0)

.

TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE IS COINCIDENT WITH HD FALLING EDGE

.

HD

CLI

X XX X X XXXX

H-COUNTER

(P

IXEL COUNTER)

X XX X X XXX XX

9

When the AD9995 is used in Slave mode, the VD and HD inputs

between CLI and CLO. Therefore, if CLI and CLO are

When returning from Standby 3 mode to normal operation, the

–35

_CONT = LO

V1

V2

V3

V4

V5

V6

VSG1

VSG2

VSG3

VSG4

VSG5

VSUB

VD

VDHDPOL

Value

VDHDPOL

Value

VDHDPOL

Value

VDHDPOL

Value

AD9995

–37–

20pF

D10

35

20pF

CLI CLO

AD9995

24MHz

XTAL

34

1M

500M

OUTPUT FROM CCD

12

DATA OUTPUTS

LINE/FIELD/DCLK TO ASIC/DSP

3V

ANALOG

SUPPLY

EXTERNAL SYNC FROM ASIC/DSP

3

SERIAL INTERFACE TO ASIC OR DSP

TO STROBE CIRCUIT

TO MECHANICAL SHUTTER CIRCUIT

3V ANALOG SUPPLY

3V RG SUPPLY

3V H1–H4 SUPPLY

5

+

MASTER CLOCK INPUT

12

V1–V4,

VSG1–VSG4,

SUBCK

TO V-DRIVER

3V

DRIVER

SUPPLY

VSUB TO CCD

RG, H1–H4 TO CCD

+

TOP VIEW

AD9995

PIN 1 IDENTIFIE

R

42 SDI

41 SL

40 REFB 39 REFT

38 AVSS

37 CCDIN

36 AVDD

35 CL

I

34 CL

O

33 TCVD

D

32 TCVSS

31 RGVDD

30 RG

29 RGVSS

D5 1

D6 2

D7 3

D8 4

D9 5

D10 6

D11 7

DRVDD 8

DRVSS 9

VSUB 10

SUBCK 11

V1 12

V2 13

V3 14

56 D4

55 D3

54 D2

53 D1

52 D0

51 DCL

K

50 HD

49 DVDD

48 DVSS

47 VD

46 SYN

C

45 STROBE

44 MSHUT

43 SC

K

V4 15

V5 16

V6 17

VSG1 18

VSG2 19

VSG3 20

VSG4 21

VSG5 22

H1 23

H2 24

HVSS 25

HVDD 26

H3 27

H4 28

+

0.1F

0.1

F

0.1

F

0.1

F

0.1

F

0.1F

4.7F

4.7

F

4.7

F

4.7

F

1F

REV. 0

CIRCUIT LAYOUT INFORMATION

The AD9995 typical circuit connection is shown in Figure 38. The PCB layout is critical in achieving good image quality from the AD999x products. All of the supply pins, particularly the AVDD1, TCVDD, RGVDD, and HVDD supplies, must be decoupled to ground with good quality, high frequency chip ca close as possible to the supply pins and should have a very low impedance path to a continuous ground plane. There should also be a 4.7 µF or larger value bypass capacitor for each main supply—AVDD, RGVDD, HVDD, and DRVDD—although this is not necessary for each individual pin. In most applica it is easier to share the supply for RGVDD and HVDD, which may be done as long as the individual supply pins are separately bypassed. A separate 3 V supply may also be used for DRVDD, but this supply pin should still be decoupled to the same ground plane as the rest of the chip. A separate ground for DRVSS is not recommended. It is recommended that the exposed paddle on the bottom of the package be soldered to a large pad, with multiple vias connecting the pad to the ground plane.

The analog bypass pins (REFT, REFB) should also be carefully decoupled to ground as close as possible to their respective pins. The analog input (CCDIN) capacitor should also be located close to the pin.

pacitors. The decoupling capacitors should be located as

Figure 38. Typical Circuit Conguration

tions,

The H1–H4 and RG traces should be designed to have low inductance to avoid excessive distortion of the signals. Heavier traces are recommended because of the large transient current demand on H1–H4 by the CCD. If possible, locating the AD9995 physically closer to the CCD will reduce the inductance on these lines. As always, the routing path should be as direct as possible from the AD9995 to the CCD.

The AD9995 also contains an on-chip oscillator for driving an external crystal. Figure 39 shows an example application using a typical 24 MHz crystal. For the exact values of the external resistors and capacitors, it is best to consult with the crystal manufacturer’s data sheet.

–36–

Figure 39. Crystal Driver Application

REV. 0

AD9995

SDATA

A0 A1 A2 A4 A5 A6 A7

D0

D1 D2 D3 D21 D22 D23

SCK

SL

A3

NOTES

1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK MAY IDLE HIGH OR LOW IN BETWEEN WRITE OPERATIONS

.

2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA.

3. IF THE REGISTER LENGTH IS <24 BITS, “DON’T CARE” BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.

4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON TH

E

PARTICULAR REGISTER WRITTEN TO. SEE THE REGISTER UPDATES SECTION FOR MORE INFORMATION.

t

DH

t

LS

t

LH

t

DS

...

8-BIT ADDRESS

24-BIT DATA

1 322 3 4 5 6 7 8 9 10 11 12 30 31

SDATA

A0 A1 A2 A4 A5 A6 A7 D0 D1 D22 D23

SCK

SL

A3

NOTES

1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.

2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS

.

3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).

4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.

D0 D1 D22 D23

D0

...

DATA FOR STARTING

REGISTER ADDRESS

DATA FOR NEXT

REGISTER ADDRESS

D2D1

...

1 322 3 4 5 6 7 8 9 10 31

3433 5655

585759

SERIAL INTERFACE TIMING

All of the internal registers of the AD9995 are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and 24-bit dataword are written starting with the LSB. To write to each register, a 32-bit operation is required, as shown in Figure 40a. Although many registers are fewer than 24 bits wide, all 24 bits must be written for each register. For example, if the register is only 10 bits wide, the upper 14 bits are don’t cares and may be lled with 0s during the serial write operation. If fewer than 24 bits are written, the register will not be updated with new data.

Figure 40a. Serial Write Operation

Figure 40b shows a more efcient way to write to the registers, using the AD9995’s address auto-increment capability. Using this method, the lowest desired address is written rst, followed by multiple 24-bit data-words. Each new 24-bit data-word will automatically be written to the next highest register address. By eliminating the need to write each 8-bit address, faster register loading is achieved. Continuous write operations may be used starting with any register location, and may be used to write to as few as two registers, or as many as the entire register space.

Figure 40b. Continuous Serial Write Operation

REV. 0

–37–

–38

AFE REGISTERS

SWITCH TO REGISTER BANK 2

REGISTER BANK 1

ADDR 0x00

ADDR 0x7F

MISCELLANEOUS REGISTERS

VD/HD REGISTERS

TIMING CORE REGISTERS

CLPOB MASK REGISTERS

VSG PATTERN REGISTERS

SHUTTER REGISTERS

ADDR 0x10

ADDR 0x20 ADDR 0x30

ADDR 0x40

ADDR 0x50

ADDR 0x60

VPAT0–VPAT9 REGISTERS

SWITCH TO REGISTER BANK 1

REGISTER BANK 2

ADDR 0x00

VSEQ0–VSEQ9 REGISTERS

FIELD 0–FIELD 5 REGISTERS

ADDR 0x7F

ADDR 0x80

ADDR 0xD0

ADDR 0xFF

ADDR 0x7E

ADDR 0xCF

WRITE TO ADDRESS 0x7F TO SWITCH REGISTER BANKS

ADDR 0xFF

ADDR 0x8F

INVALID—DO NOT ACCESS

When writing to the AD9995, Address 0x7F is used to specify

–39

V-sequence registers (Addr. 0x00 through 0xCF, exclud-

V-Sequence 3 will be updated at SCP1. If multiple writes

VD Updated

–40

AFE Operation Modes (see Table XXIV for detail).

VGAGAIN

VGA Gain.

AFE Control Modes (see Table XXV for detail).

VD/HD Master or Slave Timing (0 = Slave mode).

VDHDPOL

VD/HD Active Polarity. 0 = Low, 1 = High.

VDHDRISE

VDHDOFF

VSUBMODE

VSUB Readout Mode [0]. VSUB Keep-On Mode [1].

VSUBON

VSUB ON Position [11:0]. VSUB Active Polarity [12].

–43

VPOL_0

VPAT0 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].

V

_0

V1TOG1

_0

V1 Toggle Position 1

V1TOG2

_0

V1 Toggle Position 2

V1TOG3

_0

V1 Toggle Position 3

V2TOG1

_0

V2 Toggle Position 1

V2TOG2

_0

V2 Toggle Position 2

V2TOG3

_0

V2 Toggle Position 3

V3TOG1

_0

V3 Toggle Position 1

V3TOG2

_0

V3 Toggle Position 2

V3TOG3

_0

V3 Toggle Position 3

V4TOG1

_0

V4 Toggle Position 1

V4TOG2

_0

V4 Toggle Position 2

V4TOG3

_0

V4 Toggle Position 3

V5TOG1

_0

V5 Toggle Position 1

V5TOG2

_0

V5 Toggle Position 2

V5TOG3

_0

V5 Toggle Position 3

V6TOG1

_0

V6 Toggle Position 1

V6TOG2

_0

V6 Toggle Position 2

V6TOG3

_0

V6 Toggle Position 3

_0

V1–V6 Freeze Position 1

_0

V1–V6 Resume Position 1

_0

V1–V6 Freeze Position 2

_0

V1–V6 Resume Position 2

VPOL_1

VPAT1 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].

V

_1

V1TOG1

_1

V1 Toggle Position 1

V1TOG2

_1

V1 Toggle Position 2

V1TOG3

_1

V1 Toggle Position 3

V2TOG1

_1

V2 Toggle Position 1

V2TOG2

_1

V2 Toggle Position 2

V2TOG3

_1

V2 Toggle Position 3

V3TOG1

_1

V3 Toggle Position 1

V3TOG2

_1

V3 Toggle Position 2

V3TOG3

_1

V3 Toggle Position 3

V4TOG1

_1

V4 Toggle Position 1

V4TOG2

_1

V4 Toggle Position 2

V4TOG3

_1

V4 Toggle Position 3

V5TOG1

_1

V5 Toggle Position 1

V5TOG2

_1

V5 Toggle Position 2

V5TOG3

_1

V5 Toggle Position 3

V6TOG1

_1

V6 Toggle Position 1

V6TOG2

_1

V6 Toggle Position 2

V6TOG3

_1

V6 Toggle Position 3

_1

V1–V6 Freeze Position 1

_1

V1–V6 Resume Position 1

_1

V1–V6 Freeze Position 2

_1

V1–V6 Resume Position 2

VPOL_2

VPAT2 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].

V

_2

V1TOG1

_2

V1 Toggle Position 1

V1TOG2

_2

V1 Toggle Position 2

V1TOG3

_2

V1 Toggle Position 3

V2TOG1

_2

V2 Toggle Position 1

V2TOG2

_2

V2 Toggle Position 2

V2TOG3

_2

V2 Toggle Position 3

V3TOG1

_2

V3 Toggle Position 1

V3TOG2

_2

V3 Toggle Position 2

V3TOG3

_2

V3 Toggle Position 3

V4TOG1

_2

V4 Toggle Position 1

V4TOG2

_2

V4 Toggle Position 2

V4TOG3

_2

V4 Toggle Position 3

V5TOG1

_2

V5 Toggle Position 1

V5TOG2

_2

V5 Toggle Position 2

V5TOG3

_2

V5 Toggle Position 3

V6TOG1

_2

V6 Toggle Position 1

V6TOG2

_2

V6 Toggle Position 2

V6TOG3

_2

V6 Toggle Position 3

_2

V1–V6 Freeze Position 1

_2

V1–V6 Resume Position 1

_2

V1–V6 Freeze Position 2

_2

V1–V6 Resume Position 2

VPOL_3

VPAT3 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].

V

_3

V1TOG1

_3

V1 Toggle Position 1

V1TOG2

_3

V1 Toggle Position 2

–45

V1TOG3

_3

V1 Toggle Position 3

V2TOG1

_3

V2 Toggle Position 1

V2TOG2

_3

V2 Toggle Position 2

V2TOG3

_3

V2 Toggle Position 3

V3TOG1

_3

V3 Toggle Position 1

V3TOG2

_3

V3 Toggle Position 2

V3TOG3

_3

V3Toggle Position 3

V4TOG1

_3

V4 Toggle Position 1

V4TOG2

_3

V4 Toggle Position 2

V4TOG3

_3

V4 Toggle Position 3

V5TOG1

_3

V5 Toggle Position 1

V5TOG2

_3

V5 Toggle Position 2

V5TOG3

_3

V5 Toggle Position 3

V6TOG1

_3

V6 Toggle Position 1

V6TOG2

_3

V6 Toggle Position 2

V6TOG3

_3

V6 Toggle Position 3

_3

V1–V6 Freeze Position 1

_3

V1–V6 Resume Position 1

_3

V1–V6 Freeze Position 2

_3

V1–V6 Resume Position 2

VPOL_4

VPAT4 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].

V

_4

V1TOG1

_4

V1 Toggle Position 1

V1TOG2

_4

V1 Toggle Position 2

V1TOG3

_4

V1 Toggle Position 3

V2TOG1

_4

V2 Toggle Position 1

V2TOG2

_4

V2 Toggle Position 2

V2TOG3

_4

V2 Toggle Position 3

V3TOG1

_4

V3 Toggle Position 1

V3TOG2

_4

V3 Toggle Position 2

V3TOG3

_4

V3Toggle Position 3

V4TOG1

_4

V4 Toggle Position 1

V4TOG2

_4

V4 Toggle Position 2

V4TOG3

_4

V4 Toggle Position 3

V5TOG1

_4

V5 Toggle Position 1

V5TOG2

_4

V5 Toggle Position 2

V5TOG3

_4

V5 Toggle Position 3

V6TOG1

_4

V6 Toggle Position 1

V6TOG2

_4

V6 Toggle Position 2

V6TOG3

_4

V6 Toggle Position 3

_4

V1–V6 Freeze Position 1

_4

V1–V6 Resume Position 1

_4

V1–V6 Freeze Position 2

_4

V1–V6 Resume Position 2

–46

VPOL_5

VPAT5 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].

V

_5

V1TOG1

_5

V1 Toggle Position 1

V1TOG2

_5

V1 Toggle Position 2

V1TOG3

_5

V1 Toggle Position 3

V2TOG1

_5

V2 Toggle Position 1

V2TOG2

_5

V2 Toggle Position 2

V2TOG3

_5

V2 Toggle Position 3

V3TOG1

_5

V3 Toggle Position 1

V3TOG2

_5

V3 Toggle Position 2

V3TOG3

_5

V3 Toggle Position 3

V4TOG1

_5

V4 Toggle Position 1

V4TOG2

_5

V4 Toggle Position 2

V4TOG3

_5

V4 Toggle Position 3

V5TOG1

_5

V5 Toggle Position 1

V5TOG2

_5

V5 Toggle Position 2

V5TOG3

_5

V5 Toggle Position 3

V6TOG1

_5

V6 Toggle Position 1

V6TOG2

_5

V6 Toggle Position 2

V6TOG3

_5

V6 Toggle Position 3

_5

V1–V6 Freeze Position 1

_5

V1–V6 Resume Position 1

_5

V1–V6 Freeze Position 2

_5

V1–V6 Resume Position 2

VPOL_6

VPAT6 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].

V

_6

V1TOG1

_6

V1 Toggle Position 1

V1TOG2

_6

V1 Toggle Position 2

V1TOG3

_6

V1 Toggle Position 3

V2TOG1

_6

V2 Toggle Position 1

V2TOG2

_6

V2 Toggle Position 2

V2TOG3

_6

V2 Toggle Position 3

V3TOG1

_6

V3 Toggle Position 1

V3TOG2

_6

V3 Toggle Position 2

V3TOG3

_6

V3 Toggle Position 3

V4TOG1

_6

V4 Toggle Position 1

V4TOG2

_6

V4 Toggle Position 2

V4TOG3

_6

V4 Toggle Position 3

V5TOG1

_6

V5 Toggle Position 1

V5TOG2

_6

V5 Toggle Position 2

V5TOG3

_6

V5 Toggle Position 3

V6TOG1

_6

V6 Toggle Position 1

V6TOG2

_6

V6 Toggle Position 2

V6TOG3

_6

V6 Toggle Position 3

_6

V1–V6 Freeze Position 1

_6

V1–V6 Resume Position 1

_6

V1–V6 Freeze Position 2

_6

V1–V6 Resume Position 2

VPOL_7

VPAT7 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].

V

_7

V1TOG1

_7

V1 Toggle Position 1

V1TOG2

_7

V1 Toggle Position 2

V1TOG3

_7

V1 Toggle Position 3

V2TOG1

_7

V2 Toggle Position 1

V2TOG2

_7

V2 Toggle Position 2

V2TOG3

_7

V2 Toggle Position 3

V3TOG1

_7

V3 Toggle Position 1

V3TOG2

_7

V3 Toggle Position 2

V3TOG3

_7

V3 Toggle Position 3

V4TOG1

_7

V4 Toggle Position 1

V4TOG2

_7

V4 Toggle Position 2

V4TOG3

_7

V4 Toggle Position 3

V5TOG1

_7

V5 Toggle Position 1

V5TOG2

_7

V5 Toggle Position 2

V5TOG3

_7

V5 Toggle Position 3

V6TOG1

_7

V6 Toggle Position 1

V6TOG2

_7

V6 Toggle Position 2

V6TOG3

_7

V6 Toggle Position 3

_7

V1–V6 Freeze Position 1

_7

V1–V6 Resume Position 1

_7

V1–V6 Freeze Position 2

_7

V1–V6 Resume Position 2

VPOL_8

VPAT8 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].

V

_8

V1TOG1

_8

V1 Toggle Position 1

V1TOG2

_8

V1 Toggle Position 2

V1TOG3

_8

V1 Toggle Position 3

V1TOG4

_8

V1 Toggle Position 4

–48

V2TOG1

_8

V2 Toggle Position 1

V2TOG2

_8

V2 Toggle Position 2

V3TOG3

_8

V2 Toggle Position 3

V3TOG4

_8

V2 Toggle Position 4

V3TOG1

_8

V3 Toggle Position 1

V4TOG2

_8

V3 Toggle Position 2

V4TOG3

_8

V3 Toggle Position 3

V4TOG4

_8

V3 Toggle Position 4

V5TOG1

_8

V4 Toggle Position 1

V5TOG2

_8

V4 Toggle Position 2

V5TOG3

_8

V4 Toggle Position 3

V6TOG4

_8

V4 Toggle Position 4

V6TOG1

_8

V5 Toggle Position 1

V6TOG2

_8

V5 Toggle Position 2

V6TOG3

_8

V5 Toggle Position 3

V6TOG4

_8

V5 Toggle Position 4

V6TOG1

_8

V6 Toggle Position 1

V6TOG2

_8

V6 Toggle Position 2

V6TOG3

_8

V6 Toggle Position 3

V6TOG4

_8

V6 Toggle Position 4

_8

V1–V6 Freeze Position 1

_8

V1–V6 Resume Position 1

_8

V1–V6 Freeze Position 2

_8

V1–V6 Resume Position 2

VPOL_9

VPAT9 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].

V

_9

V1TOG1

_9

V1 Toggle Position 1

V1TOG2

_9

V1 Toggle Position 2

V1TOG3

_9

V1 Toggle Position 3

V1TOG4

_9

V1 Toggle Position 4

V2TOG1

_9

V2 Toggle Position 1

V2TOG2

_9

V2 Toggle Position 2

V3TOG3

_9

V2 Toggle Position 3

V3TOG4

_9

V2 Toggle Position 4

V3TOG1

_9

V3 Toggle Position 1

V4TOG2

_9

V3 Toggle Position 2

V4TOG3

_9

V3 Toggle Position 3

V4TOG4

_9

V3 Toggle Position 4

V5TOG1

_9

V4 Toggle Position 1

V5TOG2

_9

V4 Toggle Position 2

V5TOG3

_9

V4 Toggle Position 3

V6TOG4

_9

V4 Toggle Position 4

–49

V6TOG1

_9

V5 Toggle Position 1

V6TOG2

_9

V5 Toggle Position 2

V6TOG3

_9

V5 Toggle Position 3

V6TOG4

_9

V5 Toggle Position 4

V6TOG1

_9

V6 Toggle Position 1

V6TOG2

_9

V6 Toggle Position 2

V6TOG3

_9

V6 Toggle Position 3

V6TOG4

_9

V6 Toggle Position 4

_9

V1–V6 Freeze Position 1

_9

V1–V6 Resume Position 1

_9

V1–V6 Freeze Position 2

_9

V1–V6 Resume Position 2

_0

VPATSEL

_0

VMASK

_0

VPATREPO

_0

VPATREPE

_0

VPATSTART

_0

–50

_1

VPATSEL

_1

VMASK

_1

VPATREPO

_1

VPATREPE

_1

VPATSTART

_1

_2

VPATSEL

_2

VMASK

_2

VPATREPO

_2

VPATREPE

_2

VPATSTART

_2

–51

_3

VPATSEL

_3

VMASK

_3

VPATREPO

_3

VPATREPE

_3

VPATSTART

_3

_4

VPATSEL

_4

VMASK

_4

VPATREPO

_4

VPATREPE

_4

VPATSTART

_4

–52

_5

VPATSEL

_5

VMASK

_5

VPATREPO

_5

VPATREPE

_5

VPATSTART

_5

_6

VPATSEL

_6

VMASK

_6

VPATREPO

_6

VPATREPE

_6

VPATSTART

_6

–53

_7

VPATSEL

_7

VMASK

_7

VPATREPO

_7

VPATREPE

_7

VPATSTART

_7

_8

VPATSEL

_8

VMASK

_8

VPATREPO

_8

VPATREPE

_8

VPATSTART

_8

–54

_9

VPATSEL

_9

VMASK

_9

VPATREPO

_9

VPATREPE

_9

VPATSTART

_9

VSEQSEL0_0

_0

VSEQSEL1_0

_0

VSEQSEL2_0

_0

VSEQSEL3_0

_0

VSEQSEL4_0

_0

VSEQSEL5_0

_0

VSEQSEL6_0

_0

V-Sequence Change Position #1 for Field 0.

_0

V-Sequence Change Position #2 for Field 0.

_0

V-Sequence Change Position #3 for Field 0.

_0

V-Sequence Change Position #4 for Field 0.

VDLEN

_0

VD Field Length (Number of Lines) for Field 0.

_0

–55

VPATSECOND

_0

VSG Active Line 1.

_0

VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).

_0

V-Sequence Change Position #5 for Field 0.

_0

V-Sequence Change Position #6 for Field 0.

VSEQSEL0_1

_1

VSEQSEL1_1

_1

VSEQSEL2_1

_1

VSEQSEL3_1

_1

VSEQSEL4_1

_1

VSEQSEL5_1

_1

VSEQSEL6_1

_1

V-Sequence Change Position #1 for Field 1.

_1

V-Sequence Change Position #2 for Field 1.

_1

V-Sequence Change Position #3 for Field 1.

_1

V-Sequence Change Position #4 for Field 1.

VDLEN

_1

VD Field Length (Number of Lines) for Field 1.

_1

VPATSECOND

_1

VSG Active Line 1.

_1

VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).

_1

V-Sequence Change Position #5 for Field 1.

_1

V-Sequence Change Position #6 for Field 1.

–56

VSEQSEL_2

_2

VSEQSEL1_2

_2

VSEQSEL2_2

_2

VSEQSEL3_2

_2

VSEQSEL4_2

_2

VSEQSEL5_2

_2

VSEQSEL6_2

_2

V-Sequence Change Position #1 for Field 2.

_2

V-Sequence Change Position #2 for Field 2.

_2

V-Sequence Change Position #3 for Field 2.

_2

V-Sequence Change Position #4 for Field 2.

VDLEN0

_2

VD Field Length (Number of Lines) for Field 2.

_2

VPATSECOND

_2

VSG Active Line 1.

_2

VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).

_2

V-Sequence Change Position #5 for Field 2.

_2

V-Sequence Change Position #6 for Field 2.

VSEQSEL_3

_3

VSEQSEL1_3

_3

VSEQSEL2_3

_3

VSEQSEL3_3

_3

–57

VSEQSEL4_3

_3

VSEQSEL5_3

_3

VSEQSEL6_3

_3

V-Sequence Change Position #1 for Field 3.

_3

V-Sequence Change Position #2 for Field 3.

_3

V-Sequence Change Position #3 for Field 3.

_3

V-Sequence Change Position #4 for Field 3.

VDLEN

_3

VD Field Length (Number of Lines) for Field 3.

_3

VPATSECOND

_3

VSG Active Line 1.

_3

VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).

_3

V-Sequence Change Position #5 for Field 3.

_3

V-Sequence Change Position #6 for Field 3.

VSEQSEL0

_4

VSEQSEL1

_4

VSEQSEL2

_4

VSEQSEL3

_4

VSEQSEL4

_4

VSEQSEL5

_4

VSEQSEL6

_4

V-Sequence Change Position #1 for Field 4.

V-Sequence Change Position #2 for Field 4.

V-Sequence Change Position #3 for Field 4.

V-Sequence Change Position #4 for Field 4.

–58

VDLEN_4

VD Field Length (Number of Lines) for Field 4.

VPATSECOND_4

VSG Active Line 1.

VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).

V-Sequence Change Position #5 for Field 4.

V-Sequence Change Position #6 for Field 4.

VSEQSEL0

_5

VSEQSEL1

_5

VSEQSEL2

_5

VSEQSEL3

_5

VSEQSEL4

_5

VSEQSEL5

_5

VSEQSEL6

_5

V-Sequence Change Position #1 for Field 5.

V-Sequence Change Position #2 for Field 5.

V-Sequence Change Position #3 for Field 5.

V-Sequence Change Position #4 for Field 5.

VDLEN_5

VD Field Length (Number of Lines) for Field 5.

VPATSECOND_5

VSG Active Line 1.

VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).

V-Sequence Change Position #5 for Field 5.

V-Sequence Change Position #6 for Field 5.

–59

8 mm Body

PIN 1 INDICATOR

TOP

VIEW

7.75

BSC SQ

8.00

BSC SQ

1

56

14

15

43

42

28

29

BOTTOM

VIEW

6.25

6.10

5.95

0.50

0.40

0.30

0.23

0.18

0.50 BSC

12 MAX

0.20 REF

0.80 MAX

0.65 NOM

6.50

REF

SEATING PLANE

0.60 MAX

PIN 1 INDICATOR

COPLANARITY

0.08

SQ

0.05 MAX

0.02 NOM

0.25 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

–60

Datasheet AD9995 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

H-Driver and RG Outputs

Digital Data Outputs

HORIZONTAL CLAMPING AND BLANKING

Individual CLPOB and PBLK Patterns

Individual HBLK Patterns

EXPOSURE AND READOUT EXAMPLE

DC RESTORE

ANALOG FRONT END DESCRIPTION AND OPERATION

Correlated Double Sampler

A/D Converter

Optical Black Clamp

Digital Data Outputs

Generating Software SYNC without External SYNC Signal

CIRCUIT LAYOUT INFORMATION

SERIAL INTERFACE TIMING