Datasheet AD9959 Datasheet (Analog Devices)

4 Channel 500MSPS DDS with 10-bit DACs

Preliminary Technical Data

FEATURES

Four synchronized DDS channels @500 MSPS Independent Frequency/Phase/Amplitude control between channels Matched latencies for Frequency/Phase/Amplitude changes Excellent channel to channel isolation (>60dB) Linear Frequency/Phase/Amplitude sweeping capability Up to 16 levels of Frequency/Phase/Amplitude modulation (pin

selectable P0-P3) Individually programmable DAC full scale currents Four integrated 10-bit D/A converters (DACs) 32-bit Frequency tuning resolution 14-bit Phase Offset resolution 10-bit Output Amplitude Scaling resolution Serial I/O Port (SPI) with enhanced data throughput

FUNCTIONAL BLOCK DIAGRAM

Σ

32 32

Σ

32 32

Σ

32

Σ

32

TIMING & CONTROL LOGIC

SYSTEM

CLK

Figure 1 AD9959 Block Diagram

SYNC_IN

SYNC_OUT

I/O_UPDATE

SYNC_CLK

REF_CLK

FTW

BUFFER / XTAL

OSCILLATOR

CLK_MODE_SEL

32

÷4

REF CLOCK MULTIPLIER

FTW

4x to 20x

Σ

M U X

Software/Hardware controlled power-down Dual supply operation (1.8 V DDS core / 3.3 V serial I/O) Built-in synchronization for multiple devices Selectable REF_CLK multipier (PLL) 4x to 20x (bypassable) Selectable REF_CLK crystal operation 56 pin LFCSP package

APPLICATIONS

Agile L.O. frequency synthesis Phased array radar / sonar Instrumentation Synchronized clocking RF source for AOTF

DDS CORE

COS(X)

15

DDS CORE

COS(X)

15

DDS CORE

COS(X)

15

DDS CORE

COS(X)

15

14

1.8V 1.8V 3.3V

AVDD DVDD

10

AMP /

AMP

×

10

×

10

×

10

×

10

CONTROL

REGISTERS

CHANNEL

REGISTERS

PROFILE

REGISTERS

P

S

2

1

0

PHASE /

PHASE

Σ

P S 3

DAC

SCALABLE

DAC REF

CURRENT

DVDD_I/O

I/O

Port

Buffer

AD9959

IOUT

IOUT IOUT

DAC_RSET

PWR_DWN_CTL

MASTER_RESET

SCLK

CS

SDIO_0 SDIO_1 SDIO_2 SDIO_3

Rev. PrD

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Preliminary Technical Data AD9959

TABLE OF CONTENTS

Features……………………………………………….1

Functional Block Diagram…………….……………...1

Specifications…………………………….……...……3

Absolute Maximum Ratings………….……….......….6

Equivalent Circuits……………………………………6

Product Overview…………………………………….7

Pin Configuration………………………………….....8

Pin Function Description……………….…………….9

Typical Performance Characteristics……………...…10

Application Circuits………………………………….13

Theory of Operation.....................................................14

Modes of Operation.....................................................16

Single Tone………...............................................16

Matched Pipe Line Delay……………………….16

REF CLK ………………………….. ………16

Serial Port Operation……………….…………………28

Overview………………………………………..28

General Serial Port Operation…………………..28

Serial I/O Port Pin Description…………………29

Serial I/O Port Function Description…………...29

MSB / LSB Transfer description……...….…….29

Serial I/O Modes of Operation…………………30

Serial I/O Timing……………………………….31

Control Register Map…………………………...……33

Channel Register Map……………..…………………34

Channel Register Map……………..…………………35

Register Map Bit Description……………………...…36

Package Outline…….……………..…………………40

Scalable DAC reference…………….…………..17

Power Down Functions………………………….17

Direct Modulation……….………………………18

Linear Sweep……………………………………21

Output Ramp…………………………………….24

Synchronizing multiple AD9959 devices..….…..26

REVISION HISTORY

PrA- Intial Release

PrB- Pin Out change

PrC-Internal edit update

Rev. PrD | Page 2 of 41

Preliminary Technical Data AD9959

AD9959—SPECIFICATIONS

Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R Frequency = 500 MSPS (REF_CLK multiplier bypassed)

Parameter

REF CLOCK INPUT CHARACTERISTICS

Frequency Range REF_CLK Multiplier bypassed 0 500 MHz REF_CLK Multiplier enabled at 4x(min) 25 125 MHz REF_CLK Multiplier enabled at 20x(max) 5 25 MHz Internal VCO range w/ REF_CLK multiplier enabled 100 500 MHz Crystal REF_CLK source mode 20 30 MHz Input Power Sensitivity -5 3 dBm External 50 ohm termination Input voltage level 400 mV Input Capacitance 3 pF Input Impedance 1500 ohms

Duty Cycle w/ REF_CLK Multiplier bypassed 50 %

Duty Cycle w/ REF_CLK Multiplier enabled 35 65 % CLK Mode Select logic 1 Voltage 1.25 V Not a 3.3V digital input CLK Mode Select logic 0 Voltage 0.6 V Not a 3.3V digital input

DAC OUTPUT CHARACTERISTICS

Resolution 10 Bits Full Scale Ouput Current 10 mA Gain Error -10 10 %FS Output Offset 0.6 uA Differential Nonlinearity -0.5 0.5 LSB Integral Nonlinearity -1 1 LSB Output Capactiance

Voltage Compliance Range

Channel to Channel Isolation 60 dB Channel to Channel Output Amplitude Matching Error 2 %

WIDEBAND SFDR

1-20 MHz Analog Out -65 dBc

20-60 MHz Analog Out -62 dBc

60-100 MHz Analog Out -59 dBc 100-150 MHz Analog Out -56 dBc 150-200 MHz Analog Out -54 dBc

NARROWBAND SFDR

1.1 MHz Analog Out (+/- 10kHz) -90 dBc

1.1 MHz Analog Out (+/- 50kHz) -88 dBc

1.1 MHz Analog Out (+/- 250kHz) -86 dBc

1.1 MHz Analog Out (+/- 1MHz) -85 dBc

15.1 MHz Analog Out (+/- 10kHz)

15.1 MHz Analog Out (+/- 50kHz) -87 dBc

15.1 MHz Analog Out (+/- 250kHz) -85 dBc

15.1 MHz Analog Out (+/- 1MHz) -83 dBc

40.1 MHz Analog Out (+/- 10kHz)

40.1 MHz Analog Out (+/- 50kHz) -87 dBc

40.1 MHz Analog Out (+/- 250kHz) -84 dBc

40.1 MHz Analog Out (+/- 1MHz) -82 dBc

Min Typ

5

AVDD–

0.50

-90

Max Units

pF

AVDD

+ 0.50

= 1.96 kΩ, External Reference Clock

SET

Test Conditions/Comments

REF_CLK inputs must be AC

coupled due to internal biasing

Must be referenced to AVDD

V

Wideband SFDR defined as DC to

dBc

Nyquist

Rev. PrD | Page 3 of 41

Preliminary Technical Data AD9959

Parameter

75.1 MHz Analog Out (+/- 10kHz) -87 dBc

75.1 MHz Analog Out (+/- 50kHz) -85 dBc

75.1 MHz Analog Out (+/- 250kHz) -83 dBc

75.1 MHz Analog Out (+/- 1MHz) -82 dBc

100.3 MHz Analog Out (+/- 10kHz) -87 dBc

100.3 MHz Analog Out (+/- 50kHz) -85 dBc

100.3 MHz Analog Out (+/- 250kHz) -83 dBc

100.3 MHz Analog Out (+/- 1MHz) -81

200.3 MHz Analog Out (+/- 10kHz) -87 dBc

200.3 MHz Analog Out (+/- 50kHz) -85 dBc

200.3 MHz Analog Out (+/- 250kHz) -83 dBc

200.3 MHz Analog Out (+/- 1MHz) -81

PHASE NOISE CHARACTERISTICS

Residual Phase Noise @15.1 MHz(Aout)

@1kHz offset TBD dBc/ Hz @10kHz offset TBD dBc/ Hz @100kHz offset TBD dBc/ Hz @1MHz offset TBD dBc/ Hz

Residual Phase Noise @ 75.1 MHz(Aout)

@1kHz offset TBD dBc/ Hz @10kHz offset TBD dBc/ Hz @100kHz offset TBD dBc/ Hz @1MHz offset TBD dBc/ Hz

Residual Phase Noise @ 200.1 MHz(Aout)

@1kHz offset TBD dBc/ Hz @10kHz offset TBD dBc/ Hz @100kHz offset TBD dBc/ Hz

@1MHz offset TBD dBc/ Hz Residual Phase Noise @ 15.1 MHz(Aout) w/ REF CLK multiplier enabled 4x

@1kHz offset TBD dBc/ Hz

@10kHz offset TBD dBc/ Hz

@100kHz offset TBD dBc/ Hz

@1MHz offset TBD dBc/ Hz

Residual Phase Noise @ 75.1 MHz(Aout) w/ REF CLK multiplier enabled 4x

@1kHz offset TBD dBc/ Hz

@10kHz offset TBD dBc/ Hz

@100kHz offset TBD dBc/ Hz

@1MHz offset TBD dBc/ Hz Residual Phase Noise @ 200.1 MHz(Aout) w/ REF CLK multiplier enabled 4x

@1kHz offset

@10kHz offset

@100kHz offset

@1MHz offset

SERIAL PORT TIMING CHARACTERISTICS

Maximum Frequency

Minimum Clock Pulsewidth Low (t

Minimum Clock Pulsewidth High (t

) TBD

PWL

) TBD

PWH

Min Typ

TBD

Max Units Test Conditions/Comments

dBc

dBc/ Hz

200 MHz

ns

Rev. PrD | Page 4 of 41

Preliminary Technical Data AD9959

Maximum Clock Rise/Fall Time

Minimum Data Setup Time (tDS) TBD

Minimum Data Hold Time TBD

MISC TIMING CHARACTERISTICS

Master_Reset minimum Pulsewidth TBD

I/O_Update minimum Pulsewidth 1

Minimum setup time (IO_Update to Sync_CLK) TBD

Minimum hold time (IO_Update to Sync_CLK) 0 Minimum setup time (Profile inputs to Sync_CLK) TBD Minimum hold time (Profile inputs to Sync_CLK) 0

DATA LATENCY (PIPE LINE DELAY)

Freq, Phase, Amplitude words to DAC output w/ matched latency enabled

Frequency word to DAC output w/ matched latency disabled TBD TBD

Phase Offset word to DAC output w/ matched latency disabled TBD TBD

Amplitude word to DAC output w/ matched latency disabled TBD TBD

CMOS LOGIC INPUTS

VIH 2.2

VIL

Logic 1 Current 3

Logic 0 Current -12

Input Capacitance 2

CMOS LOGIC OUTPUTS (1 mA Load)

VOH 2.8

VOL

POWER SUPPLY

Total Power Dissipation- all channels ON, single-tone mode TBD

Maximum Power Dissipation- all channels, freq accumulator output multiplier ON Iavdd – All Channels ON, Single tone mode TBD

Iavdd – All Ch(s) ON, Freq accum, and output multiplier ON TBD

Idvdd – All Ch(s) ON, Single tone mode TBD

Idvdd – All Ch(s) ON, Freq accum, and output multiplier ON TBD

Idvdd_I/O TBD

Power down Mode TBD

TBD TBD

TBD

TBD ns

ns

Sync CLK

ns Rising edge to rising edge

ns

Sys Clks

V

0.6 V

12 uA

uA

pF

V

0.4 V

mW

mA

Rev. PrD | Page 5 of 41

Preliminary Technical Data AD9959

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C DVDD_I/O (Pin 49) 4 V AVDD, DVDD 2 V Digital Input Voltage (DVDD_I/O = 3.3 V) –0.7 V to +4V Digital Output Current 5 mA Storage Temperature –65°C to +150°C Operating Temperature –40°C to +105°C Lead Temperature (10 sec Soldering) 300°C

θJA 21°C/W

θJC 2°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

CMOS

DIGITAL

INPUTS

DVDD_I/O= 3.3V

INPUT

AVOID OVERDRIVING

DIGITAL INPUTS.

FORWARD BIASING

DIODES MAY COUPLE

DIGITAL NOISE ON

POWER PINS.

OUTPUT

DAC OUPUTS

Iout

TERMINATE OUTPUTS

INTO AVDD. DO NO T

EXCEED OUTPUT

VOLTAGE COMPLIANCE.

Iout

REF_CLK

AVDD AVDD

OSC OSC

OSC / REF_CLK

1.5 k

INPUTS

AVDD

zz

AMP

1.5 k REF_CLK

Figure 1 Equivalent input and output circuits

Rev. PrD | Page 6 of 41

REF_CLK INPUTS ARE

INTERNALLY BIASED AND

NEED TO BE AC-COUPLED.

OSC INPUTS ARE DC

COUPLED

Friday, Feb 4, 2005 4:06 PM /

Preliminary Technical Data

PRODUCT OVERVIEW

The AD9959 consists of four DDS cores that provide independent frequency, phase, and amplitude control between channels. This flexibility can be used to correct imbalances between signals due to analog processing such as filtering, amplification, or PCB layout related mismatches. Since all channels share a common system clock, they are inherently synchronized. If additional channels are required, synchronizing multiple AD9959s is a simple task.

The AD9959 can perform 2/4/8 or 16 level modulation of frequency, phase or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.

The AD9959 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers a SPI compatible mode of operation which is virtually identical to the SPI operation found in earlier ADI DDS products. The flexibility is provided by four data (SDIO_0:3) pins that allow four programmable modes of serial I/O operation.

The AD9959 uses advanced DDS technology which provides low power dissipation with high performance. The device incorporates four integrated high speed 10-bit DACs with excellent wideband and narrowband SFDR. Each channel has a 32-bit frequency tuning word, 14-bits of phase offset, and a 10-

AD9959

bit output scale multiplier.

The DDS acts as a high resolution frequency divider with the REF_ CLK as the input and the DAC providing the output. The REF_CLK input source is common to all DDS channels, and can be driven directly, or used in combination with an integrated REF_CLK multiplier (using a PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REF_CLK input also features an oscillator circuit to support an external crystal as the REF_CLK source. The crystal must be between 20MHz and 30MHz. The crystal can be used in combination with or without the REF_CLK multiplier.

The DAC outputs are supply referenced and must be terminated into AVDD by a resistor, or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable a different full scale current for each channel.

The AD9959 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) must be powered by a

1.8V supply. The digital I/O interface (SPI) operates at 3.3V and requires that the pin labeled “DVDD_I/O” (pin 49) be connected to 3.3V.

The AD9959 operates over the industrial temperature range of 40C to +85C.

Preliminary Technical Data AD9959

PIN CONFIGURATION

I/O_UPDATE

DGND

55

56

SDIO_3

DVDD

SYNC_CLK 54

53

52

51

SCLK

49

48

50

47

CS

DVDD_ I/O

SDIO_0

SDIO_1

SDIO_2

DVDD

DGND

P3

46

45

44

43

SYNC_IN

SYNC_OUT

MASTER_RESET

PWR_DWN_CTL

AVDD

AGND

AVDD

CH2_IOUT

CH2 _IOUT

AGND

AVDD

AGND

CH3_IOUT CH3_IOUT

1

2 3 4 5 6 7 8

9 10 11 12 13 14

16

15

AVDD

AGND

AD9959

56-LD LFCSP

TOP VIEW

(Not to Scale)

17

18

19

20

AVDD

AGND

DAC_RSET

22

23

24

21

AVDD

REF_CLK

25

AGND

REF_CLK

CLK_MODE_SEL

Notes :

1) The exposed EPAD on bottom side of package is an electrical connection and must be soldered to ground.

2) Pin 49 is DVDD_IO and is tied to 3.3V.

42

P2

41

P1 P0

40 39

AVDD

38

AGND

37

AVDD

36

CH1_IOUT

35

CH1_IOUT

34

AGND

33

AVDD

32

AGND

31

AVDD

30

CH0_IOUT

29

CH0_IOUT

26

27

28

AVDD

AGND

LOOP _FILTER

Rev. PrD | Page 8 of 41

Preliminary Technical Data AD9959

Table 3. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 SYNC_IN I Used to synchronize multiple AD9959s. Connect to the SYNC_OUT pin of the master AD9959. 2 SYNC_OUT O Used to synchronize multiple AD9959s. Connect to the SYNC_IN pin of the slave AD9959. 3 MASTER_RESET I Active high reset pin. Asserting the RESET pin forces the AD9959’s internal registers to their default state, as

4 PWR_DWN_CTL I External Power-Down Control. 5,7,11,15,19,21, 26,31,33,37,39 6,10,12,16,18,20, 25,28,32,34,38 45, 55 DVDD I Digital Power Supply Pins (1.8 V). 44, 56 DGND I Digital Power Ground Pins. 8 CH2_IOUT O True DAC Output. Terminate into AVDD.

9

13 CH3_IOUT O True DAC Output. Terminate into AVDD.

14

17 DAC_RSET I Establishes the reference current for all DACs. A 1.91 kΩ resistor (nominal) is connected from pin 17 to AGND. 22

23 REF_CLK I Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this is the input. See

24 CLK_MODE_SEL I CAUTION: Do not drive this pin beyond 1.8V. Control Pin for the Oscillator Section. When high (1.8V), the

27 LOOP_FILTER I Connect to the external zero compensation network of the PLL loop filter for the REFCLK multiplier. For a 20x

AVDD I Analog Power Supply Pins (1.8V).

AGND I Analog Ground Pins.

_________ CH2_IOUT

_________ CH3_IOUT

REF_CLK

described in the serial I/O port register map section in this document.

O Complementary DAC Output. Terminate into AVDD.

I Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this

pin should be decoupled to AVDD or AGND with a 0.1 µF capacitor.

Mode of Opertion section for Reference Clock configuration schematic.

oscillator section is enabled to accept a crystal as the REFCLK source. When low, the oscillator section is bypassed.

multiplier value the network should be a 1.2kΩ resistor in series with a 1.2 nF capacitor tied to AVDD.

29

30 CH0_IOUT O True DAC Output. Terminate into AVDD.

35

36 CH1_IOUT O True DAC Output. Terminate into AVDD. 40, 41, 42, 43

46 I/O_UPDATE I A rising edge detected on this pin transfers data from serial port buffer to active registers. 47 CS

48 SCLK I Serial data clock for I/O operations. Data bits are written on rising edge of SCLK and read on the falling edge of

49 DVDD_I/O I 3.3 V Digital Power Supply for SPI port and digital I/O. 50, 51 52, 53 54 SYNC_CLK O I/O_UPDATE and Profile signals must meet the set-up and hold requirements with respect to this signal in

_________ CH0_IOUT

_________ CH1_IOUT

PS0, PS1, PS2, PS3

SDIO_0, SDIO_1 SDIO_2, SDIO_3

O Complementary DAC Output. Terminate into AVDD.

I These pins are ata pins when modulating. They are synchronous to the SYNC_CLK (pin 54). Any change in

Profile inputs transfers the contents of the internal buffer memory to the I/O active registers (same as an external I/O _UPDATE).

I Active low chip select allowing multiple devices to share a common I/O bus (SPI).

SCLK.

I/O Data pin SDIO_0 is dedicated to the serial port I/O only. Data pins SDIO_1:3 can be used for the serial port I/O

or used as data pins for ramp up/down (RU/RD) of the DAC output amplitude.

order to guarantee a fixed pipeline delay of data to DAC outputs.

Rev. PrD | Page 9 of 41

TYPICAL PERFORMANCE CHARACTERISTICS

Figure x. F

= 1.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

= 40.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

Figure x. F

= 15.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

Figure x. F

= 75.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

Figure x. F

= 100.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

Figure x. F

= 200.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

Preliminary Technical Data AD9959

Figure x. F

= 1.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

= 40.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

Figure x. F

= 15.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

Figure x. F

= 75.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

Figure x. F

= 100.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

Rev. PrD | Page 11 of 41

Figure x. F

= 200.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

Preliminary Technical Data AD9959

Figure x. Residual Phase Noise with F

100.1 MHz 200.1 MHz

F

= 500 MHz with REF_CLK Multiplier bypassed

CLK

= 15.1 MHz, 40.1 MHz,75.1 MHz

OUT

Figure x. Residual Phase Noise with F

100.1 MHz 200.1 MHz

F

= 500 MHz with REF_CLK Multiplier = 4x

CLK

Figure x. Residual Phase Noise with F

100.1 MHw00.1 MHz

F

= 500 MHz with REF_CLK Multiplier = 20x

CLK

= 15.1 MHz, 40.1 MHz,75.1 MHz

OUT

= 15.1 MHz, 40.1 MHz,75.1 MHz

OUT

Rev. PrD | Page 12 of 41

Preliminary Technical Data AD9959

APPLICATION CIRCUITS

REF CLK

AD9959

RF / IF Input Modulated / Demodulated

LPF

signal

Figure x. L.O. for Up/Down conversion

FILTER

AD9959

LOOP

VCO

REF CLK

PHASE

COMPARATOR

LPF

Figure x. Digitally Programmable Divide-by-N Function in PLL

I Baseband

LPF

I

CH 0

AD9959

REF CLK

CH 1

Q

LPF

Q Baseband

Figure x. Quadrature Up Conversion

Rev. PrD | Page 13 of 41

Preliminary Technical Data AD9959

=

THEORY OF OPERATION

DDS Core

The AD9959 has four DDS cores each consisting of a 32-bit phase accumulator and phase-to-amplitude converter. Together these digital blocks generate a digital sine wave when the phase accumulator is clocked and the phase increment value (frequency tuning word) is greater than zero. The phase-toamplitude converter simultaneously translates phase information to amplitude information by a COS (θ) operation.

The output frequency (f

) of each DDS channel is a function of

O

roll over rate of each phase accumulator. The exact relationship is given below where f is the frequency tuning word and 2

is defined as the system clock rate, FTW

S

32

represents the phase

accumulator’s capacity.

()

SO

3132

202/ ≤≤= FTWwithfFTWf

Since all four channels share a common system clock, they are inherently synchronized.

The DDS core architecture also supports the capability to phase offset the output signal. This is performed by the channel phase offset word (CPOW). The CPOW is a 14-bit register that stores a phase offset value. This value is added to the output of the phase accumulator to offset the current phase of the output signal. Each channel has its own phase offset word register. This feature can be used for placing all channels in a known phase relationship relative to one another. The exact value of phase offset is given by the following formula:

I/6.19R

OUTSET

The maximum full-scale output current of the combined DAC outputs is 15mA, but limiting the output to 10mA provides optimal spurious-free dynamic range (SFDR) performance. The DAC output voltage compliance range is AVDD + 0.5 V to AVDD – 0.5 V. Voltages developed beyond this range may cause excessive harmonic distortion. Proper attention should be paid to the load termination to keep the output voltage within its compliance range. Exceeding this range could potentially damage the DAC output circuitry.

DAC

Iout

AVDD

Mini circuits p/n (T1 1T)

1 : 1

25 ohm

LPF

50 ohms

Figure x Typical DAC output termination configuration

MODES OF OPERATION

There are many combinations of modes (single-tone, modulation, linear sweep etc.) that the AD9959 can perform simultaneously.

However, some modes require multiple data pins which can impose limitations. The following guidelines may help determine if a specific combination of modes can be performed simultaneously by the AD9959.

POW

⎛

=Φ 360

⎜ ⎝

⎞ ⎟

14

2

⎠

°×

D/A Converter (DAC)

The AD9959 incorporates four 10-bit current output DACs. The DAC converts a digital code (amplitude) into a discrete analog quantity. The DAC’s current outputs can be modeled as a current source with high output impedance (typically 100k ohms). Unlike many DACs, these current outputs require termination into AVDD via resistor or center-tapped transformer for expected current flow.

Each DAC has complementary outputs that provide a combined full-scale output current (I

OUT + IOUTB

). The outputs always sink current and their sum equals the full scale current at any point in time. The full-scale current is controlled by means of an external resistor (R bits discussed in the Modes of Operation. The (R

) and the scalable DAC current control

SET

) resistor is

SET

connected between the DAC_RSET pin and analog ground (AGND). The full-scale current is proportional to the resistor value as follows:

Rev. PrD | Page 14 of 41

AD9959 Channel Constraint Guidelines

1. The following modes can be enabled on any channel, in any combination at the same time.

• Single Tone Generation.

• 2 Level Modulation.

• Linear sweep.

2. Any one channel or any two channels in any combination can perform 4-level modulation. The remaining channels can be in single tone generation mode.

3. Any one channel can perform 8-level modulation. The three remaining channels can be in single tone mode.

4. Any one channel can perform 16-level direct modulation. The three remaining channels can be in single tone mode.

5. The RU/RD function can be used on all four channels in single tone generation mode.

6. When profile pins P2 and P3 are used for RU/RD, any two channels can perform 2-level modulation with RU/RD or any two channels can perform linear frequency or phase sweep with RU/RD. The other two channels can be in single tone generation

Preliminary Technical Data AD9959

mode.

7. When profile pin P3 is used for RU/RD, any channel can be used in 8-level modulation with RU/RD. The other three channels can be in single tone generation mode.

8. When SDIO_1:3 pins are used for RU/RD, any one channel or any two channels or any three channels or all four channels can perform 2-level modulation with RU/RD. Any channels not in the 2-level modulation can be in single tone generation mode.

The serial I/O is restricted in 1 bit mode for the above condition.

9. When the SDIO_1:3 pins are used for RU/RD, any one or any two channels can perform 4-level modulation with RU/RD. Any channels not in the 4-level modulation can be in single tone generation mode.

The serial I/O is restricted in 1 bit mode for the above condition.

Power Supplies

The AVDD and DVDD supply pins provide power to the DDS core and supporting analog circuitry. These pins should be connected to 1.8V nominal.

The DVDD_IO pin should be connected by 3.3V nominal. All digital inputs are 3.3V logic except the CLK_MODE_SEL input.

10. When the SDIO_1:3 pins are used for RU/RD, any one of the channels can perform 16-level modulation with RU/RD. The other three channels can be in single tone generation mode.

The serial I/O is restricted in 1 bit mode for the above condition.

11. Amplitude modulation or linear amplitude sweep modes and the RU/RD function can not operate at the same time without disabling one or the other. But frequency and phase modulation can operate at the same time as the RU/RD function.

The CLK_MODE_SEL (pin 24) is an analog input and should operate on 1.8V logic.

Serial I/O Port

Refer to the Serial I/O Port Operation section.

Rev. PrD | Page 15 of 41

Preliminary Technical Data AD9959

MODES OF OPERATION

SINGLE-TONE MODE

Single-tone mode is the default mode of operation after a master reset signal. In this mode, all four DDS channels share a common address location for the frequency tuning word (register address 04hex) and phase offset word address location (register address 05hex). Channel enable bits are provided in combination with these shared addresses. As a result, the frequency tuning word and/or phase offset word can be independently programmed between channels (see steps 1 through 5 below). The channel enable bits do not require an I/O UPDATE to enable or disable a channel.

The channel enable bits are found in the Control Register Map section of this data sheet. The specific register is called “Channel Select Register” or CSR (register address 00hex). The channel enable bits are enabled or disabled immediately after the CSR’s data byte is written.

Address sharing enables channels to be written simultaneously, if desired. The default state enables all channel enable bits. Therefore, the frequency tuning word and/or phase offset word will be common to all channels, but written only one time through the serial I/O port.

The following steps are a basic protocol to program a different frequency tuning word and/or phase offset word for each channel using the channel enable bits.

1)

Power-up DUT and issue a Master Reset. A Master

Reset places the part in single-tone mode and also single-bit mode for serial programming operations (refer to Serial I/O Operation). Frequency tuning words and phase offset words default to zero at this point.

2)

Enable only one Channel Enable bit (address 00hex),

disable the other Channel Enable bits.

3)

Using the serial I/O port, program the desired

frequency tuning word (address 04hex) and/or phase offset word (address 05hex) for the enabled channel.

4)

Repeat steps 2 and 3 for each channel.

5)

Send an I/O UPDATE signal. After an I/O UPDATE,

all channels should output their programmed frequency and/or phase offset value.

delays between the three input ports. The feature is enabled by asserting the Match pipe delay bit found in the (Channel Function Register (CSR) (address 03hex). This feature is available in Single-Tone mode only.

REFERENCE CLOCK INPUT CIRCUITRY

The Reference Clock input circuitry has two modes of operation controlled by the logic state of pin 24 (Clock Mode Select). The first mode (logic low) configures as an input buffer. In this mode, the Reference Clock must be ac-coupled to the input due to internal dc biasing. This mode supports either differential or single-ended configurations. If single-ended is chosen the complementary reference clock input (pin 23) should be de-coupled to AVDD via a 0.1µf capacitor. The following diagrams exemplify Reference Clock configurations for the AD9959.

Refernce

Clock

Source

0.1uF

1 : 1 Balun

50 ohms

0.1uF

REF_CLK

pin 23

REF_CLK

pin 22

The Reference clock inputs can also support an LVPECL or PECL driver as the Reference Clock source.

TERMINATION

LVPECL /

PECL

DRIVER

0.1uF

REF_CLK

pin 23

REF_CLK

pin 22

The second mode of operation (pin 24 = logic high = 1.8V) provides an internal oscillator for crystal operation. In this mode, both clock inputs are dc-coupled via the crystal leads and bypassed to ground with capacitors. The range of crystal frequencies supported is from 20 to 30 MHz. The following is the configuration for using a crystal.

Single-Tone Mode - Matched pipe-line delay

In Single-Tone Mode, the AD9959 offers matched pipe line delay to the DAC input for all frequency, phase and amplitude changes. This avoids having to figure out the different pipe line

Rev. PrD | Page 16 of 41

Preliminary Technical Data AD9959

22 pF

REF_CLK

pin 23

25 MHz

XTAL

22 pF

REF_CLK

pin 22

REFERENCE CLOCK MODES

The AD9959 supports multiple Reference Clock configurations to generate the internal system clock. Flexibility of producing the internal system clock is provided by enabling the on-chip oscillator, and/or the 4x to 20x Reference Clock Multiplier (PLL). However these circuits are typically disabled to achieve the best output ac performance (PLL defaults bypassed).

The following instructs how to use the on-chip oscillator and PLL.

Enabling the on-chip oscillator for crystal operation is performed by driving the CLK_MODE_SEL (pin 24) to logic high (1.8V logic). With the on-chip oscillator enabled, connect an external crystal to the REF_CLK and REF_CLKB inputs to produce a low frequency reference clock. The crystal’s frequency must be in the range of 20 MHz to 30 MHz.

The Reference Clock Multiplier (PLL) allows multiplication of the REF_CLK frequency. Control of the PLL is accomplished by programming the 5-bit REF_CLK multiplier portion in Function Register One (FR1), bits <22:18>.

When programmed for values ranging from 04hex to14hex (4 decimal to 20 decimal), the PLL multiplies the REF_CLK input frequency by the corresponding decimal value. However, the output frequency of the PLL is restricted to a frequency range of 100 MHz to500 MHz. The PLL is bypassed by programming a value outside the range of 4 to 20 (decimal). Whenever the PLL is engaged or value changed, time must be allocated to allow the PLL to lock (approximately 1ms)

The table below summarizes the clock modes of operation.

CLK_MODE_SEL

Pin (24)

High = 1.8V logic

FR1<22:18> PLL bits = M

4 ≤ M ≤ 20

Oscillator

Enabled

Yes F

High = 1.8V logic M < 4,or M > 20 Yes F

Low

4 ≤ M ≤ 20

No F

Low M < 4,or M > 20 No F

SCALABLE DAC REFERENCE CURRENT CONTROL MODE

The R

is common to all four DACs. As a result, the full scale

set

currents are equal as a default. The scalable DAC reference can be used to set each DAC’s full scale current independently from one another. This is accomplished by using the CFR register bits<9:8>. The following table shows how each DAC can be individually scaled for independent channel control. This provides for binary attenuation.

CFR <9:8> LSB Current State

1 1 Full Scale

1 0 Half Scale

0 1 Quarter Scale

0 0 Eighth Scale

System Clock

(F

SYS CLK

= F

SYS CLK

= F

SYS CLK

= F

SYS CLK

)

= F

× M 100 < F

OSC

20 < F

OSC

× M 100 < F

REF CLK

0 < F

REF CLK

MIN / MAX

Frequency Range (MHz)

< 500

SYS CLK

< 30

SYS CLK

< 500

SYS CLK

< 500

SYS CLK

POWER DOWN FUNCTIONS OF THE AD9959

The AD9959 supports an externally controlled power down feature as well as the more common software programmable power down bits found in previous ADI DDS products.

The software control power down allows the Input Clock circuitry, DAC and the digital logic (for each separate channel) to be individually powered down via unique control bits

(CFR<7:6>). These bits are not active when the externally controlled power down pin (PWR_DWN_CTL) is high.

When the PWR_DWN_CTL input pin is high, the AD9959 will enter a power down mode based on the FR1<6> bit. When the PWR_DWN_CTL input pin is low, the external power down control is inactive.

Rev. PrD | Page 17 of 41

Preliminary Technical Data AD9959

When the FR1<6> bit is zero, and the PWR_DWN_CTL input pin is high, the AD9959 is put into a “fast recovery power down” mode. In this mode, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, oscillator, and clock input circuitry is NOT powered down.

When the FR1<6> bit is high, and the PWR_DWN_CTL pin is high, the AD9959 is put into the “full power down” mode. In this mode, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up. When the PLL is bypassed, the PLL is shut down to conserve power.

When the PWR_DWN_CTL input pin is high, the individual power down bits (CFR<7:6>) & FR1<7>) are invalid (don’t care) and are unused. When the PWR_DWN_CTL input pin is low, the individual power down bits controls the power down modes of operation.

AFP (CFR<23:22>) Linear Sweep

Enable

(CFR<14>)

0 0 X Modulation disabled.

0 1 0 Amplitude Modulation

1 0 0 Frequency Modulation

1 1 0 Phase Modulation

Modulation Level bits (FR1<9:8>) DESCRIPTION

0 0 2-level Modulation

0 1 4-level Modulation

1 0 8-level Modulation

DESCRIPITON

NOTE – The power down signals are all designed such that a logic 1 indicates the low power mode and a logic 0 indicates powered up mode.

MODULATION MODE

The AD9959 can perform 2/4/8 or 16 level modulation of frequency, phase or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. Each channel can be programmed separately for modulation but the ability to modulate multiple channels simultaneously is constrained by the number of profile pins and their modulation level. The AD9959 also has the ability to ramp up/ramp down (RU/RD) the output amplitude (using the 10-bit output scalar) before and/or after a modulation (FSK, PSK only) sequence. If the RU/RD feature is desired, unused profile pins or unused SDIO_1:3 pins can be configured for the RU/RD operation.

In direct modulation mode, each channel has its own set of control bits (CFR bits <23:22>) to determine the type (frequency, phase or amplitude) of modulation. Each channel has 16 profile registers. Addresses 0Ahex - 18hex are profile registers for direct modulation of frequency, phase or amplitude. Addresses 04hex, 05hex, and 06hex are dedicated registers for frequency, phase and amplitude respectively. These registers contain the beginning profile. Frequency modulation uses all 32 bits; phase modulation uses 14-bits; and amplitude modulation uses 10-bits. When modulating phase or amplitude, the word value must be MSB aligned in the profile registers and unused bits are “don’t cares”

1 1 16-level Modulation

When the AFP bits are logical zero for a channel, Modulation Level bits and RU/RD bits are don’t cares for that specific channel.

When modulating, the ramp-up / ramp-down feature is limited, based on pins available for controlling the feature. See the table below for details.

RU/RD bits (FR1<11:10>)

0 0 RU/RD disabled.

0 1 Only profile pins 2 and 3 available for RU/RD operation.

1 0 Only profile pin 3 available for RU/RD operation.

1 1 Only SDIO pins 1, 2, and 3 available for RU/RD operation.

Forces the serial I/O to only be used in 1 bit mode.

DESCRIPTION

When the profile pins are used for RU/RD, logic 0 is for ramp up and logic 1 is for ramp down.

Note: Due to the number of available channels and limited data pins, it is necessary to assign the profile pins and/or SDIO_1:3 pins to a dedicated channel. This is controlled by the Profile Pin Configuration or PPC bits (FR1 <14:12>). SDIO pins are for RU/RD only.

2-Level Modulation - No RU/RD

For modulation, AFP bits (CFR<23:22>) and Level bits (FR1<9:8>) are programmed. The AFP bits set the type of modulation and the Level bits set the level. The Linear Sweep enable bit must be set to logic 0. See the tables below.

Rev. PrD | Page 18 of 41

Modulation level bits are set to 00 (2-level). AFP bits are set to the desired modulation type. RU/RD bits and the Linear Sweep bit are disabled. The table below displays how the profile pins and channels are assigned.

Preliminary Technical Data AD9959

Profile Pin

Configuration

(PPC) bits

(FR1<14:12>)

X X X CH0 CH1 CH2 CH3 2- Level Mode All Channels,

P0 P1 P2 P3

DESCRIPTION

No RU/RD

In the above condition, only profile pin P0 can be used to modulate channel 0. If P0 pin is logic 0 register 0 (address 04hex) is chosen, if logic 1 register 1 (address 0Ahex) is chosen.

4-Level Modulation – No RU/RD

Modulation level bits are set to 10 (8-level). AFP bits are set to non-zero value. RU/RD bits and the Linear Sweep bit are disabled. Note: The AFP bits of the three channels not being used must be set to 00. The table below displays how the profile pins and channels are assigned.

Profile Pin Configuration bits (FR1<14:12>)

X 0 0

X 0 1

P0 P1 P2 P3

CH0 CH0 CH0 X

CH1 CH1 CH1 X

DESCRIPTION

8 level Modulation on CH0 and CH1, no RU/RD

8 level Modulation on CH0 and CH2, no RU/RD

Modulation level bits are set to 01 (4-level). AFP bits are set to the desired modulation type. RU/RD bits and the Linear Sweep bit are disabled. Note: The other two channels not being used should have their AFP bits set to 00 due to the lack of profile pins. The table below displays how the profile pins and channels are assigned to each other.

Profile Pin Configuration (PPC) bits (FR1<14:12>)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

P0 P1 P2 P3

CH0 CH0 CH1 CH1

CH0 CH0 CH2 CH2

CH0 CH0 CH3 CH3

CH1 CH1 CH2 CH2

CH1 CH1 CH3 CH3

CH2 CH2 CH3 CH3

DESCRIPTION

4 level Modulation on CH0 and CH1, no RU/RD

4 level Modulation on CH0 and CH2, no RU/RD

4 level Modulation on CH0 and CH3, no RU/RD

4 level Modulation on CH1 and CH2, no RU/RD

4 level Modulation on CH1 and CH3, no RU/RD

4 level Modulation on CH2 and CH3, no RU/RD

For the above condition, the profile register chosen is based on the two bit value presented to profile pins <P0:P1> or <P2:P3>. For example, if PPC = 010 and <P1:P2>= 11 and <P2:P3>= 01. The contents of profile register 3 of channel 0 will be presented to channel 0 and the contents of profile register 1 of channel 3 will be presented to Channel 3.

8-Level Modulation – No RU/RD

X 1 0

X 1 1

CH2 CH2 CH2 X

CH3 CH3 CH3 X

8 level Modulation on CH0 and CH3, no RU/RD

8 level Modulation on CH1 and CH2, no RU/RD

For this condition, the profile register (1 of 16) chosen is based on the three bit value presented to the profile <P0-P2> pins. For example if PPC = X10 and <P0-P2> = 111, the contents of profile register 7 of channel 0 are presented to channel 0.

16-Level Modulation – No RU/RD

Modulation level bits are set to 11 (16-level). AFP bits are set to the desired modulation type. RU/RD bits and the Linear Sweep bit are disabled. The AFP bits of the three channels not being used must be set to 00. The table below displays how the profile pins and channels are assigned.

Profile Pin Configuration (PPC) bits (FR1<14:12>)

X 0 0

X 0 1

X 1 0

X 1 1

P0 P1 P2 P3

CH0 CH0 CH0 CH0

CH1 CH1 CH1 CH1

CH2 CH2 CH2 CH2

CH3 CH3 CH3 CH3

DESCRIPTION

16 level Modulation on CH0, no RU/RD

16 level Modulation on CH1, no RU/RD

16 level Modulation on CH2, no RU/RD

16 level Modulation on CH3, no RU/RD

For the above conditions, the profile register chosen is based on the four bit value presented to profile <P0-P3> pins. For example if PPC = X11 and <P0-P3>= 1110, the contents of

Rev. PrD | Page 19 of 41

Preliminary Technical Data AD9959

profile register 14 of channel 3 will be presented to channel 3.

2-Level Modulation using Profile pins for RU/RD

With the RU/RD bits = 01, profile pins P2 and P3 are available for RU/RD. Note, only a modulation level of two is available in this mode. See table below for available pin assignments.

Profile Pin Configuration bits FR1<14:12>

0 0 0 CH0 CH1 CH0

0 0 1 CH0 CH2 CH0

0 1 0 CH0 CH3 CH0

0 1 1 CH1 CH2 CH1

1 0 0 CH1 CH3 CH1

1 0 1 CH2 CH3 CH2

P0 P1 P2

RU/RD

P3

CH1

RU/RD

CH2

RU/RD

CH3

RU/RD

CH2

RU/RD

CH3

RU/RD

CH3

RU/RD

DESCRIPTION

2 Level Modulation w/ RU/RD , CH0, CH1

2 Level Modulation w/ RU/RD , CH0, CH2

2 Level Modulation w/ RU/RD , CH0, CH3

2 Level Modulation w/ RU/RD , CH1, CH2

2 Level Modulation w/ RU/RD , CH1, CH3

2 Level Modulation w/ RU/RD , CH2, CH3

8-Level Modulation using a Profile pin for RU/RD

With the RU/RD bits = 10, profile pin P3 is available for RU/RD. Note, Only a modulation level of eight is available. See table below for available pin assignments.

Profile Pin Configuration bits FR1<14:12>

X 0 0 CH0 CH0 CH0 CH0

X 0 1 CH1 CH1 CH1 CH1

P0 P1 P2 P3

RU/RD

DESCRIPTION

8 Level Modulation with RU/RD , Channel 0

8 Level Modulation with RU/RD , Channel 1

Modulation using SDIO pins for RU/RD

For RU/RD bits = 11, SDIO pins 1, 2 and 3 are available for RU/RD. In this mode, Modulation levels of 2/4/16 are available. Note, the serial I/O port can only be used in 1 bit serial mode.

2-Level Modulation using SDIO pins for RU/RD

Profile Pin Configuration bits (FR1<14:12>)

P0 P1 P2 P3

X X X CH0 CH1 CH2 CH3

For the above configuration, each profile pin is dedicated to a specific channel. In this case, the SDIO pins can be used for the RU/RD function as described in the table below.

SDIO pins

1 2 3

0 0 0 Triggers the ramp up function for CH #0

0 0 1 Triggers the ramp down function for CH #0

0 1 0 Triggers the ramp up function for CH #1

0 1 1 Triggers the ramp down function for CH #1

1 0 0 Triggers the ramp up function for CH #2

1 0 1 Triggers the ramp down function for CH #2

1 1 0 Triggers the ramp up function for CH #3

1 1 1 Triggers the ramp down function for CH #3

4-Level Modulation using SDIO pins for RU/RD

For RU/RD = 11 (SDIO pins 1, 2 are available for RU/RD) and the Modulation level set to four see table below for pin assignments, including SDIO pin assignments.

Profile Pin Configuration bits (FR1<14:12>)

P0 P1 P2 P3

DESCRIPTION

SDIO 1 SDIO 2 SDIO

3

X 1 0 CH2 CH2 CH2 CH2

RU/RD

X 1 1 CH3 CH3 CH3 CH3

RU/RD

8 Level Modulation with RU/RD , Channel 2

8 Level Modulation with RU/RD , Channel 3

Rev. PrD | Page 20 of 41

0 0 0 CH0 CH0 CH1 CH1 CH0

RU/RD

0 0 1 CH0 CH0 CH2 CH2 CH0

RU/RD

CH1

RU/RD

CH2

RU/RD

NA

Preliminary Technical Data AD9959

RU/R

0 1 0 CH0 CH0 CH3 CH3 CH0

RU/RD

0 1 1 CH1 CH1 CH2 CH2 CH1

RU/RD

1 0 0 CH1 CH1 CH3 CH3 CH1

RU/RD

1 0 1 CH2 CH2 CH3 CH3 CH2

RU/RD

CH3

RU/RD

CH2

RU/RD

CH3

RU/RD

CH3

RU/RD

NA

For the above configuration, the Profile register is chosen based on the two bit value presented to <P1:P2> or <P3:P4>.For example if PPC = 011 and <P0:P1> = 11 and <P2:P3> = 01. The contents of Profile register 3 of channel 1 will be presented to channel 1 and the contents of Profile register 1 of channel 2 will be presented to channel 2. SDIO pins 1 and 2 will provide the RU/RD function.

16-Level Modulation using SDIO pins for RU/RD

RU/RD = 11 (SDIO pin 1 available for RU/RD) and the level set to sixteen. See the pin assignment in the table below.

Profile Pin Configuration (FR1<14:12>)

X 0 0 CH0 CH0 CH0 CH0 CH0

X 0 1 CH1 CH1 CH1 CH1 CH1

P0 P1 P2 P3

SDIO 1 SDIO 2 SDIO

NA NA

RU/RD

NA NA

RU/RD

3

bandwidth containment compared to direct modulation modes by replacing greater instantaneous changes with more gradual, user-defined changes between S0 and E0.

In linear sweep mode, S0 (frequency, phase, or amplitude) is loaded into profile register 0 (1 of 3 addresses 04hex – 06hex depending on the type of sweep) and E0 is loaded into profile register 1 (address 0Ahex). The profile pins will be used to trigger and control the direction of the linear sweep for frequency, phase, or amplitude. All channels can be programmed separately for a linear sweep. In linear sweep mode, profile pin 0 is dedicated to channel 0. Profile pin 1 is dedicated to channel 1 and so on.

The AD9959 has the ability to ramp up/ramp down (RU/RD) the output amplitude (using the 10-bit output scalar) before and/or after a linear sweep. If the RU/RD feature is desired, unused profile pins or unused SDIO_1:3 pins can be configured for the RU/RD operation.

To enable linear sweep mode for a particular channel, AFP bits (CFR<23:22>), modulation level bits (FR1<9:8>) and the linear sweep enable bit (CFR) bit<14> are programmed. The AFP bits instruct what type of linear sweep is to be performed. The modulation level bits must be set to 00 (2-level) for that specific channel. See the tables below.

AFP (CFR<23:22>) Linear Sweep

Enable

(CFR<14>)

0 0 1 N/A

0 1 1 Amplitude Sweep

1 0 1 Frequency Sweep

DESCRIPITON

X 1 0 CH2 CH2 CH2 CH2 CH2

X 1 1 CH3 CH3 CH3 CH3 CH3

RU/R D

NA NA

D

NA NA

For the above configuration, the Profile register is chosen based on the four bit value presented to <P0-P3>. For example, if PPC = 1110 and <P0-P1> = 1101, the contents of Profile register 13 of channel 2 will be presented to channel 2. SDIO_1 pin provides the RU/RD function.

SHAPED (LINEAR SWEEP) MODULATION MODE

Linear sweep enables the user to sweep frequency, phase or amplitude from a starting point (S0) to an ending point (E0). The purpose of linear sweep modes is to provide better

Rev. PrD | Page 21 of 41

1 1 1 Phase Sweep

Modulation Level bits (FR1<9:8>) DESCRIPTION

0 0 2-level Modulation

0 1 4-level Modulation

1 0 8-level Modulation

1 1 16-level Modulation

Setting the slope of the Linear Sweep

The slope of the linear sweep is set by of the intermediate step size (delta tuning word) between S0 and E0 and the time spent (Sweep ramp rate word) at each step. The resolution of the delta tuning word is 32-bits for frequency, 14-bits for phase, and 10bits for amplitude. The resolution for the delta ramp rate word is 8-bits.

Preliminary Technical Data AD9959

There are two delta tuning words and two sweep ramp rate words for each channel, the rising delta tuning word (RDW, address 08hex) and rising sweep ramp rate (RSRR, address 07hex bits<7:0>) apply when sweeping up or towards E0. The falling delta tuning word (FDW, address 09hex) and falling sweep ramp rate (FSRR, address 07hex bits <15:8>) apply when stepping down or towards S0. The following graph displays a linear sweep up and then down using a profile pin. Note, the no dwell bit is disabled, else the sweep accumulator returns to zero upon reaching EO.

EO

)

RDW

f,p,a f,p,a

LINEAR SWEEP

FREQUENCY / PHASE / AMPLITUDE

(

SO

For a piece-wise or a non-linear transition between S0 and E0, the delta tuning words and/or ramp rate words can be reprogrammed during the transition to produce the desired response.

The formulas for calculating the step size of RDW or FDW for delta frequency, delta phase, or delta amplitude is as follows

⎛

=∆

⎜ ⎝

t

PROFILE PIN

RDW

32

2

RSRR

⎞ ⎟

⎠

TIME

×

FSRR

FDW

t

CLKSYNCf _

The sweep ramp rate block (timer) consists of a loadable 8-bit down counter that continuously counts down from the loaded value to a count of 1. When the ramp rate timer equals 1, the proper ramp rate value is loaded and the counter begins counting down to one again. This load and count down operation continues for as long as the timer is enabled, unless the timer is forced to load before reaching a count of 1.

The ramp rate timer can be loaded before reaching a count of 1 by one of two methods.

1) Method one is by changing the profile pin. When the profile pin changes from logic 0 to logic 1, the rising sweep ramp rate register (RSRR) value is loaded into the ramp rate timer, which then proceeds to count down as normal. When the profile pin changes from a logic one to a logic zero, the falling sweep ramp rate register (FSRR) value is loaded into the ramp rate timer, which then proceeds to count down as normal.

2) The second method in which the sweep ramp rate timer can be loaded before reaching a count of 1 is if the CFR<14> bit is set and an I/O update is issued. If sweep is enabled and CFR<14> is set, the ramp rate timer loads the value determined by the profile pin. If the profile pin is high the ramp rate timer loads the RSRR. If the profile pin is low the ramp rate timer loads the FSRR.

Frequency Linear Sweep example: AFP bits =10, Modulation Level bits = 00, Sweep Enable = 1, No dwell bit = 0.

In linear sweep mode, when the profile pin transitions from a low to high, the RDW is applied to the input of the sweep accumulator and the RSRR register is loaded into the sweep rate timer.

RDW

⎛

=∆Φ 360

⎜ ⎝

RDW

⎛

=∆a

⎜ ⎝

The formula for calculating delta time from RSRR or FSRR is:

RSRR

⎛

=

⎜ ⎝

The maximum sweep rate at 500MSPS is (1/SYNC_CLK =125 MHz) x 256 = 2.048µs. The minimum sweep rate is (1/SYNC_CLK) x 1 = 8.0ns

⎞ ⎟

14

2

⎠

⎞ ⎟

10

2

⎠

⎞ ⎟

8

2

⎠

×

1024

°×

CLKSYNCt _/1

Rev. PrD | Page 22 of 41

The RDW accumulates at the rate given by the ramp rate (RSRR) until the output is equal to the CTW1 register value. The sweep is complete and the output is held constant in frequency.

When the profile pin transitions from high to low, the FDW is applied to the input of the sweep accumulator and the FSRR register is loaded into the sweep rate timer.

The FDW accumulates at the rate given by the ramp rate (FSRR) until the output is equal to the CTW0 register value. The sweep is complete and the output is held constant in frequency.

The Linear Sweep block diagram is displayed below.

Preliminary Technical Data AD9959

Sweep Accumulator

FDW

RDW

MUX

1

Profile pin

Rate Time

Load Control

Logic

0

8-bit loadable down counter

FSRR

0

MUX

32

1

Ramp Rate Timer:

8

0

MUX

1

RSRR

32

Profile pin

32

Z

Accumulator Reset

Logic

Linear Sweep – No Dwell Feature

The Linear Sweep function can be operated with a “no dwell” feature. If the Linear Sweep No Dwell bit is set (CFR<15>), the rising sweep is started in an identical manner to the non-no dwell linear sweep mode. That is, upon detecting logic 1 on the Profile input pin the rising sweep action is initiated. The word continues to sweep up at the rate set by the rising sweep ramp rate at the resolution set by the rising delta tuning word until it reaches the terminal frequency. Upon reaching the terminal frequency, the output frequency immediately drops back to the starting point and remains until a logic one is detected on the

Fout

Sweep Adder

32

-1

0

MUX

1

Limit Logic to

keep sweep between

S0 and E0

1

0

CTW0

32

CTW1

32

Profile pin. Figure x below is an example of the linear sweep mode operation when the Linear Sweep No Dwell bit is set. The points labeled A indicate where a rising edge is detected on the Profile pin and the points labeled B indicate where the AD9959 has determined Fout has reached E0 and automatically returns to S0.

FTW 1

FTW 0

A

Single Tone Mode Linear Sweep M ode E nabled - no dwell bit set

A

Rev. PrD | Page 23 of 41

BBB

A

Time

Preliminary Technical Data AD9959

The falling ramp rate register and the falling delta word are unused in this mode.

Continuous and “Clear and Release” Sweep and Phase Accumulator Clear Functions

The AD9959 allows for a programmable continuous zeroing of the sweep logic and the phase accumulator as well as a “clear and release”, or automatic zeroing function. CFR<4> is the Automatic Clear Sweep Accumulator bit and CFR<2> is the Automatic Clear Phase Accumulator bit. The continuous clear bits are located in CFR, where CFR<3> clears the Sweep accumulator and CFR<1> clears the Phase Accumulator.

Continuous Clear bits

The continuous clear bits are simply static control signals that, when active high, hold the respective accumulator at zero for the entire time the bit is active. When the bit goes low, inactive, the respective accumulator is allowed to operate.

Clear and Release bits

The Auto Clear Sweep Accumulator bit, when set, clears and releases the sweep accumulator upon receiving an I/O update or change in the Profile input pins. The Auto Clear Phase Accumulator, when set, clears and releases the phase accumulator upon receiving an I/O update or change in the Profile input pins. The automatic clearing function is repeated for every subsequent I/O update or change in Profile pins until the clear and release bits are reset via the serial port.

OUTPUT AMPLITUDE RAMP MODE

The 10-bit scale factor (multiplier) of the AD9959 is used to control the ramp-up and ramp-down (RU/RD) time of an onoff emission from the DAC. This function is used in burst transmissions of digital data to reduce the adverse spectral impact of short, abrupt bursts of data. This function may be bypassed by clearing the Multiplier enable bit (ACR<12> = 0).

Automatic and manual RU/RD modes are supported.

The auto mode generates a zero up to full scale (10-bits) linear ramp at a rate determined by the amplitude ramp rate control register. The start and direction of the ramp is controlled by profile pins or the SDIO1:3 pins.

Manual mode allows the user to directly control the output amplitude by manually writing to the amplitude scale factor

value in the amplitude Control register (address 06hex). Manual mode is enabled by setting bits ACR<12> = 1 and ACR<11> =

0.

AUTO RU/RD Mode Operation

The auto RU/RD mode is active when bits ACR<12> and ACR<11> are both set. When auto RU/RD is enabled, the scale factor is internally generated and applied to the multiplier input port for scaling the output. The scale factor is the output of a 10-bit counter that increments/decrements at a rate determined by the contents of the 8-bit output ramp rate register. The scale factor increases external pin is high and decreases if the pin is low. The scale factor is an unsigned value such that all 0s multiply the output by 0 (decimal) and 0x3FF multiplies the output by 0.99902 (decimal).

For those users who use the full amplitude (10-bits) but need fast ramp rates, the internally generated scale factor step size is controlled via the <15:14> bits in the ACR register. The following table describes the increment/decrement step size of the internally generated scale factor per the ACR<15:14> bits.

Auto-Scale Factor Step Size

ASF<15:14> (Binary) Increment/Decrement Size

00 1 01 2 10 4 11 8

A special feature of this mode is that the maximum output amplitude allowed is limited by the contents of the amplitude scale factor register. This allows the user to ramp to a value less than full scale.

Ramp Rate Timer

The ramp rate timer is a loadable down counter, which generates the clock signal to the 10-bit counter that generates the internal scale factor. The ramp rate timer is loaded with the value of the ASFR every time the counter reaches 1 (decimal). This load and count down operation continues for as long as the timer is enabled unless the timer is forced to load before reaching a count of 1.

If the Load ARR Timer bit ACR<10> is set, the ramp rate timer is loaded upon an I/O update, change in profile input or upon reaching a value of 1. The ramp timer can be loaded before reaching a count of 1 by three methods.

Method one is by changing profile pin(s) or SDIO(1:3) pins. When the control signal changes state the ACR value is loaded into the ramp rate timer, which then proceeds to count down as normal.

The second method in which the sweep ramp rate timer can be

Rev. PrD | Page 24 of 41

Preliminary Technical Data AD9959

loaded before reaching a count of 1 is if the Load ARR Timer bit (ACR<10>) is set and an I/O update is issued.

The last method in which the sweep ramp rate timer can be loaded before reaching a count of 1 is when going from the inactive AUTO RU/RD mode mode.

RU/RD Pin to Channel Assignment

1) When all four channels are in single tone mode, the profile

pins are used for RU/RD operation.

Profile Pin RU/RD operation

P0 For Ch 0

P1 For Ch 1

P2 For Ch 2

P3 For Ch 3

2) When both linear sweep and RU//RD modes are activated,

SDIO_1:3 are used for RU/RD operation.

LS & RU/RD modes enable

simultaneously

Enable for CH #0 Enable for CH#0 Enable for CH#1 Enable for CH#1 Enable for CH#2 Enable for CH#2 Enable for CH#3 Enable for CH#3

SDIO_1,2,3 Ramp up/down control signal

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

to the active AUTO RU/RD

assignment

ramp up function for CH #0 ramp down function for CH #0 ramp up function for CH #1 ramp down function for CH #1 ramp up function for CH #2 ramp down function for CH #2 ramp up function for CH #3 ramp down function for CH #3

In modulation mode, please refer to the modulation mode

3) section for pin assignments.

Rev. PrD | Page 25 of 41

Preliminary Technical Data AD9959

SYNCHRONIZING MULTIPLE AD9959 DEVICES

The AD9959 allows easy synchronization of multiple AD9959 devices. Multiple devices are considered synchronized when the internal state machines (divider) that generate SYNC_CLK are identical for all parts. Each part generates SYNC_CLK by dividing System Clock by 4. At power-up, this divider is not initialized therefore the phase of SYNC_CLK can be offset between multiple devices. To correct for the offset and align the SYNC_CLK edges there exist three methods (one automatic mode two manual modes and) of synchronizing SYNC_CLKS. These modes will force the internal state machines of multiple devices to a known state which will align SYNC_CLKS.

Note: The user should send a coincident REF_CLK to all devices. Any mismatches between devices in REF_ CLK phase will propagate through each device

Automatic Mode Synchronization

In automatic mode, multiple part synchronization is achieved by connecting the SYNC_OUT pin on the master device to the SYNC_IN input of the slave device(s). Devices are configured as master and slaves through programming bits, accessible via the serial port.

Figure x below shows a configuration for synchronizing multiple AD9959 devices in automatic mode. In this configuration, the AD9510 (clock distribution device) was chosen to provide a coincident REF CLK and SYNC_OUT signal to all devices.

Automatic Mode Chip Synchronization - General Operation

The first step is to program the Master and Slave devices for their respective roles. Enabling the master device is performed by writing its Master Enable bit (FR2[6]) true. This causes the SYNC_OUT of the master device to output a pulse that has a pulse width equal to one system clock period and a frequency of 4 System clock periods. Enabling device(s) as slaves is performed by writing the Slave Enable bit (FR2[7]) true.

In automatic synchronizing mode, the slave device(s) sample SYNC_OUT pulse from the master device and a comparison of all state machines is made by the auto synchronization circuitry. If the slave device(s) state machines are not identical to the master, the slave device(s) state machines are stalled for one system clock cycle. This auto sample/compare/act procedure

Rev. PrD | Page 26 of 41

will produce a synchronized slave device within 3 SYNC_CLK periods. If the Slave Enable bit remains valid and the reference clock was to become momentarily corrupted, causing the slave device(s) to lose synchronization with the master, the slaves will automatically re-synchronize.

Delay time between SYNC_OUT and SYNC_IN

If the SYNC_OUT pulse is unable to propagate to the slave device(s) in one System Clock period the devices will most likely be out of sync. This can be the case at high system clock rates. The System Clock Offset bits (FR2[1:0]) can compensate for this delay. The default state of these bits is 00 which implies the SYNC_OUT of master and the SYNC_IN of slave have a propagation delay of less than one system clock period. If the propagation time is greater than one system clock period, the

Preliminary Technical Data AD9959

time should be measured and the appropriate offset programmed-in

The table below describes the delays required per System Clock Offset value.

System Clock

SYNC_OUT / SYNC_IN

Offset Value

Propagation delay

00

01

10

11

≤ delay ≤ 1

0

≤ delay ≤ 2

1

≤ delay ≤ 3

2

≤ delay ≤ 4

3

A benefit of the programmable System Clock offset feature is device(s) can be programmed to differing times, which allows for flexibility in a system.

Automatic Synchronization Status bits

An active high sync status bit is generated when the synchronization logic is enabled and the parts are not in sync. This sync status bit is accessible via the serial port only

. If the slave device(s) are determined to be synchronized, this status bit is not set. This bit can be read through the serial port bit (FR2[5]) and is automatically cleared when read.

The synchronization routine continues to operate regardless of the state of the status bit. The status bit can be masked by writing the Synchronization Status Mask bit true (FR2[4]). Masking the status bit causes the status bit to not be updated with the status information. The status bit is always low when masked.

Manual Software Mode Synchronization

Manual software mode is enabled by setting the Manual SW Synchronization bit (FR1<0>) true in a device. In this mode, the I/O UPDATE that writes the Manual SW Synchronization bit true “stalls” the state machine of the clock generator for one System Clock cycle. Stalling the clock generation state machine by one cycle has the affect of changing the phase relationship of SYNC_CLK between devices by one system clock period or 90 degrees.

The synchronization is complete when the master and slave(s) devices have their SYNC_CLK signals in phase.

clock cycle. The user must determine if the devices have their SYNC_CLK signals in phase. The SYNC_IN input can be left floating as it has an internal pull-up. The SYNC_OUT is not used.

Manual Hardware Mode Synchronization

Manual hardware mode is enabled by setting the Manual SW Synchronization bit (FR1<1>) true in a device. In Manual HW Synchronization mode, a “stall” of the clock generation state machines by one System Clock cycle performed each time a rising edge is detected on the SYNC_IN input. Stalling SYNC_CLK’s state machine by one cycle has the affect of changing the phase relationship of SYNC_CLK between devices by one system clock period or 90 degrees.

The synchronization is complete when the master and slave device(s) have their SYNC_CLK signals in phase.

In Manual HW Synchronization mode, the user must determine if the devices have their SYNC_CLK signals in phase. The SYNC_OUT is not used.

SYNCHRONIZATION OF UPDATES (I/O UPDATE)

SYNC_CLK and I/O_UPDATE relationship

Data into the AD9959 is synchronous to the SYNC_CLK pin. That is, the I/O_UPDATE the SYNC_CLK clock provided by the AD9959.

This enables synchronization of external hardware with the AD9959’s internal data clock. This is accomplished by forcing any external hardware to obtain its timing from SYNC_CLK. External hardware that is timed using the SYNC_CLK signal can then be used to provide the I/O update signal to the AD9959. The I/O update signal coupled with SYNC_CLK is used to transfer internal buffer register contents into the Control Registers of the device. The combination of the SYNC_CLK and I/O update pins provides the user with constant latency relative to System clock and also ensures phase continuity of the analog output signal when a new tuning word or phase offset value is asserted.

pin is sampled on the rising edge of

Note: The user must re-write the Manual SW Synchronization bit true to stall the clock generation state machine by another system

Rev. PrD | Page 27 of 41

Preliminary Technical Data AD9959

SERIAL I/O PORT SECTION

OVERVIEW

The AD9959 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers a SPI compatible mode of operation which is virtually identical to the SPI operation found in earlier ADI DDS products. The flexibility is provided by four data (SDIO_0:3) pins that allow four programmable modes of serial I/O operation.

Three of the four data pins (SDIO_1:3) are not dedicated for serial I/O port operation only. These pins can also be used to initiate a ramp-up/ramp-down (RU/RD) of the 10-bit amplitude output scalar. In addition, one of these pins (SDIO_3) can also be used to provide the SYNC_I/O function that re-synchronizes the Serial I/O port controller if out proper sequence.

The maximum speed of the serial I/O port SCLK is 200 MHz but the four data (SDIO_0:3) pins can be used to further increase data throughput. The maximum data throughput using all SDIO_0:3 pins is 800Mbits/s.

Note:

All channels share addresses (03hex – 18hex) located in the register map section. The address sharing enables all four DDS channels to be written to simultaneously. For example, if a common frequency tuning word is desired for all four channels, it can be written one time through the serial I/O port to all four channels. This is the default mode of operation (all channels enabled). To enable each channel to be independent from one another, the four channel bits found in the “Channel Select Register” (CSR) are used.

Effectively there are four sets or copies of addresses (03hex to 18hex) that channel enable bits can access to provide channel independency. Further discussion on programming channels to be common or independent from one another is found in the control register’s description section.

GENERAL SERIAL PORT OPERATION

Serial operations of the AD9959 occur at the register level, not the byte level. For the AD9959, the serial port controller recognizes the register address in the instruction byte and automatically generates the proper number of byte(s) addresses. That is, the controller expects that all byte(s) contained in the register address be accessed. The SYNC_I/O function can be used to abort an I/O operation, thereby allowing less than all bytes to be accessed. This feature can be used to only program a part of the addressed register. Note, only the completed bytes will be affected.

There are two phases to a serial communications cycle. Phase 1 is the instruction cycle, which is writing the instruction byte into the AD9959. Each bit of the instruction byte is registered on each corresponding rising edge of SCLK. The instruction

Rev. PrD | Page 28 of 41

byte provides the serial port controller with information regarding the data transfer cycle. The instruction byte defines whether the upcoming data transfer is either a write or read operation and also contains the serial address of the address register.

Phase 2 of the I/O cycle is the actual data transfer (write/read) between the serial port controller and the serial port buffer. The number of bytes transferred during this phase of the communication cycle is a function of the register being accessed. The actual number of additional SCLK rising edges required for the data transfer and instruction byte depends on the number of byte(s) in the register and the serial I/O mode of operation.

For example, when accessing Function Register 1, (FR1) which is three bytes wide, phase 2 of the I/O cycle requires that three bytes be transferred. After transferring all data bytes per the instruction byte, the communication cycle is completed for that register.

At the completion of any communication cycle, the AD9959 serial port controller expects the next set of rising SCLK edges to be the instruction byte for the next communication cycle. All data into the AD9959, is registered on the rising edge of SCLK. All read data is driven out of the AD9959 on the falling edge of SCLK.

Each set of communication cycles does not require an I/O_UPDATE to be issued. The I/O_UPDATE transfers data from the I/O port buffer to active registers. The I/O_UPDATE can be sent for each communication cycle or can be sent when all serial operations are complete. However, data is not active until the I/O_UPDATE is sent. The only exception is with the channel enable bits in the Channel Select Register (CSR). These bits do not require an I/O_UPDATE to be enabled. This will be discussed later.

CS

SCLK

SDIO (s)

t

PRE

t

DSU

SYMBOL DEFINITION MIN

t

PRE

t

SCK

t

DSU

t

SCLKPWH

t

SCLKWL

t

DHLD

t

SCLK

t

SCLKPWHtSCLKPWL

t

DHLD

CS SETUP TIME TDB PERIOD OF SERIAL DATA CLOCK TDB SERIAL DATA SETUP TIME TBD SERIAL DATA CLOCK PULSEWIDTH HIGH TBD SERIAL DATA CLOCK PULSEWIDTH LOW TBD SERIAL DATA HOLD TIME TBD

Figure x Setup and hold timing for the serial IO port.

Preliminary Technical Data AD9959

CS

SCLK

SDIO (s) SDO (SDIO_2)

t

DV

SYMBOL DEFINITION MIN

t

DV

DATA VALID TIME 0ns

INSTRUCTION BYTE DESCRIPTION

Table The instruction byte contains the following information:

MSB D6 D5 D4 D3 D2 D1 LSB

R/Wb X X A4 A3 A2 A1 A0

R/Wb—Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. Logic High indicates read operation. Logic 0 indicates a write operation.

X, X—Bits 6 and 5 of the instruction byte are Don’t Care bits.

Figure x Timing diagram for Data Read for serial IO port.

.

bit or 4-bit Serial I/O modes. It is available in single-bit (3-wire) mode only. The SDO function does not have a dedicated SDO pin (see table x). It uses the SDIO_2 pin. In SDO mode, data is read from the SDIO_2 pin for protocols that use separate lines for transmitting and receiving data. Bits <2:1> in the CSR register (address 00hex) controls the configuration of this pin.

A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. The internal byte addresses are generated by the AD9959.

SERIAL I/O PORT PIN DESCRIPTION

SCLK--- Serial Data Clock. The serial clock pin is used to synchronize data to and from the internal state machines of the AD9959. The maximum SCLK toggle frequency is 200 MHz.

---Chip Select. The Chip select pin allows for more than one

CS AD9959 device on the same set of serial communications lines. The chip select is an active low enable. Defined SDIO inputs will go to a high impedance state when

CS

is high. If CS is

driven high during any communications cycle, that cycle is

CS

suspended until

is reactivated low. The CS pin can be tied low

in systems that maintain control of SCLK.

SDIO(0:3)---Serial Data I/O. All four SDIO pins are not dedicated SDIO inputs. Only SDIO_0 pin is dedicated SDIO pins. SDIO_1:3 pins can also be used for other functions (see table x and the OSK modulation description). Otherwise, data is always written into the AD9959 on these pins. However, these pins can be used as bi-directional data lines for write and read operations per the instruction byte. Bits <2:1> in the Channel Select Register (CSR address 00hex) control the configuration of these pins. The default state configures the SDIO input as bidirectional.

SERIAL I/O PORT FUNCTION DESCRIPTION

SDO---Serial Data Out. The SDO function is not available in 2-

SYNC_I/O---The SYNC_I/O function in not available in 4-bit Serial I/O mode. The SYNC_I/O function does not have a dedicated SYNC_I/O Pin. It is shared by the SDIO_3 pin (see table x). In 4-bit serial mode, the SDIO_3 pin is dedicated to the

th

4

data (SDIO) pin. Bits <2:1> in the CSR register (address 00hex) controls the configuration of this pin. Otherwise the SYNC_I/O function is used to synchronize the I/O port state machines without affecting the addressable registers contents. An active high input on the SYNC_I/O (SDIO_3) pin causes the current communication cycle to abort. After SDIO_3 returns low (Logic 0) another communication cycle may begin, starting with the instruction byte write.

MSB/LSB TRANSFER DESCRIPTION

The AD9959 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by CSR <0> in the channel select register (CSR). MSB first is the default mode. When CSR<0> is set high, the AD9959 serial port is in LSB first format. The instruction byte must be written in the format indicated by CSR<0>. That is, if the AD9959 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. If the AD9959 is in MSB first mode (default), the instruction byte must be written from most significant bit to least significant bit.

Example Operation

To write the Function Register 1 (FR1) in MSB first format apply an instruction byte of (MSB>00000001<LSB) starting with the MSB bit. From this instruction, the internal controller

Rev. PrD | Page 29 of 41

Preliminary Technical Data AD9959

will recognize a write transfer of three bytes starting with the MSB bit <23> in the FR1 address (01h). After the first data byte <23:16> is written, the internal byte address generation logic will decrement, which is the destination of the second byte <15:8>, starting with bit <15>. After the second byte is written, the internal byte address generation logic will decrement, which is the destination of the third and last byte <7:0> for FR1, starting with bit <7>. After the third byte is written, the I/O communication cycle is complete and the next byte is considered an instruction byte.

To write the Function Register 1 (FR1) in LSB first format apply an instruction byte of (MSB>00000001<LSB) starting the LSB bit. From this instruction, the internal controller will recognize a write transfer of three bytes starting with the LSB bit <0> in the FR1 address (01h). After the first data byte <7:0> is written, the internal byte address generation logic will increment, which is the destination of the second byte <15:8>, starting with bit <8>. After the second byte is written, the internal byte address generation logic will increment, which is the destination of the third and last byte <23:16> for FR1, starting with bit <16>. After the third byte is written, the I/O communication cycle is complete and the next byte is considered an instruction byte.

SERIAL I/O MODES OF OPERATION

The following are the four programmable modes of the serial I/O port operation.

1) Single-bit serial 2-wire mode (default mode).

2)

Single-bit serial 3-wire mode.

3)

2-bit serial mode.

Clock Clock Clock Clock

CSB Chip

Select

SDIO_0 Serial

Data I/O

SDIO_1 *Not used

for SDIO

SDIO_2 *Not used

for SDIO

SDIO_3

SYNC_I/ O SYNC_I/O SYNC_I/O

Chip

Select

Serial

Data In

*Not used

for SDIO

Serial

Data Out

(SDO)

Chip

Select

Serial

Data I/O

Serial

Data I/O

*Not used

for SDIO

Chip

Select

Serial

Data I/O

Serial

Data I/O

Serial

Data I/O

Serial

Data I/O

In this serial mode, these pins can be used for RU/RD

*

operation.

The following two bits (CSR<2:1>) in the Channel Select Register set the serial I/O mode of operation are defined below.

CSR<2:1> = 00 -- Single bit serial mode (2-wire mode). CSR<2:1> = 01 -- Single bit serial mode (3-wire mode). CSR<2:1> = 10 -- 2-bit serial mode CSR<2:1> = 11 -- 4-bit serial mode.

4)

4-bit serial mode (SYNC_I/O not available).

Selection of the desired mode of operation is found in the Channel Select Register (CSR). The CSR register’s address is 00hex. The bits in the CSR that configured the SPI port are bits <2:1>. After powering up, the Channel Select Register is typically the first register to be addressed in a serial I/O communication cycle.

The following table displays the function of all (6) serial IO interface pins, depending on the mode of serial IO operation programmed.

Table x Serial IO Port Pin Function vs Serial I/O Mode

AD9959

Name

SCLK Serial Serial Serial Serial

Single bit

Serial-2

wire mode

Single bit Serial – 3

wire mode

2-bit Serial mode

Serial mode

4-bit

Rev. PrD | Page 30 of 41

Single-bit Serial (2 and 3-wire) Modes

The Single-bit Serial mode interface allows read/write access to all registers that configure the AD9959. MSB first or LSB first transfer formats are supported. In addition, the Single-bit Serial mode interface port can be configured as either a single pin I/O, which allows a two-wire interface or two unidirectional pins for in/out, which enable a three wire interface. One optional feature is SYNC_I/O which enables greater flexibility for system design-in of the AD9959. The SYNC_I/O function is enabled by controlling the SDIO_3 pin.

In Single-bit Serial Mode, two-wire interface operation, the SDIO_0 pin is the single serial data I/O pin. In Single-bit Serial Mode three-wire interface operation, the SDIO_0 pin is the serial data input pin and the SDIO_2 pin is the output data pin. Regardless of the number of wires used in the interface, the SDIO_3 pin is configured as an input and operates as the SYNC_I/O pin in the Single-bit serial mode and 2-bit serial mode. The SDIO_1 pin is unused in this mode.

2-bit Serial Mode

The SPI port in 2-bit serial mode is identical to that for single-

Preliminary Technical Data AD9959

bit serial mode except that two bits of data are registered on each rising edge of SCLK. Therefore, it only takes 4 clock cycles to transfer 8-bits of information. The SDIO_0 pin contains the “even numbered” data bits using the notation D<7:0> and the SDIO_1 pin contains the “odd numbered” data bits. This even and odd numbered pin/data alignment is valid in both MSB and LSB first formats.

4-bit Serial Mode

The SPI port in 4-bit serial mode is identical to that for singlebit serial mode except that four bits of data are registered on each rising edge of SCLK. Therefore, it only takes 2 clock cycles to transfer 8-bits of information. The SDIO_0 and SDIO_2 pins

The following figures xx through xx represent write timing diagrams for each serial I/O modes available. Both MSB and LSB first modes are shown. LSB first bits are shown in parenthesis. The Clock Stall Low/High feature shown is not required. It is used to show that data (SDIO) must have the proper setup time relative to the rising edge of SCLK.

contains the “even numbered” data bits using the notation D<7:0>, where the SDIO_0 pin contains the lower significant bit of the nibble. The SDIO_1 and SDIO_3 pins contain the “odd numbered” data bits, where the SDIO_1 pin contains the lower significant bit of the nibble to be accessed.

[Note to users …. When programming the part for 4-bit serial mode, be sure to keep the SDIO_3 pin at logic zero until the device is programmed out of the single bit Serial mode. Failure to do so can result in the serial I/O portcontroller being out of sequence.]

CS

SCLK

SDIO_0

I

7

INSTRUCTION CYCLE DATA TRANSFER CYCLE

I

6I5

(I

1

)

I

4I3

2

)

3

(I

)

(I

2

5

)(I6)

(I

4

)

I

0

I

1

(I7)(I0)

7

D

5

D

6

(D

1

)(D

D

(D

2

)

4

3

)

D

Figure x. Single- bit Serial mode Write Timing- Clock Stall Low

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK

D

SDIO_1

SDIO_0

I

7

1

)(I3)

(I

I

6

0

)

(I

I5I

I

4

(I

2

)

3

5

(I

I

2

(I

4

)(I7)

)

(I

D

I

1

I

0

6

)

7

(D1)(D3)

D

6

0

)

(D

3

D

5

D

4

D

1

7

)

(D

5

)

(D

D

0

D

2

6

)

(D

4

)(D2)

Figure x 2-bit Serial mode Write timing- Clock Stall Low

3

4

)

(D

5

)

D

0

7

)

(D

6

)(D0)(D

D

1

D

2

D

Rev. PrD | Page 31 of 41

Preliminary Technical Data AD9959

INSTRUCTION CYCLE

CS

SCLK

I

7

I

3

)

(I

7

)

SDIO_3

SDIO_2

SDIO_1

SDIO_0

(I

I

6

I

2

)

6

(I

)

(I

I

1

I

5

1

)

5

)

(I

I

0

I

4

(I

4

)

0

)

Figure x 4-bit Serial Mode Write timing- Clock Stall Low

The following figures xx through xx represent read timing diagrams for each serial I/O modes available. Both MSB and LSB first modes are shown. LSB first bits are shown in parenthesis. The Clock Stall Low/High feature shown is not required. It is used to show that data (SDIO) must have the proper setup time relative to the rising edge of SCLK for the instruction byte and the read data will follow the falling edge of SCLK.

DATA TRANSFER CYCLE

D

7

3

)(D7)

6

2

)

5

4

0

)

3

D

2

(D

6

)

D

1

5

)

(D

D

0

(D

4

)

D

(D

D

(D

D

(D1)

D

(D

CS

SCLK

SDIO_0

CS

SCLK

SDIO_0

INSTRUCTION CYCLE

I

7

I

(I

6

0

)

I4I

I

5

2

)(I1)

(I

3

)

I

2

3

4

)(I5)(I6)

(I

I

0

I

1

(I7)

DATA TRANSFER CYCLE

D6D5D

D

7

1

)(D3)(D

(D

4

D

2

D

3

D

1

D

0

7

5

)(D4)(D2)

)(D6)(D0)(D

Figure x Single-bit Serial Mode (2-wire) Read Timing- Clock Stall High.

INSTRUCTION CYCLE

I

7

I

6

I

4

I

5

(I

2

)(I1)(I3)(I4)

I

2

I

3

5

)(I6)

(I

I

1

I

0

(I7)(I0)

DATA TRANSFER CYCLE

DON'T CARE

D

5

D

6

D

7

1

)(D3)(D

(D

D

4

D

2

D

3

5

)(D4)(D2)

D

0

1

7

)(D6)(D0)(D

Figure x Single-bit Serial Mode (3-wire) Read Timing- Clock Stall Low.

Rev. PrD | Page 32 of 41

Preliminary Technical Data AD9959

INSTRUCTION CYCLE

CS

SCLK

I

SDIO_1

SDIO_0

I

7

(I

1

)(I3)

I

6

(I

0

)(I2)

3

I

5

I

4

1

(I7)

5

)

(I

I

0

I

2

(I

4

)

(I

6

)

Figure x 2-bit Serial Mode Read Timing- Clock Stall High.

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK

I

7

I

3

(I

(I7)

3

SDIO_3

SDIO_2

SDIO_1

SDIO_0

)

I

6

I

2

(I

2

)

6

)

(I

I

1

I

5

1

)

5

)

(I

I

0

I

4

(I

4

)

(I

0

)

DATA TRANSFER CYCLE

D

7

D

5

1

)(D3)(D

(D

D

4

D

6

D

3

D

7

3

)(D7)

(D

D

6

D

2

(D

6

2

)

(D

D

5

D

1

(D

1

)

5

D

0

D

4

(D

0

)

4

(D

)

D3D

5

)

(D

D

2

(D

4

)(D2)

1

7

)

D

0

(D

6

)(D0)

Figure x 4-bit Serial Mode Read Timing- Clock Stall High

CONTROL REGISTERS MAP

The Control Registers are listed in the following table. The serial addresses for each control register are shown in hexadecimal format. Angle brackets <> are used to reference specific bits or ranges of bits. For example, <3> designates bit 3 while <7:3> designates the range of bits from 7 down to 3, inclusive. A detailed description of each bit will follow the register layout tables.

Table x Control Registers Map

Register Name

(Address)

Channel Select

Register (CSR)

(00hex)

Function

Register

One

(FR1)

(01hex)

Bit Range

<7:0> *Note 1

<7:0>

<15:8> Open Profile Pin Configuration

<23:16> VCO gain PLL Divider Ratio

(MSB)

Bit 7

CH3 Enable

Clock Input

Power D own

Bit 6

*Note 1

CH2 Enable

Ext Power

Down Mode

Bit 5

*Note 1

CH1 Enable

Sync CLK

Disable

<14:12>

Bit 4

*Note 1

CH0 Enable

DAC Ref Power

Down

<22:18>

Bit 3

Must b e zero Serial IO Mode Select

Open Open

Ramp Up / Down (RU/RD)

<11:10>

Bit 2

Bit 1

<2:1>

Manual HW

SYNC

Modulation Level

Charge Pump Control

Manual SW

<9:8>

<17:16>

(LSB)

Bit 0

LSB First F0h

SYNC

Default

Va lu e

00h

Rev. PrD | Page 33 of 41

Preliminary Technical Data AD9959

Function

Register

Two (FR2)

(02hex)

*Note 1

The bits above, in gray background, do not require an I/O Update CLK to be activated. These particular bits are active immediately after the byte containing the bits is written. All other bits need an I/O update CLK to become active. The four Channel enable bits above are used to enable/disable any combination of the four channels.

CHANNEL REGISTERS MAP

The Channel Registers are listed in the following tables. The serial addresses for each channel register are shown in hexadecimal format. Angle brackets <> are used to reference specific bits or ranges of bits. For example, <3> designates bit 3 while <7:3> designates the range of bits from 7 down to 3, inclusive. A detailed description of each bit will follow the register layout tables.

<7:0> Slave Enable Master E nable Sync . Status Mask Sync

<15:8> Mast er Auto

Clear. Sweep

Accum

Master Clear

Sweep. Accum

Master Auto Clear Phase

Accum

Status

Master Clear

Phase Accum

All four channels default being enabled.

Open

<3:2>

Open

<11:10>

System Clock Offset

<1:0>

Open

<9:8>

00h

Table x Channel Register Map

Register Name

(Address)

*Note 2

Channel Function

Register

(CFR)

(03hex)

*Note 2 <7:0> Frequency Tuning Word #0 <7:0> 00h

Bit

Range

<7:0> Digital

<15:8>

<23:16>

(MSB)

Bit 7

Power

Down

Linear

Sweep No

Dwell

Amplitude Frequency Phase

DAC Power

Linear Sweep

Select<23:22>

Bit 6

Down

Enable

Bit 5

Match Pipe

Delays Active

Load SRR@I/O

UPDATE

Open

<21:20>

Rev. PrD | Page 34 of 41

Bit 4

Auto Clear

Sweep Ac cum

Open Open Must be zero

Bit 3

Clear Sweep

Accum

Open Open

Auto Clear

Phase Accum

Bit 2

Bit 1

*Note 3

Clear Phase

Accum

DAC LSB Control

<18:16>

<9:8>

(LSB)

Bit 0

Enable SINE

Output

Default

Va lu e

02h

03h

00h

Preliminary Technical Data AD9959

Channel Frequency

Tuning Word #0

(CTW0)

(04hex)

Channel Phase Offset Word #0

(CPW0)

(05hex)

<15:8> Frequency Tuning Word #0 <15:8> 00h

<23:16> Frequency Tuning Word #0 <23:16> 00h

<31:24> Frequency Tuning Word #0 <31:24> 00h

<7:0> Phase Offset Word #0 <7:0> 00h *Note 2

<15:8> Open<15:14> Phase Offset Word #0 <13:8> 00h

*Note 2

Channel Amplitude

Control Word #0

(CAW0)

(06hex)

Channel Linear

Sweep R egister

(LSR)

(07hex)

*Note 2

Channel LSR Rising

Delta Word

(RDW)

(08hex)

*Note 2

Channel LSR Falling

Delta Word

(FDW)

(09hex)

<7:0> Amplitude Scale Factor <7:0> 00h

<15:8> Increment / Decrement

<23:16> Amplitude Ramp Rate <23:16> 00h

<7:0> Linear Sweep Rising Ramp Rate <7:0> (RSRR) xxh *Note 2

<15:8> Linear Sweep Falling Ramp Rate <15:8> (FSRR) xxh

<7:0> Rising Delta Word <7:0> xxh

<15:8> Rising Delta Word <15:8> xxh

<23:16> Rising Delta Word <23:16> xxh

<31:24> Rising Delta Word <31:24> xxh

<7:0> Falling Delta Word <7:0> xxh

<15:8> Falling Delta Word <15:8> xxh

<23:16> Falling Delta Word <23:16> xxh

<31:24> Falling Delta Word <31:24> xxh

Step Size <15:14>

Open Amplitude

Multi plier

enable

Ramp-Up

/Ramp-down

enable

Load ARR @I/O

UPDATE

Amplitude Scale Factor <9:8>

00h

*Note 2:

They are (4) sets of Channel Registers and Profile Registers, one per channel. This is not shown in the Channel or Profile Register Maps. The reason is the addresses of all Channel Registers and Profile Registers are the same for each channel. Therefore, the channel enable bits determine if the channel’s Channel Registers and/or Profile Registers are written to or not.

For example, if the user wants 4 different frequencies for all four DDS channels, the following protocol will suffice.

1) Enable (logic 1) the “CH 0” bit only located in the Channel Select Register, disable the other three channels (logic 0).

2) Write the desired frequency tuning word for CH 0 above, then disable the “CH0” bit (logic 0)

3) Enable the “CH 1” bit only located in the Channel Select Register, disable the other three channels.

4) Write the desired frequency tuning word for CH 1 above, then disable the “CH 1” bit.

5) Repeat same sequence for “CH 2” and “CH 3” channels, then send IO_UPDATE.

*Note 3: The Clear Accumulator bit is set to logic “1” after a Master Reset. It self clears or is set to a logic “0” when an I/O_Update is

asserted

.

Rev. PrD | Page 35 of 41

Preliminary Technical Data AD9959

Profile Register Map

The Profile Registers are listed in the following tables. The serial addresses for each channel register are shown in hexadecimal format. Angle brackets <> are used to reference specific bits or ranges of bits. For example, <3> designates bit 3 while <7:3> designates the range of bits from 7 down to 3, inclusive. A detailed description of each bit will follow the register layout tables.

Register Name

(address)

Bit

Range

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

Default

Va lu e

Ch Word #1 (CTW1)

(0Ah)

Ch Word #2 (CTW2)

(0Bh)

Ch Word #3 (CTW3)

(0Ch)

Ch Word #3 (CTW4)

(0Dh)

Ch Word #5 (CTW5)

(0Eh)

Ch Word #6 (CTW6)

(0Fh)

Ch Word #7 (CTW7)

(10h)

Ch Word #8 (CTW8)

(11h)

Ch Word #9 (CTW9)

(12h)

Ch Word #10 (CTW10)

(13h)

Ch Word #11 (CTW11)

(14h)

Ch Word #12 (CTW12)

(15h)

<31:0> Freq. Tuning Word #2 <31:0> or Phase Word #2 <31:18> or Amplitude Word #2 <31:22> xxh

Ch Word #13 (CTW13)

(16h)

Ch Word #14 (CTW14)

(17h)

Ch Word #15 (CTW15)

(18h)

<31:0> Freq. Tuning Word #2 <31:0> or Phase Word #2 <31:18> or Amplitude Word #2 <31:22> xxh

Channel Select Register (CSR) Description

The CSR register determines if channels are enabled or disabled by the status of the (4) channel enable bits. All four channels are enabled by their default state. The CSR register also determines which serial mode of operation is selected. In addition, the CSR register offers a choice of MSB first or LSB first format. The functionality of each bit is detailed below.

The CSR is comprised of one byte located in address 00h.

CSR<0>: LSB First

CSR<0> = 0 (default), the serial interface accepts serial

data in MSB first format.

CSR<0> = 1, the serial interface accepts serial data in LSB first format.

CSR<2:1>: Serial I/O Mode Select

CSR<2:1>=00: Single bit serial (2-wire mode). CSR<2:1>=01:

Single bit serial (3-wire mode). CSR<2:1>=10: 2-bit serial mode CSR<2:1>=11: 4-bit serial mode.

Rev. PrD | Page 36 of 41

Preliminary Technical Data AD9959

See Serial Mode of Operation for more details.

FR1<5>: Sync CLK Disable

CSR<3> = Must be set to zero.

CSR<7:4>: Channel Enable bits

Note: The CSR<7:4> bits are active immediately after being

written. They do not require an IO_UPDATE to take affect.

They are (4) sets of Channel Registers and Profile Registers, one per channel. This is not shown in the Channel or Profile Register Maps. The reason is the addresses of all Channel Registers and Profile Registers are the same for each channel. Therefore, the channel enable bits determine if the channel’s Channel Registers and/or Profile Registers are written to or not.

Multiple channels can be simultaneously written to using these bits.

For example:

CSR<7:4>=1001: Only Channels 3 and 0 will receive commands from the Channel Registers and/or Profile Registers.

CSR<7:4>=0010: Only Channel 1 will receive commands from the Channel Registers and/or Profile Registers.

Function Register 1 (FR1) Description

FR1 is comprised of 3 bytes located in address 01h. The FR1 is used to control the various functions, features, and modes of the AD9959. The functionality of each bit is detailed below.

FR1<0>: Software Manual Synchronization bit

FR1<0>=0 (default), the software manual synchronization

feature of multiple AD9959s is inactive.

FR1<0>=1, the software manual synchronization feature of multiple AD9959s is active.

See synchronizing Multiple AD9959 devices section for details.

FR1<1>: Hardware Manual Synchronization bit

FR1<5> = 0 (default), the SYNC_CLK pin is active.

FR1<5> = 1, The SYNC_CLK pin assumes a static logic 0 state

(disabled). In this state the pin drive logic is shut down. However, the synchronization circuitry remains active internally to maintain normal device operation.

FR1<6>: External Power Down Mode

FR1<6> = 0 (default) the external power down mode is in the

“fast recovery power down” mode. In this mode, when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are NOT powered down.

FR1<6> = 1, the external power down mode is in the “full power down” mode. In this mode, when the Ext PWR_DWN_CTL input pin is high, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up.

FR1<7>: Clock Input Power Down

FR1<7> = 0 (default), the Clock Input Circuitry is enabled for

operation.

FR1<7> = 1, the Clock Input Circuitry is disabled and is in a low power dissipation state.

FR1<9:8>: Modulation Level bits

These bits control the level (2/4/8/16) of modulation to be performed for that channel. See the Modulation Description section in this document for more details.

FR1<10:11>: RU/RD bits

These bits control the amplitude ramp up/ramp down time of the channel. See the Output Amplitude Ramp Mode Description section for more details.

FR1<1>=0 (default), the hardware manual synchronization feature of multiple AD9959s is inactive.

FR1<1>=1, the hardware manual synchronization feature of multiple AD9959s is active.

See synchronizing Multiple AD9959 devices section for details.

FR1<2:3>: Open

FR1<4>: DAC Reference Power Down

FR1<4>=0 (default) DAC reference is enabled.

FR1<4>=1 DAC reference is powered down.

Rev. PrD | Page 37 of 41

FR1<12:14>: Profile Pin Configuration pins

Controls the configuration of the data and SDIO pins for the different Modulation modes. See the Modulation Description section in this document for details.

FR1<15> Open

FR1<17:16>: Charge Pump Control

FR1<17:16> = 00 (default) the charge pump current is 75µA. FR1<17:16> = 01 the charge pump current is 100µA. FR1<17:16> = 10 the charge pump current is 125µ A. FR1<17:16> = 11 the charge pump current is 150 µA.

FR1<22:18> REF CLK Mulitipler ( PLL) Divider values.

Preliminary Technical Data AD9959

FR1<22:18> IF the value is 4 or 20 (decimal) or between 4 and 20, the PLL is enabled and the value of these bits sets the multiplication of the PLL.

FR1<22:18> If the value is outside of 4 and 20 (decimal) the PLL is disabled.

FR1<23>: PLL VCO gain

FR1<23> = 0 (default) the low range (System clock below

200Mhz).

FR1<23> = 1 the high range (System clock above 200Mhz).

zeros into) the phase accumulator for one cycle upon reception of the I/O UPDATE sequence indicator on all four channels.

FR2<14>: Master Clear Sweep Accumulator

FR2<14> = 0 (default), the sweep accumulator functions as

normal.

FR2<14> = 1, the sweep accumulator memory elements for all four channels are asynchronously cleared.

FR2<15>: Master Auto Clear sweep accumulator

FR2<15> = 0 (default), a new delta word is applied to the input,

as in normal operation, but not loaded into the accumulator.

Function Register 2 (FR2) Description

The FR2 is comprised of 2 bytes located in parallel address 02h. The FR2 is used to control the various functions, features, and modes of the AD9959. The functionality of each bit is detailed below.

FR2<1:0>: System clock offset

See the Synchronizing Multiple Devices section for more details.

FR2<3:2>Open

FR2<4>: Mask sync status

See the Synchronizing Multiple Devices section for more details

FR2<5>: Sync. Status

See the Synchronizing Multiple Devices section for more details

FR2<6>: Master Enable bit

See the Synchronizing Multiple Devices section for more details.

FR2<7>: Slave Enable bit

See the Synchronizing Multiple Devices section for more details

FR2<11:8> Open

FR2<15> = 1, this bit automatically synchronously clears (loads

zeros into) the sweep accumulator for one cycle upon reception of the I/O_UPDATE sequence indicator on all four channels.

Channel Function Register (CFR) Description

CFR<0>: Enable SINE Output

CFR<0> = 0 (default), the angle-to-amplitude conversion logic

employs a COSINE function.

CFR<0> = 1, the angle-to-amplitude conversion logic employs a SINE function.

CFR<1>: Clear Phase Accumulator

CFR<1> = 0 (default), the phase accumulator functions as

normal.

CFR<1> = 1, the phase accumulator memory elements are asynchronously cleared.

CFR<2>: Clear Phase Accumulator

CFR<2> = 0 (default), a new frequency tuning word is applied

to the inputs of the phase accumulator, but not loaded into the accumulator.

FR2<12>: Master Clear Phase Accumulator

FR2<12> = 0 (default), the phase accumulator functions as

normal.

FR2<12> = 1, the phase accumulator memory elements for all four channels are asynchronously cleared.

FR2<13>: Master Auto Clear Phase Accumulator

FR2<13> = 0 (default), a new frequency tuning word is applied

to the inputs of the phase accumulator, but not loaded into the accumulator.

FR2<13> = 1, this bit automatically synchronously clears (loads

Rev. PrD | Page 38 of 41

CFR<2> = 1, this bit automatically synchronously clears (loads zeros into) the phase accumulator for one cycle upon reception of the I/O UPDATE sequence indicator.

CFR<3>: Clear Frequency Accumulator

CFR<3> = 0 (default), the sweep accumulator functions as

normal.

CFR<3> = 1, the sweep accumulator memory elements are asynchronously cleared. CFR<4>: Auto Clear Sweep Accumulator

CFR<4> = 0 (default), a new delta word is applied to the input, as in normal operation, but not loaded into the accumulator.

Preliminary Technical Data AD9959

CFR<4> = 1, this bit automatically synchronously clears (loads zeros into) the sweep accumulator for one cycle upon reception of the I/O UPDATE sequence indicator.

CFR<5>: Match Pipe Delays Active

CFR<5> = 0 (default), match pipe delay mode is inactived.

CFR<18:16>: Open

CFR<23:22>: Amplitude Frequency Phase Select

Controls what type of modulation is to be performed for that channel. See the Modulation Description section in this document for details.

CFR<5> = 1, match pipe delay mode is active. See the section on pipe matched application parts for details.

CFR<6>: DAC Power Down

CFR<6> = 0 (default), the DAC is enabled for operation.

CFR<6> = 1, the DAC is disabled and is in its lowest power

dissipation state.

CFR<7>: Digital Power Down

CFR<7> = 0 (default), the Digital core is enabled for operation.

CFR<7> = 1, the Digital core is disabled and is in its lowest

power dissipation state.

CFR<8:9>: DAC LSB Control

CFR<8:9>= 00 (default), The DAC is at the largest LSB value.

CFR<10>: Must be set to zero

CFR<13>: Linear Sweep ramp rate load @I/O UPDATE

CFR<13> = 0 (default), the linear sweep ramp rate timer is loaded only upon timeout (timer ==1) and is NOT loaded due to a I/O UPDATE input signal.

Channel Frequency Tuning Word (CFTWO) Description

CFTW0<32:0>: Frequency tuning word #0 for each channel

Channel Phase Offset Word (CPOW) Description

CPO0<13:0> Phase offset word #0 for each channel

CPO0<15:14> Open

Amplitude Control Register (ACR) Description

ACR<9:0> Amplitude Scale Factor for each Channel

ACR<10>: Amplitude ramp rate load control bit.

ACR<10> = 0 (default), the amplitude ramp rate timer is loaded

only upon timeout (timer ==1) and is NOT loaded due to a I/O UPDATE input signal (or change in PS bits).

ACR<10> = 1, the amplitude ramp rate timer is loaded upon timeout (timer ==1) or at the time of a I/O UPDATE input signal (or change in PS bits).

ACR<11>: AUTO RU/RD enable (only valid when ACR<12> is active high).

CFR<13> = 1, the linear sweep ramp rate timer is loaded upon timeout (timer ==1) or at the time of a I/O UPDATE input signal.

CFR<14>: Linear Sweep Enable

CFR<14> = 0 (default), the linear sweep capability of the

AD9959 is inactive.

CFR<14> = 1, the linear sweep capability of the AD9959 is enabled. When enabled, the Delta Frequency Tuning Word is applied to the Frequency accumulator at the programmed ramp rate

CFR<15>: Linear Sweep No Dwell

CFR<15> = 0 (default) the Linear Sweep no dwell function is

inactive.

CFR<15> = 1, the Linear Sweep no dwell function is active. If

CFR<15> is active, the Linear Sweep no dwell function is

activated. See the Linear Sweep section of this document for details. If CFR<14> is clear, this bit is a don’t care.

Rev. PrD | Page 39 of 41

ACR<11> = 0 (default). When ACR<12> is active, a logic 0 on ACR<11> enables the MANUAL RU/RD operation. See the

OUTPUT AMPLITUDE RAMP MODE section of this document for details.

ACR<11> = 1, if ACR<12> is active, a logic 1 on ACR<11> enables the AUTO RU/RD operation. See the OUTPUT AMPLITUDE RAMP MODE section of this document for details.

ACR<12>: Amplitude Multiplier Enable

ACR<12> = 0 (default,) Amplitude Multiplier is disabled. The

clocks to this scaling function (AUTO RU/RD) are stopped for power savings and the data from the DDS core is routed around the multipliers.

ACR<12> = 1, Amplitude Multiplier is enabled.

ACR<13> Open

ACR<15:14> Amplitude Increment/Decrement Step Size.

ACR<23:16> Amplitude Ramp Rate value

Preliminary Technical Data AD9959

Channel Linear Sweep Register (LSR) Description

LSR<15:0> Linear Sweep Rising Ramp Rate

Channel Linear Sweep Rising Delta Word Register (RDW) Description

RDW<31:0> 32-bit Rising Delta tuning word

Channel Linear Sweep Falling Delta Word Register (FDW) Description

FDW<31:0> 32bit falling Delta tuning word

Rev. PrD | Page 40 of 41

Preliminary Technical Data AD9959

PR05246-0-2/05(PrD)

ORDERING GUIDE

AD9959 Products Temperature Range Package Description Package Outline

AD9959YSV –40°C to +85°C 56-Lead Chip Scale Package, Exposed Pad (LFCSP) SV-56 AD9959YSV-REEL7 –40°C to +85°C 500 Device 7-Inch Reel of 56-Lead LFCSP SV-64 AD9959/PCB Evaluation Board

Rev. PrD | Page 41 of 41