Datasheet AD9958 Datasheet (Analog Devices)

DUAL Channel 500MSPS DDS with 10-bit DACs

Preliminary Technical Data

FEATURES

Two synchronized DDS channels @500 MSPS
Independent frequency / phase / amplitude
control between all channels
Matched latencies for Freq, Phase, and Amplitude changes
Excellent channel to channel isolation
Frequency sweeping capability
Up to 16 levels of modulation (pin selectable)
Programmable DAC full scale current
Two integrated 10-bit D/A converters(DACs)
32-bit frequency tuning resolution
14-bit phase offset resolution
10-bit output amplitude scaling resolution
Serial I/O Port(SPI) with enhanced data throughput

FUNCTIONAL BLOCK DIAGRAM

AD9958

Software/Hardware controlled power-down
Dual supply operation (1.8 V DDS core / 3.3 V serial I/O)
Built-in synchronization for multiple devices
Selectable REF CLK multipier(PLL) 4x to 20x (bypassable)
Selectable REF CLK crystal operation
56 pin LFCSP package

APPLICATIONS

Agile L.O. frequency synthesis
Phased array radar / sonar
Instrumentation
Synchronized clocking
RF source for AOTF

SYNC_IN

SYNC_OUT

IO_UPDATE

SYNC_CLK

OSC / REF_CLK

OSC / REF_CLK

ACCUMULATOR

ACCUMULATOR

32

DFTW

BUFFER / XTAL

OSCILLATOR

CLK_MODE_SEL

FREQUENCY

FREQUENCY

RAMP
RATE

÷4

32

32

8

REF CLOCK
MULTIPLIER

4x to 20x

Σ

32

Σ

32

32

FTW

Timing & Control Logic

SYSTEM

CLK

M
U
X

AVDD DVDD

Figure 1 AD9958 Block Diagram

Σ

Σ

PHASE

OFFSET

DDS CORE

Σ

Σ

1.8V1.8V

COS(X)

15

DDS CORE

COS(X)

15

14

10

10

AMP

CONTROL

CONTROL

REGISTERS

CHANNEL

REGISTERS

PROFILE

REGISTERS

P

P

P

P

S

S

S

S

0

3

2

1

×

10

×

10

10

DAC

DAC

SCALABLE

DAC REF

CURRENT

I/O

Port

Buffer

3.3V

DVDD_IO

IOUT
IOUT

IOUT
IOUT

DAC_RSET

PWR_DWN_CTL

MASTER_RESET

SCLK

CS

SDIO_0
SDIO_1
SDIO_2
SDIO_3

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD9958 Preliminary Technical Data

AD9958—SPECIFICATIONS

Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R
Frequency = 500 MSPS (REF_CLK multiplier bypassed)

Parameter

REF CLOCK INPUT CHARACTERISTICS

Frequency Range
REF_CLK Multiplier bypassed 0 500 MHz
REF_CLK Multiplier enabled at 4x(min) 25 125 MHz
REF_CLK Multiplier enabled at 20x(max) 5 25 MHz
Internal VCO range w/ REF_CLK multiplier enabled 100 500 MHz
Crystal Ref Clock source mode 20 30 MHz
Input Power Sensitivity -15 3 dBm External 50 ohm termination
Input voltage level 400 mV
Input Capacitance 3 pF
Input Impedance 1500 ohms

Duty Cycle w/ REF_CLK Multiplier bypassed 50 %

Duty Cycle w/ REF_CLK Multiplier enabled 35 65 %
CLK Mode Select logic 1 Voltage 1.25 V Not a 3.3V digital input
CLK Mode Select logic 0 Voltage 0.6 V Not a 3.3V digital input

DAC OUTPUT CHARACTERISTICS

Resolution 10 Bits
Full Scale Ouput Current 10 mA
Gain Error -10 10 %FS
Output Offset 0.6 uA
Differential Nonlinearity -0.5 0.5 LSB
Integral Nonlinearity -1 1 LSB
Output Capactiance

Voltage Compliance Range

Channel to Channel Isolation 60 dB
Channel to Channel amplitude matching error 2 %

WIDEBAND SFDR

1-20 MHz Analog Out -65 dBc

20-60 MHz Analog Out -62 dBc

60-100 MHz Analog Out -59 dBc
100-150 MHz Analog Out -56 dBc
150-200 MHz Analog Out -54 dBc

NARROWBAND SFDR

1.1 MHz Analog Out (+/- 10kHz) -90 dBc

1.1 MHz Analog Out (+/- 50kHz) -88 dBc

1,1 MHz Analog Out (+/- 250kHz) -86 dBc

1.1 MHz Analog Out (+/- 1MHz) -85 dBc

15.1 MHz Analog Out (+/- 10kHz)

15.1 MHz Analog Out (+/- 50kHz) -87 dBc

15.1 MHz Analog Out (+/- 250kHz) -85 dBc

15.1 MHz Analog Out (+/- 1MHz) -83 dBc

40.1 MHz Analog Out (+/- 10kHz)

40.1 MHz Analog Out (+/- 50kHz) -87 dBc

40.1 MHz Analog Out (+/- 250kHz) -84 dBc

40.1 MHz Analog Out (+/- 1MHz) -82 dBc

Min Typ

5

AVDD–

0.50

-90

-90

Max Units

pF

AVDD

+ 0.50

= 1.96 kΩ, External Reference Clock

SET

Test Conditions/Comments

REF_CLK inputs must be AC

coupled due to internal biasing

Must be referenced to AVDD

V

Wideband SFDR defined as DC to

dBc

dBc

Nyquist

Rev. PrB | Page 2 of 9

Preliminary Technical Data AD9958

Parameter

75.1 MHz Analog Out (+/- 10kHz) -87 dBc

75.1 MHz Analog Out (+/- 50kHz) -85 dBc

75.1 MHz Analog Out (+/- 250kHz) -83 dBc

75.1 MHz Analog Out (+/- 1MHz) -82 dBc

100.1 MHz Analog Out (+/- 10kHz) -87 dBc

100.1 MHz Analog Out (+/- 50kHz) -85 dBc

100.1 MHz Analog Out (+/- 250kHz) -83 dBc

100.1 MHz Analog Out (+/- 1MHz) -81

200.1 MHz Analog Out (+/- 10kHz) -87 dBc

200.1 MHz Analog Out (+/- 50kHz) -85 dBc

200.1 MHz Analog Out (+/- 250kHz) -83 dBc

200.1 MHz Analog Out (+/- 1MHz) -81

PHASE NOISE CHARACTERISTICS

Residual Phase Noise @15.1 MHz(Aout)

@1kHz offset TBD dBc/ Hz
@10kHz offset TBD dBc/ Hz
@100kHz offset TBD dBc/ Hz
@1MHz offset TBD dBc/ Hz

Residual Phase Noise @ 75.1 MHz(Aout)

@1kHz offset TBD dBc/ Hz
@10kHz offset TBD dBc/ Hz
@100kHz offset TBD dBc/ Hz
@1MHz offset TBD dBc/ Hz

Residual Phase Noise @ 200.1 MHz(Aout)

@1kHz offset TBD dBc/ Hz
@10kHz offset TBD dBc/ Hz
@100kHz offset TBD dBc/ Hz

@1MHz offset TBD dBc/ Hz
Residual Phase Noise @ 15.1 MHz(Aout)
w/ REF_CLK multiplier enabled 4x

@1kHz offset TBD dBc/ Hz

@10kHz offset TBD dBc/ Hz

@100kHz offset TBD dBc/ Hz

@1MHz offset TBD dBc/ Hz

Residual Phase Noise @ 75.1 MHz(Aout)
w/ REF_CLK multiplier enabled 4x

@1kHz offset TBD dBc/ Hz

@10kHz offset TBD dBc/ Hz

@100kHz offset TBD dBc/ Hz

@1MHz offset TBD dBc/ Hz
Residual Phase Noise @ 200.1 MHz(Aout)
w/ REF_CLK multiplier enabled 4x

@1kHz offset

@10kHz offset

@100kHz offset

@1MHz offset

SERIAL PORT TIMING CHARACTERISTICS

Maximum Frequency 200

Minimum Clock Pulsewidth Low (t

Minimum Clock Pulsewidth High (t

) TBD

PWL

) TBD

PWH

Min Typ

TBD

TBD

TBD

TBD

Max Units Test Conditions/Comments

dBc

dBc

dBc/ Hz

dBc/ Hz

dBc/ Hz

dBc/ Hz

MHz

ns

ns

Rev. PrB | Page 3 of 9

AD9958 Preliminary Technical Data

Maximum Clock Rise/Fall Time TBD

Minimum Data Setup Time (tDS) TBD

Minimum Data Hold Time TBD

MISC TIMING CHARACTERISTICS

Master_Reset minimum Pulsewidth TBD

I/O_Update minimum Pulsewidth 1

Minimum setup time (IO_Update to Sync_CLK) TBD

Minimum hold time (IO_Update to Sync_CLK) 0

Minimum setup time (Profile inputs to Sync_CLK)
Minimum hold time (Profile inputs to Sync_CLK)

DATA LATENCY (PIPE LINE DELAY)

Matched pipe line of Freq, Phase, Amplitude TBD

Frequency word to DAC output TBD

Phase Offset word to DAC output TBD

Amplitude word to DAC output TBD

CMOS LOGIC INPUTS

VIH 2.2

VIL

Logic 1 Current 3

Logic 0 Current -12

Input Capacitance 2

CMOS LOGIC OUTPUTS (1 mA Load)

VOH 2.8

VOL

POWER SUPPLY

Total Power Dissipation- all channels ON, single-tone mode TBD

Maximum Power Dissipation- all channels, freq accumulator
output multiplier ON
Iavdd – All Channels ON, Single tone mode TBD

Iavdd – All Ch(s) ON, Freq accum, and output multiplier ON TBD

Idvdd – All Ch(s) ON, Single tone mode TBD

Idvdd – All Ch(s) ON, Freq accum, and output multiplier ON TBD

Idvdd_I/O TBD

Power down Mode TBD

TBD

TBD

0

ns

ns

ns

Sync CLK

Sync CLK

ns Rising edge to rising edge

ns Rising edge to rising edge

Sys Clks matched

Sys Clks unmatched

Sys Clks unmatched

Sys Clks unmatched

ns

ns

Pipeline delays for Freq, Phase,
Amp changes are programmable to
match one another.

V

0.6 V

12 uA

uA

pF

V

0.4 V

mW

mA

mA

mA

mA

mA

mA

Rev. PrB | Page 4 of 9

Preliminary Technical Data AD9958

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C
DVDD_I/O (Pin 49) 4 V
AVDD, DVDD 2 V
Digital Input Voltage (DVDD_I/O = 3.3 V) –0.7 V to +4V
Digital Output Current 5 mA
Storage Temperature –65°C to +150°C
Operating Temperature –40°C to +105°C
Lead Temperature (10 sec Soldering) 300°C

θJA 21°C/W

θJC 2°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CMOS

DIGITAL

INPUTS

DVDD_I/O= 3.3V

INPUT

AVOID OVERDRIVING

DIGITAL INPUTS.

FORWARD BIASING

DIIODES MAY COUPLE

DIGITAL NOISE ON

POWER PINS.

OUTPUT

DAC OUPUTS

Iout

TERMINATE OUTPUTS

INTO AVDD. DO NOTE

EXCEED OUTPUT

VOLTAGE COMPLIANCE.

Iout

OSC / REF_CLK

INPUTS

AVDD

1.5 k

REF_CLK

AVDD AVDD

OSC OSC

NEED TO BE AC-COUPLED.

zz

AMP

REF_CLK INPUT S ARE

INTERNALLY BIASED AND

OSC INPUTS ARE DC

COUPLED

1.5 k
REF_CLK

Figure 1 Equivalent input and output circuits

Rev. PrB | Page 5 of 9

AD9958 Preliminary Technical Data

PRODUCT OVERVIEW

The AD9958 consists of two independently programmable DDS
channels. Since both channels share a common system clock,
they are inherently synchronized. If more than two channels are
required, synchronizing multiple AD9958s is a simple task. The
AD9958 features independent frequency, phase, and amplitude
control of each channel; this allows for the correction of
imbalances due to analog processing such as filtering,
amplification, or PCB layout related mismatches. The AD9958
supports frequency sweeping for radar and instrumentation
applications.

The AD9958 uses advanced DDS technology which provides
low power dissipation with high performance. The device
incorporates two integrated high speed 10-bit DAC with
excellent wideband and narrowband SFDR. Each DDS has a 32­bit frequency tuning word, 14-bits of phase offset, and a 10-bit
output scale multiplier.

Each DAC has it own programmable reference to enable a
different full scale current for each channel.

Each DDS acts as a high resolution frequency divider with the
REF_CLK as the input and the DAC providing the output. The
REF_CLK input source is common to both DDS channels, and can be
driven directly, or used in combination with an integrated REF_CLK
multiplier (using a PLL) up to a maximum of 500 MSPS. The
REF_CLK multiplication factor is programmable from 4 to 20, in
integer steps. The REF_CLK input features an oscillator which
supports either a crystal as a source, or may be bypassed. The crystal
frequency must be between 20MHz and 30MHz. The crystal can be
used with or without the REF_CLK multiplier.

The DAC outputs are supply referenced and must be terminated into
AVDD by a resistor, or an AVDD center-tapped transformer.

The AD9958 comes in a space-saving 56-lead LFCSP package. The
DDS core (AVDD and DVDD pins) must be powered by a 1.8V supply.
The digital I/O interface (SPI) operates at 3.3V and requires that the
pin labeled “DVDD_I/O” (pin 49) be connected to 3.3V.

The AD9958 operates over the extended industrial temperature range
of -40C to +85

Rev. PrB | Page 6 of 9

Preliminary Technical Data AD9958

PIN CONFIGURATION

I/O_UPDATE

DVDD_ I/O

DVDD

DGND

SYNC_CLK
54

55

56

SDIO_1

SDIO_2

SDIO_3

53

SDIO_0

52

51

50

CS

SCLK

49

48

47

DVDD

DGND

P3

46

45

44

43

SYNC_IN

SYNC_OUT

MASTER_RESET

PWR_DWN_CTL

AVDD

AGND

AVDD

TBD
TBD

AGN D

AVDD

AGND

TBD
TBD

1

2
3
4
5
6
7
8

9
10
11
12
13
14

16

15

AVDD

AGND

AD9958

56-LD LFC S P

TOP VIEW

(Not to Scale)

17

18

19

20

AVDD

AGND

AGND

DAC_RSET

21

AVDD

22

23

24

25

26

27

AVDD

AGND

OSC / REF_CLK

OSC / REF_CLK

CLK_MO DE_SEL

LOO P_FILTER

42

P2

41

P1
P0

40
39

AVDD

38

AGND

37

AVDD

36

TBD

35

TBD

34

AGND

33

AVDD
AGND

32
31

AVDD

30

TBD

29

TBD

28

AGND

Notes 1) The exposed EPAD on bottom side of package is an electrical connection and must be
soldered to ground.

2) Pin 49 is DVDD_IO and is tied to 3.3V.

Rev. PrB | Page 7 of 9

AD9958 Preliminary Technical Data

Table 3. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 SYNC_IN I Used to synchronize multiple AD9959s. Connect to the SYNC_OUT pin of the master AD9959.
2 SYNC_OUT O Used to synchronize multiple AD9959s. Connect to the SYNC_IN pin of the slave AD9959.
3

MASTER_RESET
4 PWR_DWN_CTL I External Power-Down Control.
5,7,11,15,19,21,
26,31,33,37,39
6,10,12,16,18,20,
25,28,32,34,38
45, 55 DVDD I Digital Power Supply Pins (1.8 V).
44, 56 DGND I Digital Power Ground Pins.
8 TBD
9 TBD
13 TBD
14 TBD
17 DAC_R

22

23 OSC / REF_CLK I

24 CLK_MODE_SEL I

27 LOOP_FILTER I

29 TBD
30 TBD
35 TBD
36 TBD
40, 41,
42, 43

46 I/O_UPDATE I A rising edge detected on this pin transfers data from serial port buffer to active registers.
47
48 SCLK I

49 DVDD_I/O I 3.3 V Digital Power Supply for SPI port and I/O (excluding CLK_MODE_SEL).
50, 51
52, 53
54 SYNC_CLK O

AVDD I Analog Power Supply Pins (1.8V).

AGND I Analog Ground Pins.

I

SET

/ REF_CLK

OSC

PS0, PS1,

PS2, PS3

CS

SDIO_0, SDIO_1

SDIO_2, SDIO_3

I

Active high reset pin. Asserting the RESET pin forces the AD9959’s internal registers to their
default state, as described in the serial I/O port register map section in this document.

These pins are still being evaluated for DAC outputs for
Channels 0 and 1.

Establishes the reference current for all DACs. A 1.962 kΩ resistor (nominal) is connected from
pin 17 to AGND.

I

Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in single­ended mode, this pin should be decoupled to AVDD or AGND with a 0.1 µF capacitor.

Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this is
the input.

Control Pin for the Oscillator Section. When high (1.8V), the oscillator section is enabled to
accept a crystal as the REFCLK source. When low, the oscillator section is bypassed.

CAUTION: Do not drive this pin beyond 1.8V.
Connect to the external zero compensation network of the PLL loop filter for the REFCLK

multiplier. For a 20x multiplier value the network should be a 1.2kΩ resistor in series with a 1.2
nF capacitor tied to AVDD.

These pins are still being evaluated for DAC outputs for
Channels 0 and 1.

I

These Pins are synchronous to the SYNC_CLK (pin 54). Any change in Profile inputs transfers
the contents of the internal buffer memory to the I/O active registers (same as an external I/O
_UPDATE).

I Active low chip select allowing multiple devices to share a common I/O bus (SPI).

Serial data clock for I/O operations. Data bits are written on rising edge of SCLK and read on
the falling edge of SCLK.

I/O

These data pins have multiple functions. Data I/O pins for the serial I/O port operation. They
are also used as data pins in modulation modes.

I/O_UPDATE and Profile signals should meet the set-up and hold requirements with respect to
this signal in order to guarantee a fixed pipeline delay of data to DAC outputs.

Rev. PrB| Page 8 of 9

Preliminary Technical Data AD9958

PR05252-0-11/04(PrB)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrB | Page 9 of 9