New AD9949A supports CCD line length > 4096 pixels
Correlated double sampler (CDS)
0 dB to 18 dB pixel gain amplifier (PxGA®)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
12-bit, 36 MSPS analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing driver
Precision Timing™ core with < 600 ps resolution
On-chip 3 V horizontal and RG drivers
40-lead LFCSP package
APPLICATIONS
Digital still cameras
High speed digital imaging applications
FUNCTIONAL BLOCK DIAGRAM
Precision Timing
Core
AD9949
GENERAL DESCRIPTION
The AD9949 is a highly integrated CCD signal processor for
digital still camera applications. Specified at pixel rates of up to
36 MHz, the AD9949 consists of a complete analog front end
with A/D conversion, combined with a programmable timing
driver. The Precision Timing core allows adjustment of high
speed clocks with < 600 ps resolution.
The analog front end includes black level clamping, CDS,
PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver
provides the high speed CCD clock drivers for RG and H1 to
H4. Operation is programmed using a 3-wire serial interface.
Packaged in a space-saving, 40-lead LFCSP package, the
AD9949 is specified over an operating temperature range of
−20°C to +85°C.
REFT REFB
6dB TO 42dB
INTERNAL
CLOCKS
PRECISION
GENERATOR
HDVD
CCDIN
RG
H1 TO H4
4
AD9949
CDS
HORIZONTAL
DRIVERS
0dB TO 18dB
PxGA
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
The total power dissipated by the HVDD supply may be approximated using the equation
Total HVDD Power = (CLOAD x HVDD x Pixel Frequency) x HVDD x (Number of H – Outputs Used)
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply, reduces the power dissipation.
DIGITAL SPECIFICATIONS
T
to T
MIN
Table 2.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage VIH 2.1 V
Low Level Input Voltage VIL 0.6 V
High Level Input Current IIH 10 µA
Low Level Input Current IIL 10 µA
Input Capacitance CIN 10 pF
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA VOH 2.2 V
Low Level Output Voltage, IOL = 2 mA VOL 0.5 V
CLI INPUT
Resolution 12 Bits
Differential Nonlinearity (DNL) −1.0 ±0.5 +1.0 LSB
No Missing Codes Guaranteed
Integral Nonlinearity (INL) 8 LSB
Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (REFT) 2.0 V
Reference Bottom Voltage (REFB) 1.0 V
SYSTEM PERFORMANCE Specifications include entire signal chain
VGA Gain Accuracy
Peak Nonlinearity, 500 mV Input Signal 0.15 0.6 % 12 dB gain applied
Total Output Noise 0.8 LSB rms AC grounded input, 6 dB gain applied
Power Supply Rejection (PSR) 50 dB Measured with step change on supply
Minimum Gain (Code 0) 5.0 5.5 6.0 dB
Maximum Gain (Code 1023) 40.5 41.5 42.5 dB
500mV TYP
RESET TRANSIENT
50mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT SIGNAL RANGE
03751-002
Rev. B | Page 4 of 36
Page 5
AD9949
TIMING SPECIFICATIONS
CL = 20 pF, f
Table 4.
Parameter Symbol Min Typ Max Unit
MASTER CLOCK (CLI) (See Figure 16)
CLI Clock Period t
CLI High/Low Pulse Width t
Delay from CLI to Internal Pixel Period Position t
CLPOB PULSE WIDTH (PROGRAMMABLE)1 t
SAMPLE CLOCKS (See Figure 18)
SHP Rising Edge to SHD Rising Edge tS1 12.5 13.9 ns
DATA OUTPUTS (See Figure 19 and Figure 20)
Output Delay From Programmed Edge tOD 6 ns
Pipeline Delay 11 Cycles
SERIAL INTERFACE (SERIAL TIMING SHOWN IN Figure 14 and Figure 15)
Maximum SCK Frequency f
SL to SCK Setup Time tLS 10 ns
SCK to SL Hold Time tLH 10 ns
SDATA Valid to SCK Rising Edge Setup tDS 10 ns
SCK Falling Edge to SDATA Valid Hold tDH 10 ns
SCK Falling Edge to SDATA Valid Read tDV 10 ns
1
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
= 36 MHz, unless otherwise noted.
CLI
27.8 ns
CLI
11.2 13.9 16.6 ns
ADC
6 ns
CLIDLY
2 20 Pixels
COB
10 MHz
SCLK
Rev. B | Page 5 of 36
Page 6
AD9949
ABSOLUTE MAXIMUM RATINGS
Table 5.
With
Parameter
AVDD and TCVDD AVSS −0.3 V to +3.9 V
HVDD and RGVDD
DVDD and DRVDD
Any VSS Any VSS −0.3 V to +0.3 V
Digital Outputs DRVSS −0.3 V to DRVDD + 0.3 V
CLPOB/PBLK and HBLK DVSS −0.3 V to DVDD + 0.3 V
SCK, SL, and SDATA DVSS −0.3 V to DVDD + 0.3 V
RG RGVSS −0.3 V to RGVDD + 0.3 V
H1 to H4 HVSS −0.3 V to HVDD + 0.3 V
REFT, REFB, and CCDIN AVSS −0.3 V to AVDD + 0.3 V
Junction Temperature 150°C
Lead Temperature (10 s) 300°C
Respect to Rating
HVSS,
RGVSS
DVSS,
DRVSS
−0.3 V to +3.9 V
−0.3 V to +3.9 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
40-Lead LFCSP Package: θ
1
θJA is measured using a 4-layer PCB with the exposed paddle soldered to the
board.
= 27°C/W1.
JA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.
Rev. B | Page 6 of 36
Page 7
AD9949
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HVSS
HVDD
SL
SCK
SDI
31
30
REFB
REFT
29
28
AVSS
27
CCDIN
26
AVDD
25
CLI
TCVDD
24
23
TCVSS
RGVDD
22
RG
21
H4
H3
RGVSS
03751-003
DRVSS
DRVDD
D0 (LSB)
CLP/PBLK
HBLK
DVDD
DVSSHDVD
403938373635343332
1
D1
D2
D3
D4
D5
D6
D7
D8
10
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
AD9949
TOP VIEW
11
121314151617181920
H2
H1
D9
D10
(MSB) D11
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 to 4 D1 to D4 DO Data Outputs
5 DRVSS P Digital Driver Ground
6 DRVDD P Digital Driver Supply
7 to 13 D5 to D11 DO Data Outputs (D11 is MSB)
14 H1 DO CCD Horizontal Clock 1
15 H2 DO CCD Horizontal Clock 2
16 HVSS P H1 to H4 Driver Ground
17 HVDD P H1 to H4 Driver Supply
18 H3 DO CCD Horizontal Clock 3
19 H4 DO CCD Horizontal Clock 4
20 RGVSS P RG Driver Ground
21 RG DO CCD Reset Gate Clock
22 RGVDD P RG Driver Supply
23 TCVSS P Analog Ground for Timing Core
24 TCVDD P Analog Supply for Timing Core
25 CLI DI Master Clock Input
26 AVDD P Analog Supply for AFE
27 CCDIN AI Analog Input for CCD Signal (Connect through Series 0.1 µF Capacitor)
28 AVSS P Analog Ground for AFE
29 REFT AO Reference Top Decoupling (Decouple with 1.0 µF to AVSS)
30 REFB AO Reference Bottom Decoupling (Decouple with 1.0 µF to AVSS)
31 SL DI 3-Wire Serial Load
32 SDI DI 3-Wire Serial Data Input
33 SCK DI 3-Wire Serial Clock
34 VD DI Vertical Sync Pulse
35 HD DI Horizontal Sync Pulse
36 DVSS P Digital Ground
37 DVDD P Digital Supply
38 HBLK DI Optional HBLK Input
39 CLP/PBLK DO CLPOB or PBLK Output
40 D0 DO Data Output LSB
1
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
Rev. B | Page 7 of 36
Page 8
AD9949
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively, must
be present over all operating conditions.
Integral Nonlinearity (INL)
INL is the deviation of each individual code measured from a
true straight line from zero to full scale. The point used as zero
scale occurs 0.5 LSB before the first code transition. Positive full
scale is defined as a level 1 LSB and 0.5 LSB beyond the last
code transition. The deviation is measured from the middle of
each particular output code to the true straight line.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9949 from a straight line.
The point used as zero scale occurs 0.5 LSB before the first code
transition. Positive full scale is defined as a level 1 LSB and
0.5 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
straight line reference. The error is then expressed as a
percentage of the 2 V ADC full-scale signal. The input signal is
appropriately gained up to fill the ADC’s full-scale range.
Tot a l O ut p ut Noi s e
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship
n
1 LSB = (ADC full scale/2
where n is the bit resolution of the ADC. For the AD9949,
1 LSB is approximately 0.488 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
codes)
Rev. B | Page 8 of 36
Page 9
AD9949
EQUIVALENT INPUT/OUTPUT CIRCUITS
DATA
CLI
AVDD
R
AVSS
Figure 3. CCDIN (Pin 27)
AVDD
330Ω
25kΩ
+
1.4V
AVSS
Figure 4. CLI (Pin 25)
DVSS
AVSS
03751-004
03751-005
DRVDD
DVDD
330Ω
DVSS
03751-007
Figure 6. Digital Inputs (Pins 31 to 35, 38)
HVDD OR RGVDD
DATA
ENABLEDOUT
HVSS OR RGVSS
03751-008
Figure 7. H1 to H4 and RG (Pins 14 to 15, 18 to 19, 21)
THREE-STATEDOUT
DVSSDRVSS
Figure 5. Data Outputs D0 to D11 (Pins 1 to 4, 7 to 13, 40)
03751-006
Rev. B | Page 9 of 36
Page 10
AD9949
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
400
0.5
0
DNL (LSB)
–0.5
–1.0
ADC OUTPUT CODE
400005001000 1500 2000 2500 3000 3500
03751-009
Figure 8. Typical D NL
48
40
32
24
16
OUTPUT NOISE (LSB)
8
350
300
VDD = 3.3V
250
POWER DISSIPATION (mW)
200
150
= 3.0V
V
DD
= 2.7V
V
DD
SAMPLE RATE (MHz)
36182430
03751-011
Figure 10. Power Curves
0
VGA GAIN CODE (LSB)
10000200400600800
03751-010
Figure 9. Output Noise vs. VGA Gain
Rev. B | Page 10 of 36
Page 11
AD9949
SYSTEM OVERVIEW
CCD
V-DRIVER
H1 TO H4, RG
CCDIN
Figure 11. Typical Application
V1 TO Vx, VSG1 TO VSGx, SUBCK
AD9949
INTEGRATED
AFE + TD
SERIAL
INTERFACE
DOUT
HD, VD
CLI
DIGITAL IMAGE
PROCESSING
ASIC
Figure 11 shows the typical system application diagram for the
AD9949. The CCD output is processed by the AD9949’s AFE
circuitry, which consists of a CDS, a PxGA, a VGA, a black level
clamp, and an ADC. The digitized pixel information is sent to
the digital image processor chip where all postprocessing and
compression occurs. To operate the CCD, CCD timing
parameters are programmed into the AD9949 from the image
processor through the 3-wire serial interface. From the system
master clock, CLI, provided by the image processor, the
AD9949 generates the high speed CCD clocks and all internal
AFE clocks. All AD9949 clocks are synchronized with VD and
HD. The AD9949’s horizontal pulses (CLPOB, PBLK, and
HBLK) are programmed and generated internally.
The H-drivers for H1 to H4 and RG are included in the
AD9949, allowing these clocks to be directly connected to the
CCD. The H-drive voltage of 3 V is supported in the AD9949.
Figure 12 shows the horizontal and vertical counter dimensions
for the AD9949. All internal horizontal clocking is programmed
using these dimensions to specify line and pixel locations.
H-COUNTER BEHAVIOR
When the maximum horizontal count of 4096 pixels is
exceeded, the H-counter in the AD9949 rolls over to zero and
continues counting. It is, therefore, recommended that the
maximum counter value not be exceeded.
However, the newer AD9949A version behaves differently. In
the AD9949A, the internal H-counter holds at its maximum
count of 4095 instead of rolling over. This feature allows the
AD9949A to be used in applications containing a line length
greater than 4096 pixels. Although no programmable values for
03751-012
the horizontal blanking or clamping are available beyond pixel
4095, the H, RG, and AFE clocking continues to operate,
sampling the remaining pixels on the line.
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
03751-013
Figure 12. Vertical and Horizontal Counters
VD
HD
CLI
MAX VD LENGTH IS 4095 LINES
MAX HD LENGTH IS 4095 PIXELS
Figure 13. Maximum VD/HD Dimensions
Rev. B | Page 11 of 36
03751-014
Page 12
AD9949
A
SERIAL INTERFACE TIMING
The AD9949’s internal registers are accessed through a 3-wire
serial interface. Each register consists of an 8-bit address and a
24-bit data-word. Both the 8-bit address and 24-bit data-word
are written starting with the LSB. To write to each register, a
32-bit operation is required, as shown in Figure 14. Although
many registers are less than 24 bits wide, all 24 bits must be
written for each register. If the register is only 16 bits wide, then
the upper eight bits may be filled with zeros during the serial
write operation. If fewer than 24 bits are written, the register
will not be updated with new data.
Figure 15 shows a more efficient way to write to the registers by
using the AD9949’s address auto-increment capability. Using
this method, the lowest desired address is written first, followed
by multiple 24-bit data-words. Each new 24-bit data-word is
written automatically to the next highest register address. By
eliminating the need to write each 8-bit address, faster register
loading is achieved. Address auto-increment may be used starting with any register location and may be used to write to as few
as two registers or as many as the entire register space.
SDAT
SDATA
8-BIT ADDRESS
A0A1 A2A4 A5 A6 A7
SCK
SL
VD
132234567891011123031
t
LS
A3
t
DS
D1 D2 D3D21 D22 D23
D0
t
DH
24-BIT DATA
...
...
...
...
t
LH
SL UPDATEDVD/HD UPDATED
...
HD
NOTES
1. INDIVIDUAL SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS <24 BITS, THEN DON’T CARE BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.
4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
Figure 14. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
A0 A1A2A4A5 A6 A7D0 D1D22 D23
A3
...
DATA FOR NEXT
REGISTER ADDRESS
D0 D1D22 D23
...
03751-015
D0
...
D2D1
SCK
SL
132234567891031
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
...
...
...
34335655
...
585759
...
...
03751-016
Figure 15. Continuous Serial Write Operation
Rev. B | Page 12 of 36
Page 13
AD9949
COMPLETE REGISTER LISTING
1. All addresses and default values are expressed in
hexadecimal.
2. All registers are VD/HD updated as shown in Figure 14,
except for the registers indicated in Table 7, which are SL
updated.
Table 7. SL Updated Registers
Register Description
OPRMODE AFE Operation Modes
CTLMODE AFE Control Modes
SW_RESET Software Reset Bit
TGCORE _RSTB Reset Bar Signal for Internal TG Core
PREVENTUPDATE Prevents Update of Registers
VDHDEDGE VD/HD Active Edge
FIELDVAL Resets Internal Field Pulse
HBLKRETIME Retimes the HBLK to Internal Clock
CLPBLKOUT CLP/BLK Output Pin Select
CLPBLKEN Enables CLP/BLK Output Pin
H1CONTROL H1/H2 Polarity/Edge Control
RGCONTROL RG Polarity/Edge Control
DRVCONTROL RG and H1 to H4 Drive Current
SAMPCONTROL SHP/SHD Sampling Edge Control
DOUTPHASE Data Output Phase Adjustment
Rev. B | Page 13 of 36
Page 14
AD9949
Table 8. AFE Register Map
Data Bit
Address
00 [11:0] 4 OPRMODE AFE Operation Modes. (See Table 14.)
01 [9:0] 0 VGAGAIN VGA Gain.
02 [7:0] 80 CLAMP LEVEL Optical Black Clamp Level.
03 [11:0] 4 CTLMODE AFE Control Modes. (See Table 15.)
04 [17:0] 0 PxGA GAIN01 PxGA Gain Registers for Color 0 [8:0] and Color 1 [17:9].
05 [17:0] 0 PxGA GAIN23 PxGA Gain Registers for Color 2 [8:0] and Color 3 [17:9].
Content
Table 9. Miscellaneous Register Map
Data Bit
Address
10 [0] 0 SW_RST
11 [0] 0 OUT_CONTROL
12 [0] 0 TGCORE_RSTB
13 [11:0] 0 UPDATE
14 [0] 0 PREVENTUPDATE
15 [0] 0 VDHDEDGE
16 [1:0] 0 FIELDVAL
17 [0] 0 HBLKRETIME
18 [1:0] 0 CLPBLKOUT
19 [0] 1 CLPBLKEN
1A [0] 0 TEST MODE
Content
Default Value Name Description
Default Value Name Description
Software Reset.
1 = Reset all registers to default, then self-clear back to 0.
20 [3:0] F CLPOBPOL Start Polarities for CLPOB Sequences 0, 1, 2, and 3.
21 [23:0] FFFFFF CLPOBTOG_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
22 [23:0] FFFFFF CLPOBTOG_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
23 [23:0] FFFFFF CLPOBTOG_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
24 [23:0]
25 [7:0] 0 CLPOBSPTR CLPOB Sequence Pointers for Region 0 [1:0], 1 [3:2], 2[5:4], 3[7:6].
26 [11:0] FFF CLPOBSCP1 CLPOB Sequence-Change Position 1.
27 [11:0] FFF CLPOBSCP2 CLPOB Sequence-Change Position 2.
28 [11:0] FFF CLPOBSCP3 CLPOB Sequence-Change Position 3.
Content
Table 11. PBLK Register Map
Data Bit Con-
Address
30 [3:0] F PBLKPOL Start Polarities for PBLK Sequences 0, 1, 2, and 3.
31 [23:0] FFFFFF PBLKTOG_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
32 [23:0] FFFFFF PBLKTOG_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
33 [23:0] FFFFFF PBLKTOG_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
34 [23:0]
35 [7:0] 0 PBLKSPTR PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].
36 [11:0] FFF PBLKSCP1 PBLK Sequence-Change Position 1.
37 [11:0] FFF PBLKSCP2 PBLK Sequence-Change Position 2.
38 [11:0] FFF PBLKSCP3 PBLK Sequence-Change Position 3.
tent
Default Value
(Hex)
FFFFFF
0
Default Value
(Hex)
FFFFFF
0
Name Description
CLPOBTOG_3
CLPOBSCP0
Name Description
PBLKTOG_3
PBLKSCP0
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
CLPOB Sequence-Change Position 0 (Hard-Coded to 0).
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
PBLK Sequence-Change Position 0 (Hard-Coded to 0).
Rev. B | Page 15 of 36
Page 16
AD9949
Table 12. HBLK Register Map
Data Bit
Address
40 [0] 0 HBLKDIR
41 [0] 0 HBLKPOL
42 [0] 1 HBLKEXTMASK
43 [3:0] F HBLKMASK
44 [23:0] FFFFFF HBLKTOG12_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
45 [23:0] FFFFFF HBLKTOG34_0 Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
46 [23:0] FFFFFF HBLKTOG56_0 Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
47 [23:0] FFFFFF HBLKTOG12_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
48 [23:0] FFFFFF HBLKTOG34_1 Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
49 [23:0] FFFFFF HBLKTOG56_1 Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
4A [23:0] FFFFFF HBLKTOG12_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
4B [23:0] FFFFFF HBLKTOG34_2 Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
4C [23:0] FFFFFF HBLKTOG56_2 Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
4D [23:0] FFFFFF HBLKTOG12_3 Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
4E [23:0] FFFFFF HBLKTOG34_3 Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
4F [23:0]
50 [7:0] 0 HBLKSPTR HBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].
51 [11:0] FFF HBLKSCP1 HBLK Sequence-Change Position 1.
52 [11:0] FFF HBLKSCP2 HBLK Sequence-Change Position 2.
53 [11:0] FFF HBLKSCP3 HBLK Sequence-Change Position 3.
0 = Data Outputs Are Driven.
1 = Data Outputs Are Three-Stated.
0 = Latch Data Outputs with DOUT Phase.
1 = Output Latch Transparent.
0 = Binary Encode Data Outputs.
1 = Gray Encode Data Outputs.
Rev. B | Page 17 of 36
Page 18
AD9949
PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9949 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for gener-
ating the timing used for both the CCD and the AFE: the reset
gate (RG), horizontal drivers (H1 to H4), and the SHP/SHD
sample clocks. A unique architecture makes it routine for the
system designer to optimize image quality by providing precise
control over the horizontal CCD readout and the AFE correlated double sampling.
TIMING RESOLUTION
The Precision Timing core uses a 1× master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 16 illustrates how the internal timing
core divides the master clock period into 48 steps or edge
positions. Therefore, the edge resolution of the Precision Timing
core is (t
refer to the Applications Information section.
/48). For more information on using the CLI input,
CLI
POSITION
CLI
1 PIXEL
PERIOD
t
CLIDLY
P[0]P[48] = P[0]P[12]P[24]P[36]
...
HIGH SPEED CLOCK PROGRAMMABILITY
Figure 17 shows how the high speed clocks, RG, H1 to H4,
SHP, and SHD, are generated. The RG pulse has programmable rising
and falling edges and may be inverted using the
polarity control. The horizontal clocks H1 and H3 have
programmable r
Th
e
H2 and H4 clocks are always inverses of H1 and H3, re-
ising and falling edges and polarity control.
spectively. Table 16 summarizes the high speed timing registers
and their parameters.
Each edge location setting is 6 bits wide, but only 48 valid edge
locations are available. Therefore, the register values are
mapped into four quadrants, with each quadrant containing
12 edge locations. Table 17 shows the correct register values for
the corresponding edge locations.
...
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
Figure 16. High Speed Clock Resolution from CLI Master Clock Input
3
CCD SIGNAL
RG
H1/H3
H2/H4
12
56
PROGRAMMABLE CLOCK POSITIONS:
1. RG RISING EDGE.
2. RG FALLING EDGE.
3. SHP SAMPLE LOCATION.
4. SHD SAMPLE LOCATION.
5. H1/H3 RISING EDGE POSITION6. H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3).
Figure 17. High Speed Clock Programmable Locations
4
t
CLIDLY
= 6 ns TYP).
03751-017
03751-018
Rev. B | Page 18 of 36
Page 19
AD9949
Table 16. H1CONTROL, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters
Parameter Length Range Description
Polarity 1b High/Low Polarity Control for H1/H3 and RG (0 = No Inversion, 1 = Inversion).
Positive Edge 6b 0 to 47 Edge Location Positive Edge Location for H1/H3 and RG.
Negative Edge 6b 0 to 47 Edge Location Negative Edge Location for H1/H3 and RG.
Sample Location 6b 0 to 47 Sample Location Sampling Location for SHP and SHD.
Drive Control 3b 0 to 7 Current Steps Drive Current for H1 to H4 and RG Outputs, 0 to 7 Steps of 4.1 mA Each.
DOUT Phase 6b 0 to 47 Edge Location Phase Location of Data Outputs with Respect to Pixel Period.
Table 17. Precision Timing Edge Locations
Quadrant Edge Location (Decimal) Register Value (Decimal) Register Value (Binary)
I 0 to 11 0 to 11 000000 to 001011
II 12 to 23 16 to 27 010000 to 011011
III 24 to 35 32 to 43 100000 to 101011
IV 36 to 47 48 to 59 110000 to 111011
H-DRIVER AND RG OUTPUTS
In addition to the programmable timing positions, the AD9949 features on-chip output drivers for the RG and H1 to H4 outputs. These
drivers are powerful enough to directly drive the CCD inputs. The H-driver and RG driver current can be adjusted for optimum rise/fall
time into a particular load by using the DRVCONTROL register (Address 0×62). The DRVCONTROL register is divided into five different 3-bit values, each one being adjustable in 4.1 mA increments. The minimum setting of 0 is equal to OFF or three-state, and the maximum setting of 7 is equal to 30.1 mA.
As shown in Figure 18, the H2/H4 outputs are inverses of H1/H3. The internal propagation delay resulting from the signal inversion is
less than l ns, which is significantly less than the typical rise time driving the CCD load. This results in a H1/H2 crossover voltage at approximately 50% of the output swing. The crossover voltage is not programmable.
DIGITAL DATA OUTPUTS
The AD9949 data output phase is programmable using the DOUTPHASE register (Address 0×64). Any edge from 0 to 47 may be programmed, as shown in Figure 19. The pipeline delay for the digital data output is shown in Figure 20.
H1/H3
H2/H4
t
RISE
t
<<
t
PD
RISE
FIXED CROSSOVER VOLTAGE
Figure 18. H-Clock Inverse Phase Relationship
t
PD
H1/H3H2/H4
03751-019
Rev. B | Page 19 of 36
Page 20
AD9949
CLI
CCDIN
SHD
(INTERNAL)
DOUT
1 PIXEL PERIOD
CLI
DOUT
P[0]P[48] = P[0]
t
OD
NOTES
1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
2. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
N– 1
N
Figure 20. Pipeline Delay for Digital Data Output
N + 1
03751-020
03751-021
Rev. B | Page 20 of 36
Page 21
AD9949
HORIZONTAL CLAMPING AND BLANKING
The AD9949’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual
sequences are defined for each signal, which are then organized
into multiple regions during image readout. This allows the
dark pixel clamping and blanking patterns to be changed at
each stage of the readout to accommodate different image
transfer timing and high speed line shifts.
INDIVIDUAL CLPOB AND PBLK SEQUENCES
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 21. These two signals are independently
programmed using the parameters shown in Table 18. The start
polarity, first toggle position, and second toggle position are
fully programmable for each signal. The CLPOB and PBLK
HD
CLPOB
1
PBLK
PROGRAMMABLE SETTINGS:
1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).
2. FIRST TOGGLE POSITION.
3. SECOND TOGGLE POSITION.
32
ACTIVE
Figure 21. Clamp and Preblank Pulse Placement
signals are active low and should be programmed accordingly.
Up to four individual sequences can be created for each signal.
INDIVIDUAL HBLK SEQUENCES
The HBLK programmable timing shown in Figure 22 is similar
to CLPOB and PBLK. However, there is no start polarity
control.
Only the toggle positions are used to designate the
start and the stop positions of the blanking period. Additionally,
there is a polarity control, HBLKMASK, which designates the
polarity of the horizontal clock signals H1 to H4 during the
blanking period. Setting HBLKMASK high sets H1 = H3 = low
and H2 = H4 = high during the blanking,
as shown in Figure 23.
Up to four individual sequences are available for HBLK.
Table 18. CLPOB and PBLK Individual Sequence Parameters
Parameter Length Range Description
Polarity 1b High/Low Starting Polarity of Clamp and PBLK Pulses for Sequences 0 to 3.
Toggle Position 1 12b 0 to 4095 Pixel Location First Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 2 12b 0 to 4095 Pixel Location Second Toggle Position within the Line for Sequences 0 to 3.
Table 19. HBLK Individual Sequence Parameters
Parameter Length Range Description
HBLKMASK 1b High/Low Masking Polarity for H1 for Sequences 0 to 3 (0 = H1 Low, 1 = H1 High).
Toggle Position 1 12b 0 to 4095 Pixel Location First Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 2 12b 0 to 4095 Pixel Location Second Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 3 12b 0 to 4095 Pixel Location Third Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 4 12b 0 to 4095 Pixel Location Fourth Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 5 12b 0 to 4095 Pixel Location Fifth Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 6 12b 0 to 4095 Pixel Location Sixth Toggle Position within the Line for Sequences 0 to 3.
...
03751-023
Rev. B | Page 21 of 36
Page 22
AD9949
HD
...
HBLK
H1/H3
H1/H3
H2/H4
HBLK
H1/H3
H2/H4
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).
...
...
Figure 23. HBLK Masking Control
TOG1
TOG2
TOG3
TOG4
TOG5
TOG6
...
03751-024
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
03751-025
Figure 24. Generating Special HBLK Patterns
Table 20. Horizontal Sequence Control Parameters for CLPOB, PBLK, and HBLK
Register Length Range Description
SCP 12b 0 to 4095 Line Number CLOB/PBLK/HBLK SCP to Define Horizontal Regions 0 to 3.
SPTR 2b 0 to 3 Sequence Number Sequence Pointer for Horizontal Regions 0 to 3.
Rev. B | Page 22 of 36
Page 23
AD9949
GENERATING SPECIAL HBLK PATTERNS
Six toggle positions are available for HBLK. Normally, only two
of the toggle positions are used to generate the standard HBLK
interval. However, the additional toggle positions may be used
to generate special HBLK patterns, as shown in Figure 24. The
pattern in this example uses all six toggle positions to generate
two extra groups of pulses during the HBLK interval. By
changing the toggle positions, different patterns can be created.
CLPOB, PBLK, and HBLK each have a separate set of SCPs. For
example, CLPOBSCP1 defines Region 0 for CLPOB, and in that
region any of the four individual CLPOB sequences may be
selected with the CLPOBSPTR register. The next SCP defines a
new region and in that region, each signal can be assigned to a
different individual sequence. The sequence control registers
are summarized in Table 20.
HORIZONTAL SEQUENCE CONTROL
The AD9949 uses sequence change positions (SCP) and
sequence pointers (SPTR) to organize the individual horizontal
sequences. Up to four SCPs are available to divide the readout
into four separate regions, as shown in Figure 25. The SCP0 is
always hard-coded to Line 0, and SCP1 to SCP3 are register
programmable. During each region bounded by the SCP, the
SPTR registers designate which sequence is used by each signal.
SEQUENCE CHANGE OF POSITION 0
SEQUENCE CHANGE OF POSITION 1
SEQUENCE CHANGE OF POSITION 2
SEQUENCE CHANGE OF POSITION 3
(V-COUNTER = 0)
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE
PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
Figure 25. Clamp and Blanking Sequence Flexibility
SINGLE FIELD (1 VD INTERVAL)
EXTERNAL HBLK SIGNAL
The AD9949 can also be used with an external HBLK signal.
Setting the HBLKDIR register (Address 0×40) to high disables
the internal HBLK signal generation. The polarity of the external signal is specified using the HBLKPOL register, and the
masking polarity of H1 is specified using the HBLKMASK
register. Table 21 summarizes the register values when using an
external HBLK signal.
CLAMP AND PBLK SEQUENCE REGION 0
CLAMP AND PBLK SEQUENCE REGION 1
CLAMP AND PBLK SEQUENCE REGION 2
CLAMP AND PBLK SEQUENCE REGION 3
03751-026
Table 21. External HBLK Register Parameters
Register Length Range Description
HBLKDIR 1b High/Low
Specifies HBLK Internally Generated or Externally Supplied.
1 = External.
HBLKPOL 1b High/Low
External HBLK Active Polarity.
0 = Active Low.
1 = Active High.
The H-Counter reset occurs seven CLI cycles following the HD falling edge. The PxGA steering is synchronized with the reset of the
internal H-Counter (see Figure 26).
As mentioned in the H-Counter Behavior section, the AD9949 H-counter rolls over to zero and continues counting when the maximum
counter length is exceeded. The newer AD9949A product does not roll over but holds at its maximum value until the next HD rising edge
occurs.
VD
HD
CLI
H-COUNTER
(PIXEL COUNTER)
PxGA GAIN
REGISTER
H-COUNTER
RESET
XXXXXXX
X
X
XXXXXXX
NOTES
1. INTERNAL H-COUNTER IS RESET 7 CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE IS COINCIDENT WITH HD FALLING EDGE.
3. PxGA STEERING IS SYNCRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
X
X
012345678910111214150123
X
X
0001121110031100
02
Figure 26. H-Counter Synchronization
3
03751-027
Rev. B | Page 24 of 36
Page 25
AD9949
POWER-UP PROCEDURE
RECOMMENDED POWER-UP SEQUENCE
When the AD9949 is powered up, the following sequence is
recommended (refer to Figure 27 for each step):
1. Turn on the power supplies for the AD9949.
2. Apply the master clock input, CLI, VD, and HD.
3. Although the AD9949 contains an on-chip, power-on reset,
a software reset of the internal registers is recommended.
Write a 1 to the SW_RST register (Address 0×10), which
resets the internal registers to their default values. This bit
is self-clearing and automatically resets back to 0.
4. The Precision Timing core must be reset by writing a 0 to
the TGCORE_RSTB register (Address 0×12) followed by
writing a l to the TGCORE_RSTB register. This starts the
internal timing core operation.
5. Write a 1 to the PREVENTUPDATE register (Address
0×14). This prevents the updating of the serial register
data.
6. Write to the desired registers to configure high speed
timing and horizontal timing.
7. Write a 1 to the OUT_CONTROL register (Address 0×11).
This allows the outputs to become active after the next
VD/HD rising edge.
8. Write a 0 to the PREVENTUPDATE register (Address
0×14). This allows the serial information to be updated at
next VD/HD falling edge.
9. The next VD/HD falling edge allows register updates to
occur, including OUT_CONTROL, which enables all clock
outputs.
VDD
(INPUT)
(INPUT)
SERIAL
WRITES
(OUTPUT)
(OUTPUT)
DIGITAL
OUTPUTS
CLI
VD
HD
1
2
t
PWR
345678
...
2
9
ODD FIELDEVEN FIELD
1H
...
H2/H4
H1/H3, RG
CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS
UPDATED AT VD/HD EDGE
Figure 27. Recommended Power-Up Sequence
1V
...
...
03751-028
Rev. B | Page 25 of 36
Page 26
AD9949
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9949 signal processing chain is shown in Figure 28.
Each processing step is essential in achieving a high quality
image from the raw CCD pixel data.
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V to be compatible with the 3 V supply
voltage of the AD9949.
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 17 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and the CCD signal level, respectively. The placement of
the SHP and SHD sampling edges is determined by the setting
of the SAMPCONTROL register located at Address 0×63.
Placement of these two clock signals is critical in achieving the
best performance from the CCD.
The gain in the CDS is fixed at 0 dB by default. Using Bits D10
and D11 in the AFE operation register, the gain may be reduced
to −2 dB or −4 dB. This allows the AD9949 to accept an input
signal of greater than 1 V p-p. See Table 14 for register details.
Table 22. Adjustable CDS Gain
Operation Register Bits
D11 D10 CDS Gain Max CDS Input
0 0 0 dB 1.0 V p-p
0 1 −2 dB 1.2 V p-p
1 0 −4 dB 1.6 V p-p
1 1 0 dB 1.0 V p-p
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA has the capability to multiplex its gain value
on a pixel-to-pixel basis (see Figure 29). This allows lower
output color pixels to be gained up to match higher output color
pixels. Also, the PxGA may be used to adjust the colors for
white balance, reducing the amount of digital processing that
needed. The four different gain values are switched according
is
to the color steering circuitry. Three different color steering
modes for different types of CCD color filter arrays are
programmable in the AFE CTLMODE register at Address 0×03
(see Figure 33 to Figure 35 for timing examples). For example,
progressive steering mode accommodates the popular Bayer
arrangement of red, green, and blue filters (see Figure 30).
1.0µF
CCDIN
DC RESTORE
1.5V
SHP
0dB, –2dB, –4dB
SHD
CDS
SHP SHD
0dB ~ 18dB
PxGA
PxGA GAIN
REGISTERS
DOUT
PHASECLPOB PBLK
PRECISION
TIMING
GENERATION
Figure 28. Analog Front End Functional Block Diagram
6dB ~ 42dB
VGA
VGA GAIN
REGISTER
V-H
TIMING
GENERATION
DAC
1.0µF 1.0µF
1.0V 2.0V
INTERNAL
VREF
12-BIT
ADC
OPTICAL BLACK
CLAMP
DIGITAL
FILTER
REFTREFB
2V FULL SCALE
CLAMP LEVEL
REGISTER
CLPOB
8
AD9949
OUTPUT
DATA
LATCH
PBLK
DOUT
PHASE
12
DOUT
03751-029
Rev. B | Page 26 of 36
Page 27
AD9949
HD
SHP/SHD
VD
8
PxGA
COLOR
STEERING
CONTROL
2
4:1
4:1
MUX
MUX
VGACDS
PxGA STEERING
3
SELECTION
GAIN0
GAIN1
GAIN2
GAIN3
MODE
PxGA GAIN
REGISTERS
Figure 29. PxGA Block Diagram
CCD: PROGRESSIVE BAYER
Gb
Gb
R
R
RGrGr
GbB
B
R
Gr
GbB
B
LINE0GAIN0, GAIN1, GAIN0, GAIN1, ...
LINE1
Gr
LINE2
COLOR STEERING MODE:
PROGRESSIVE
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
Figure 30. CCD Color Filter Example—Progressive Scan
The same Bayer pattern can also be interlaced, and the
interlaced mode should be used with this type of CCD (see
Figure 31). The color steering performs the proper multiplexing
of the R, G, and B gain values (loaded into the PxGA gain
registers) and is synchronized by the user with vertical (VD)
and horizontal (HD) sync pulses. For timing information,
see Figure 34.
CCD: INTERLACED BAYER
EVEN FIELD
RRGrGr
RRGrGr
RRGrGr
RRGrGr
COLOR STEERING MODE:
INTERLACED
LINE0GAIN0, GAIN1, GAIN0, GAIN1, ...
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
CONTROL
REGISTER
BITS D0 TO D1
03751-031
03751-030
A third type of readout uses the Bayer pattern divided into three
different readout fields. The 3-field mode should be used with
this type of CCD (see Figure 32). The color steering performs
the proper multiplexing of the R, G, and B gain values (loaded
into the PxGA gain registers) and is synchronized by the user
with vertical (VD) and horizontal (HD) sync pulses. For timing
information, see Figure 35.
CCD: 3-FIELD READOUT
FIRST FIELD
RGr
R
Gb
R
Gb
SECOND FIELD
Gb
R
Gb
R
THIRD FIELD
R
Gb
R
GbGbB
Gr
GbB
B
RGr
Gr
GbB
B
GbB
B
RGr
Gr
GbB
B
RGr
Gr
RGr
Gr
GbB
B
RGr
Gr
B
Figure 32. CCD Color Filter Example—Three-Field Readout
COLOR STEERING MODE:
THREE FIELD
LINE0GAIN0, GAIN1, GAIN0, GAIN1, ...
LINE1
LINE2
LINE0GAIN2, GAIN3, GAIN2, GAIN3, ...
LINE1
LINE2
LINE0GAIN0, GAIN1, GAIN0, GAIN1, ...
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
03751-033
ODD FIELD
GbGbBB
GbGbBB
GbGbBB
GbGbBB
Figure 31. CCD Color Filter Example—Interlaced Readout
LINE0GAIN2, GAIN3, GAIN2, GAIN3, ...
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN2, GAIN3, GAIN2, GAIN3, ...
03751-032
Rev. B | Page 27 of 36
Page 28
AD9949
FIELDVAL
VD
HD
PxGA GAIN
REGISTER
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES.
3. FIELDVAL IS ALWAYS RESET TO 0 ON VD FALLING EDGES.
FIELDVAL = 0
110XX
0
2203311
FIELDVAL = 0
02203311110000
Figure 33. PxGA Color Steering—Progressive Mode
FIELDVAL
VD
HD
PxGA GAIN
REGISTER
NOTES
1. FIELDVAL = 0 (START OF FIRST FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
2. FIELDVAL = 1 (START OF SECOND FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 2323 LINE.
3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER 0 (FIELDVAL = 0) OR 2 (FIELDVAL = 1).
4. FIELDVAL WILL TOGGLE BETWEEN 0 AND 1 ON EACH VD FALLING EDGE.
FIELDVAL = 0
0
110XX
0031122
FIELDVAL = 1FIELDVAL = 0
311000033221
Figure 34. PxGA Color Steering—Interlaced Mode
03751-034
1
03751-035
FIELDVAL
VD
HD
PxGA GAIN
REGISTER
FIELDVAL = 0
110XX
0
NOTES
1. FIELDVAL = 0 (START OF FIRST FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
2. FIELDVAL = 1 (START OF SECOND FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 2323 LINE.
3. FIELDVAL = 2 (START OF THIRD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
4. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES.
5. FIELDVAL WILL INCREMENT AT EACH VD FALLING EDGE, REPEATING THE 0...1...2...0...1...2 PATTERN.
2233322
FIELDVAL = 1FIELDVAL = 2
311002200113
Figure 35. PxGA Color Steering—Three-Field Mode
Rev. B | Page 28 of 36
3
03751-036
Page 29
AD9949
The PxGA gain for each of the four channels is variable from
0 dB to 18 dB in 512 steps, specified using the PxGA GAIN01
and PxGA GAIN23 registers. The PxGA gain curve is shown in
Figure 36. The PxGA GAIN01 register contains nine bits each
for PxGA Gain0 and Gain1, and the PxGA GAIN23 register
contains nine bits each for PxGA Gain2 and Gain3.
18
15
12
9
PxGA GAIN (dB)
6
VGA GAIN (dB)
42
36
30
24
18
12
0
VGA GAIN REGISTER CODE
Figure 37. VGA Gain Curve (PxGA Not Included)
10230127255383511639767895
03751-038
3
0
0
64128192256320384448511
PxGA GAIN REGISTER CODE
Figure 36. PxGA Gain Curve
03751-037
VARIABLE GAIN AMPLIFIER
The VGA stage provides a gain range of 6 dB to 42 dB, programmable with 10-bit resolution through the serial digital
interface. The minimum gain of 6 dB is needed to match a 1 V
input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems, the equivalent gain range is 0
dB to 36 dB.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain can be calculated for any gain register value by
using the equation
Gain (db) = (0.0351 × Code) + 6 dB
where the code range is 0 to 1023.
There is a restriction on the maximum amount of gain that can
be applied to the signal. The PxGA can add as much as 18 dB,
and the VGA is capable of providing up to 42 dB. However, the
maximum total gain from the PxGA and VGA is restricted to
42 dB. If the registers are programmed to specify a total gain
higher than 42 dB, the total gain is clipped at 42 dB.
ADC
The AD9949 uses a high performance ADC architecture,
optimized for high speed and low power. DNL performance is
typically better than 0.5 LSB. The ADC uses a 2 V input range.
See Figure 9 and Figure 10 for typical linearity and noise
performance plots for the AD9949.
OPTICAL BLACK CLAMP
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixe
on each line, the ADC output is compared with a fixed
terval
black level reference, selected by the user in the clamp level reg
l in-
ister. The value can be programmed between 0 LSB and 255 LSB
in 256 steps. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
DAC. Normally, the optical black clamp loop is turned on once
horizontal line, but this loop can be updated more slowly to
per
suit a particular application. If external digital clamping is used
during the postprocessing, the AD9949 optical black clamping
may be disabled using Bit D2 in the OPRMODE register. When
the loop is disabled, the clamp level register may still be used to
provide programmable offset adjustment
.
The CLPOB pulse should be placed during the CCD’s optical
black pixels. It is recommended that the CLPOB pulse duration
be at least 20 pixels wide to minimize clamp noise. Shorter pulse
widths may be used, but clamp noise may increase and the
ability to track low frequency variations in the black level will
be reduced. See the Horizontal Clamping and Blanking and
Applications Information sections for timing examples.
DIGITAL DATA OUTPUTS
The AD9949 digital output data is latched using the DOUT
phase register value, as shown in Figure 28. Output data timing
is shown in Figure 19 and Figure 20. It is also possible to leave
the output latches transparent, so that the data outputs are valid
immediately from the ADC. Programming the AFE control
register Bit D4 to a 1 sets the output latches transparent. The
data outputs can also be disabled (three-stated) by setting the
AFE control register Bit D3 to a 1.
The data output coding is normally straight binary, but the
coding may be changed to gray coding by setting the AFE
control register Bit D5 to a 1.
Rev. B | Page 29 of 36
Page 30
AD9949
S
APPLICATIONS INFORMATION
CIRCUIT CONFIGURATION
The AD9949 recommended circuit configuration is shown in
Figure 38. Achieving good image quality from the AD9949
requires careful attention to PCB layout. All signals should be
routed to maintain low noise performance. The CCD output
signal should be directly routed to Pin 27 through a 0.1 µF
capacitor. The master clock CLI should be carefully routed to
Pin 25 to minimize interference with the CCDIN, REFT, and
REFB signals.
The digital outputs and clock inputs are located on Pins 1 to 13
and Pins 31 to 40 and should be connected to the digital ASIC
away from the analog and CCD clock signals. Placing series
resistors close to the digital output pins may help to reduce
digital code transition noise. If the digital outputs must drive a
load larger than 20 pF, buffering is recommended to minimize
additional noise. If the digital ASIC can accept gray code, the
AD9949’s outputs can be selected to output data in gray code
format using the control register Bit D5. Gray coding helps reduce
potential digital transition noise compared with binary coding.
The H1–H4 and RG traces should have low inductance to avoid
excessive distortion of the signals. Heavier traces are recommended because of the large transient current demand on
H1–H4 from the capacitive load of the CCD. If possible,
physically locating the AD9949 closer to the CCD will reduce
the inductance on these lines. As always, the routing path
should be as direct as possible from the AD9949 to the CCD.
GROUNDING AND DECOUPLING
RECOMMENDATIONS
As shown in Figure 38, a single ground plane is recommended
for the AD9949. This ground plane should be as continuous as
possible, particularly around Pins 23 to 30. This ensures that all
analog decoupling capacitors provide the lowest possible
impedance path between the power and bypass pins and their
respective ground pins. All high frequency decoupling
capacitors should be located as close as possible to the package
pins. It is recommended that the exposed paddle on the bottom
of the package be soldered to a large pad, with multiple vias
connecting the pad to the ground plane.
All the supply pins must be decoupled to ground with good
quality, high frequency chip capacitors. There should also be a
4.7 µF or larger bypass capacitor for each main supply—AVDD,
RGVDD, HVDD, and DRVDD—although this is not necessary
for each individual pin. In most applications, it is easier to share
the supply for RGVDD and HVDD, which may be done as long
as the individual supply pins are separately bypassed. A separate
3 V supply may be used for DRVDD, but this supply pin should
still be decoupled to the same ground plane as the rest of the
chip. A separate ground for DRVSS is not recommended.
The reference bypass pins (REFT, REFB) should be decoupled
to ground as close as possible to their respective pins. The
analog input (CCDIN) capacitor should also be located close to
the pin.
DRIVER
UPPLY
VD/HD/HBLK INPUTS
CLP/BLK OUTPUT
3V
+
4.7µF 0.1µF
OUTPUTS
DATA
3V ANALOG SUPPLY
12
DRVSS
DRVDD
D1
D2
D3
D4
D5
D6
D7
D8
4
D0 (LSB)
CLP/PBLK
40
39
1
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
D9
D10
0.1µF
HBLK37 DVDD36 DVSS35 HD34 VD33 SCK32 SDI31 SL
38
AD9949
TOP VIEW
17
15
H2
16
HVSS
18
H3
HVDD
19
H4
13
14
H1
(MSB) D11
Figure 38. Recommended Circuit Configuration
20
RGVSS
0.1µF
3
30
REFB
29
REFT
28
AVSS
27
CCDIN
26
AVDD
25
CLI
24
TCVDD
23
TCVSS
22
RGVDD
21
RG
SERIAL
INTERFACE
1µF
1µF
0.1µF4.7µF
+
4.7µF
4
0.1µF
0.1µF
+
0.1µF
+
4.7µF
H DRIVER
SUPPLY
H1 TO H4
CCD SIGNAL
MASTER
CLOCK INPUT
3V ANALOG
SUPPLY
RG OUTPUT
RG DRIVER
SUPPLY
03751-039
Rev. B | Page 30 of 36
Page 31
AD9949
DRIVING THE CLI INPUT
The AD9949’s master clock input (CLI) may be used in two
different configurations, depending on the application.
Figure 41 shows a typical dc-coupled input from the master
clock source. When the dc-coupled technique is used, the
master clock signal should be at standard 3 V CMOS logic
levels. As shown in Figure 42, a 1000 pF ac-coupling capacitor
may be used between the clock source and the CLI input. In this
configuration, the CLI input is self-biased to the proper dc voltage level of approximately 1.4 V. When the ac-coupled technique is used, the master clock signal can be as low as ±500 mV
in amplitude.
AD9949
25
CLI
ASIC
MASTER CLOCK
Figure 41. CLI Connection, DC-Coupled
03751-042
AD9949
1819141521
Figure 39. CCD Connections (2 H-Clock)
AD9949
1415181921
Figure 40. CCD Connections (4 H-Clock)
H2RGH3H4H1
H2H1RG
CCD IMAGER
H4RGH1H2H3
H4
H3RG
CCD IMAGER
27
SIGNAL
OUT
SIGNAL
OUT
CCDIN
CCDIN
27
H2 H1
03751-040
03751-041
AD9949
25
CLI
1nF
LPF
ASIC
MASTER CLOCK
Figure 42. CLI Connection, AC-Coupled
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 43 shows an example CCD layout. The horizontal
register contains 28 dummy pixels, which occur on each line
clocked from the CCD. In the vertical direction, there are
10 optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 in the back.
To configure the AD9949 horizontal signals for this CCD, three
sequences can be used. Figure 44 shows the first sequence that
should be used during vertical blanking. During this time, there
are no valid OB pixels from the sensor, so the CLPOB signal is
not used. PBLK may be enabled during this time, because no
valid data is available.
Figure 45 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines in
order to stabilize the clamp loop of the AD9949.
Figure 46 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB signal.
03751-043
Rev. B | Page 31 of 36
Page 32
AD9949
2
SEQUENCE 2 (OPTIONAL)
2 VERTICAL OB LINES
8 DUMMY PIXELS
SEQUENCE 1: VERTICAL BLANKING
CCDIN
SHP
SHD
H1/H3
H2/H4
HBLK
V
4 OB PIXELS
VERTICAL SHIFT
EFFECTIVE IMAGE AREA
H
HORIZONTAL CCD REGISTER
Figure 43. Example CCD Configuration
DUMMYINVALID PIXELSINVALID PIX
48 OB PIXELS
USE SEQUENCE 3
10 VERTICAL OB LINES
USE SEQUENCE 2
03751-044
VERT SHIFT
PBLK
CLPOB
SEQUENCE 2: VERTICAL OPTICAL BLACK LINES
OPTICAL
BLACK
CCDIN
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
VERTICAL SHIFT
Figure 44. Horizontal Sequence During Vertical Blanking
DUMMY
OPTICAL BLACK
Figure 45. Horizontal Sequences During Vertical Optical Black Pixels
VERT SHIFT
03751-045
03751-046
Rev. B | Page 32 of 36
Page 33
AD9949
C
SEQUENCE 3: EFFECTIVE PIXEL LINES
CCDIN
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
LPOB
OPTICAL
BLACK
VERTICAL SHIFT
DUMMY
OB
EFFECTIVE PIXELS
OPTICAL BLACK
VERT SHIFT
03751-047
Figure 46. Horizontal Sequences During Effective Pixels
Rev. B | Page 33 of 36
Page 34
AD9949
OUTLINE DIMENSIONS
PIN 1
INDICATOR
1.00
0.85
0.80
12° MAX
SEATING
PLANE
6.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
5.75
BCS SQ
0.20 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.60 MAX
0.50
BSC
0.50
0.40
0.30
0.08
0.60 MAX
31
30
EXPOSED
(BOTTOM VIEW)
21
20
PAD
4.50
REF
PIN 1
40
11
INDICATOR
1
4.25
4.10 SQ
3.95
10
0.25 MIN
Figure 47. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body
(CP-40)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9949KCP −20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40
AD9949KCPRL −20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40
AD9949KCPZ1 −20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40
AD9949KCPZRL1 −20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40
AD9949AKCPZ
AD9949AKCPZRL
1
Z = PB-free part.
2
The AD9949A is recommended for new designs and supports CCD line lengths > 4096 pixels.
1, 2
−20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40
1, 2
−20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40