Complete 10-Bit and 12-Bit, 25 MHz
FEATURES
25 MSPS correlated double sampler (CDS)
6 dB to 40 dB 10-bit variable gain amplifier (VGA)
Low noise optical black clamp circuit
Preblanking function
10-bit (AD9943), 12-bit (AD9944) 25 MSPS A/D converter
No missing codes guaranteed
3-wire serial digital interface
3 V single-supply operation
Space-saving 32-lead 5 mm × 5 mm LFCSP package
APPLICATIONS
Digital still cameras
Digital video camcorders
PC cameras
Portable CCD imaging devices
CCTV cameras
CCD Signal Processors
AD9943/AD9944
GENERAL DESCRIPTION
The AD9943/AD9944 are complete analog signal processors
for CCD applications. They feature a 25 MHz single-channel
architecture designed to sample and condition the outputs of
interlaced and progressive scan area CCD arrays. The signal
chain for the AD9943/AD9944 consists of a correlated double
sampler (CDS), a digitally controlled variable gain amplifier
(VGA), and a black level clamp. The AD9943 offers 10-bit
ADC resolution, while the AD9944 contains a true 12-bit ADC.
The internal registers are programmed through a 3-wire
serial digital interface. Programmable features include gain
adjustment, black level adjustment, input clock polarity, and
power-down modes. The AD9943/AD9944 operate from a
single 3 V power supply, typically dissipate 79 mW, and are
packaged in space-saving 32-lead LFCSP packages.
CCDIN
AVDD
AVSS
AD9943/AD9944
CDS
REGISTERS
INTERFACE
FUNCTIONAL BLOCK DIAGRAM
REFT
REFB
BAND GAP
REFERENCE
6dB–40dB
VGA
10
CONTROL
DIGITAL
SDATASCKSL
Figure 1. Functional Block Diagram
10-/12-BIT
ADC
CLP
INTERNAL
TIMING
PBLK
10/12
DATACLKSHDSHP
DRVDD
DRVSS
DOUT
CLPOB
DVDD
DVSS
02905-B-001
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9943/AD9944
TABLE OF CONTENTS
AD9943/AD9944 Specifications..................................................... 3
Internal Register Map .................................................................... 13
General Specifications ................................................................. 3
Digital Specifications ................................................................... 3
AD9943 System Specifications ....................................................... 4
AD9944 System Specifications ....................................................... 5
Timing Specifications....................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
AD9943 Pin Configuration and Function Descriptions............. 8
AD9944 Pin Configuration and Function Descriptions............. 9
Te r m in o l o g y .................................................................................... 10
Equivalent Input Circuits .............................................................. 11
Typical Performance Characteristics ...........................................12
REVISION HISTORY
Serial Interface................................................................................ 14
Circuit Description and Operation.............................................. 15
DC Restore .................................................................................. 15
Correlated Double Sampler ...................................................... 15
Optical Black Clamp .................................................................. 15
A/D Converter............................................................................ 16
Variable Gain Amplifier ............................................................ 16
CCD Mode Timing ........................................................................ 17
Applications Information.............................................................. 18
Internal Power-On Reset Circuitry.......................................... 19
Grounding and Decoupling Recommendations .................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format..................................................................Universal
Updated Outline Dimensions....................................................... 20
Changes to Ordering Guide.......................................................... 20
5/03—Data Sheet changed from Rev. 0 to Rev. A
Added AD9944....................................................................Universal
Changes to Features Section............................................................ 1
Updated Ordering Guide................................................................. 5
Replaced TPC 3................................................................................. 9
Added Figure 12.............................................................................. 15
Updated Outline Dimensions....................................................... 16
Rev. B | Page 2 of 20
AD9943/AD9944
AD9943/AD9944 SPECIFICATIONS
GENERAL SPECIFICATIONS
T
to T
MIN
Table 1.
Parameter Min Typ Max Unit
TEMPERATURE RANGE
Operating −20 +85 °C
Storage −65 +150 °C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver 2.7 3.6 V
POWER CONSUMPTION
Normal Operation 79 mW
Power-Down Mode 150 µW
MAXIMUM CLOCK RATE 25 MHz
DIGITAL SPECIFICATIONS
DRVDD = DVDD = 2.7 V, CL = 20 pF, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current I
Low Level Input Current I
Input Capacitance C
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA V
Low Level Output Voltage, IOL = 2 mA V
, AVDD = DVDD = DRVDD = 3 V, f
MAX
= 25 MHz, unless otherwise noted.
SAMP
IH
IL
IH
IL
IN
2.1
10
10
10
0.6 V
V
µA
µA
pF
OH
OL
2.2
0.5 V
V
Rev. B | Page 3 of 20
AD9943/AD9944
AD9943 SYSTEM SPECIFICATIONS
T
to T
MIN
Table 3.
Parameter Min Typ Max Unit Conditions
CDS
Maximum Input Range before Saturation1 1.0 V p-p
Allowable CCD Reset Transient1 500 mV See input waveform in footnote.
Maximum CCD Black Pixel Amplitude1 100 mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC output.
A/D CONVERTER
Resolution 10 Bits
Differential Nonlinearity (DNL) ±0.3 LSB
No Missing Codes Guaranteed
Data Output Coding Straight binary
Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (REFT) 2.0 V
Reference Bottom Voltage (REFB) 1.0 V
SYSTEM PERFORMANCE Specifications include entire signal chain.
Gain Range
Gain Accuracy ±1 dB
Peak Nonlinearity 500 mV Input Signal 0.1 % 12 dB gain applied.
Total Output Noise 0.3 LSB rms AC grounded input, 6 dB gain applied.
Power Supply Rejection (PSR) 50 dB Measured with step change on supply.
1
Input signal characteristics defined as follows:
, AVDD = DVDD = DRVDD = 3 V, f
MAX
= 25 MHz, unless otherwise noted.
SAMP
Minimum Gain 5.3 dB See Figure 13 for VGA gain curve.
Maximum Gain 40 41.5 dB
See Variable Gain Amplifier section for VGA
gain equation.
Minimum Clamp Level 0 LSB
Maximum Clamp Level 63.75 LSB
Low Gain (VGA Code = 0) 5.3 dB
Maximum Gain (VGA Code = 1023) 40 41.5 dB
500mV TYP
RESET TRANSIENT
OPTICAL BLACK PIXEL
100mV TYP
1V TYP
INPUT SIGNAL RANGE
02905-B-002
Rev. B | Page 4 of 20
AD9943/AD9944
AD9944 SYSTEM SPECIFICATIONS
T
to T
MIN
Table 4.
Parameter Min Typ Max Unit Conditions
CDS
Maximum Input Range before Saturation
Allowable CCD Reset Transient1 500 mV See input waveform in footnote.
Maximum CCD Black Pixel Amplitude1 100 mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
Minimum Gain 5.3 dB See Figure 13 for VGA gain curve.
Maximum Gain 40 41.5 dB See Variable Gain Amplifier section for VGA
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC output.
A/D CONVERTER
Resolution 12 Bits
Differential Nonlinearity (DNL) ±0.4 LSB
No Missing Codes Guaranteed
Data Output Coding Straight binary
Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (REFT) 2.0 V
Reference Bottom Voltage (REFB) 1.0 V
SYSTEM PERFORMANCE Specifications include entire signal chain.
Gain Range
Gain Accuracy ±1 dB
Peak Nonlinearity 500 mV Input Signal 0.1 % 12 dB gain applied.
Total Output Noise 0.9 LSB rms AC grounded input, 6 dB gain applied.
Power Supply Rejection (PSR) 50 dB Measured with step change on supply.
1
Input signal characteristics defined as follows:
, AVDD = DVDD = DRVDD = 3 V, f
MAX
1
= 25 MHz, unless otherwise noted.
SAMP
1.0 V p-p
Minimum Clamp Level 0 LSB
Maximum Clamp Level 255 LSB
Low Gain (VGA Code = 0) 5.3 dB
Maximum Gain (VGA Code = 1023) 40 41.5 dB
gain equation.
500mV TYP
RESET TRANSIENT
OPTICAL BLACK PIXEL
100mV TYP
1V TYP
INPUT SIGNAL RANGE
02905-B-002
Rev. B | Page 5 of 20
AD9943/AD9944
TIMING SPECIFICATIONS
CL = 20 pF, f
Table 5.
Parameter Symbol Min Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period t
DATACLK High/Low Pulse Width t
SHP Pulse Width t
SHD Pulse Width t
CLPOB Pulse Width
SHP Rising Edge to SHD Falling Edge t
SHP Rising Edge to SHD Rising Edge t
Internal Clock Delay t
DATA OUTPUTS
Output Delay t
Pipeline Delay 9 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SL to SCK Setup Time t
SCK to SL Hold Time t
SDATA Valid to SCK Rising Edge Setup t
SCK Falling Edge to SDATA Valid Hold t
1
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
= 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11.
SAMP
CONV
ADC
SHP
1
t
SHD
COB
S1
S2
ID
OD
SCLK
LS
LH
DS
DH
40 ns
16 20 ns
10 ns
10 ns
2 20 Pixels
10 ns
16 20 ns
3.0 ns
9.5 ns
10 MHz
10 ns
10 ns
10 ns
10 ns
Rev. B | Page 6 of 20
AD9943/AD9944
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter (With Respect To) Min Max Unit
AVDD (AVSS) −0.3 +3.9 V
DVDD (DVSS) −0.3 +3.9 V
DRVDD (DRVSS) −0.3 +3.9 V
Digital Outputs (DRVSS) −0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK (DVSS) −0.3 DVDD + 0.3 V
CLPOB, PBLK (DVSS) −0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS (AVSS) −0.3 DVDD + 0.3 V
REFT, REFB, CCDIN −0.3 AVDD + 0.3 V
Junction Temperature 150 °C
Lead Temperature (10 sec) 300 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The thermal resistance of a 32-Lead LFCSP package
(with the exposed bottom pad soldered to the board GND)
is θ
= 27.7°C/W.
JA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 20
AD9943/AD9944
A
AD9943 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 NC
31 NC
30 NC
29 NC
28 NC
27 SCK
26 SDAT
25 SL
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
NC = NO CONNECT
PIN 1
INDICATOR
AD9943
TOP VIEW
D8 9
D9 10
DRVDD 11
DVDD 13
DRVSS 12
DATACLK 14
DVSS 15
PBLK 16
24 REFB
23 REFT
22 CCDIN
21 AVSS
20 AVDD
19 SHD
18 SHP
17 CLPOB
02905-B-003
Figure 2. AD9943 Pin Configuration
Table 7. AD9943 Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 to 10 D0 to D9 DO Digital Data Outputs.
11 DRVDD P Digital Output Driver Supply.
12 DRVSS P Digital Output Driver Ground.
13 DVDD P Digital Supply.
14 DATACLK DI Digital Data Output Latch Clock.
15 DVSS P Digital Supply Ground.
16 PBLK DI Preblanking Clock Input.
17 CLPOB DI Black Level Clamp Clock Input.
18 SHP DI CDS Sampling Clock for CCD Reference Level.
19 SHD DI CDS Sampling Clock for CCD Data Level.
20 AVDD P Analog Supply.
21 AVSS P Analog Ground.
22 CCDIN AI Analog Input for CCD Signal.
23 REFT AO A/D Converter Top Reference Voltage Decoupling.
24 REFB AO A/D Converter Bottom Reference Voltage Decoupling.
25 SL DI Serial Digital Interface Load Pulse.
26 SDATA DI Serial Digital Interface Data Input.
27 SCK DI Serial Digital Interface Clock Input.
28 to 30 NC NC Internally pulled down. Float or connect to GND.
31 to 32 NC NC Internally not nonnected.
1
Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
Rev. B | Page 8 of 20
AD9943/AD9944
AD9944 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 D1
31 D0
30 NC
29 NC
28 NC
27 SCK
26 SDATA25 SL
D2 1
D3 2
D4 3
D5 4
D6 5
D7 6
D8 7
D9 8
NC = NO CONNECT
PIN 1
INDICATOR
AD9944
TOP VIEW
D10 9
D11 10
DRVDD 11
DVDD 13
DRVSS 12
DATACLK 14
DVSS 15
PBLK 16
24 REFB
23 REFT
22 CCDIN
21 AVSS
20 AVDD
19 SHD
18 SHP
17 CLPOB
02905-B-004
Figure 3. AD9944 Pin Configuration
Table 8. AD9944 Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 to 10 D2 to D11 DO Digital Data Outputs.
11 DRVDD P Digital Output Driver Supply.
12 DRVSS P Digital Output Driver Ground.
13 DVDD P Digital Supply.
14 DATACLK DI Digital Data Output Latch Clock.
15 DVSS P Digital Supply Ground.
16 PBLK DI Preblanking Clock Input.
17 CLPOB DI Black Level Clamp Clock Input.
18 SHP DI CDS Sampling Clock for CCD Reference Level.
19 SHD DI CDS Sampling Clock for CCD Data Level.
20 AVDD P Analog Supply.
21 AVSS P Analog Ground.
22 CCDIN AI Analog Input for CCD Signal.
23 REFT AO A/D Converter Top Reference Voltage Decoupling.
24 REFB AO A/D Converter Bottom Reference Voltage Decoupling.
25 SL DI Serial Digital Interface Load Pulse.
26 SDATA DI Serial Digital Interface Data Input.
27 SCK DI Serial Digital Interface Clock Input.
28 to 30 NC NC Internally pulled down. Float or connect to GND.
31 D0 DO Digital Data Output.
32 D1 DO Digital Data Output.
1
Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
Rev. B | Page 9 of 20
AD9943/AD9944
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore
every code must have a finite width. No missing codes
guaranteed to 10-bit resolution indicates that all 1024 codes,
respectively, must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full-signal chain specification, refers to the
peak deviation of the output of the AD9943/AD9944 from a
true straight line. The point used as zero scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9943/AD9944’s power supply. The PSR specification is
calculated from the change in the data outputs for a given
step change in the supply voltage.
Internal Delay for SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from the time a sampling edge is applied to the
AD9943/AD9944 until the actual sample of the input signal is
held. Both SHP and SHD sample the input signal during the
transition from low to high, so the internal delay is measured
from each clock’s rising edge to the instant the actual internal
sample is taken.
()
where N is the bit resolution of the ADC. For example, 1 LSB of
the AD9943 is 1.95 mV.
N
codesScaleFullADC
2LSB1 =
Rev. B | Page 10 of 20
AD9943/AD9944
EQUIVALENT INPUT CIRCUITS
AVDD
60Ω
INPUT
DVDD
330Ω
DVSS
Figure 4. Digital Inputs—SHP, SHD, DATACLK, CLOB, PBLK, SCK, SL
DVDD
DATA
THREE-
STATE
DVSS
Figure 5. Data Outputs
DRVDD
DRVSS
AVSS
02905-B-005
AVSS
02095-B-007
Figure 6. CCDIN (Pin 22)
DOUT
02905-B-006
Rev. B | Page 11 of 20
AD9943/AD9944
–
–
TYPICAL PERFORMANCE CHARACTERISTICS
100
0.50
90
80
70
60
POWER DISSIPATION (mV)
50
40
10
VDD = 3.3V
VDD = 3.0V
VDD = 2.7V
SAMPLE RATE (MHz)
Figure 7. AD9943/AD9944 Power vs. Sample Rate
0.50
0.25
0
–0.25
0.25
0
0.25
20
2515
02905-B-008
0.50
0 800 1600 2400 3200 4000
02905-B-010
Figure 9. AD9944 Typical DNL Performance
–0.50
0
200 600 800
400
Figure 8. AD9943 Typical DNL Performance
1000
02905-B-009
Rev. B | Page 12 of 20
AD9943/AD9944
INTERNAL REGISTER MAP
All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (AD9943 = 32 LSB clamp level, and
AD9944 = 128 LSB clamp level).
Table 9.
Address Bits
Register Name A2 A1 A0 Data Bits Function
Operation 0 0 0 D0 Software Reset (0 = normal operation, 1 = reset all registers to default).
D2, D1 Power-Down Modes (00 = normal power, 01 = standby, 10 = total shutdown).
D3 OB Clamp Disable (0 = clamp on, 1 = clamp off).
D5, D4 Test Mode. Should always be set to 00.
D6 PBLK Blanking Level (0 = blank output to zero, 1 = blank to ob clamp level).
D8, D7 Test Mode 1. Should always be set to 00.
D11 to D9 Test Mode 2. Should always be set to 000.
Control 0 0 1 D0 SHP/SHD Input Polarity (0 = active low, 1 = active high).
D1 DATACLK Input Polarity (0 = active low, 1 = active high).
D2 CLPOB Input Polarity (0 = active low, 1 = active high).
D3 PBLK Input Polarity (0 = active low, 1 = active high).
D4 Three-State Data Outputs (0 = outputs active, 1 = outputs three-stated).
D5 Data Output Latching (0 = latched by DATACLK, 1 = latch is transparent).
D6 Data Output Coding (0 = binary output, 1 = gray code output).
D11 to D7 Test Mode. Should always be set to 00000.
Clamp Level 0 1 0 D7 to D0
VGA Gain 0 1 1 D9 to D0 VGA Gain (0 = 6 dB, 1023 = 40 dB).
OB Clamp Level (AD9943: 0 = 0 LSB, 255 = 63.75 LSB,
AD9944: 0 = 0 LSB, 255 = 255 LSB).
Rev. B | Page 13 of 20
AD9943/AD9944
A
SERIAL INTERFACE
SDATA
t
DS
SCK
TEST BIT
A2 0A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
t
DH
D11
t
LS
SL
NOTES
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
3. ALL 12 DATA BITS D0–D11 MUST BE WRITTEN. IF THE REGISTER CONTAINS FEWER THAN 12 BITS, ZEROS SHOULD BE USED
FOR THE UNDEFINED BITS.
4. TEST BIT IS FOR INTERNAL USE ONLY AND MUST BE SET LOW.
t
LH
02905-B-011
Figure 10. Serial Write Operation
TEST
BIT
SDAT
SCK
A0 A1 A2 D0 D1 D2 D3 D4 D5 D10 D11
116234567 8910
SL
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 12-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 12-BIT DATA-WORD. (ALL 12 BITS MUST BE WRITTEN.)
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT THE NEXT SL RISING EDGE.
0
DATA FOR STARTING
REGISTER ADDRESS
...
15
Figure 11. Continuous Serial Write Operation to All Registers
DATA FOR NEXT
REGISTER ADDRESS
D0 D1 D10 D11
...
1817 2827
D0
D2D1
302931
...
...
...
02905-B-012
Rev. B | Page 14 of 20
AD9943/AD9944
CIRCUIT DESCRIPTION AND OPERATION
DC RESTORE
0.1µF
CCDIN
CDS
Figure 12. CCD Mode Block Diagram
The AD9943/AD9944 signal processing chain is shown in
Figure 12. Each processing step is essential for achieving a high
quality image from the raw CCD pixel data.
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V, which is compatible with the 3 V single
supply of the AD9943/AD9944.
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract video
information and reject low frequency noise. The timing shown
in Figure 14 illustrates how the two CDS clocks, SHP and SHD,
are used, respectively, to sample the reference level and data
level of the CCD signal. The CCD signal is sampled on the
rising edges of SHP and SHD. Placement of these two clock
signals is critical for achieving the best performance from the
CCD. An internal SHP/SHD delay (t
internal propagation delays.
) of 3 ns is caused by
ID
6dB TO 40dB
VGA
10
VGA GAIN
REGISTER
INTERNAL
V
REF
2V FULL SCALE
8
REGISTER
10/12
DOUT
CLPOB
02905-B-013
8-BIT
DAC
10-/12-BIT
ADC
OPTICAL BLACK
CLAMP
DIGITAL
FILTERING
CLAMP LEVEL
OPTICAL BLACK CLAMP
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with the
fixed black level reference selected by the user in the clamp level
register. The resulting error signal is filtered to reduce noise, and
the correction value is applied to the ADC input through a D/A
converter. Normally, the optical black clamp loop is turned on
once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital
clamping is used during the post processing, the optical black
clamping for the AD9943/AD9944 may be disabled using
Bit D3 in the operation register. Refer to Table 9 and Figure 10
and Figure 11.
When the loop is disabled, the clamp level register may still be
used to provide programmable offset adjustment. Horizontal
timing is shown in Figure 15. The CLPOB pulse should be
placed during the CCD’s optical black pixels. It is recommended
that the CLPOB pulse be used during valid CCD dark pixels.
The CLPOB pulse should be a minimum of 20 pixels wide to
minimize clamp noise. Shorter pulse widths may be used, but
clamp noise may increase and the loop’s ability to track low
frequency variations in the black level is reduced.
Rev. B | Page 15 of 20
AD9943/AD9944
(
)
A/D CONVERTER
The ADC uses a 2 V input range. Better noise performance
results from using a larger ADC full-scale range. The ADC uses
a pipelined architecture with a 2 V full-scale input for low noise
performance.
42
36
30
VARIABLE GAIN AMPLIFIER
The VGA stage provides a gain range of 6 dB to 40 dB,
programmable with 10-bit resolution through the serial digital
interface. The minimum gain of 6 dB is needed to match a 1 V
input signal with the ADC full-scale range of 2 V. A plot of the
VGA gain curve is shown in Figure 13.
()
dB3.5dB035.0dB +×= CodeVGAGainVGA
34
VGA GAIN (dB)
18
12
6
0
511 639 767 895 1023
383127
255
VGA GAIN REGISTER MODE
Figure 13. VGA Gain Curve
02905-B-014
Rev. B | Page 16 of 20
AD9943/AD9944
K
CCD MODE TIMING
CCD
SIGNAL
DATACL
OUTPUT
DATA
t
ID
SHP
SHD
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
N N + 1 N + 2 N + 9 N + 10
t
ID
t
S1
t
OD
N– 10 N– 9 N– 8 N– 1 N
t
S2
t
CP
Figure 14. CCD Mode Timing
02905-B-015
HORIZONTAL
EFFECTIVE PIXELS
CCD
SIGNAL
CLPOB
PBLK
OUTPUT
DATA
EFFECTIVE PIXEL DATA
NOTES
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
OPTICAL BLACK PIXELS
OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA
BLANKING
Figure 15. Typical CCD Mode Line Clamp Timing
DUMMY PIXELS EFFECTIVE PIXELS
02905-B-016
Rev. B | Page 17 of 20
AD9943/AD9944
APPLICATIONS INFORMATION
The AD9943/AD9944 are complete analog front end (AFE)
products for digital still camera and camcorder applications. As
shown in Figure 12, the CCD image (pixel) data is buffered and
sent to the AD9943/AD9944 analog input through a series input
capacitor. The AD9943/AD9944 perform the dc restoration,
CDS, gain adjustment, black level correction, and analog-todigital conversion. The AD9943/AD9944’s digital output data is
then processed by the image processing ASIC. The internal
registers of the AD9943/AD9944—used to control gain, offset
level, and other functions—are programmed by the ASIC or
microprocessor through a 3-wire serial digital interface. A
system timing generator provides the clock signals for both the
CCD and the AFE.
OUT
DIGITAL
OUTPUTS
SERIAL
INTERFACE
DIGITAL IMAGE
PROCESSING
ASIC
02905-B-017
CCD
V-DRIVE
CCD
TIMING
AD9943/AD9944
ADC
CCDIN
REGISTER
CDS/CLAMP
TIMING
TIMING
GENERATOR
DATA
V
OUT
BUFFER
0.1µF
Figure 16. System Applications Diagram
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
SERIAL
INTERFACE
NC
NCNCNCNCSCK
32 31 30 29 28 27 26 25
PIN 1
IDENTIFIER
AD9943
TOP VIEW
(Not to Scale)
3
SDTA
SL
24 REFB
23 REFT
22 CCDIN
21 AVSS
20 AVDD
19 SHD
18 SHP
17 CLPOB
1.0µF
1.0µF
0.1µF
0.1µF
CCDIN
3V
ANALOG
SUPPLY
DATA
OUTPUTS
910
10
3V
DRIVER
SUPPLY
NC = NO CONNECT
D8
0.1µF
D9
12 13 14 15 16
11
DVDD
DRVSS
DRVDD
DVSS
DATACLK
0.1µF
PBLK
3V
ANALOG
SUPPLY
5
CLOCK
INPUTS
02905-B-018
Figure 17. AD9943 Recommended Circuit Configuration for CCD Mode
Rev. B | Page 18 of 20
AD9943/AD9944
SERIAL
INTERFACE
D0
D1
32 31 30 29 28 27 26 25
D2 1
D3 2
D4 3
D5 4
D6 5
D7 6
D8 7
D9 8
910
D11
D10
12
DATA
OUTPUTS
3V
DRIVER
SUPPLY
0.1µF
3
NCNCNC
PIN 1
IDENTIFIER
AD9944
TOP VIEW
(Not to Scale)
12 13 14 15 16
11
DVDD
DRVSS
DRVDD
SCK
SDTA
DVSS
DATACLK
0.1µF
SL
PBLK
3V
ANALOG
SUPPLY
24 REFB
23 REFT
22 CCDIN
21 AVSS
20 AVDD
19 SHD
18 SHP
17 CLPOB
1.0µF
1.0µF
0.1µF
0.1µF
5
CLOCK
INPUTS
CCDIN
3V
ANALOG
SUPPLY
NC = NO CONNECT
Figure 18. AD9944 Recommended Circuit Configuration for CCD Mode
INTERNAL POWER-ON RESET CIRCUITRY
After power-on, the AD9943/AD9944 automatically reset all
internal registers and perform internal calibration procedures.
This takes approximately 1 ms to complete. During this time,
normal clock signals and serial write operations may occur.
However, serial register writes are ignored until the internal
reset operation is completed.
GROUNDING AND DECOUPLING RECOMMENDATIONS
As shown in Figure 17 and Figure 18, a single ground plane is
recommended for the AD9943/AD9944. This ground plane
should be as continuous as possible. This ensures that all analog
decoupling capacitors provide the lowest possible impedance
path between the power and bypass pins and their respective
ground pins. All decoupling capacitors should be located as
02905-B-019
close as possible to the package pins. A single clean power
supply is recommended for the AD9943 and AD9944, but a
separate digital driver supply may be used for DRVDD (Pin 11).
DRVDD should always be decoupled to DRVSS (Pin 12), which
should be connected to the analog ground plane. Advantages of
using a separate digital driver supply include using a lower
voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing
digital power dissipation and potential noise coupling. If the
digital outputs must drive a load larger than 20 pF, buffering
is the recommended method to reduce digital code transition
noise. Alternatively, placing series resistors close to the digital
output pins may also help reduce noise.
Note: The exposed pad on the bottom of the AD9943/AD9944
should be soldered to the GND plane of the printed circuit
board.
Rev. B | Page 19 of 20
AD9943/AD9944
R
OUTLINE DIMENSIONS
0.08
0.60 MAX
25
24
EXPOSED
PAD
(BOTTOM VIEW)
17
16
32
1
8
9
3.50 REF
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
0.25 MIN
PIN 1
INDICATO
1.00
0.85
0.80
12° MAX
SEATING
PLANE
5.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
4.75
BSC SQ
0.20 REF
0.05 MAX
0.02 NOM
0.60 MAX
0.50
BSC
0.50
0.40
0.30
COPLANARITY
Figure 19. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body
(CP-32)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9943KCP
AD9943KCPRL
AD9943KCPZ
1
AD9943KCPZRL1
AD9944KCP
AD9944KCPRL
AD9944KCPZ1
AD9944KCPZRL1
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
1
Z = Pb-free part.
Lead Frame Chip Scale (LFCSP) CP-32
Lead Frame Chip Scale (LFCSP) CP-32
Lead Frame Chip Scale (LFCSP) CP-32
Lead Frame Chip Scale (LFCSP) CP-32
Lead Frame Chip Scale (LFCSP) CP-32
Lead Frame Chip Scale (LFCSP) CP-32
Lead Frame Chip Scale (LFCSP) CP-32
Lead Frame Chip Scale (LFCSP) CP-32
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02905–0–5/04(B)
Rev. B | Page 20 of 20
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