Datasheet AD9876 Datasheet (Analog Devices)

a

A

Broadband Modem

Mixed-Signal Front End

AD9876

FEATURES
Low Cost 3.3 V CMOS Mixed-Signal Front End (MxFE™)
Converter for Broadband Modems
10-/12-Bit D/A Converter (TxDAC+

®

)
64/32 MSPS Input Word Rate
2/4 Interpolating LPF or BPF Transmit Filter
128 MSPS DAC Output Update Rate
Wide (26 MHz) Transmit Bandwidth
Power-Down Mode

10-/12-Bit 50 MSPS A/D Converter

Fourth Order Low-Pass Filter 12 MHz or 26 MHz
with Bypass
–6 dB to +36 dB Programmable Gain Amplifier

Internal Clock Multiplier (PLL)
Clock Outputs
Voltage Regulator Controller
48-Lead LQFP Package

APPLICATIONS
Powerline Networking
Home Phone Networking
xDSL
Broadband Wireless
Home RF

PRODUCT DESCRIPTION

The AD9876 is a single-supply broadband modem mixed-signal
front end (MxFE) IC. The device contains a transmit path
interpolation filter and DAC and a receive path PGA, LPF, and
ADC supporting a variety of broadband modem applications.
Also on-chip is a PLL clock multiplier that provides all required
clocks from a single crystal or clock input. The AD9876 provides
12-bit converter performance on both the Tx and Rx path.

The TxDAC+ uses a selectable digital 2× or 4× interpolation
low-pass or band-pass filter to further oversample transmit data
and reduce the complexity of analog reconstruction filtering.
The transmit path signal bandwidth can be as high as 26 MHz
at an input data rate of 64 MSPS. The 12-bit DAC provides
differential current outputs for optimum noise and distortion
performance. The DAC full-scale current can be adjusted from
2 to 20 mA by a single resistor, providing 20 dB of additional
gain range.

The receive path consists of a PGA, LPF, and ADC. The PGA has
a gain range of –6 dB to +36 dB, programmable in 2 dB steps,
adding 42 dB of dynamic range to the receive path. The receive

FUNCTIONAL BLOCK DIAGRAM

PWR DN

Tx QUIET

GAIN

Tx [5:0]

Tx SYNC

CLK-A

CLK-B

Rx SYNC

Rx [5:0]

SPORT

3

12 12

Tx

MUX

REGISTER
CONTROL

Rx

MUX

12

Kx INTERPOLATION

LPF/BPF

PLL-A

CLOCK GEN

PLL-B

 M/N

ADC

 L

PGA

AD9876

TxDAC+

V

REF

VRC

LPF

PGA

Tx+

Tx–

GATE

FB

OSCIN

XTAL

Rx+

Rx–

path LPF cutoff frequency can be programmed to either 12 MHz
or 26 MHz. The filter cutoff frequency can also be tuned or
bypassed where filter requirements differ. The 12-bit ADC uses
a multistage differential pipeline architecture to achieve excellent
dynamic performance with low power consumption.

The AD9876 provides a voltage regulator controller (VRC) that
can be used with an external power MOSFET transistor to form
a cost-effective 1.3 V linear regulator.

The digital transmit and receive ports are each multiplexed to a
bus width of six bits and are clocked at a frequency of twice the
12-bit word rate.

The AD9876 ADC and/or DAC can also be used at sampling
rates as high as 64 MSPS in a 6-bit resolution nonmulti­plexed mode.

The AD9876 is pin compatible with the 10-bit AD9875. Both are
available in a space-saving 48-lead LQFP package. They are speci­fied over the industrial (–40°C to +85°C) temperature range.

MxFE is a trademark of Analog Devices, Inc.
TxDAC+ is a registered trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com

2

Fax: [phone] © Analog Devices, Inc., 2002

AD9876–SPECIFICATIONS

(VS = 3.3 V 10%, f
100  DAC single-ended load, unless otherwise noted. )

= 32 MHz, f

OSCIN

= 128 MHz, Gain = –6 dB, R

DAC

= 4.02 k,

SET

Test

Parameter Temp Level Min Typ Max Unit

OSCIN CHARACTERISTICS

Frequency Range Full II 10 64 MHz
Duty Cycle Full II 40 50 60 %
Input Capacitance 25°C III 3 pF
Input Impedance 25°C III 100 M⍀

CLOCK OUTPUT CHARACTERISTICS

CLK A Jitter (f

Derived from PLL) 25°C III 14 ps rms

CLKA

CLK A Duty Cycle 25°C III 50 ±5%
CLK B Jitter (f

Derived from PLL) 25°C III 33 ps rms

CLKB

CLK B Duty Cycle 25°C III 50 ± 5%

Tx CHARACTERISTICS

Tx Path Latency, 4× Interpolation Full II 86 f

DAC

Cycles

Interpolation Filter Bandwidth (–0.1 dB)

4× Interpolation, LPF Full II 13 MHz
2× Interpolation, LPF Full II 26 MHz

TxDAC

Resolution Full II 12 Bits
Conversion Rate Full II 10 128 MHz
Full-Scale Output Current Full II 2 10 20 mA
Voltage Compliance Range Full II –0.5 +1.5 V
Gain Error Full II –5 ± 2+5 % FS
Output Offset (Single-Ended) Full II 0 2 5 µA
Differential Nonlinearity Full III ±1 LSB
Integral Nonlinearity 25°C III ±2 LSB
Output Capacitance 25°C III 5 pF
Phase Noise @ 1 kHz Offset, 10 MHz Signal 25°C III –100 dBc/Hz
Signal-to-Noise and Distortion (SINAD)

10 MHz Analog Out AD9876 (20 MHz BW) Full I 62.5 65 dB

Wideband SFDR (to Nyquist, 64 MHz Max) 25°C III

5 MHz Analog Out 25°C III 80 dBc
10 MHz Analog Out 25°C III 74 dBc

Narrow-Band SFDR (3 MHz Window):

10 MHz Analog Out 25°C III 88 dBc

IMD (f1 = 6.9 MHz, f2 = 7.1 MHz) 25°C III –80 dBFS

Rx PATH CHARACTERISTICS

Resolution NA NA 12 Bits
Conversion Rate Full II 7.5 64 MHz
Pipeline Delay, ADC Clock Cycles NA NA 5.5 Cycles
DC Accuracy

Differential Nonlinearity Full II –1.0 ± 0.25 +1.0 LSB
Integral Nonlinearity Full II –4.5 ± 0.5 +3.5 LSB

Dynamic Performance (ADC Clocked Direct)

= –0.5 dBFS, f = 5 MHz)

(A

IN

@ f

OSCIN

= 32 MHz
Signal-to-Noise and Distortion Ratio (SINAD) Full I 60.8 63.2 dB
Effective Number of Bits (ENOB) Full I 9.8 10.2 Bits
Signal-to-Noise Ratio (SNR) 25°C III 64 dB
Total Harmonic Distortion (THD) 25°C III –70 dB
Spurious-Free Dynamic Range (SFDR) 25°C III 72 dB

Dynamic Performance (ADC Clocked, PLLB/2)

AIN = –0.5 dBFS, f = 5 MHz

(
@ F

PLLB/2

= 50 MHz

)

Signal-to-Noise and Distortion Ratio (SINAD) 25°C III 56 dB
Effective Number of Bits (ENOB) 25°C III 9.3 Bits
Signal-to-Noise Ratio (SNR) 25°C III 59 dB
Total Harmonic Distortion (THD) 25°C III –63 dB
Spurious-Free Dynamic Range (SFDR) 25°C III 68 dB

–2–

REV. A

AD9876

Test

Parameter Temp Level Min Typ Max Unit

Rx PATH GAIN/OFFSET

Minimum Programmable Gain 25°C III –6 dB
Maximum Programmable Gain (12 MHz Filter) 25°C III 36 dB
Maximum Programmable Gain (26 MHz Filter) 25°C III 30 dB
Gain Step Size 25°C III 2 dB
Gain Step Accuracy 25°C III ±0.4 dB
Gain Range Error 25°C III ±1.0 dB
Offset Error, PGA Gain = 0 dB 25°C III ±10 LSB
Absolute Gain Error 25°C III ±0.8 dB

Rx PATH INPUT CHARACTERISTICS

Input Voltage Range Full III 4 Vppd
Input Capacitance 25°C III 4 pF
Differential Input Resistance 25°C III 270 Ω
Input Bandwidth (–3 dB) 25°C III 50 MHz
Input Referred Noise (at –36 dB Gain with Filter) 25°C III 16 µV rms
Input Referred Noise (at –6 dB Gain with Filter) 25°C III 684 µV rms
Common-Mode Rejection 25°C III 40 dB

Rx PATH LPF (Low Cutoff Frequency)

Cutoff Frequency 25°C III 12 MHz
Cutoff Frequency Variation 25°C III ± 7%
Attenuation @ 22 MHz 25°C III 20 dB
Pass-Band Ripple 25°C III ±1.0 dB
Group Delay Variation 25°C III 30 ns
Settling Time

(to 1% FS, Min to Max Gain Change) 25°C III 150 ns

Total Harmonic Distortion at Max Gain (THD) 25°C III –68 dBc

Rx PATH LPF (High Cutoff Frequency)

Cutoff Frequency 25°C III 26 MHz
Cutoff Frequency Variation 25°C III ± 7%
Attenuation @ 44 MHz 25°C III 20 dB
Pass-Band Ripple 25°C III ±1.2 dB
Group Delay Variation 25°C III 15 ns
Settling Time

(to 1% FS, Min to Max Gain Change) 25°C III 80 ns

Total Harmonic Distortion at Max Gain (THD) 25°C III –65 dBc

Rx PATH DIGITAL HPF

Latency (ADC Clock Source Cycles) Full II 1 Cycle
Roll-Off in Stop Band Full II 6 dB/Octave
–3 dB Frequency Full II f

Rx PATH DISTORTION PERFORMANCE

IMD: f1 = 6.5 MHz, f2 = 7.7 MHz
12 MHz Filter : 0 dB Gain 25°C III –65 dBc

: 30 dB Gain 25°C III –57 dBc

26 MHz Filter : 0 dB Gain 25°C III –65 dBc

: 30 dB Gain 25°C III –56 dBc

POWER-DOWN/DISABLE TIMING

DAC I
DAC I

OFF after Tx QUIET Asserted Full II 200 ns

OUT

ON after Tx QUIET De-Asserted Full II 1 µs

OUT

Power-Down Delay (Active to Power-Down)

DAC Full II 400 ns
Interpolator Full II 200 ns

Power-Up Delay (Power-Down to Active)

DAC Full II 40 µs
PLL Full II 10 µs
ADC Full II 1000 µs
PGA Full II 1 µs
LPF Full II 1 µs
Interpolator Full II 200 ns
VRC Full II 2 µs

Minimum RESET Pulsewidth Low (tRL) Full II 5 f

/400 Hz

ADC

OSCIN

Cycles

REV. A

–3–

AD9876

Test

Parameter Temp Level Min Typ Max Unit

Tx PATH INTERFACE

Maximum Input Nibble Rate, 2× Interpolation Full II 128 MHz
Tx Setup Time (t
Tx Hold Time (tHD) Full II 0 ns

Rx PATH INTERFACE

Maximum Output Nibble Rate Full II 110 MHz
Rx Data Valid Time (t
Rx Data Hold Time (tHT) Full II 1.5 ns

SERIAL CONTROL BUS

Maximum SCLK Frequency (f
Clock Pulsewidth High (t
Clock Pulsewidth Low (t
Clock Rise/Fall Time Full II 1 ms
Data/Chip-Select Setup Time (t
Data Hold Time (t
Data Valid Time (tDV) Full II 20 ns

CMOS LOGIC INPUTS

Logic “1” Voltage Full II
Logic “0” Voltage Full II 0.4 V
Logic “1” Current Full II 12 µA
Logic “0” Current Full II 12 µA
Input Capacitance 25°C III 3 µF

CMOS LOGIC OUTPUTS (1 mA Load)

Logic “1” Voltage Full II
Logic “0” Voltage Full II 0.4 V
Digital Output Rise/Fall Time Full II 1.5 2.5 ns

POWER SUPPLY

All Blocks Powered Up

I
I

(Total Supply Current) Full I 262 288 mA

S_TOTAL

(Tx QUIET Pin Asserted) 25°C III 172 mA

S_TOTAL

Digital Supply Current (I
Analog Supply Current (I

Power Consumption of Functional Blocks:

Rx LPF 25°C III 110 mA
ADC and SPGA 25°C III 55 mA
Rx Reference 25°C III 2 mA
Interpolator 25°C III 33 mA
DAC 25°C III 18 mA
PLL-B 25°C III 8 mA
PLL-A 25°C III 24 mA
Voltage Regulator Controller 25°C III 1 mA

All Blocks Powered Down

Supply Current I
Supply Current I

Power Supply Rejection

Tx Path (∆V
Rx Path (∆VS = ⫾10%) 25°C III 54 dB

RECEIVE-TO-TRANSMIT ISOLATION

(10 MHz, Full-Scale Sine Wave Output/Output)
Isolation: Tx Path to Rx Path, Gain = +36 dB 25°C III –75 dB
Isolation: Rx Path to Tx Path, Gain = –6 dB 25°C III –70 dB

VOLTAGE REGULATOR CONTROLLER

Output Voltage (V
Line Regulation (∆V
Load Regulation (∆V
Maximum Load Current (I

Specifications subject to change without notice.

) Full II 3.0 ns

SU

) Full II 3.0 ns

VT

) Full II 25 MHz

SCLK

) Full II 18 ns

PWH

) Full II 18 ns

PWL

) Full II 25 ns

) Full II 0 ns

DH

, f

S

OSCIN

, f

S

OSCIN

= ⫾10%) 25°C III 62 dB

S

with SI2301 Connected) Full I 1.25 1.30 1.35 V

FB

/∆V

FB%

/∆I

FB

DS

V

– 0.7 V

DRVDD

V

– 0.6 V

DRVDD

+ I

DRVDD

)25°C III 185 mA

AVDD

)25°C III 77 mA

DVDD

= 32 MHz Full II 19 22 mA
Idle Full II 10 12 mA

× 100%) 25°C III 100 %

DVDD%

)25°C III 60 mΩ

LOAD

) Full II 250 mA

LOAD

–4–

REV. A

REV. A

AD9876

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Power Supply (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA

Digital Inputs . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V

Analog Inputs . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

EXPLANATION OF TEST LEVELS

I–Devices are 100% production tested at 25°C and guaran-

teed by design and characterization testing for industrial
operating temperature range (–40°C to +85°C).

II –Parameter is guaranteed by design and/or characteriza-

tion testing.

III – Parameter is a typical value only.

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

48-Lead LQFP

= 57°C/W

␪

JA

= 28°C/W

␪

JC

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9876BST –40°C to +85°C 48-Lead LQFP ST-48
AD9876-EB –40°C to +85°CEvaluation Board
AD9876BSTRL –40°C to +85°CBST Reel

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9876 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. A

–5–

AD9876

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 OSCIN Crystal Oscillator Inverter Input
2 SENABLE Serial Bus Enable Input
3 SCLK Serial Bus Clock Input
4 SDATA Serial Bus Data I/O
5, 38, 47 AVDD Analog 3.3 V Power Supply
6, 9, 39, 42, 43, 46 AVSS Analog Ground
7Tx+ Transmit DAC+ Output
8 Tx– Transmit DAC– Output
10 FSADJ DAC Full-Scale Output Current Adjust with External Resistor
11 REFIO DAC Band Gap Decoupling Node
12 PWR DN Power-Down Input
13 DVSS Digital Ground
14 DVDD Digital 3.3 V Power Supply
15 FB Regulator Feedback Input
16 GATE Regulator Output to FET Gate
17 GAIN Transmit Data Port (Tx [5:0]) Mode Select Input
18 Tx QUIET Transmit Quiet Input
19–24 Tx [5:0] Transmit Data Input
25 Tx SYNC Transmit Synchronization Strobe Input
26 CLK-A L × f
27 CLK-B M/N × f
28 Rx SYNC Receive Data Synchronization Strobe Output
29–34 Rx[5:0] Receive Data Output
35 DRVDD Digital I/O 3.3 V Power Supply
36 DRVSS Digital I/O Ground
37 RESET Reset Input
40 REFB ADC Reference Decoupling Node
41 REFT ADC Reference Decoupling Node
44 Rx+ Receive Path + Input
45 Rx– Receive Path – Input
48 XTAL Crystal Oscillator Inverter Output

Clock Output

OSCIN

OSCIN

Clock Output

OSCIN

SENABLE

SCLK

SDATA

AVDD

AVSS

Tx+

Tx–

AVSS

FSADJ

REFIO

PWR DN

PIN CONFIGURATION

XTAL

AVDD

AVSS

Rx–

Rx+

AVSS

AVSS

AD9876

GAIN

Tx QUIET

Tx [5]

REFT

Tx [4]

48 4 7 46 45 44 39 38 3743 4 2 41 40

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

DVSS

FB

DVDD

TOP VIEW

(Not to Scale)

GATE

–6–

REFB

Tx [3]

AVSS

Tx [2]

AVDD

Tx [1]

RESET

36

35

34

33

32

31

30

29

28

27

26

25

Tx [0]

DRVSS

DRVDD

Rx [0]

Rx [1]

Rx [2]

Rx [3]

Rx [4]

Rx [5]

Rx SYNC

CLK-B

CLK-A

Tx SYNC

REV. A

AD9876

DEFINITIONS OF SPECIFICATIONS
CLOCK JITTER

The clock jitter is a measure of the intrinsic jitter of the PLL
generated clocks. It is a measure of the jitter from one rising
and of the clock with respect to another edge of the clock nine
cycles later.

DIFFERENTIAL NONLINEARITY ERROR
(DNL, NO MISSING CODES)

An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicates that all 1024
codes, respectively, must be present over all operating ranges.

INTEGRAL NONLINEARITY ERROR (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.”
before the first code transition. Positive full scale is de
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.

PHASE NOISE

Single-sideband phase noise power density is specified relative to
the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the
carrier. Phase noise can be measured directly on a generated
single tone with a spectrum analyzer that supports noise marker
measurements. It detects the relative power between the carrier
and the offset (1 kHz) sideband noise and takes the resolution
bandwidth (rbw) into account by subtracting 10 log(rbw). It also
adds a correction factor that compensates for the implementation
of the resolution bandwidth, log display, and detector characteristic.

OUTPUT COMPLIANCE RANGE

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation, resulting in nonlinear per­formance or breakdown.

SPURIOUS–FREE DYNAMIC RANGE (SFDR)

The difference, in dB, between the rms amplitude of the DACs
output signal (or ADCs input signal) and the peak spurious
signal over the specified bandwidth (Nyquist bandwidth, unless
otherwise noted).

PIPELINE DELAY (LATENCY)

The number of clock cycles between conversion initiation and
the associated output data being made available.

The point used as negative full scale occurs 1/2 LSB

fined as a

OFFSET ERROR

First transition should occur for an analog value 1/2 LSB above
negative full scale. Offset error is defined as the deviation of the
actual transition from that point.

GAIN ERROR

The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur for an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between the first and
last code transitions and the ideal difference between the first
and last code transitions.

INPUT REFERRED NOISE

The rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in LSB
and converted to an equivalent voltage. This results in a noise
figure that can be directly referred to the Rx input of the AD9876.

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

SINAD is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the num­ber of bits. Using the following formula:

N SINAD dB=

()

it is possible to get a measure of performance expressed as N,
the effective number of bits.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic com­ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.

POWER SUPPLY REJECTION

Power supply rejection specifies the converters maximum
full-scale change when the supplies are varied from nominal to
minimum and maximum specified voltages.

–. .176 602

REV. A

–7–

AD9876

–Typical Tx Digital Filter Performance Characteristics

10

0

–10

–20

–30

–40

–50

–60

MAGNITUDE – dB

–70

–80

–90

–100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

INTERPOLATION

FILTER

INCLUDING SIN(X)/X

NORMALIZED – f

s

TPC 1. 4 Low-Pass Interpolation Filter

10

0

–10

–20

–30

–40

–50

–60

MAGNITUDE – dB

–70

–80

–90

–100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

INTERPOLATION

FILTER

INCLUDING SIN(X)/X

NORMALIZED – f

S

TPC 2. 2 Low-Pass Interpolation Filter

10

0

–10

–20

–30

–40

–50

–60

MAGNITUDE – dB

–70

–80

–90

–100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

INCLUDING SIN(X)/X

INTERPOLATION

FILTER

NORMALIZED – f

S

TPC 4. 2 Band-Pass Interpolation Filter, fS /2 Modula­tion, Adjacent Image Preserved

10

0

–10

–20

–30

–40

–50

–60

MAGNITUDE – dB

–70

–80

–90

–100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

INTERPOLATION

FILTER

INCLUDING SIN(X)/X

NORMALIZED – fS

TPC 5. 4 Band-Pass Interpolation Filter, fS /4 Modulation,
Lower Image Preserved

10

0

–10

–20

–30

INCLUDING SIN(X)/X

–40

–50

–60

MAGNITUDE – dB

–70

–80

–90

–100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
NORMALIZED – f

INTERPOLATION

S

FILTER

TPC 3. 4 Band-Pass Interpolation Filter, fS /2 Modula­tion, Adjacent Image Preserved

10

0

–10

–20

–30

–40

–50

–60

MAGNITUDE – dB

–70

–80

–90

–100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

INTERPOLATION

FILTER

NORMALIZED – fS

INCLUDING SIN(X)/X

TPC 6. 4 Band-Pass Interpolation Filter, fS /4 Modulation,
Upper Image Preserved

–8–

REV. A

f

OUT

– MHz

80

75

50

70

65

60

55

132465798101211 13 1514 16 1817

MAGNITUDE – dBc

f

DATA

= 50MSPS

f

DATA

= 32MSPS

Typical AC Characteristics Curves for TxDAC+

10

0

–10

–20

–30

–40

–50

MAGNITUDE – dBc

–60

–70

–80

–90

013263851647790102115128

FREQUENCY – MHz

( (R

= 4.02 k, R

SET

= 100 )

DAC

AD9876

TPC 7. Single-Tone Spectral Plot @ f
f

= 5 MHz, 4 LPF

OUT

10

0

–10

–20

–30

–40

–50

MAGNITUDE – dBc

–60

–70

–80

–90

010203040506070 80 90100

FREQUENCY – MHz

TPC 8. Single-Tone Spectral Plot @ f
f

= 11 MHz, 2 LPF

OUT

10

0

–10

–20

–30

–40

–50

–60

MAGNITUDE – dBc

–70

–80

–90

–100

TPC 9. Dual-Tone Spectral Plot @ f

= 6.9 MHz and 7.1 MHz, 4 LPF

f

OUT

FREQUENCY – MHz

DATA

= 32 MSPS,

DATA

= 50 MSPS,

DATA

= 32 MSPS,

TPC 10. Out-of-Band SFDR vs. f

OUT

@ f

= 32 MSPS

DATA

and 50 MSPS

90

85

80

f

= 32MSPS

= 50MSPS

f

– MHz

OUT

OUT

@ f

DATA

DATA

= 32 MSPS

75

70

MAGNITUDE – dBc

65

60

132465798101211 13 1514 16 1817

f

DATA

TPC 11. In-Band SFDR vs. f
and 50 MSPS

10

0

–10

–20

–30

–40

–50

–60

MAGNITUDE – dBc

–70

–80

–90

7.56.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4

–100

FREQUENCY – MHz

TPC 12. Dual-Tone Spectral Plot @ f

= 6.9 MHz and 7.1 MHz, 2 LPF

f

OUT

= 50 MSPS,

DATA

7.56.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4

REV. A

–9–

AD9876

Typical AC Characteristics Curves for TxDAC

10

0

–10

–20

–30

–40

–50

–60

MAGNITUDE – dBc

–70

–80

–90

–100

–1 0123456789

FREQUENCY OFFSET – kHz

(R

= 4.02 k, R

SET

MAGNITUDE – dBc

= 100 )

DAC

10

0

–10

–20

–30

–40

–50

–60

–70

35791113 15 17 19 21 23

FREQUENCY – MHz

TPC 13. Phase Noise Plot @ f
f

= 10 MHz, 4 LPF

OUT

10

0

–10

–20

–30

–40

–50

–60

MAGNITUDE – dBc

–70

–80

–90

–100

–1 0123456789

FREQUENCY OFFSET – kHz

TPC 14. Phase Noise Plot @ f
f

= 10 MHz, 2 LPF

OUT

= 32 MSPS,

DATA

= 50 MSPS,

DATA

TPC 15. In-Band Multitone Spectral Plot

@ f

10

–10

–20

–30

–40

MAGNITUDE – dBc

–50

–60

–70

= 50 MSPS, f

DATA

0

311 3121 41 51 61 71 81 91 101

= k  195 kHz, 2 LPF

OUT

FREQUENCY – MHz

TPC 16. Wideband Multitone Spectral Plot
@ f

= 50 MSPS, f

DATA

= k 195 kHz, 2 LPF

OUT

–10–

REV. A

Typical Tx Digital Filter Performance Characteristics

40

38

36

34

32

30

28

FREQUENCY – MHz

26

24

22

20

64 80 96 112 128 144 160 176 192

TPC 17. Rx vs. Tuning Target, f

ADC

LPF with Wideband Rx LPF = 1

= 32 MHz,

18

17

16

15

14

13

12

FREQUENCY – MHz

11

10

9

8

48 64 80 96 112 128 144 160 176 192

TPC 19. fC vs. Tuning Target, f
LPF with Wideband Rx LPF = 0

AD9876

= 32 MHz,

ADC

0.60

0.40

0.20

0.00

–0.20

MAGNITUDE – dB

–0.40

–0.60

–0.80

–6 –4 –2 024681012141618202224262830323436

VGA GAIN – dB

TPC 18. PGA Gain Error vs. Gain

2.5

2.4

2.3

2.2

2.1

2.0

1.9

MAGNITUDE – dB

1.8

1.7

1.6

1.5
–6 –4 –2 024681012141618202224262830323436

VGA GAIN – dB

TPC 20. PGA Gain Step Size vs. Gain

REV. A

–11–

AD9876

Typical AC Characterization Curves for Rx Path

LOG MAG 5dB/REF – 0dB –3.0dB

0

10.8MHz

DELAY 10ns/REF 0s 72.188ns

9.0MHz

0

1MHz 10MHz 100MHz

TPC 21. Rx LPF Frequency Response, Low f
Nominal Tuning Targets

LOG MAG 5dB/REF 0dB –3.0dB

26.5MHz

0

1MHz 10MHz 100MHz

TPC 22. Rx LPF Frequency Response, High f
Nominal Tuning Targets

LOG MAG 5dB/REF 0dB –3.0dB

0

14.5MHz

1MHz 10MHz 100MHz

C

TPC 24. Rx LPF Group Delay, Low fC Nominal
Tuning Targets

DELAY 5ns/REF 0s 34.431ns

22.5MHz

0

1MHz 10MHz 100MHz

C

TPC 25. Rx LPF Group Delay, High fC, Nominal
Tuning Targets

DELAY 10ns/REF 0s 51.244ns

14.5MHz

1MHz 10MHz 100MHz

TPC 23. Rx LPF Frequency Response, Low f
0  60 and 0  96 Turning Targets

0

1MHz 10MHz 100MHz

C

–12–

TPC 26. Rx LPF Group Delay, Low fC, 0  60 and



96 Tuning Targets

0

REV. A

AD9876

Typical AC Characterization Curves for Rx Path

LOG DELAY 5dB/REF –2dB –5.1933dB

33.5MHz

1MHz 10MHz 100MHz

TPC 27. Rx LPF Frequency Response, High fC,
0



60 and 0  96 Tuning Targets

LOG MAG 5dB/REF 0dB –3.01dB

COR

AVG

78.8MHz

16

0

0

(continued)

LOG DELAY 5ns/REF 0s 29.97ns

29.5MHz

COR

AVG

16

1MHz 10MHz 100MHz

TPC 30. Rx LPF Group Delay, High fC, 0  60 and
0



96 Tuning Targets

700

600

500

V



400

FILTER ENABLED

0

10kHz 100kHz 1MHz

TPC 28. Rx HPF Frequency Response, f

4000

3800

3600

3400

3200

3000

ADC OUTPUT CODE

2800

2600

2400

051015 20 25 30 35 40

f

= 50MHz

ADC

ADC CLOCK CYCLES

f

ADC

ADC

= 32MHz

TPC 29. Rx Path Setting, 1/2 Scale Rising Step
with Gain Change

= 32 MHz

300

200

ADC INPUT RMS NOISE –

FILTER BYPASSED

100

0

–6 1442434

GAIN SETTING

–

dB

TPC 31. Rx Input Referred Noise vs. Gain

= 32 MSPS, fIN = 1 MHz

@ f

ADC

4000

3800

3600

3400

3200

3000

ADC OUTPUT CODE

2800

2600

2400

f

= 32MHz

ADC

051015 20 25 30 35 40

ADC CLOCK CYCLES

f

ADC

= 50MHz

TPC 32. Rx Path Setting, 1/2 Scale Falling Step
with Gain Change

REV. A

–13–

AD9876

Typical AC Characterization Curves for Rx Path

11.0

10.5

10.0

9.5

9.0

ENOB

8.5

8.0

7.5

7.0
10 20

f

PLLB/2

f

– MHz

S

f

OSCIN

30 40 50

TPC 33. Rx Path ENOB vs. f

11.0

10.5

10.0

9.5

9.0

ENOB

8.5

8.0

7.5

7.0

046810

f

21214161820

PLLB/2

f

IN

f

– MHz

OSCIN

TPC 36. Rx Path ENOB vs. f

ADC

IN

70

65

60

55

50

MAGNITUDE – dB

45

40

f

OSCIN

10 20

f

PLLB/2

30 40 50

f

– MSPS

S

TPC 34. Rx Path SNR vs. f

70

65

60

55

50

MAGNITUDE – dB

45

40

0 4681021214161820

f

f

f

IN

OSCIN

PLLB/2

– MHz

TPX 37. Rx Path SNR vs. f

(Gain = –6 dB, fIN = 5 MHz)

–50

–55

–60

–65

–70

MAGNITUDE – dB

–75

–80

ADC

IN

TPC 35. Rx Path THD vs. f

–50

–55

–60

–65

–70

MAGNITUDE – dB

–75

–80

f

OSCIN

f

PLLB/2

10 20

0 4681021214161820

TPC 38. Rx Path THD vs. f

30 40 50

f

– MSPS

S

f

PLLB/2

f

OSCIN

f

– MHz

IN

ADC

IN

11.0

10.5

f

f

PLLB/2

12 18

GAIN – dB

OSCIN

10.0

9.5

ENOB

9.0

8.5

8.0
–6 6

0243036

TPC 39. Rx Path ENOB vs. Gain

70

65

60

MAGNITUDE – dB

55

50

–6 6

0243036

f

PLLB/2

f

OSCIN

12 18

GAIN – dB

TPC 40. Rx Path SNR vs. Gain

–14–

–50

–55

–60

MAGNITUDE – dB

–65

–70

–6 6

f

PLLB/2

f

OSCIN

0243036

12 18

GAIN – dB

TPC 41. Rx Path THD vs. Gain

REV. A

AD9876

TRANSMIT PATH

The AD9876 transmit path consists of a digital interface port, a
programmable interpolation filter, and a transmit DAC. All
clock signals required by these blocks are generated from the

signal by the PLL-A clock generator. The block diagram

f

OSCIN

below shows the interconnection between the major functional
components of the transmit path.

f

OSCIN

AD9876

TxDAC+

f

OSCIN

Tx+

Tx–

OSCIN

XTAL

Tx QUIET

GAIN

Tx [5:0]

Tx SYNC

CLK-A

12 12

Tx

DEMUX

f

CLK-A

Kx INTERPOLATION

CLOCK GEN

LPF/BPF

PLL-A

ⴛ L

f

DAC

= L ⴛ

Figure 1. Transmit Path Block Diagram

DIGITAL INTERFACE PORT

The Transmit Digital Interface Port has several modes of opera­tion. In its default configuration, the Tx Port accepts six bit
nibbles through the Tx [5:0] and Tx SYNC pins and demul­tiplexes the data into 12-bit words before passing it to the
interpolation filter. The input data is sampled on the rising edge

CLK-A

.

of f

Additional programming options for the Tx Port allow: sampling
the input data on the falling edge of f
of f

, and reversing the order of the nibbles. Also, the Tx Port

CLK-A

, inversion or disabling

CLK-A

interface can be controlled by the GAIN pin to provide direct
access to the Rx Path Gain Adjust Register. All of these modes
are fully described in the Register Programming Definitions sec­tion of this data sheet.

The data format is twos complement, as shown below:

011 . . 11: Maximum

000 . . 01: Midscale + 1 LSB
000 . . 00: Midscale
111 . . 11: Midscale – 1 LSB
111 . . 10: Midscale – 2 LSB

100 . . 00: Minimum

The data can be translated to a straight binary data format by
simply inverting the most significant bit.

The timing of the interface is fully described in the Transmit
Port Timing section of this data sheet.

PLL-A CLOCK DISTRIBUTION

Figure 1 shows the clock signals used in the transmit path. The
DAC sampling clock, f
frequency equal to L × f

, is generated by PLL-A. f

DAC

OSCIN

, where f

is the internal signal

OSCIN

DAC

has a

generated either by the crystal oscillator when a crystal is con­nected between the OSCIN and XTAL pins, or by the clock that
is fed into the OSCIN pin, and L is the multiplier programmed
through the serial port. L can have the values of 1, 2, 4, or 8.

The transmit path expects a new half-word of data at the rate
of f

. When the Tx multiplexer is enabled, the frequency

CLK-A

of Tx Port is:

ffKLfK

=× =× ×22/

CLK A DAC OSCIN−

where K is the interpolation factor that can be programmed to be
1, 2, or 4. When the Tx multiplexer is disabled, the frequency of
the Tx Port is:

ffKLfK

==×/

CLK A DAC OSCIN−

Note, this will result in a 6-bit data path.

INTERPOLATION FILTER

The interpolation filter can be programmed to run at 2× and 4×
upsampling ratios in each of three different modes. The transfer
functions of these six configurations are shown in TPCs 1–6.
The X-axis of each of these figures corresponds to the frequency
normalized to f

. These transfer functions show both the

DAC

discrete time transfer function of the interpolation filters alone
and with the SIN(x)/x transfer function of the DAC. The
interpolation filter can also be programmed into a pass­through mode if no interpolation filtering is desired.

The contents of the interpolation filter are not cleared by
hardware or software resets. It is recommended to “flush” the
transmit path with zeros before transmitting data.

The table below contains the following parameters as a function
of the mode that it is programmed.

Latency – The number of clock cycles from the time a digital
impulse is written to the DAC until the peak value is output at
the T+ and T– pins.

Flush – The number of clock cycles from the time a digital
impulse is written to the DAC until the output at the Tx+ and
Tx– pins settles to zero.

f

(0.1 dB, 3 dB) – This indicates the lower 0.1 dB or 3 dB

LOWER

cutoff frequency of the interpolation filter as a fraction of f

DAC

,

the DAC sampling frequency.

f

(0.1 dB, 3 dB) – This indicates the upper 0.1 dB or 3 dB

UPPER

cutoff frequency of the interpolation filter as a fraction of f

DAC

,

the DAC sampling frequency.

Table I. Interpolation Filter Parameters vs. Mode

Register 7 [7:4] 0 ⴛ 00 ⴛ 10 ⴛ 40 ⴛ 50 ⴛ 80 ⴛ C

Mode 4 × LPF 2 × LPF 4 × BPF 2 × BPF 4 × BPF 4 × BPF

Adj. Adj. Lower Upper

Latency, f
Clock Cycles

Flush, f

DAC

Clock Cycles

f

0.1 dB 0 0 0.398 0.276 0.148/ 0.274/

LOWER,

f

0.1 dB 0.102 0.204 0.602 0.724 0.226/ 0.352/

UPPER,

f

3 dB 0 0 0.381 0.262 0.131/ 0.257/

LOWER,

f

3 dB 0.119 0.238 0.619 0.738 0.243/ 0.369/

UPPER,

86 30 86 3 86 86

DAC

128 48 128 48 148 142

0.774 0.648

0.852 0.762

0.757 0.631

0.869 0.743

REV. A

–15–

AD9876

D/A CONVERTER

The AD9876 DAC provides differential output current on the
Tx+ and Tx– pins. The value of the output currents are comple­mentary, meaning that they will always sum to I

, the full-scale

FS

current of the DAC. For example, when the current from Tx+ is
at full-scale, the current from Tx– is zero. The two currents will
typically drive a resistive load that will convert the output
currents to a voltage. The Tx+ and Tx– output currents are
inherently ground seeking and should each be connected to
matching resistors, R

, that are tied directly to AGND.

L

The full-scale output current of the DAC is set by the value of
the resistor placed from the FSADJ pin to AGND. The relation­ship between the resistor, R

, and the full-scale output current

SET

is governed by the following equation:

IR

= 39 4.

FS SET

The full-scale current can be set from 2 to 20 mA. Generally,
there is a trade-off between DAC performance and power con­sumption. The best DAC performance will be realized at an I

FS

of 20 mA. However, the value of IFS adds directly to the overall
current consumption of the device.

The single-ended voltage output appearing at the Tx+ and Tx–
nodes are:

VIR

=×

Tx Tx L++

VIR

=×

Tx Tx L−−

Note that the full-scale voltage of V

Tx+

and V

should not

Tx–

exceed the maximum output compliance range of 1.5 V to pre­vent signal compression. To maintain optimum distortion and
linearity performance, the maximum voltages at V

Tx+

and V

Tx–

should not exceed 0.5 V.

The single-ended full-scale voltage at either output node will be:

VIR

=×

FS FS L

The differential voltage, V

VTTR

DIFF Tx Tx L

, appearing across V

DIFF

=−

()

+−

×

Tx+

and V

Tx–

is:

and

VIR

DIFF FS FS L_

=×

For optimum performance, a differential output interface is rec­ommended

since any common-mode noise or distortion can be

suppressed.

It should be noted that the differential output impedance of the
DAC is 2 × R

and any load connected across the two output

L

resistors will load down the output voltage accordingly.

RECEIVE PATH DESCRIPTION

The receive path consists of a two-stage PGA, a continuous time,
4-pole LPF, an ADC, a digital HPF, and a digital data multiplexer.
Also working in conjunction with the receive path is an offset
correction circuit and a digital phase-lock loop. Each of these
blocks will be discussed in detail in the following sections.

PROGRAMMABLE GAIN AMPLIFIER

The PGA has a programmable gain range from –6 dB to +36 dB
if the narrower (approximately 12 MHz) LPF bandwidth is

selected, or if the LPF is bypassed. If the wider (approximately
26 MHz) LPF bandwidth is selected, the gain range is –6 dB to
+30 dB. The PGA is comprised of two sections, a continuous
time PGA (CPGA) and a switched capacitor PGA (SPGA). The
CPGA has possible gain settings of 0, 6, 12, 18, 24, and 30. The
SPGA has possible gain settings of –6, –4, –2, 0, +2, +4, and +6
dB. Table V shows how the gain is distributed for each pro­grammed gain setting.

The CPGA input appears at the device Rx+ and Rx– input pins.
The input impedance of this stage is nominally 270 ⍀ differen-
tial and is not gain dependent. It is best to ac-couple the input
signal to this stage and let the inputs self bias. This will lower
the offset voltage of the input signal, which is important at higher
gains, since any offset will lower the output compliance range of
the CPGA output. When the inputs are driven by direct coupling,
the dc level should be AVDD/2. However, this could lead to
larger dc offsets and consequently reduce the dynamic range of the
Rx path.

LOW-PASS FILTER

The low-pass filter (LPF) is a programmable, multistage, fourth
order filter comprised of two real poles and a complex pole pair.
The first real pole is implemented within the CPGA. The second
filter stage implements a complex pair of poles. The last real
pole is implemented in a buffer stage that drives the SPGA.

There are two pass-band settings for the LPF. Within each pass
band the filters are tunable over about a ±30% frequency range.
The formula for the cutoff frequency is:

ff64 64 Target

CUTOFF LOW ADC

ff158 64 Target

CUTOFF HIGH ADC

=× +

=× +

()

()

where Target is the decimal value programmed as the tuning
target in Register 5.

This filter may also be bypassed by setting Bit 0 of Register 4.
In this case, the bandwidth of the Rx path will decrease with
increasing gain and will be approximately 50 MHz at the highest
gain settings.

ADC

The AD9876’s analog-to-digital converter implements a pipe­lined multistage architecture to achieve high sample rates while
consuming low power. The ADC distributes the conversion over
several smaller A/D subblocks, refining the conversion with
progressively higher accuracy as it passes the results from stage
to stage. As a consequence of the distributed conversion, ADCs
require a small fraction of the 2

N

comparators used in a tradi­tional n-bit flash-type A/D. A sample-and-hold function within
each of the stages permits the first stage to operate on a new
input sample while the remaining stages operate on preceding
samples. Each stage of the pipeline, excluding the last, consists
of a low resolution flash A/D connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier amplifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipe­line. One bit of redundancy is used in each one of the stages to
facilitate digital correction of flash errors. The last stage simply
consists of a flash A/D.

–16–

REV. A

AD9876

AINP
AINN

A/D

SHA

GAIN SHA

D/A

A/D

D/A

CORRECTION LOGIC

A/D

GAIN

AD9876

Figure 2. ADC Theory of Operation

The digital data outputs of the ADC are represented in two’s
complement format. They saturate to full scale or zero when the
input signal exceeds the input voltage range.

The twos complement data format is shown below:

011 . . 11: Maximum

000 . . 01: Midscale + 1 LSB
000 . . 00: Midscale
111 . . 11: Midscale – 1 LSB
111 . . 10: Midscale – 2 LSB

100 . . 00: Minimum

The maximum value will be output from the ADC when the
Rx+ input is 1 V or more greater than the Rx– input. The mini­mum value will be output from the ADC when the Rx– input is
1 V or more greater than the Rx+ input. This results in a full­scale ADC voltage of 2 Vppd.

The data can be translated to straight binary data format by
simply inverting the most significant bit.

The best ADC performance will be achieved when the ADC
clock source is selected from f

and the OSCIN pin is driven

OSCIN

from a low jitter clock source. The amount of degradation from
jitter on the ADC clock will depend on how quickly the input is
varying at the sampling instance. TPC 36 charts this effect in
the form of

ENOB

vs. input frequency for the two clocking

scenarios.

The maximum sample rate of the ADC in Full-Precision Mode,
that is outputting 12 bits, is 55 MSPS. TPC 33 shows the ADC
performance in ENOB versus f

. The maximum sample rate

ADC

of the ADC in Half-Precision Mode, that is outputting five bits,
is 64 MSPS. The timing of the interface is fully described in the
Receive Port Timing section of this data sheet.

CLOCK AND OSCILLATOR CIRCUITRY

The AD9876’s internal oscillator generates all sampling clocks
from a fundamental frequency quartz crystal. Figure 3a shows
how the quartz crystal is connected between OSCIN (Pin 1) and
XTAL (Pin 48) with parallel resonant load capacitors as speci­fied by the crystal manufacturer. The internal oscillator circuitry
can also be overdriven by a TTL-level clock applied to OSCIN
with XTAL left unconnected.

The PLL has a frequency capture range between 10 MHz
and 64 MHz.

AD9876

XTAL

OSCIN

C1

XTAL

Y1

C2

Figure 3a. Connections for a Fundamental Mode Crystal

VOLTAGE REGULATOR CONTROLLER

The AD9876 contains an on-chip voltage regulator controller
(VRC) for providing a linear 1.3 V supply for low voltage digital
circuitry or other external use. The VRC consists of an op amp
and a resistive voltage divider. As shown in Figure 3b, the resis­tive divider establishes a voltage of 1.3 V at the inverting input
of the amplifier when DVDD is equal to its nominal voltage of

3.3 V. The feedback loop around the op amp will adjust the gate
voltage such that the voltage at the FB pin, V

, will be equal to

FB

the voltage at the inverting input of the op amp.

3.3V

DVDD

AD9876

2R

S

G

1.3R

GATE

FB

VFB = 1.3V

D

SI2301

C

V

OUT

DIGITAL HPF

Following the ADC, there is a bypassable digital HPF. The
response is a single-pole IIR HPF. The transfer function is:

11

Hz Z Z

=

1099994 1 98466

()

–. –

()()

––

where the sampling period is equal to the ADC clock period.
This results in a 3 dB frequency approximately 1/400th of the
ADC sampling rate. The transfer functions are plotted for
32 MSPS and 50 MSPS in TPC 29 and TPC 32.

The digital HPF introduces a 1 ADC clock cycle latency. If the
HPF function is not desired, the HPF can be bypassed and the
latency will not be incurred.

REV. A

–17–

Figure 3b. Connections for 1.3 V Linear Regulator

The maximum current output from the circuit is largely depen­dent on the MOSFET device. For the SI2301 shown, 250 mA
can be delivered. The regulated output voltage should have bulk
decoupling and high frequency decoupling capacitors to ground
as required by the load. The regulator circuit will be stable for
capacitive loads between 0.1 µF and 47 µF.

It should be noted that the regulated output voltage, V

FB

, is
proportional to DVDD. Therefore, the percentage variation in
DVDD will also be seen at the regulated output voltage. The
load regulation is roughly equal to the ON resistance of the
MOSFET device chosen. For the SI2301, this is about 60 mΩ.

AD9876

AGC TIMING CONSIDERATIONS

When implementing the AGC timing loop, it is important to
consider the delay and settling time of the Rx path in response
to a change in gain. Figure 4 shows the delay the receive signal
experiences through the blocks of the Rx path. Whether the gain
is programmed through the serial port or over the Tx [5:0] pins,
the gain takes effect immediately with the delays shown below.
When gain changes do not involve the CPGA, the new gain will
be evident in samples after seven ADC clock cycles. When the
gain change does involve the CPGA, it takes an additional 45 ns
to 70 ns due to the propagation delays of the buffer, LPF and
PGA. Table V, details the PGA programming map.

GAIN

REGISTER

5ns

DECODE

LOGIC

DIGITAL

HPF

1 CLK

CYCLE

ADC SHA

5 CLK

CYCLE

1/2 CLK

CYCLE

BUFFER

10ns

LPF

25ns or 50ns

PGA

10ns

Figure 4. AGC Timing

Transmit Port Timing

The AD9876 transmit port consists of a 6-bit databus Tx [5:0],
a clock, and a Tx SYNC signal. Two consecutive nibbles of the
Tx data are multiplexed together to form a 12-bit data-word.
The clock appearing on the CLK-A pin is a buffered version of
the internal Tx data sampling clock. Data from the Tx port is
read on the rising edge of this sampling clock. The Tx SYNC
signal is used to indicate to which word a nibble belongs. The
first nibble of every word is read while Tx SYNC is low, the
second nibble of that same word is read on the following Tx
SYNC high level. The timing is illustrated in the Figure 5.

t

SU

CLK-A

t

Tx SYNC

Tx [5:0]

Tx 0 LSB

Tx 1 MSB

HD

Tx 2 LSB

Tx 3 MSBTx 1 LSB Tx 2 MSB

Figure 5. Transmit Timing Diagram AD9876

The Tx Port is highly configurable and offers the following options.

Negative edge sampling can be chosen by two different methods;
either by setting the Tx Port Negative Edge Sampling Bit (Reg­ister 3, Bit 7) or the Invert CLK-A Bit (Register 8, Bit 6). The
main difference between the two methods is that setting Register
3, Bit 7 inverts the internal sampling clock and will affect only
the transmit path, even if CLK-A is used to clock the Rx
data. However, inverting CLK-A would affect both the Rx and
Tx paths if they both use CLK-A.

The first nibble of each word can be read in as the least signifi

cant

nibble by setting the Tx LS Nibble First Bit (Register 7, Bit 2).

Also, the Tx path can be used in a Reduced Resolution Mode
by setting the Tx Port Multiplexer Bypass Bit (Register 7, Bit

0). In this mode, the Tx data-word becomes six bits and is read
in a single cycle. The clocking modes are the same as described
above, but the level of Tx SYNC is irrelevant.

If Tx SYNC is low for more than one clock cycle, the last trans­mit data will read continuously until Tx SYNC is brought high
for the second nibble of a new transmit word. This feature can
be used to “flush” the interpolator filters with zeros.

PGA Adjust Timing

In addition to the serial port, the Tx [5:1] pins can be used to
write to the Rx Path Gain Adjust Bits (Register 6, Bits 4:0).
This provides a faster way to update the PGA gain. A high level
on the GAIN pin with Tx SYNC low programs the PGA setting
on either the rising edge or falling edge of CLK-A. The GAIN
pin must be held high, Tx SYNC must be held low, and GAIN
data must be stable for three clock cycles to successfully update
the PGA GAIN value. A low level on the GAIN pin enables data
to be fed to the interpolator and DAC.

t

SU

CLK-A

t

Tx SYNC

Tx [5:0]

GAIN

GAIN

HD

Figure 6. GAIN Programming

Receive Port Timing

The AD9876 receives port consists of a six bit databus Rx [5:0],
a clock, and an Rx SYNC signal. Two consecutive nibbles of the
Rx data are multiplexed together to form a 10-/12-bit data-word.
The Rx data is valid on the rising edge of CLK-A when the
ADC Clock Source PLL-B/2 Bit (Register 3, Bit 6) is set to 0.
The Rx SYNC signal is used to indicate to which word a nibble
belongs. The first nibble of every word is transmitted while Rx
SYNC is low, the second nibble of that same word is transmit­ted on the following Rx SYNC high level. When Rx SYNC is
low, the sampled nibble is read as the most significant nibble.
When the Rx SYNC is high, the sampled nibble is read as the
least significant nibble. The timing is illustrated in Figure 7.

t

HT

CLK-A/-B

t

Rx SYNC

Rx [5:0]

Rx 0 LSB

VT

Rx 1 MSB

Rx 1 LSB Rx 2 MSB

Rx 2 LSB

Rx 3 MSB

Figure 7. Receive Timing Diagram

The Rx Port is highly configurable and offers the following
options.

Negative edge sampling can be chosen by setting the Invert
CLK-A Bit (Register 8, Bit 6) or the Invert CLK-B Bit (Register
8, Bit 7), depending on the clock selected as the ADC sampling

–18–

REV. A

AD9876

SENABLE

SCLK

SDATA

t

DH

t

DS

t

DS

t

PWH

t

SCLK

t

PWL

INSTRUCTION BIT 7

INSTRUCTION BIT 6

SENABLE

SCLK

SDATA

DATA BIT n

DATA BIT n–1

t

DV

source. Inverting CLK-A would affect the Tx sampling edge as
well as the Rx sampling edge.

The first nibble of each word can be read in as the least signifi

cant

nibble by setting the Rx LS Nibble First Bit (Register 8, Bit 2).

Also, the Rx path can be used in a Reduced Resolution Mode
by setting the Rx Port Multiplexer Bypass Bit (Register 8, Bit

0). In this mode, the Rx data-word becomes six bits and is read
in a single cycle. The Clocking Modes are the same as described
above, but the level of Rx SYNC will stay low.

The Rx [5:0] pins can be put into a high impedance state by
setting the Three-State Rx Port Bit (Register 8, Bit 3).

SERIAL INTERFACE FOR REGISTER CONTROL

The serial port is a 3-wire serial communications port consisting of
a clock (SCLK), chip select (SENABLE), and a bidirectional
data (SDATA) signal. The interface allows read/write access to
all registers that configure the AD9876 internal parameters. Single
or multiple byte transfers are supported as well as MSB first or
LSB first transfer formats.

General Operation of the Serial Interface

Serial communication over the serial interface can be from 1 to
5 bytes in length. The first byte is always the instruction byte.
The instruction byte establishes whether the communication is
going to be a read or write access, the number of data bytes to
be transferred, and the address of the first register to be accessed.
The instruction byte transfer is complete immediately upon the
8th rising edge of SCLK after SENABLE is asserted. Likewise,
the data registers change immediately upon writing to the 8th bit
of each data byte.

Instruction Byte

The instruction byte contains the following information as
shown below.

Bits I4:I0 – A4:A0

These bits determine which register is accessed during the data
transfer portion of the communications cycle. For multibyte
transfers, this address is the starting byte address. The remain­ing register addresses are generated by the AD9876/AD9875.

Serial Interface Port Pin Description

SCLK—Serial Clock

The serial clock pin is used to synchronize data transfers to and
from the AD9876 and to run the internal state machines. SCLK
maximum frequency is 25 MHz. All data transmitted to the
AD9876 is sampled on the rising edge of SCLK. All data read
from the AD9876 is validated on the rising edge of SCLK and is
updated on the falling edge.

SENABLE—Serial Interface Enable

The SENABLE pin is active low. It enables the serial communi­cation to the device. SENABLE select should stay low during
the entire communication cycle. All input on the serial port is
ignored when SENABLE is inactive.

SDATA—Serial Data I/O

The signal on this line is sampled on the first eight rising edges
of SCLK after SENABLE goes active. Data is then read from or
written to the AD9876 depending on what was read.

Figures 8 and 9 show the timing relationships between the three
SPI signals.

Table II. Instruction Byte Information

BSMBSL

7I6I5I4I3I2I1I0I

W/R1N0N4A3A2A1A0A

Bit I7 – R/W

This bit determines whether a read or a write data transfer will
occur after the instruction byte write. Logic high indicates read
operation; logic zero indicates a write operation.

Bits I6:I5 – N1:N0

These two bits determine the number of bytes to be transferred
during the data transfer cycle. The bit decodes are shown in the
table below.

Table III. Decode Bits

N1:N0 Description

0:0 Transfer 1 Byte
0:1 Transfer 2 Bytes
1:0 Transfer 3 Bytes

REV. A

1:1 Transfer 4 Bytes

–19–

Figure 8. Timing Diagram Register Write to AD9876

Figure 9. Timing Diagram Register Read from AD9876

MSB/LSB Transfers

The AD9876 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. The
bit order is controlled by the SPI LSB First Bit (Register 0, Bit

6). The default value is 0, MSB first. Multibyte data transfers in
MSB format can be completed by writing an instruction byte
that includes the register address of the last address to be accessed.
The AD9876 will automatically decrement the address for each
successive byte required for the multibyte communication cycle.

When the SPI LSB First Bit (Register 0, Bit 6) is set high, the
serial port interprets both instruction and data bytes LSB first.
Multibyte data transfers in LSB format can be completed by
writing an instruction byte that includes the register address of

AD9876

the first address to be accessed. The AD9876 will automatically
increment the address for each successive byte required for the
multibyte communication cycle.

Figures 10a and 10b show how the serial port words are built
for each of these modes.

SENABLE

INSTRUCTION CYCLE DATA TRANSFER CYCLE

Notes on Serial Port Operation

The serial port is disabled and all registers are set to their default
values during a hardware reset. During a software reset, all
registers except Register 0 are set to their default values. Regis­ter 0 will remain at the last value sent, with the exception that
the Software Reset Bit will be set to 0.

The serial port is operated by an internal state machine and is
dependent on the number of SCLK cycles since the last time
SENABLE went active. On every eighth rising edge of SCLK, a

SCLK

I6

SDATA

R/W

I5

(N)

(N)

I3I4

I2 I1 I0

D7ND6

N

D0

D2

D1

0

0

0

Figure 10a. Serial Register Interface Timing MSB-First

byte is transferred over the SPI. During a multibyte write cycle,
this means the registers of the AD9876 are not simultaneously
updated but occur sequentially. For this reason, it is recom­mended that single byte transfers be used when changing the
SPI configuration or performing a software reset.

SENABLE

SCLK

SDATA

INSTRUCTION CYCLE DATA TRANSFER CYCLE

I6

I5

I0

I3 I4I2I1

R/W

(N)

(N)

D2

D0

D1

0

0

0

D7

ND6N

Figure 10b. Serial Register Interface Timing LSB-First

Table IV. Register Layout

Address Default
(hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (hex) Comments

0 SPI Software 0 × 00 Read/Write

LSB First Reset

1 Power- Power- Power- Power- Power- Power- Power- Power- 0 × 00 Read/Write

Down Down Down Down Down Down Down Down PWR DN
Regulator PLL-B PLL-A DAC Interpolator Rx ADC and Rx LPF and Pin Low

Reference FPGA CPGA

2 Power- Power- Power- Power- Power- Power- Power- Power- 0 × 9F Read/Write

Down Down Down Down Down Down Down Down PWR DN
Regulator PLL-B PLL-A DAC Interpolator Rx ADC and Rx LPF and Pin High

Reference FPGA CPGA

3Tx Port ADC Clock PLL-B PLL-B PLL-A 0 × 02 Read/Write

Negative Source (×M) Multiplier (N) Divider (×M) Multiplier
EdgePLL-B/2 <5:4> <3:3> <1:0>
Sampling

4Rx Port Rx LPF Rx Path Rx Digital Fast ADC Wideband Enable Rx LPF 0 × 01 Read/Write

Negative Tuning DC Offset HPF Sampling Rx LPF 1-Pole Bypass
Edge In Progress Correction Bypass Rx LPF
Sampling (Read-Only)

5Rx LPF fc Adjust <7:0> 0 × 80 Read/Write

6 PGA Rx Path Gain Adjust <4:0> 0 × 00 Read/Write

Gain Set
by Register

7Interpolation Filter Select Power-Down Tx Port Tx Port 0 × 00 Read/Write

<3:0> Interpolator LS Nibble Demultiplexer

at First Bypass

Tx QUIET

Pin Low

8 Invert Invert Disable Disable Three-State Rx Port Rx Port 0 × 00 Read/Write

CLK-B CLK-A CLK-B CLK-A Rx Port LS Nibble Multiplexer

First Bypass

FDie Revision Number <3:0> Read- Only

–20–

REV. A

AD9876

REGISTER PROGRAMMING DEFINITIONS
REGISTER 0 – RESET/SPI CONFIGURATION
Bit 5: Software Reset

Setting this bit high resets the chip. The PLLs will relock to the
input clock and all registers (except Register 0 × 0, Bit 6) revert to
their default values. Upon completion of the reset, Bit 5 is reset to 0.

The content of the interpolator stages are not cleared by software
or hardware resets. It is recommended to “flush” the transmit
path with zeros before transmitting data.

Bit 6: SPI LSB First

Setting this bit high causes the serial port to send and receive
data least significant bit (LSB) first. The default low state con­figures the serial port to send and receive data most significant
bit (MSB) first.

REGISTERS 1 AND 2—POWER-DOWN

The combination of the PWR DN pin and Registers 1 and 2
allow for the configuration of two separate pin selectable power
settings. The PWR DN pin selects between two sets of individually
programmed operation modes.

When the PWR DN pin is low, the functional blocks corre­sponding to the bits set in Register 1 will be powered down.

When the PWR DN pin is high, the functional blocks corre­sponding to the bits set in Register 2 will be powered down.

Bit 0: Power-Down Receive Filter and CPGA

Setting this bit high powers down and bypasses the Rx LPF and
coarse programmable gain amplifier.

Bit 1: Power-Down ADC and FPGA

Setting this bit high powers down the ADC and fine program­mable gain amplifier (FPGA).

Bit 2: Power-Down Rx Reference

Setting this bit high powers down the ADC reference. This bit
should be set if an external reference is applied.

Bit 3: Power-Down Interpolators

Setting this bit high powers down the transmit digital interpolators.
It does not clear the content of the data path.

Bit 4: Power-Down DAC

Setting this bit high powers down the transmit DAC.

Bit 5, Bit 6: Power-Down PLL-A, PLL-B

Setting these bits high powers down the on-chip phase-lock
loops that generated CLK-A and CLK-B, respectively. When
powered down, these clocks are high impedance.

Bit 7: Power-Down Regulator

Setting this bit high powers down the on-chip voltage control regulator.

REGISTER 3—CLOCK SOURCE CONFIGURATION

The AD9876 integrates two independently programmable PLLs
referred to as PLL-A and PLL-B. The outputs of the PLLs are
used to generate all the chips internal and external clock signals
from the f
from PLL-A. If f

signal. All Tx path clock signals are derived

CLKIN

is programmed as the ADC sampling

CLKIN

clock source, then the Rx port clocks are also derived from
PLL-A. Otherwise, the ADC sampling clock is PLL-B/2 and the
Rx path clocks are derived from PLL-B.

There is a restriction that the values of L and K both be equal to
4 when f

is selected as the ADC sampling clock source.

CLKIN

However, the best receive path performance is obtained when

f

is selected as the ADC sampling clock source and should

CLKIN

be used as the ADC sampling clock whenever possible.

Bit 1, 0: PLL-A Multiplier

Bits 1 and 0 determine the multiplication factor (L) for PLL-A
and the DAC sampling clock frequency, f

f

= L × f

DAC

CLKIN

DAC.

Bit 1, 0

0, 0: L = 1
0, 1: L = 2
1, 0: L = 4
1, 1: L = 8

Bit 5 to 2: PLL-B Multiplier/Divider

Bits 5 to 2 determine the multiplication factor (M) and division
factor (N) for the PLL-B and the CLK-B frequency. For multi­plexed 10-/12-bit data, f
6-bit data, f

CLK-B

= (f

= f

CLK-B

/2) × M/N. All nine combinations of M

CLKIN

× M/N. For nonmultiplexed

CLKIN

and N values are valid, yielding seven unique M/N ratios.

Bit 5,4 Bit 3,2

0, 0: M = 3 0, 0: N = 2
0, 1: M = 4 0, 1: N = 4
1, 0: M = 6 1, 0: N = 1

Bit 6: ADC Clock Source PLL-B/2

Setting Bit 6 high selects PLL-B/2 as the ADC sampling clock
source. In this mode, the Rx data and CLK-B will run at a rate
of f

Setting Bit 6 low selects the f

. Rx SYNC will run at f

CLK-B

CLKIN

/2.

CLK-B

signal as the ADC sampling
clock source. This mode of operation yields the best ADC
performance if an external crystal is used or a low jitter clock
source drives the OSCIN pin.

Bit 7: Tx Port Negative Edge Sampling

Setting Bit 7 high will cause the Tx Port to sample the Tx DATA
and Tx SYNC on the falling edge of CLK-A. By default, the Tx
Port sampling occurs on the rising edge of CLK-A. The timing
is shown in Figure 5.

REGISTER 4—RECEIVE FILTER SELECTION

The AD9876 receive path has a continuous time 4-pole LPF
and a 1-pole digital HPF. The 4-pole LPF has two selectable
cutoff frequencies. Additionally, the filter can be tuned around
those two cutoff frequencies. These filters can also be bypassed
to different degrees as described below.

The continuous time 4-pole low-pass filter is automatically
calibrated to one of two selectable cutoff frequencies.

The cutoff frequency f
ADC sampling frequency f

is described as a function of the

CUTOFF

and can be influenced (±30%) by

ADC

the Rx Filter Tuning Target word in Register 5.

ff64 64 Target

CUTOFF LOW ADC

ff158 64 Target

CUTOFF HIGH ADC

Bit 0: Rx LPF Bypass

=× +

=× +

()

()

Setting this bit high bypasses the 4-pole LPF. The filter is auto­matically powered down when this bit is set.

Bit 1: Enable 1-Pole Rx LPF

The AD9876 can be configured with an additional 1-pole ~16 MHz
input filter for applications that require steeper filter roll-off or
want to use the 1-pole filter instead of the 4-pole receive low­pass filter. The 1-pole filter is untrimmed and subject to cutoff
frequency variations of ⫾20%.

REV. A

–21–

AD9876

Bit 2: Wideband Rx LPF

This bit selects the nominal cutoff frequency of the 4-pole LPF.
Setting this bit high selects a nominal cutoff frequency of 28.8 MHz.
When the wideband filter is selected, the Rx path gain is limited
to 30 dB.

Bit 3: Fast ADC Sampling

Setting this bit increases the quiescent current in the SVGA
block. This may provide some performance improvement
when the ADC sampling frequency is greater than 50 MSPS
(in 6-Bit Mode).

Bit 4: Rx Digital HPF Bypass

Setting this bit high bypasses the 1-pole digital HPF that follows
the ADC. The digital filter must be bypassed for ADC sampling
above 50 MSPS.

Bit 5: Rx Path DC Offset Correction

Writing a 1 to this bit triggers an immediate receive path offset
correction and reads back zero after the completion of the offset
correction.

Bit 6: Rx LPF Tuning in Progress

This bit indicates when the receive filter calibration is in progress.
The duration of a receive filter calibration is about 500 ms.
Writing to this bit has no effect.

Bit 7: Rx Port Negative Edge Sampling

Setting this bit high disables the automatic background receive
filter calibration. The AD9876 automatically calibrates the
receive filter on reset and every few (~2) seconds thereafter to
compensate for process and temperature variation, power sup­ply, and long term drift. Programming a 1 to this bit disables
this function. Programming a 0 triggers an immediate first cali­bration and enables the periodic update.

REGISTER 5—RECEIVE FILTER TUNING TARGET

This register sets the filter tuning target as a function of f

OSCIN

.

See Register 4 description.

REGISTER 6—Rx PATH GAIN ADJUST

The AD9876 uses a combination of a continuous time PGA
(CPGA) and a switched capacitor PGA (SPGA) for a gain range
of –6 dB to +36 dB with a resolution of 2 dB. The Rx path gain
can be programmed over the serial interface by writing to the
Rx Path Gain Adjust Register or directly using the GAIN and
MSB aligned Tx [5:1] Bits. The register default value is 0 × 00
for the lowest gain setting (–6 dB). The register always reads
back the actual gain setting irrespective of which of the two
programming modes were used.

Table V describes the gains and how they are achieved as a
function of the Rx Path adjust bits.

Bit 5: PGA Gain Set by Register

Setting this bit high will result in the Rx Path Gain being set by
writing to the PGA Gain Control Register. Default is zero which
selects writing the gain through the Tx [5:1] pins in conjunction
with the gain pin.

Table V. PGA Programming Map

Rx Path Rx Path CPGA SPGA
Gain [4:0] Gain Gain Gain

0 × 00 –6 –6 0
0 × 01 –4 –6 2
0 × 02 –2 –6 4
0 × 03 0 –6 6
0 × 04 2 –6 8
0 × 05 4 –6 10
0 × 06 606
0 × 07 808
0 × 08 10 0 10
0 × 09 12 6 6
0 × 0A 14 6 8
0 × 0B 16 6 10
0 × 0C 18 12 6
0 × 0D 20 12 8
0 × 0E 22 12 10
0 × 0F 24 18 6
0 × 10 26 18 8
0 × 11 28 18 10
0 × 12* 30/30 18/24 12/6
0 × 13* 30/32 18/24 12/8
0 × 14* 30/34 18/24 12/10
0 × 15* 30/36 18/24 12/12

*When the Wideband Rx Filter Bit is set high, the Rx Path Gain is limited to

30 dB. The first of the two values in the chart refers to this mode. The second
number refers to the mode when the lower Rx LPF Cutoff Frequency is cho­sen, or the Rx LPF Filter is bypassed.

REGISTER 7—TRANSMIT PATH SETTINGS

The AD9876 transmit path has a programmable interpolation
filter that proceeds the transmit DAC. The interpolation filter
can be programmed to operate in seven different modes. Also,
the digital interface can be programmed to operate in several
different modes. These modes are described below.

Bit 0: Transmit Port Demultiplexer Bypass

Setting Bit 0 high bypasses the input data demultiplexer. In this
mode, consecutive nibbles on the Tx [5:0] pins are treated as
individual words to be sent through the Tx path. This creates a
six bit data path. The state of Tx SYNC is ignored in this mode.

Bit 2: Transmit Port Least Significant Nibble First

Setting Bit 2 high reconfigures the AD9876 for a Transmit
Mode that expects least significant nibble before the most
significant nibble.

Bit 3: Power-Down Interpolator at Tx QUIET Pin Low

Setting Bit 3 high enables the Tx QUIET pin to shut off the
DAC output. If the bit is set to 1, then pulling the Tx QUIET
pin low will power down the interpolator filters. In most appli­cations, the interpolator filter will need to be flushed with 0s
before or after being powered down.

–22–

REV. A

AD9876

Bit 4 to Bit 7: Interpolation Filter Select

Bits 4 to 7 define the interpolation filter characteristics and
interpolation rate.
Bits 7:4;
0 × 2; Interpolation Bypass
0 × 0; see TPC 1. 4× Interpolation, LPF
0 × 1; see TPC 2. 2× Interpolation, LPF
0 × 4; see TPC 3. 4× Interpolation, BPF, Adjacent Image
0 × 5; see TPC 4. 2× Interpolation, BPF, Adjacent Image
0 × 8; see TPC 5. 4× Interpolation, BPF, Lower Image
0 × C; see TPC 6. 4× Interpolation, BPF, Upper Image

The interpolation factor has a direct influence on the CLK-A
output frequency. When the transmit input data multiplexer is
enabled (10-/12-Bit Mode):

ffK

CLK A DAC−

=×2

where K is the interpolation factor. When the transmit input data
multiplexer is disabled (5-/6-Bit Mode):

ffK

CLK A DAC−

=

where K is the interpolation factor.

REGISTER 8—RECEIVER AND CLOCK OUTPUT SETTINGS

Bit 0: Rx Port Multiplexer Bypass

Setting this bit high bypasses the Rx Port output multiplexer.
This will output only the 6 MSBs of the ADC word. This mode
enables ADC sampling rates above 55 MSPS.

Bit 2: Rx Port LS Nibble First

Reconfigures the AD9876 for a Receive Mode that expects less
significant bits before the most significant bits.

Bit 3: Three-State Rx Port

This bit sets the receive output Rx [5:0] into a high impedance
Three-State Mode. It allows for sharing the bus with other devices.

Bit 4, Bit 5: Disable CLK-A, Disable CLK-B

Setting Bit 4 or Bit 5 stops CLK-A or CLK-B, respectively,
from toggling. The output is held low. Setting Bit 4 or Bit 5
fixes CLK-A or CLK-B to a low output level, respectively.

Bit 6: Invert CLK-A

Setting Bit 6 high inverts the CLK-A output signal.

Bit 7: Invert CLK-B

Setting this bit high inverts the CLK-B output signal. This effec­tively changes the timing of the Rx [5:0] and Rx SYNC signals
from rising edge triggered to falling edge triggered with respect
to the CLK-B signal.

REGISTER F, DIE REVISION

This register stores the die revision of the chip. It is a Read­Only Register.

PCB DESIGN CONSIDERATIONS

Although the AD9876 is a mixed-signal device, the part should
be treated as an analog component. The digital circuitry on-chip
has been specially designed to minimize the impact that the
digital switching noise will have on the operation of the analog

circuits. Following the power, grounding and layout recommen­dations in this section will help you get the best performance
from the MxFE.

Component Placement

If the three following guidelines of component placement are
followed, chances for getting the best performance from the
MxFE

are greatly increased. First, manage the path of return
currents flowing in the ground plane so that high frequency
switching currents from the digital circuits do not flow on the
ground plane under the MxFE or analog circuits. Second, keep
noisy digital signal paths and sensitive receive signal paths as
short as possible. Third, keep digital (noise generating) and
analog (noise susceptible) circuits as far away from each other
as possible.

In order to best manage the return currents, pure digital circuits
that generate high switching currents should be closest to the
power supply entry. This will keep the highest frequency return
current paths short and prevent them from traveling over the
sensitive MxFE and analog portions of the ground plane. Also,
these circuits should be generously bypassed at each device
which will further reduce the high frequency ground currents.
The MxFE should be placed adjacent to the digital circuits,
such that the ground return currents from the digital sections
will not flow in the ground plane under the MxFE. The analog
circuits should be placed furthest from the power supply.

The AD9876 has several pins that are used to decouple sensitive
internal nodes. These pins are REFIO, REFB, and REFT. The
decoupling capacitors connected to these points should have
low ESR and ESL. These capacitors should be placed as close
to the MxFE as possible and be connected directly to the analog
ground plane.

The resistor connected to the FSADJ pin should also be placed close
to the device and connected directly to the analog ground plane.

Power Planes and Decoupling

The AD9876 evaluation board demonstrates a good power
supply distribution and decoupling strategy. The board has four
layers: two signal layers, one ground plane, and one power plane.
The power plane is split into a 3VDD section used for the 3 V
digital logic circuits, a DVDD section used to supply the digital
supply pins of the AD9876, an AVDD section used to supply
the analog supply pins of the AD9876/AD9875, and a VANLG
section that supplies the higher voltage analog components on
the board. The 3VDD section will typically have the highest
frequency currents on the power plane and should be kept the
furthest from the MxFE and analog sections of the board. The
DVDD portion of the plane brings the current used to power
the digital portion of the MxFE to the device. This should be
treated similarly to the 3VDD power plane and be kept from
going underneath the MxFE or analog components. The MxFE
should largely sit on the AVDD portion of the power plane.
The AVDD and DVDD power planes may be fed from the same
low noise voltage source; however, they should be decoupled
from each other to prevent the noise generated in the DVDD
portion of the MxFE from corrupting the AVDD supply. This
can be done by using ferrite beads between the voltage source and
DVDD and between the source and the AVDD. Both DVDD
and AVDD should have a low ESR, bulk decoupling capacitor

REV. A

–23–

AD9876

on the MxFE side of the ferrite as well as a low ESR, ESL
decoupling capacitors on each supply pin (i.e., the AD9876
requires five power supply decoupling caps, one each on Pins 5,
38, 47, 14, and 35). The decoupling caps should be placed as close
to the MxFE supply pins as possible. An example of the proper
decoupling is shown in the AD9876 evaluation board schematic.

Ground Planes

In general, if the component placing guidelines discussed earlier
can be implemented, it is best to have at least one continuous
ground plane for the entire board. All ground connections should be
made as short as possible. This will result in the lowest impedance
return paths and the quietest ground connections.

If the components cannot be placed in a manner that will keep the
high frequency ground currents from traversing under the MxFE
and analog components, it may be necessary to put current steering
channels into the ground plane to route the high frequency
currents around these sensitive areas. These current

steering

channels should be made only when and where necessary.

OUTLINE DIMENSIONS

48-Lead Plastic Quad Flatpack [LQFP]

1.4 mm Thick
(ST-48)

Dimensions shown in millimeters

Signal Routing

The digital Rx and Tx signal paths should be kept as short as
possible. Also, the impedance of these traces should have
a controlled characteristic impedance of about 50 Ω. This will
prevent poor signal integrity and the high currents that can
occur during undershoot or overshoot caused by ringing. If the
signal traces cannot be kept shorter than about 1.5 inches, series
termination resistors (33 Ω to 47 Ω) should be placed close to
all signal sources. It is a good idea to series-terminate all clock
signals at their source, regardless of trace length.

The receive Rx⫹ and Rx⫺ signals are the most sensitive
signals on the entire board. Careful routing of these signals
is essential for good receive path performance. The Rx⫹ and
Rx⫺ signals form a differential pair and should be routed
together as a pair. By keeping the traces adjacent to each other,
noise coupled onto the signals will appear as common mode and
will be largely rejected by the MxFE receive input. Keeping the
driving point impedance of the receive signal low and placing
any low-pass filtering of the signals close to the MxFE will
further reduce the possibility of noise corrupting these signals.

C02599–0–10/02(A)

1.45

1.40

1.35

0.15

0.05

SEATING

PLANE

ROTATED 90ⴗ CCW

VIEW A

0.08 MAX
COPLANARITY

1.60 MAX

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09

7ⴗ

3.5ⴗ
0ⴗ

COMPLIANT TO JEDEC STANDARDS MS-026BBC

PIN 1

INDICATOR

VIEW A

1

12

0.50

BSC

48

13

9.00 BSC

TOP VIEW

(PINS DOWN)

37

24

36

25

0.27

0.22

0.17

7.00

BSC

Revision History

Location Page

10/02—Data Sheet changed from REV. 0 to REV. A.

Changes to to Table IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Changes to REGISTER 3—CLOCK SOURCE CONFIGURATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PRINTED IN U.S.A.

–24–

REV. A