Fourth Order Low-Pass Filter 12 MHz or 26 MHz
with Bypass
–6 dB to +36 dB Programmable Gain Amplifier
Internal Clock Multiplier (PLL)
Clock Outputs
Voltage Regulator Controller
48-Lead LQFP Package
APPLICATIONS
Powerline Networking
Home Phone Networking
xDSL
Broadband Wireless
Home RF
PRODUCT DESCRIPTION
The AD9875 is a single-supply broadband modem mixedsignal front end (MxFE) IC. The devices contain a transmit
path Interpolation Filter and DAC, and a receive path PGA,
LPF, and ADC supporting a variety of broadband modem
applications. Also on chip is a PLL clock multiplier that provides all required clocks from a single crystal or clock input.
The AD9875 provides 10-bit converter performance on both
the Tx and Rx paths.
The TxDAC+ uses a selectable digital 2× or 4× interpolation
low-pass or band-pass filter to further oversample transmit
data and reduce the complexity of analog reconstruction filtering.
The transmit path signal bandwidth can be as high as 26 MHz
at an input data rate of 64 MSPS. The 10-bit DAC provides
differential current outputs for optimum noise and distortion
performance. The DAC full-scale current can be adjusted
from 2 mA to 20 mA by a single resistor, providing 20 dB of
additional gain range.
The receive path consists of a PGA, LPF, and ADC. The two-stage
PGA has a gain range of –6 dB to +36 dB, and is programmable
in 2 dB steps, adding 42 dB of dynamic range to the receive path.
FUNCTIONAL BLOCK DIAGRAM
PWR DN
Tx QUIET
GAIN
Tx [5:0]
Tx SYNC
CLK-A
CLK-B
Rx SYNC
Rx [5:0]
SPORT
3
1010
Tx
MUX
REGISTER
CONTROL
Rx
MUX
10
Kx INTERPOLATION
LPF/BPF
PLL-A
CLOCK GEN
PLL-B
M/N
ADC
L
PGA
AD9875
TxDAC+
V
REF
VRC
LPF
PGA
Tx+
Tx–
GATE
FB
OSCIN
XTAL
Rx+
Rx–
The receive path LPF cutoff frequency can be programmed to either
12 MHz or 26 MHz. The filter cutoff frequency can also be tuned
or bypassed where filter requirements differ. The 10-bit ADC
uses a multistage differential pipeline architecture to achieve
excellent dynamic performance with low power consumption.
The AD9875 provides a voltage regulator controller (VRC) that
can be used with an external power MOSFET transistor to form
a cost-effective 1.3 V linear regulator.
The digital transmit and receive ports are each multiplexed to a
bus width of 5/6 bits and are clocked at a frequency of twice the
10-bit word rate.
The AD9875 ADC and/or DAC can also be used at higher
sampling rates as high as 64 MSPS in a 5-bit resolution nonmultiplexed mode.
The AD9875 is pin compatible with the 12-bit AD9876. Both are
available in a space-saving 48-lead LQFP package. They are specified
over the industrial (–40°C to +85°C) temperature range.
MxFE is a trademark of Analog Devices, Inc.
TxDAC+ is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
ResolutionFullII10Bits
Conversion RateFullII10128MHz
Full-Scale Output CurrentFullII21020mA
Voltage Compliance RangeFullII–0.5+1.5V
Gain ErrorFullII–5± 2+5% FS
Output OffsetFullII0719µA
Differential Nonlinearity25°CIII0.5LSB
Integral Nonlinearity25°CIII1LSB
Output Capacitance25°CIII5pF
Phase Noise @ 1 kHz Offset, 10 MHz Signal25°CIII–90dBc/Hz
Signal-to-Noise and Distortion (SINAD)
10 MHz Analog Out AD9875 (20 MHz BW)FullI5961dB
Wideband SFDR (to Nyquist, 64 MHz Max)25°CIII
5 MHz Analog Out25°CIII78dBc
10 MHz Analog Out25°CIII72dBc
Narrowband SFDR (3 MHz Window)
10 MHz Analog Out25°CIII80dBc
IMD (f1 = 6.9 MHz, f2 = 7.1 MHz)25°CIII–76dBFS
Rx PATH CHARACTERISTICS
ResolutionFullII10Bits
Conversion RateFullII7.555MHz
Pipeline Delay, ADC Clock CyclesFullII5.5Cycles
DC Accuracy
Differential Nonlinearity25°CII–1.0± 0.25+1.0LSB
Integral Nonlinearity25°CII–2.0± 0.5+2.0LSB
Dynamic Performance
= –0.5 dBFS, f = 5 MHz)
(A
IN
OSCIN
= 32 MHz
@ f
Signal-to-Noise and Distortion Ratio (SINAD)25°CIII59.6dB
Effective Number of Bits (ENOB)25°CIII9.5Bits
Signal-to-Noise Ratio (SNR)25°CIII60dB
Total Harmonic Distortion (THD)25°CIII–65dB
Spurious Free Dynamic Range (SFDR)25°CIII68dB
Dynamic Performance
AIN = –0.5 dBFS, f = 10 MHz
(
PLLB/2
= 50 MHz
@ F
)
Signal-to-Noise and Distortion Ratio (SINAD)25°CIII54dB
Effective Number of Bits (ENOB)25°CIII8.6Bits
Signal-to-Noise Ratio (SNR)25°CIII55dB
Total Harmonic Distortion (THD)25°CIII–61dB
Spurious Free Dynamic Range (SFDR)25°CIII68dB
–2–
REV. A
Page 3
AD9875
Test
ParameterTempLevelMinTypMaxUnit
Rx PATH GAIN/OFFSET
Minimum Programmable Gain25°CIII–6dB
Maximum Programmable Gain
(12 MHz Filter)25°CIII36dB
(26 MHz Filter)25°CIII30dB
Gain Step Size25°CIII2dB
Gain Step Accuracy25°CIII± 0.4dB
Gain Range Error25°CIII± 1.0dB
Offset Error, PGA Gain = 0 dB (AD9875)25°CIII± 4.0LSB
Absolute Gain Error, PGA Gain = 0 dB25°CIII±0.8dB
Rx PATH INPUT CHARACTERISTICS
Input Voltage Range25°CIII4Vppd
Input Capacitance25°CIII4pF
Differential Input Resistance25°CIII270Ω
Input Bandwidth (–3 dB)25°CIII50MHz
Input Referred Noise (at +36 dB Gain with Filter) 25°CIII16µV rms
Input Referred Noise (at –6 dB Gain with Filter)25°CIII684µV rms
Common-Mode Rejection25°CIII40dB
Rx PATH LPF (Low Cutoff Frequency)
Cutoff Frequency25°CIII12MHz
Cutoff Frequency Variation25°CIII± 7%
Attenuation @ 22 MHz25°CIII20dB
Passband Ripple25°CIII± 1.0dB
Group Delay Variation25°CIII30ns
Settling Time
(to 1% FS, Min to Max Gain Change)25°CIII150ns
Total Harmonic Distortion at Max Gain (THD)25°CIII–68dBc
Rx PATH LPF (High Cutoff Frequency)
Cutoff Frequency25°CIII26MHz
Cutoff Frequency Variation25°CIII± 7%
Attenuation @ 44 MHz25°CIII20dB
Passband Ripple25°CIII± 1.2dB
Group Delay Variation25°CIII15ns
Settling Time
(to 1% FS, Min to Max Gain Change)25°CIII80ns
Total Harmonic Distortion at Max Gain (THD)25°CIII–65dBc
Rx PATH DIGITAL HPF
Latency (ADC Clock Source Cycles)FullII1Cycle
Roll-Off in StopbandFullII6dB/Octave
–3 dB FrequencyFullIIf
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
AD9875BST–40°C to +85°C48-Lead LQFPST-48
AD9875-EB–40°C to +85°CEvaluation Board
AD9875BSTRL–40°C to +85°CBST Reel
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9875 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–5–
Page 6
AD9875
PIN FUNCTION DESCRIPTIONS
PinNameFunction
1OSCINCrystal Oscillator Inverter Input
2SENABLESerial Bus Enable Input
3SCLKSerial Bus Clock Input
4SDATASerial Bus Data I/O
5, 38, 47AVDDAnalog 3.3 V Power Supply
6, 9, 39, 42, 43, 46AVSSAnalog Ground
7Tx+Transmit DAC+ Output
8Tx–Transmit DAC– Output
10FSADJDAC Full-Scale Output Current Adjust with External Resistor
11REFIODAC Bandgap Decoupling Node
12PWR DNPower-Down Input
13DVSSDigital Ground
14DVDDDigital 3.3 V Power Supply
15FBRegulator Feedback Input
16GATERegulator Output to FET Gate
17GAINTransmit Data Port (Tx[5:0]) Mode Select Input
18Tx QUIETTransmit Quiet Input
19–24Tx[5:0]Transmit Data Input
25Tx SYNCTransmit Synchronization Strobe Input
26CLK-AL × f
27CLK-BM/N × f
28Rx SYNCReceive Data Synchronization Strobe Output
29–34Rx[5:0]Receive Data Output
35DRVDDDigital I/O 3.3 V Power Supply
36DRVSSDigital I/O Ground
37RESETReset Input
40REFBADC Reference Decoupling Node
41REFTADC Reference Decoupling Node
44Rx+Receive Path + Input
45Rx–Receive Path – Input
48XTALCrystal Oscillator Inverter Output
Clock Output
OSCIN
OSCIN
Clock Output
OSCIN
SENABLE
SCLK
SDATA
AVDD
AVSS
Tx+
Tx–
AVSS
FSADJ
REFIO
PWR DN
PIN CONFIGURATION
XTAL
AVDD
AVSS
Rx–
Rx+
AVSS
AVSS
AD9875
GAIN
Tx QUIET
Tx [5]
REFT
Tx [4]
48 4 7 46 4 5 4439 38 3743 42 41 40
1
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
DVSS
FB
DVDD
TOP VIEW
(Not to Scale)
GATE
–6–
REFB
Tx [3]
AVSS
Tx [2]
AVDD
Tx [1]
RESET
36
35
34
33
32
31
30
29
28
27
26
25
Tx [0]
DRVSS
DRVDD
Rx [0]
Rx [1]
Rx [2]
Rx [3]
Rx [4]
Rx [5]
Rx SYNC
CLK-B
CLK-A
Tx SYNC
REV. A
Page 7
AD9875
DEFINITIONS OF SPECIFICATIONS
CLOCK JITTER
The clock jitter is a measure of the intrinsic jitter of the PLL
generated clocks. It is a measure of the jitter from one rising
and of the clock with respect to another edge of the clock nine
cycles later.
DIFFERENTIAL NONLINEARITY ERROR
(DNL, NO MISSING CODES)
An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicates that all 1024
codes respectively, must be present over all operating ranges.
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code from
a line drawn from “negative full scale” through “positive full
scale.” The point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
PHASE NOISE
Single-sideband phase noise power density is specified relative to
the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the
carrier. Phase noise can be measured directly on a generated single
tone with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the carrier and
the offset (1 kHz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 log(rbw). It also adds
a correction factor that compensates for the implementation of the
resolution bandwidth, log display and detector characteristic.
OUTPUT COMPLIANCE RANGE
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation, resulting in nonlinear performance or breakdown.
SPURIOUS–FREE DYNAMIC RANGE (SFDR)
The difference, in dB, between the rms amplitude of the DACs
output signal (or ADC’s input signal) and the peak spurious
signal over the specified bandwidth (Nyquist bandwidth unless
otherwise noted).
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
the associated output data being made available.
OFFSET ERROR
First transition should occur for an analog value 1/2 LSB above
negative full scale. Offset error is defined as the deviation of the
actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur for an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
INPUT REFERRED NOISE
The rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in LSB,
and converted to an equivalent voltage. This results in a noise
figure that can be directly referred to the Rx input of the AD9875.
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
SINAD is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the number
of bits. Using the following formula,
N = (SINAD – 1.76) dB/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
POWER SUPPLY REJECTION
Power Supply Rejection specifies the converters maximum
full-scale change when the supplies are varied from nominal to
minimum and maximum specified voltages.
REV. A
–7–
Page 8
AD9875
–Typical Tx Digital Filter Performance Characteristics
TPC 21. Rx LPF Frequency Response, Low fC Nominal
Tuning Targets
LOG MAG5dB/REF 0dB–3.0dB
26.5MHz
0
1MHz10MHz100MHz
TPC 22. Rx LPF Frequency Response, High fC Nominal
Tuning Targets
1MHz10MHz100MHz
TPC 24. Rx LPF Group Delay, Low fC Nominal Tuning
Targets
DELAY5ns/REF 0s34.431ns
22.5MHz
0
1MHz10MHz100MHz
TPC 25. Rx LPF Group Delay, High fC, Nominal Tuning
Targets
LOG MAG5dB/REF 0dB–3.0dB
0
1MHz10MHz100MHz
14.5MHz
TPC 23. Rx LPF Frequency Response, Low fC, 0 60 and
0 96 Tuning Targets
DELAY10ns/REF 0s51.244ns
14.5MHz
0
1MHz10MHz100MHz
TPC 26. Rx LPF Group Delay, Low fC, 0 60 and 0 96
Tuning Targets
–12–
REV. A
Page 13
600
650
700
750
800
850
900
950
1000
ADC CLOCK CYCLES
ADC OUTPUT CODE
0510152025303540
f
ADC
= 50MHz
f
ADC
= 32MHz
Typical AC Characterization Curves for Rx Path
(f
ADC
AD9875
= 32 MHz)
LOG DELAY5dB/REF –2dB–5.1933dB
33.5MHz
1MHz10MHz100MHz
0
TPC 27. Rx LPF Frequency Response, High fC, 0 60 and
96 Tuning Targets
0
LOG MAG 5dB/REF 0dB –3.01dB
78.8MHz
0
LOG DELAY 5ns/REF 0s29.97ns
29.5MHz
0
1MHz10MHz100MHz
TPC 30. Rx LPF Group Delay, High fC, 0 60 and 0 96
Tuning Targets
700
600
V
500
400
FILTER ENABLED
10kHz100kHz1MHz
TPC 28. Rx HPF Frequency Response, f
1000
950
900
850
800
750
ADC OUTPUT CODE
700
650
600
0510152025303540
ADC CLOCK CYCLES
f
ADC
= 50MHz
f
ADC
ADC
= 32 MHz
= 32MHz
TPC 29. Rx Path Setting, 1/2 Scale Rising Step with Gain
Change
300
200
FILTER BYPASSED
ADC INPUT RMS NOISE –
100
0
–61442434
TPC 31. Rx Input Referred Noise vs. Gain @ f
= 1 MHz
f
IN
GAIN SETTING
–
dB
= 32 MSPS,
ADC
TPC 32. Rx Path Setting, 1/2 Scale Falling Step with Gain
Change
REV. A
–13–
Page 14
AD9875
Typical AC Characterization Curves for Rx Path
10.0
9.5
f
9.0
8.5
ENOB
8.0
7.5
7.0
OSCIN
f
PLLB/2
15253545
1020
304050
f
– MHz
S
TPC 33. Rx Path ENOB vs. f
10.0
f
9.5
9.0
8.5
ENOB
8.0
7.5
f
PLLB/2
OSCIN
ADC
60
f
58
56
54
52
MAGNITUDE – dB
50
48
OSCIN
f
PLLB/2
1020 25 301535 40 45 50
f
S
– MHz
TPC 34. Rx Path SNR vs. f
70
65
60
55
50
MAGNITUDE – dB
45
f
OSCIN
f
PLLB/2
(Gain = –6 dB, fIN = 5 MHz)
–50
–55
–60
–65
–70
MAGNITUDE – dB
–75
–80
ADC
TPC 35. Rx Path THD vs. f
–50
–55
–60
–65
–70
MAGNITUDE – dB
–75
f
PLLB/2
f
OSCIN
15 20 25 30 35 40 45 50
10
f
S
– MHz
f
PLLB/2
f
OSCIN
ADC
7.0
0
2468101214161820
TPC 36. Rx Path ENOB vs. f
10.0
9.5
9.0
ENOB
8.5
8.0
–60
f
POSCIN
612
f
– MHz
IN
f
PLLB/2
18243036
GAIN – dB
IN
TPC 39. Rx Path ENOB vs. Gain
40
04681021214161820
f
IN
– MHz
TPX 37. Rx Path SNR vs. f
65
f
60
55
MAGNITUDE – dB
50
45
–66
OSCIN
f
PLLB/2
0243036
1218
GAIN – dB
TPC 40. Rx Path SNR vs. Gain
–80
2468101214161820
0
IN
TPC 38. Rx Path THD vs. f
–50
–55
–60
MAGNITUDE - dB
–65
–70
0121830
–66
f
PLLB/2
f
– MHz
IN
f
OSCIN
GAIN – dB
IN
2436
TPC 41. Rx Path THD vs. Gain
–14–
REV. A
Page 15
AD9875
TRANSMIT PATH
The AD9875 transmit path consists of a Digital Interface Port,
a Programmable Interpolation Filter, and a Transmit DAC. All
clock signals required by these blocks are generated from the
signal by the PLL-A clock generator. The block diagram
f
OSCIN
below shows the interconnection between the major functional
components of the transmit path.
10
= L
AD9875
TxDAC+
f
OSCIN
f
OSCIN
Tx+
Tx–
OSCIN
XTAL
Tx QUIET
GAIN
Tx [5:0]
Tx SYNC
CLK-A
Tx
DEMUX
f
CLK-A
10
Kx INTERPOLATION
LPF/BPF
PLL-A
CLOCK GEN
L
f
DAC
Figure 1. Transmit Path Block Diagram
Digital Interface Port
The transmit Digital Interface Port has several modes of
operation. In its default configuration, the Tx Port accepts six
bit nibbles through the Tx[5:0] and TxSYNC pins and demultiplexes the data into 12-bit words before passing it to the
Interpolation Filter. The input data is sampled on the rising
edge of f
CLK-A
.
Additional programming options for the Tx Port allow; sampling
the input data on the falling edge of f
abling of f
, reversing the order of the nibbles, and inputting
CLK-A
, inversion or dis-
CLK–A
nibble widths of 5 bits/5 bits. Also, the Tx Port interface can be
controlled by the GAIN pin to provide direct access to the Rx
Path Gain Adjust register. All of these modes are fully described
in the Register Programming Definitions section of this data sheet.
The data format is two’s complement, as shown below:
The data can be translated to straight binary data format by
simply inverting the most significant bit.
The timing of the interface is fully described in the Transmit
Timing section of this data sheet.
PLL-A Clock Distribution
Figure 1 shows the clock signals used in the transmit path. The
DAC sampling clock, f
frequency equal to L × f
, is generated by DPLL-A. f
DAC
OSCIN
, where f
is the internal signal
OSCIN
DAC
has a
generated either by the crystal oscillator when a crystal is connected between the OSCIN and XTAL pins, or by the clock that
is fed into the OSCIN pin, and L is the multiplier programmed
through the serial port. L can have the values of 1, 2, 4, or 8.
The transmit path expects a new half-word of data at the rate
of f
. When the Tx multiplexer is enabled, the frequency
CLK-A
of the Tx port is:
ffKLfK
=×=× ×22
CLK ADACOSCIN−
where K is the interpolation factor that can be programmed to
be 1, 2, or 4.
When the Tx multiplexer is disabled, the frequency of the Tx port is:
ffKLfK
==×
CLK ADACOSCIN−
Interpolation Filter
The interpolation filter can be programmed to run at 2× and 4×
upsampling ratios in each of three different modes. The transfer
functions of these six configurations are shown in TPCs 1–6.
The X-axis of each of these figures corresponds to the frequency
normalized to f
. These transfer functions show both the
DAC
discrete time transfer function of the interpolation filters alone
and with the SIN(x)/x transfer function of the DAC. The Interpolation Filter can also be programmed into a pass-through mode
if no interpolation filtering is desired.
The contents of the interpolation filters are not cleared by
hardware or software resets. It is recommended to “flush” the
transmit data path with zeros before transmitting data.
Table I contains the following parameters as a function of the
mode that it is programmed:
Latency – the number of clock cycles from the time a digital
impulse is written to the DAC until the peak value is output at
the Tx± pins.
Flush – the number of clock cycles from the time a digital
impulse is written to the DAC until the output at the Tx± pins
settles to zero.
f
(0.1 dB, 3 dB) – This indicates the lower 0.1 dB or 3 dB
LOWER
cutoff frequency of the interpolation filter as a fraction of f
DAC
,
the DAC sampling frequency.
f
(0.1 dB, 3 dB) – This indicates the upper 0.1 dB or 3 dB
UPPER
cutoff frequency of the interpolation filter as a fraction of f
The AD9875 DAC provides differential output current on the
Tx+ and Tx– pins. The value of the output currents are complimentary, meaning that they will always sum to I
, the full-scale
FS
current of the DAC. For example, when the current from Tx+ is
at full-scale, the current from Tx– is zero. The two currents will
REV. A
–15–
Page 16
AD9875
typically drive a resistive load which will convert the output
currents to a voltage. The Tx+ and Tx– output currents are
inherently ground seeking and should each be connected to
matching resistors, R
, that are tied directly to AGND.
L
The full-scale output current of the DAC is set by the value of
the resistor placed from the FSADJ pin to AGND. The relationship between the resistor, R
, and the full-scale output current
SET
is governed by the following equation:
IR
= 39 4.
FSSET
The full-scale current can be set from 2 mA to 20 mA. Generally, there is a trade-off between DAC performance and power
consumption. The best DAC performance will be realized at an
of 20 mA. However, the value of IFS adds directly to the
I
FS
overall current consumption of the device.
The single-ended voltage output appearing at the Tx+ and
Tx– nodes are:
VIR
=×
TXTXL++
VIR
=×
TXTXL––
Note that the full-scale voltage of V
Tx+
and V
should not exceed
Tx–
the maximum output compliance range of 1.5 V to prevent signal
compression. To maintain optimum distortion and linearity
performance, the maximum voltages at V
Tx+
and V
should not
Tx–
exceed 0.5 V.
The single ended full-scale voltage at either output node will be:
VIR
=×
FSFSL
The differential voltage, V
VIIR
DIFFTXTXL
, appearing across V
DIFF
=
–
()
+
×
–
Tx+
and V
Tx–
is:
and
VIR
DIFF
=×
FS
—
FSL
For optimum performance, a differential output interface is
recommended since any common-mode noise or distortion can
be suppressed.
It should be noted that the differential output impedance of the
DAC is 2 × R
and any load connected across the two output
L
resistors will load down the output voltage accordingly.
RECEIVE PATH DESCRIPTION
The receive path consists of a two-stage PGA, a continuous time,
4-pole LPF, an ADC, a digital HPF and a digital data multiplexer.
Also working in conjunction with the receive path is an offset
correction circuit and a digital phase lock loop. Each of these
blocks will be discussed in detail in the following sections.
Programmable Gain Amplifier
The PGA has a programmable gain range from –6 dB to +36 dB
if the narrower (approximately 12 MHz) LPF bandwidth is
selected, or if the LPF is bypassed. If the wider (approximately
26 MHz) LPF bandwidth is selected, the gain range is –6 dB to
+30 dB. The PGA is comprised of two sections, a Continuous
Time PGA (CPGA) and a Switched Capacitor PGA (SPGA).
The CPGA has possible gain settings of –6, 0, 6, 12, 18, and 24.
The SPGA has possible gain settings of 0, 2, 4, 6, 8, 10, and 12 dB.
Table I shows how the gain is distributed for each programmed
gain setting.
The CPGA input appears at the device Rx+ and Rx– input pins.
The input impedance of this stage is nominally 270 Ω differen-
tial and is not gain dependent. It is best to ac-couple the input
signal to this stage and let the inputs self bias. This will lower the
offset voltage of the input signal, which is important at higher
gains, as any offset will lower the output compliance range of the
CPGA output. When the inputs are driven by direct coupling, the
dc level should be AVDD/2. However, this could lead to larger dc
offsets and consequently reduce the dynamic range of the Rx path.
Low-Pass Filter
The Low-Pass Filter (LPF) is a programmable, multistage,
fourth order low-pass filter comprised of two real poles and a
complex pole pair. The first real pole is implemented within the
CPGA. The second filter stage implements a complex pair of
poles. The last real pole is implemented in a buffer stage that
drives the SPGA.
There are two passband settings for the LPF. Within each passband the filters are tunable over about a ⫾30% frequency range.
The formula for the cutoff frequency is:
ff Tet
CUTOFF LOWADC
ff Tet
CUTOFF HIGHADC
=× +
=×+
64 64arg
()
158 64arg
()
Where Target is the decimal value programmed as the tuning
target in Register 5.
This filter may also be bypassed by setting Bit 0 of Register 4.
In this case, the bandwidth of the Rx path will decrease with
increasing gain and be approximately 50 MHz at the highest gain
settings.
ADC
The AD9875’s analog-to-digital converter implements a pipelined
multistage architecture to achieve high sample rates while consuming low power. The ADC distributes the conversion over
several smaller A/D subblocks, refining the conversion with
progressively higher accuracy as it passes the results from stage to
stage. As a consequence of the distributed conversion, ADCs require
a small fraction of the 2
N
comparators used in a traditional n-bit
flash-type A/D. A sample-and-hold function within each of the
stages permits the first stage to operate on a new input sample
while the remaining stages operate on preceding samples. Each
stage of the pipeline, excluding the last, consists of a low resolution
flash A/D connected to a switched capacitor DAC and interstage
residue amplifier (MDAC). The residue amplifier amplifies the
difference between the reconstructed DAC output and the flash
input for the next stage in the pipeline. One bit of redundancy is
used in each one of the stages to facilitate digital correction of
flash errors. The last stage simply consists of a flash A/D.
AINP
AINN
A/D
SHA
GAINSHA
D/A
A/D
D/A
CORRECTION LOGIC
A/D
GAIN
AD9875
Figure 2. ADC Theory of Operation
–16–
REV. A
Page 17
AD9875
The digital data outputs of the ADC are represented in two’s
complement format. They saturate to full-scale or zero when the
input signal exceeds the input voltage range.
The Maximum value will be output from the ADC when the
Rx+ input is 1V or more greater than the Rx– input. The Minimum value will be output from the ADC when the Rx– input is
1 V or more greater than the Rx+ input. This results in a full-scale
ADC voltage of 2 Vppd.
The data can be translated to straight binary data format by
simply inverting the most significant bit.
The best ADC performance will be achieved when the ADC
clock source is selected from f
OSCIN
and f
is provided from
OSCIN
a low jitter clock source. The amount of degradation from jitter
on the ADC clock will depend on how quickly the input is varying
at the sampling instance. TPC 36 charts this effect in the form
of ENOB vs. input frequency for the two clocking scenarios.
The maximum sample rate of the ADC in full-precision mode,
that is outputting 10 bits, is 55 MSPS. TPC 33 shows the ADC
performance in ENOB vs. f
. The maximum sample rate
ADCCLK
of the ADC in half-precision mode, that is outputting five bits,
is 64 MSPS. The timing of the interface is fully described in the
Receive Timing section of this data sheet.
Digital HPF
Following the ADC there is a bypassable digital HPF. The
response is a single pole IIR HPF. The transfer function is
approximately:
HzZZ
=−
()
0 999940 98466..
()
−
()
Where the sampling period is equal to the ADC clock period.
This results in a 3 dB frequency approximately 1/400th of the
ADC sampling rate. The transfer functions are plotted for
32 MSPS and 50 MSPS in TPC 31 and TPC 32.
The digital HPF introduces a 1 ADC clock cycle latency. If the
HPF function is not desired, the HPF can be bypassed and the
latency will not be incurred.
Clock and Oscillator Circuitry
The AD9875’s internal oscillator generates all sampling clocks
from a fundamental frequency quartz crystal. Figure 3a shows
how the quartz crystal is connected between OSCIN (Pin 1) and
XTAL (Pin 48) with parallel resonant load capacitors as specified
by the crystal manufacturer. The internal oscillator circuitry can
also be overdriven by a TTL level clock applied to OSCIN with
XTAL left unconnected.
The PLL has a frequency capture range between 10 MHz and
64 MHz.
AD9875
XTAL
OSCIN
XTAL
Y1
C1
C2
Figure 3a. Connections for Fundamental Mode Crystal
VOLTAGE REGULATOR CONTROLLER
The AD9875 contains an on-chip voltage regulator controller
(VRC) for providing a linear 1.3 V supply for low voltage digital
circuitry or other external use. The VRC consists of an op amp
and a resistive voltage divider. As shown in Figure 3b, the resistive divider establishes a voltage of 1.3 V at the inverting input
of the amplifier when DVDD is equal to its nominal voltage of
3.3 V. The feedback loop around the op amp will adjust the gate
voltage such that the voltage at the FB pin, V
, will be equal to
FB
the voltage at the inverting input of the op amp.
3.3V
DVDD
AD9875
2R
S
G
1.3R
GATE
FB
VFB = 1.3V
D
SI2301
C
V
OUT
Figure 3b. Connections for a 1.3 V Linear Regulator
The maximum current output from the circuit is largely dependent on the MOSFET device. For the SI2301 shown, 250 mA
can be delivered. The regulated output voltage should have bulk
decoupling and high frequency decoupling capacitors to ground
as required by the load. The regulator circuit will be stable for
capacitive loads between 0.1 µF and 47 µF.
It should be noted that the regulated output voltage, V
FB
, is
proportional to DVDD. Therefore, the percentage variation in
DVDD will also be seen at the regulated output voltage. The
load regulation is roughly equal to the on resistance of the
MOSFET device chosen. For the SI2301, this is about 60 mΩ.
REV. A
–17–
Page 18
AD9875
AGC TIMING CONSIDERATIONS
When implementing the AGC timing loop it is important to consider
the delay and settling time of the Rx path in response to a change
in gain. Figure 4 shows the delay the receive signal experiences
through the blocks of the Rx path. Whether the gain is programmed
through the serial port or over the TX[5:0] pins, the gain takes
effect immediately with the delays shown below. When gain
changes do not involve the CPGA, the new gain will be evident in
samples after seven ADC clock cycles. When the gain change does
involve the CPGA, it takes an additional 45 ns to 70 ns due to the
propagation delays of the buffer, LPF and PGA. Table III, in the
Register Programming section, details the PGA programming map.
GAIN
DIGITAL
HPF
1 CLK
CYCLE
REGISTER
ADCSHA
5 CLK
CYCLE
1/2 CLK
CYCLE
5ns
DECODE
BUFFER
10ns
LOGIC
25ns OR 50ns
LPF
PGA
10ns
Figure 4. AGC Timing
Transmit Port Timing
The AD9875 transmit port consists of a 6-bit data bus Tx[5:0],
a clock and a Tx SYNC signal. Two consecutive nibbles of the
Tx data are multiplexed together to form a 10-bit data word. The
clock appearing on the CLK-A pin is a buffered version of the
internal Tx data sampling clock. Data from the Tx port is read
on the rising edge of this sampling clock. The Tx SYNC signal is
used to indicate to which word a nibble belongs. The first nibble
of every word is read while Tx SYNC is low, the second nibble
of that same word is read on the following Tx SYNC high level.
The timing is illustrated in the Figure 5.
t
CLK-A
Tx SYNC
Tx [5:0]
Tx0 LSB
Tx1 MSB
SU
t
HD
Tx2 LSB
Tx3 MSBTx1 LSB Tx2 MSB
Figure 5. Transmit Timing Diagram AD9875
The Tx port is highly configurable and offers the following options:
Negative edge sampling can be chosen by two different methods;
either by setting the Tx Port Negative Edge Sampling bit (Register 3,
Bit 7) or the Invert CLK-A bit (Register 8, Bit 6). The main
difference between the two methods is that setting Register 3,
Bit 7 inverts the internal sampling clock and will affect only the
transmit path, even if CLK–A is used to clock the Rx data. Inverting CLK-A would affect both the Rx and Tx paths if they both
use CLK-A.
The first nibble of each word can be read in as the least significant nibble by setting the Tx LS Nibble First bit (Register 7, Bit 2).
For the AD9875, the most significant nibble defaults to six bits
and the least significant nibble defaults to form four bits. This can
be changed so that the least significant nibble and most significant
nibble have five bits each. This is done by setting the Tx PortWidth Five Bits bit (Register 7, Bit 1). In all cases, the nibbles are
justified toward Bit 5.
Also, the Tx path can be used in a reduced resolution mode by
setting the Tx Port Multiplexer Bypass bit (Register 7, Bit 0). In
this mode the Tx data word becomes six bits and is read in a
single cycle. The clocking modes are the same as described
above, but the level of Tx SYNC is irrelevant.
If Tx SYNC is low for more than one clock cycle, the last transmit
data will read continuously until Tx SYNC is brought high for
the second nibble of a new transmit word. This feature can be used
to “flush” the interpolator filters with zeros.
PGA Gain Adjust Timing
In addition to the serial port, the Tx[5:1] pins can be used to
write to the Rx Path Gain Adjust bits (Register 6, Bits 4:0). This
provides a faster way to update the PGA gain. A high level on the
GAIN pin with Tx SYNC low programs the PGA setting on the
rising edge of CLK-A. A low level on the GAIN pin enables data
to be fed to the interpolator and DAC. The GAIN pin must be
held high, the Tx SYNC must be held low, and the GAIN data
must be stable for three clock cycles to successfully update the
PGA GAIN value.
It should be noted that Tx SYNC must be held low and Tx GAIN
must be held high to update the gain register. If Tx GAIN and
Tx SYNC are both high, no data is written to the gain register
of the Tx data path.
t
CLK-A
Tx SYNC
Tx [5:0]
GAIN
SU
t
HD
GAIN
Figure 6. GAIN Programming
Receive Port Timing
The AD9875 receives port consists of a six bit data bus Rx[5:0],
a clock and an Rx SYNC signal. Two consecutive nibbles of
the Rx data are multiplexed together to form a 10-bit data word.
The Rx data is valid on the rising edge of CLK-A when the
ADC Clock Source PLL-B/2 bit (Register 3, Bit 6) is set to 0.
The Rx SYNC signal is used to indicate to which word a nibble
belongs. The first nibble of every word is transmitted while
Rx SYNC is low, the second nibble of that same word is transmitted on the following Rx SYNC high level. When Rx SYNC is
low, the sampled nibble is read as the most significant nibble.
When the Rx SYNC is high, the sampled nibble is read as the
least significant nibble. The timing is illustrated in Figure 7.
t
CLK-A (-B)
Rx SYNC
Rx [5:0]
Rx0 LSB
t
VT
Rx1 MSB
HT
Rx2 LSB
Rx3 MSBRx1 LSB Rx2 MSB
Figure 7. Receive Timing Diagram
The Rx port is highly configurable and offers the following options:
Negative edge sampling can be chosen by setting the InvertCLK-A bit (Register 8, Bit 6) or the Invert CLK-B bit (Register 8,
Bit 7), depending on the clock selected as the ADC sampling
source. Inverting CLK-A would affect the Tx sampling edge as
well as the Rx sampling edge.
The first nibble of each word can be read in as the least significant nibble by setting the Rx LS Nibble First bit (Register 8, Bit 2).
–18–
REV. A
Page 19
AD9875
SENABLE
SCLK
SDATA
t
DH
t
DS
t
DS
t
PWH
t
SCLK
t
PWL
INSTRUCTION BIT 7
INSTRUCTION BIT 6
SENABLE
SCLK
SDATA
DATA BIT n
DATA BIT n–1
t
DV
For the AD9875, the most significant nibble defaults to six bits
and the least significant nibble defaults to four bits. This can be
changed so that the least significant nibble and most significant
nibble have five bits each. This is done by setting the Rx PortWidth Five Bits bit (Register 8, Bit 1). In all cases, the nibbles
are justified toward Bit 5.
Also, the Rx path can be used in a reduced resolution mode by
setting the Rx Port Multiplexer Bypass bit (Register 8, Bit 0). In
this mode the Rx data word becomes six bits and is read in a
single cycle. The clocking modes are the same as described above,
but the level of Rx SYNC will stay low.
The Rx[5:0] pins can be put into a high impedance state by
setting the Three-State Rx Port bit (Register 8, Bit 3).
SERIAL INTERFACE FOR REGISTER CONTROL
The serial port is a three wire serial communications port consisting
of a clock (SCLK), chip select (SENABLE), and a bidirectional
data (SDATA) signal. The interface allows read/write access to
all registers that configure the AD9875 internal parameters.
Single or multiple byte transfers are supported as well as MSB
first or LSB first transfer formats.
General Operation of the Serial Interface
Serial communication over the serial interface can be from 1 to
5 bytes in length. The first byte is always the instruction byte.
The instruction byte establishes whether the communication is
going to be a read or write access, the number of data bytes to
be transferred and the address of the first register to be accessed.
The instruction byte transfer is complete immediately upon the
eighth rising edge of SCLK after SENABLE is asserted. Likewise,
the data registers change immediately upon writing to the eighth
bit of each data byte.
Instruction Byte
The instruction byte contains the following information as
shown below:
Table II. Instruction Byte Information
Bits I4:I0 – A4:A0
These bits determine which register is accessed during the data
transfer portion of the communications cycle. For multibyte
transfers, this address is the starting byte address. The remaining
register addresses are generated by the AD9875.
SERIAL INTERFACE PORT PIN DESCRIPTION
SCLK—Serial Clock
The serial clock pin is used to synchronize data transfers to and
from the AD9875 and to run the internal state machines. SCLK
maximum frequency is 25 MHz. All data transmitted to the
AD9875 is sampled on the rising edge of SCLK. All data read
from the AD9875 is validated on the rising edge of SCLK and is
updated on the falling edge.
SENABLE—Serial Interface Enable
The SENABLE pin is active low. It enables the serial communication to the device. SENABLE select should stay low during
the entire communication cycle. All input on the serial port is
ignored when SENABLE is inactive.
SDATA—Serial Data I/O
The signal on this line is sampled on the first eight rising edges of
SCLK after SENABLE goes active. Data is then read from or
written to the AD9875 depending on what was read.
Figures 8 and 9 show the timing relationships between the three
SPI signals.
Figure 8. Timing Diagram Register Write to AD9875/AD9876
BSMBSL
7I6I5I4I3I2I1I0I
W/R1N0N4A3A2A1A0A
Bit I7 – R/W
This bit determines whether a read or a write data transfer will
occur after the instruction byte write. Logic high indicates read
operation; logic zero indicates a write operation.
Bits I6:I5 – N1:N0
These two bits determine the number of bytes to be transferred
during the data transfer cycle. The bit decodes are shown in the
table below:
Figure 9. Timing Diagram Register Read from AD9875/AD9876
MSB/LSB TRANSFERS
The AD9875 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. The
bit order is controlled by the SPI LSB First bit (Register 0, Bit 6).
The default is value is 0, MSB first. Multibyte data transfers in
MSB format can be completed by writing an instruction byte
that includes the register address of the last address to be accessed.
The AD9875 will automatically decrement the address for each
successive byte required for the multibyte communication cycle.
When the SPI LSB First bit (Register 0, Bit 6) is set high, the
serial port interprets both instruction and data bytes LSB first.
Multibyte data transfers in LSB format can be completed by
writing an instruction byte that includes the register address of
the first address to be accessed. The AD9875 will automatically
Page 20
AD9875
increment the address for each successive byte required for the
multibyte communication cycle. Figures 10a and 10b show how
the serial port words are built for each of these modes.
Notes on Serial Port Operation
The serial port is disabled and all registers are set to their default
values during a hardware reset. During a software reset, all registers
except register 0 are set to their default values. Register 0 will
SENABLE
SCLK
SDATA
INSTRUCTION CYCLEDATA TRANSFER CYCLE
I6
R/W
I5
(N)
(N)
I3I4
I2 I1 I0
D7ND6
N
D0
D2
D1
0
0
0
Figure 10a. Serial Register Interface Timing MSB-First
remain at the last value sent, with the exception that the Software
Reset bit will be set to 0.
The serial port is operated by an internal state machine and is
dependent on the number of SCLK cycles since the last time
SENABLE went active. On every eighth rising edge of SCLK,
a byte is transferred over the SPI. During a multibyte write cycle,
this means the registers of the AD9875 are not simultaneously
updated, but occur sequentially. For this reason, it is recommended that single byte transfers be used when changing the
SENABLE
SCLK
SDATA
INSTRUCTION CYCLEDATA TRANSFER CYCLE
I6
I0
I5
R/W
I3 I4I2I1
(N)
(N)
D2
D0
D1
0
0
0
D7
ND6N
SPI configuration or performing a software reset.
Figure 10b. Serial Register Interface Timing LSB-First
REGISTER PROGRAMMING DEFINITIONS
REGISTER 0—RESET/SPI Configuration
Bit 5: Software Reset
Setting this bit high resets the chip. The PLLs will relock to the
input clock and all registers (except Register 0 × 0, Bit 6) revert
to their default values. Upon completion of the reset, Bit 5 is
reset to 0.
The content of the interpolator stages are not cleared by software
or hardware resets. It is recommended to “flush” the transmit
path with zeros before transmitting data.
Bit 6: LSB/MSB First
Setting this bit high causes the serial port to send and receive
data least significant bit (LSB) first. The default low state configures the serial port to send and receive data most significant
bit (MSB) first.
REGISTERS 1 AND 2—POWER-DOWN
The combination of the PWR DN pin and Registers 1 and 2
allow for the configuration of two separate pin selectable power
settings. The PWR DN pin selects between two sets of individually programmed operation modes.
When the PWR DN pin is low, the functional blocks corresponding to the bits set in register 1 will be powered down.
When the PWR DN pin is high, the functional blocks corresponding to the bits set in Register 2 will be powered down
Bit 0: Power-Down Receive Filter and CPGA
Setting this bit high powers down and bypasses the Rx LPF and
coarse programmable gain amplifier.
Bit 1: Power-Down ADC and FPGA
Setting this bit high powers down the ADC and fine programmable gain amplifier (FPGA).
Bit 2: Power-Down Rx Reference
Setting this bit high powers down the ADC reference. This bit
should be set if an external reference is applied.
Bit 3: Power-Down Interpolators
Setting this bit high powers down the transmit digital interpolators.
It does not clear the content of the data path.
Bit 4: Power-Down DAC
Setting this bit high powers down the transmit DAC.
Bit 5, Bit 6: Power-Down PLL-A, PLL-B
Setting these bits high powers down the on-chip phase lock
loops which generated CLK-A and CLK-B respectively. When
powered down these clocks are high impedance.
Bit 7: Power-Down Regulator
Setting this bit high powers down the on-chip voltage control regulator.
REGISTER 3—CLOCK SOURCE CONFIGURATION
The AD9875 integrates two independently programmable PLLs
referred to as PLL-A and PLL-B. The outputs of the PLLs are
used to generate all the chips internal and external clock signals
from the f
from PLL-A. If f
signal. All Tx path clock signals are derived
CLKIN
is programmed as the ADC sampling
CLKIN
clock source, the Rx port clocks are also derived from PLL-A.
Otherwise, the ADC sampling clock is PLL-B/2 and the Rx path
clocks are derived from PLL-B.
The best Rx path performance will be gained when the ADC
sampling clock is derived from f
CLKIN
. When f
provides the
CLKIN
ADC sampling clock, the PLL-A multiplier, L, must be set to 4.
REV. A
–21–
This restriction is due to the way the output clocking for the Rx
path is implemented.
Bit 1,0: PLL-A Multiplier
Bits 1 and 0 determine the multiplication factor (L) for PLL-A
and the DAC sampling clock frequency, f
fLf
=×
DACCLKIN
DAC.
–
Bit 1,0
0,0: L = 1
0,1: L = 2
1,0: L = 4
1,1: L = 8
Bit 5 to 2: PLL-B Multiplier/Divider
Bits 5 to 2 determine the multiplication factor (M) and division
factor (N) for PLL-B and the CLK-B frequency. For multiplexed
10-/12-bit data, f
CLK-B
= (f
CLKIN
data, f
= f
CLK-B
/2) × M/N. All nine combinations of M and N
× M/N. For nonmultiplexed 6-bit
CLKIN
values are valid, yielding seven unique M/N ratios.
Bit 5,4Bit 3,2
0,0: M = 30,0: N = 2
0,1: M = 40,1: N = 4
1,0: M = 61,0: N = 1
Bit 6: ADC Clock Source PLL-B/2
Setting Bit 6 high selects PLL-B/2 as the ADC sampling Clock
source. In this mode, the Rx data and CLK-B will run at a rate
of f
. RxSYNC will run at f
CLK-B
Setting Bit 6 low selects the f
/2.
CLK-B
signal as the ADC sampling
CLKIN
clock source. This mode of operation yields the best ADC
performance if an external crystal is used or a low jitter clock
source drives the OSCIN pin.
Bit 7: Tx Port Negative Edge Sampling
Setting Bit 7 high will cause the Tx port to sample the TxDATA
and TxSYNC on the falling edge of CLK-A. By default, the Tx
Port sampling occurs on the rising edge of CLK-A. The timing
is shown in Figure 5.
REGISTER 4—RECEIVE FILTER SELECTION
The AD9875 receive path has a continuous time 4-pole LPF
and a 1-pole digital HPF. The 4-pole LPF has two selectable
cutoff frequencies. Additionally, the filter can be tuned around
those two cutoff frequencies. These filters can also be bypassed
to different degrees as described below.
The continuous time 4-pole low-pass filter is automatically
calibrated to one of two selectable cutoff frequencies.
The cutoff frequency f
ADC sampling frequency f
is described as a function of the
CUTOFF
and can be influenced (±30%) by
ADC
the Rx-Filter Tuning Target word in Register 5.
ffTet
CUTOFF LOWADC
ffTet
CUTOFF HIGHADC
Bit 0: Rx LPF Bypass
=× +
=×+
6464arg
()
15864arg
()
Setting this bit high bypasses the 4-pole LPF. The filter is
automatically powered down when this bit is set.
Bit 1: Enable 1-Pole Rx LPF
The AD9875 can be configured with an additional 1-pole ~16 MHz
input filter for applications that require steeper filter roll-off or
want to use the 1-pole filter instead of the 4-pole receive Low-Pass
filter. The 1-pole filter is untrimmed and subject to cutoff frequency
variations of ±20%.
Page 22
AD9875
Bit 2: Wideband Rx LPF
This bit selects the nominal cutoff frequency of the 4-pole LPF.
Setting this bit high selects a nominal cutoff frequency of 28.8 MHz.
When the wideband filter is selected, the Rx path gain is limited
to 30 dB.
Bit 3: Fast ADC Sampling
Setting this bit increases the quiescent current in the SVGA
block. This may provide some performance improvement
when the ADC sampling frequency is greater than 50 MSPS
(in 6-bit mode).
Bit 4: Rx Digital HPF Bypass
Setting this bit high bypasses the 1-pole digital HPF that follows
the ADC. The digital filter must be bypassed for ADC sampling
above 50 MSPS.
Bit 5: Rx Path DC Offset Correction
Writing a One to this bit triggers an immediate receive path
offset correction and reads back zero after the completion of the
offset correction.
Bit 6: Rx LPF Tuning Update In Progress
This bit indicates when receive filter calibration is in progress.
The duration of a receive filter calibration is about 500 ms.
Writing to this bit has no effect.
Bit 7: Rx LPF Tuning Update Disable
Setting this bit high disables the automatic background receive
filter calibration. The AD9875 automatically calibrates the
receive filter on reset and every few (~2) seconds thereafter to
compensate for process and temperature variation, power supply
and long term drift. Programming a one to this bit disables this
function. Programming a zero triggers an immediate first calibration and enables the periodic update.
REGISTER 5—RECEIVE FILTER TUNING TARGET
This register sets the filter tuning target as a function of f
OSCIN
.
See Register 4 description.
REGISTER 6—Rx PATH GAIN ADJUST
The AD9875 uses a combination of a continuous time PGA
(CPGA) and a switched capacitor PGA (SPGA) for a gain range
of –6 to 36 dB with a resolution of 2 dB. The Rx path gain can
be programmed over the serial interface by writing to the Rx
Path Gain Adjust register or directly using the GAIN and MSB
aligned Tx[5:1] bits. The register default value is 0 × 00 for
lowest gain setting (–6 dB). The register always reads back the
actual gain setting irrespective of which of the two programming
modes were used.
Table V describes the gains and how they are achieved as a
function of the Rx Path adjust bits.
Bit 5: PGA Gain Set through Register
Setting this bit high will result in the Rx Path Gain being set by
writing to the PGA Gain Control register. Default is zero which
selects writing the gain through the Tx[5:1] pins in conjunction
with the gain pin.
*When the Wideband Rx Filter bit is set high, the Rx Path Gain is limited to
30 dB. The first of the two values in the chart refers to this mode. The second
number refers to the mode when the lower Rx LPF cutoff frequency is chosen,
or the Rx LPF filter is bypassed.
REGISTER 7—TRANSMIT PATH SETTINGS
The AD9875 transmit path has a programmable interpolation
filter that precedes the transmit DAC. The interpolation filter
can be programmed to operate in seven different modes. Also,
the digital interface can be programmed to operate in several
different modes. These modes are described below.
Bit 0: Transmit Port Demultiplexer Bypass
Setting Bit 0 high bypasses the input data demultiplexer. In this
mode, consecutive nibbles on the TxDATA(5:0) pins are treated
as individual words to be sent through the Tx path. This creates
a six bit data path. The state of TxSYNC is ignored in this mode.
Bit 1: Transmit Port Width
If Bit 1 is set high, the Tx port will operate such that the most
significant nibble and the least significant nibble are each five
bits wide. The default mode is six bits for the most significant
nibble and four bit for the least significant nibble. The data is
always aligned to the MSB pin Tx[5]. Enabling this pin on the
AD9875 allows for a five pin versus the default six pin interface.
Bit 2: Transmit Port Least Significant Nibble First
Setting Bit 2 high reconfigures the AD9875 for a transmit
mode that expects least significant nibble before the most
significant nibble.
–22–
REV. A
Page 23
AD9875
Bit 3: Power-Down Interpolator at TxQUIET Pin Low
Setting Bit 3 high enables the TxQUIET pin to shut off the
DAC output. If the bit is set to one, then pulling the TxQUIET
pin low will power down the interpolator filters. In most applications the interpolator filter will need to be flushed with zeros
before or after being powered down.
Bit 4 to Bit 7: Interpolation Filter Select
Bits 4 to 7 define the Interpolation filter characteristic and interpolation rate.
The interpolation factor has a direct influence on the CLK-A
output frequency. When the transmit input data multiplexer is
enabled (10-bit mode):
ffK
=×2
CLK ADAC−
where K is the interpolation factor.
When the transmit input data multiplexer is disabled (5-/6-bit
mode):
ffK
=
CLK ADAC−
where K is the interpolation factor.
REGISTER 8—RECEIVER AND CLOCK OUTPUT SETTINGS
Bit 0: Rx Port Multiplexer Bypass
Setting this bit high bypasses the Rx port output multiplexer.
This will output only the 6 MSBs of the ADC word. This mode
enables ADC sampling rates above 55 MSPS.
Bit 1: Rx Port Width Five Bits
If the bit is set high, the Rx port data will be output in two
nibbles of five bits each (on pins Rx[5:1]). When this bit is low
(default), the most significant nibble will contain six bits and the
least significant nibble will have four bits. The default mode
makes the AD9875 pin compatible with the AD9876.
Bit 2: Rx Port LS Nibble First
Reconfigures the AD9875 for a receive mode that expects less
significant bits before the most significant bits.
Bit 3: Three-State Rx Port
This bit sets the receive output Rx[5:0] into a high impedance
three-state mode. It allows for sharing the bus with other devices.
Bit 4, Bit 5: Disable CLK-A, Disable CLK-B
Setting Bit 4 or Bit 5 stops CLK-A or CLK-B respectively, from
toggling. The output is held to a logic 0 level.
Bit 4, Bit 5: Disable CLK-A, Disable CLK-B
Setting Bit 4 or Bit 5 fixes CLK-A or CLK-B to a low output
level, respectively.
Bit 6: CLK-A Output Invert
Setting Bit 6 high inverts the CLK-A output signal.
Bit 7: CLK-B Output Invert
Setting this bit high inverts the CLK-B output signal. This effectively
changes the timing of the Rx[5:0] and RxSYNC signals from rising
edge triggered to falling edge triggered with respect to the CLK-B
signal.
REGISTER F—DIE REVISION
This register stores the die revision of the chip. It is a readonly register.
PCB DESIGN CONSIDERATIONS
Although the AD9875 is a mixed-signal device, the part should
be treated as an analog component. The digital circuitry on-chip
has been specially designed to minimize the impact that the
digital switching noise will have on the operation of the analog
circuits. Following the power, grounding and layout recommendations in this section will help you get the best performance
from the MxFE.
Component Placement
If the three following guidelines of component placement are
followed, chances for getting the best performance from the
are greatly increased. First, manage the path of return
MxFE
currents flowing in the ground plane so that high frequency
switching currents from the digital circuits do not flow on the
ground plane under the MxFE or analog circuits. Second, keep
noisy digital signal paths and sensitive receive signal paths as
short as possible. Third, keep digital (noise generating) and
analog (noise susceptible) circuits as far away from each other
as possible.
In order to best manage the return currents, pure digital circuits
that generate high switching currents should be closest to the
power supply entry. This will keep the highest frequency return
current paths short, and prevent them from traveling over the
sensitive MxFE and analog portions of the ground plane. Also,
these circuits should be generously bypassed at each device
which will further reduce the high frequency ground currents.
The MxFE should be placed adjacent to the digital circuits,
such that the ground return currents from the digital sections
will not flow in the ground plane under the MxFE. The analog
circuits should be placed furthest from the power supply.
The AD9875 has several pins which are used to decouple sensitive internal nodes. These pins are REFIO, REFB, and REFT.
The decoupling capacitors connected to these points should
have low ESR and ESL. These capacitors should be placed as
close to the MxFE as possible and be connected directly to the
analog ground plane.
The resistor connected to the FSADJ pin should also be placed
close to the device and connected directly to the analog ground plane.
Power Planes and Decoupling
The AD9875 evaluation board demonstrates a good power supply
distribution and decoupling strategy. The board has four layers;
two signal layers, one ground plane and one power plane. The
power plane is split into a 3VDD section used for the 3 V digital
logic circuits, a DVDD section used to supply the digital supply
pins of the AD9875, an AVDD section used to supply the analog
supply pins of the AD9875, and a VANLG section that supplies
the higher voltage analog components on the board. The 3VDD
section will typically have the highest frequency currents on the
power plane and should be kept the furthest from the MxFE and
analog sections of the board. The DVDD portion of the plane
brings the current used to power the digital portion of the MxFE
to the device. This should be treated similarly to the 3VDD power
plane and be kept from going underneath the MxFE or analog
components. The MxFE should largely sit on the AVDD portion
of the power plane.
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AD9875
The AVDD and DVDD power planes may be fed from the same
low noise voltage source; however, they should be decoupled from
each other to prevent the noise generated in the DVDD portion
of the MxFE from corrupting the AVDD supply. This can be done
by using ferrite beads between the voltage source and DVDD,
and between the source and AVDD. Both DVDD and AVDD
should have a low ESR, bulk decoupling capacitor on the MxFE
side of the ferrite as well as a low ESR, ESL decoupling capacitors
on each supply pin (i.e., the AD9875 requires five power supply
decoupling caps, one each on Pins 5, 38, 47, 14, and 35). The
decoupling caps should be placed as close to the MxFE supply
pins as possible. An example of the proper decoupling is shown
in the AD9875 evaluation board schematic.
Ground Planes
In general, if the component placing guidelines discussed earlier
can be implemented, it is best to have at least one continuous
ground plane for the entire board. All ground connections should
be made as short as possible. This will result in the lowest impedance return paths, and the quietest ground connections.
If the components cannot be placed in a manner that will keep the
high-frequency ground currents from traversing under the MxFE
and analog components, it may be necessary to put current
steering channels into the ground plane to route the high-frequency
currents around these sensitive areas. These current steering
channels should be made only when and where necessary.
Signal Routing
The digital Rx and Tx signal paths should be kept as short as
possible. Also, the impedance of these traces should have a
controlled characteristic impedance of about 50 Ω. This will
prevent poor signal integrity and the high currents that can
occur during undershoot or overshoot caused by ringing. If the
signal traces cannot be kept shorter than about 1.5 inches, then
series-termination resistors (33 Ω to 47 Ω) should be placed
close to all signal sources. It is a good idea to series-terminate all
clock signals at their source, regardless of trace length.
The receive Rx± signals are the most sensitive signals on the
entire board. Careful routing of these signals is essential for good
receive path performance. The Rx± signals form a differential pair
and should be routed together as a pair. By keeping the traces
adjacent to each other, noise coupled onto the signals will
appear as common-mode and will be largely rejected by the
MxFE receive input. Keeping the driving point impedance of
the receive signal low and placing any low-pass filtering of the
signals close to the MxFE will further reduce the possibility of
noise corrupting these signals.